i.MX6: Add ANATOP regulator init
PATCH v2 1/1 i.MX6: Add ANATOP regulator init
Init the core regulator voltage to 1.2V. This is required for the correct functioning of the GPU and when the ARM LDO is set to 1.225V. This is a workaround to fix some memory clock jitter.
Note: This should be but can't be done in the DCD. The bootloader
prevents access to the ANATOP registers.
---
v2: Rename the function set_vddsoc(mV) and export it as discused in
http://lists.denx.de/pipermail/u-boot/2012-April/122946.html
arch/arm/cpu/armv7/mx6/soc.c | 30 +++++++++++++++++++++++++++++ arch/arm/include/asm/arch-mx6/sys_proto.h | 2 + 2 files changed, 32 insertions(+), 0 deletions(-)
arch/arm/cpu/armv7/mx6/soc.c +30 -0
@@ -77,10 +77,40 @@ void init_aips(void) writel(0x00000000, &aips2->opacr4); } +/* +* Set the VDDSOC +* +* Mask out the REG_CORE[22:18] bits (REG2_TRIG) and set +* them to the specified millivolt level. +* Possible values are from 0.725V to 1.450V in steps of +* 0.025V (25mV). +*/ +void set_vddsoc (u32 mv) +{ +struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR ; +u32 val, reg =readl (&anatop->reg_core); + +if (mv <725 ) + val =0x00 ;/* Power gated off */ +else if (mv >1450 ) + val =0x1F ;/* Power FET switched full on. No regulation */ +else + val = (mv -700 ) /25 ; + +/* +* Mask out the REG_CORE[22:18] bits (REG2_TRIG) +* and set them to the calculated value (0.7V + val * 0.25V) +*/ + reg = (reg & ~(0x1F <<18 )) | (val <<18 ); +writel (reg, &anatop->reg_core); +} +int arch_cpu_init (void ) {init_aips (); +set_vddsoc (1200 );/* Set VDDSOC to 1.2V */ +return 0 ; }#endif
arch/arm/include/asm/arch-mx6/sys_proto.h +2 -0
@@ -28,6 +28,8 @@u32 get_cpu_rev (void ); +void set_vddsoc (u32 mv); +/* * Initializes on-chip ethernet controllers. * to override, implement board_eth_init()
Signature · 1 line
1.7.0.4
PATCH v2 1/1 i.MX6: Add ANATOP regulator init
Quoted 7 lines · Dirk Behme
Init the core regulator voltage to 1.2V. This is required for the correct functioning of the GPU and when the ARM LDO is set to 1.225V. This is a workaround to fix some memory clock jitter.
Note: This should be but can't be done in the DCD. The bootloader
prevents access to the ANATOP registers.
Quoted 7 lines
Signed-off-by Dirk Behme <[email protected]>CC Jason Chen <[email protected]>CC Jason Liu <[email protected]>CC Ranjani Vaidyanathan <[email protected]>CC Stefano Babic <[email protected]>CC Fabio Estevam <[email protected]>---
Applied to u-boot-imx, thanks.
Best regards,
Stefano Babic
Signature · 5 lines
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