i.mx: i.mx6x: NO_MUX_I/NO_PAD_I not set correctly

PATCH New Jason Liu 3 participants 4 messages Apr 11, 2012 – Jun 12, 2012 Arm (32-bit)

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Jason Liu

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2012-04-11 11:18 UTC #0 lore raw

PATCH 1/1 i.mx: i.mx6x: NO_MUX_I/NO_PAD_I not set correctly

If one PAD does not have mux or pad config register, we need set the NO_MUX_I/NO_PAD_I to 0, the old value is not correct

Signed-off-by Jason Liu <[email protected]>

CC Stefano Babic <[email protected]>

---
 arch/arm/include/asm/arch-mx6/mx6x_pins.h |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

arch/arm/include/asm/arch-mx6/mx6x_pins.h +2 -2

index afaa068..9979651 100644
@@ -48,8 +48,8 @@
 #define PAD_CTL_SRE_FAST	(1 << 0)
 #define PAD_CTL_SRE_SLOW	(0 << 0)
 
-#define NO_MUX_I		0x3FF
-#define NO_PAD_I		0x7FF
+#define NO_MUX_I                0
+#define NO_PAD_I                0
 
 enum {
 	MX6Q_PAD_SD2_DAT1__USDHC2_DAT1		= IOMUX_PAD(0x0360, 0x004C, 0, 0x0000, 0, 0),

Signature · 1 line

1.7.5.4

Stefano Babic

2012-04-11 11:58 UTC #1 lore raw

PATCH 1/1 i.mx: i.mx6x: NO_MUX_I/NO_PAD_I not set correctly

Quoted 14 lines · Jason Liu

If one PAD does not have mux or pad config register, we need set the NO_MUX_I/NO_PAD_I to 0, the old value is not correct
Signed-off-by Jason Liu <[email protected]>
CC Stefano Babic <[email protected]>
---
 arch/arm/include/asm/arch-mx6/mx6x_pins.h |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)
arch/arm/include/asm/arch-mx6/mx6x_pins.h +0 -0
index afaa068..9979651 100644

arch/arm/include/asm/arch-mx6/mx6x_pins.h line 55

Quoted 10 lines

arch/arm/include/asm/arch-mx6/mx6x_pins.h +2 -2

@@ -48,8 +48,8 @@
 #define PAD_CTL_SRE_FAST	(1 << 0)
 #define PAD_CTL_SRE_SLOW	(0 << 0)
 
-#define NO_MUX_I		0x3FF
-#define NO_PAD_I		0x7FF
+#define NO_MUX_I                0
+#define NO_PAD_I                0
 
 enum {
 	MX6Q_PAD_SD2_DAT1__USDHC2_DAT1		= IOMUX_PAD(0x0360, 0x004C, 0, 0x0000, 0, 0),

Agree. Please correct me if I am wrong, but with these changes we should sure that the iomux register are not set if we do not want, because in imx_iomux_v3_setup_pad:

if (sel_input_ofs)

	__raw_writel(sel_input, base + sel_input_ofs);

and NO_MUX_I = 0 should set sel_input_ofs to 0.

It is then difficult to understand why we have up now 0x3FF as value, but it neverminds..

Acked-by Stefano Babic <[email protected]>

(This is a fix, I will merge it for the release)

Best regards,
Stefano Babic

Signature · 5 lines

=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

Dirk Behme

2012-05-15 12:42 UTC #2 lore raw

PATCH 1/1 i.mx: i.mx6x: NO_MUX_I/NO_PAD_I not set correctly

Quoted 33 lines · Stefano Babic

Quoted 14 lines · Jason Liu
If one PAD does not have mux or pad config register, we need set the NO_MUX_I/NO_PAD_I to 0, the old value is not correct
Signed-off-by Jason Liu <[email protected]>
CC Stefano Babic <[email protected]>
---
 arch/arm/include/asm/arch-mx6/mx6x_pins.h |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)
arch/arm/include/asm/arch-mx6/mx6x_pins.h +0 -0
index afaa068..9979651 100644
arch/arm/include/asm/arch-mx6/mx6x_pins.h line 55
Quoted 10 lines
arch/arm/include/asm/arch-mx6/mx6x_pins.h +2 -2
@@ -48,8 +48,8 @@
 #define PAD_CTL_SRE_FAST	(1 << 0)
 #define PAD_CTL_SRE_SLOW	(0 << 0)
 
-#define NO_MUX_I		0x3FF
-#define NO_PAD_I		0x7FF
+#define NO_MUX_I                0
+#define NO_PAD_I                0
 
 enum {
 	MX6Q_PAD_SD2_DAT1__USDHC2_DAT1		= IOMUX_PAD(0x0360, 0x004C, 0, 0x0000, 0, 0),
Agree. Please correct me if I am wrong, but with these changes we should sure that the iomux register are not set if we do not want, because in imx_iomux_v3_setup_pad:
if (sel_input_ofs)
	__raw_writel(sel_input, base + sel_input_ofs);

Quoted 8 lines

and NO_MUX_I = 0 should set sel_input_ofs to 0.
It is then difficult to understand why we have up now 0x3FF as value, but it neverminds..
Acked-by Stefano Babic <[email protected]>
(This is a fix, I will merge it for the release)

I have this patch on my list of pending patches.

Should it be applied now?

Best regards

Dirk

Stefano Babic

2012-06-12 17:05 UTC #3 lore raw

PATCH 1/1 i.mx: i.mx6x: NO_MUX_I/NO_PAD_I not set correctly

In reply to Jason Liu

Quoted 14 lines · Jason Liu

If one PAD does not have mux or pad config register, we need set the NO_MUX_I/NO_PAD_I to 0, the old value is not correct
Signed-off-by Jason Liu <[email protected]>
CC Stefano Babic <[email protected]>
---
 arch/arm/include/asm/arch-mx6/mx6x_pins.h |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)
arch/arm/include/asm/arch-mx6/mx6x_pins.h +0 -0
index afaa068..9979651 100644

arch/arm/include/asm/arch-mx6/mx6x_pins.h line 55

Quoted 10 lines

arch/arm/include/asm/arch-mx6/mx6x_pins.h +2 -2

@@ -48,8 +48,8 @@
 #define PAD_CTL_SRE_FAST	(1 << 0)
 #define PAD_CTL_SRE_SLOW	(0 << 0)
 
-#define NO_MUX_I		0x3FF
-#define NO_PAD_I		0x7FF
+#define NO_MUX_I                0
+#define NO_PAD_I                0
 
 enum {
 	MX6Q_PAD_SD2_DAT1__USDHC2_DAT1		= IOMUX_PAD(0x0360, 0x004C, 0, 0x0000, 0, 0),

Applied to u-boot-imx, thanks. Sorry that it was not applied before ;-)

Best regards,
Stefano Babic

Signature · 5 lines

=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================