ARM: EXYYNOS: Use EXYNOS4210_GPEx instead of EXYNOS4_GPEx
Subsystems (4)
PATCH 1/2 ARM: EXYYNOS: Use EXYNOS4210_GPEx instead of EXYNOS4_GPEx
Also use EXYNOS4210_GPIO_Ex instead of EXYNOS4_GPIO_Ex. The GPEx gpios exist only on Exynos4210 and there are no on Exynos4x12. Redefine them to exact SoC name.
Signed-off-by Joonyoung Shim <[email protected]>
Signed-off-by Kyungmin Park <[email protected]>
--- arch/arm/mach-exynos/include/mach/gpio.h | 32 ++++++++++++++-------------- arch/arm/mach-exynos/mach-nuri.c | 16 +++++++------- arch/arm/mach-exynos/mach-origen.c | 6 ++-- arch/arm/mach-exynos/mach-universal_c210.c | 32 ++++++++++++++-------------- arch/arm/mach-exynos/setup-fimc.c | 4 +- drivers/gpio/gpio-samsung.c | 20 ++++++++-------- 6 files changed, 55 insertions(+), 55 deletions(-)
arch/arm/mach-exynos/include/mach/gpio.h +16 -16
@@ -26,11 +26,11 @@#define EXYNOS4_GPIO_C1_NR (5)#define EXYNOS4_GPIO_D0_NR (4)#define EXYNOS4_GPIO_D1_NR (4) -#define EXYNOS4_GPIO_E0_NR (5) -#define EXYNOS4_GPIO_E1_NR (8) -#define EXYNOS4_GPIO_E2_NR (6) -#define EXYNOS4_GPIO_E3_NR (8) -#define EXYNOS4_GPIO_E4_NR (8) +#define EXYNOS4210_GPIO_E0_NR (5) +#define EXYNOS4210_GPIO_E1_NR (8) +#define EXYNOS4210_GPIO_E2_NR (6) +#define EXYNOS4210_GPIO_E3_NR (8) +#define EXYNOS4210_GPIO_E4_NR (8)#define EXYNOS4_GPIO_F0_NR (8)#define EXYNOS4_GPIO_F1_NR (8)#define EXYNOS4_GPIO_F2_NR (8)
@@ -67,12 +67,12 @@ enum exynos4_gpio_number {EXYNOS4_GPIO_C1_START =EXYNOS_GPIO_NEXT (EXYNOS4_GPIO_C0 ),EXYNOS4_GPIO_D0_START =EXYNOS_GPIO_NEXT (EXYNOS4_GPIO_C1 ),EXYNOS4_GPIO_D1_START =EXYNOS_GPIO_NEXT (EXYNOS4_GPIO_D0 ), -EXYNOS4_GPIO_E0_START =EXYNOS_GPIO_NEXT (EXYNOS4_GPIO_D1 ), -EXYNOS4_GPIO_E1_START =EXYNOS_GPIO_NEXT (EXYNOS4_GPIO_E0 ), -EXYNOS4_GPIO_E2_START =EXYNOS_GPIO_NEXT (EXYNOS4_GPIO_E1 ), -EXYNOS4_GPIO_E3_START =EXYNOS_GPIO_NEXT (EXYNOS4_GPIO_E2 ), -EXYNOS4_GPIO_E4_START =EXYNOS_GPIO_NEXT (EXYNOS4_GPIO_E3 ), -EXYNOS4_GPIO_F0_START =EXYNOS_GPIO_NEXT (EXYNOS4_GPIO_E4 ), +EXYNOS4210_GPIO_E0_START =EXYNOS_GPIO_NEXT (EXYNOS4_GPIO_D1 ), +EXYNOS4210_GPIO_E1_START =EXYNOS_GPIO_NEXT (EXYNOS4210_GPIO_E0 ), +EXYNOS4210_GPIO_E2_START =EXYNOS_GPIO_NEXT (EXYNOS4210_GPIO_E1 ), +EXYNOS4210_GPIO_E3_START =EXYNOS_GPIO_NEXT (EXYNOS4210_GPIO_E2 ), +EXYNOS4210_GPIO_E4_START =EXYNOS_GPIO_NEXT (EXYNOS4210_GPIO_E3 ), +EXYNOS4_GPIO_F0_START =EXYNOS_GPIO_NEXT (EXYNOS4210_GPIO_E4 ),EXYNOS4_GPIO_F1_START =EXYNOS_GPIO_NEXT (EXYNOS4_GPIO_F0 ),EXYNOS4_GPIO_F2_START =EXYNOS_GPIO_NEXT (EXYNOS4_GPIO_F1 ), EXYNOS4_GPIO_F3_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_F2),
@@ -108,11 +108,11 @@ enum exynos4_gpio_number {#define EXYNOS4_GPC1 (_nr) (EXYNOS4_GPIO_C1_START + (_nr))#define EXYNOS4_GPD0 (_nr) (EXYNOS4_GPIO_D0_START + (_nr))#define EXYNOS4_GPD1 (_nr) (EXYNOS4_GPIO_D1_START + (_nr)) -#define EXYNOS4_GPE0 (_nr) (EXYNOS4_GPIO_E0_START + (_nr)) -#define EXYNOS4_GPE1 (_nr) (EXYNOS4_GPIO_E1_START + (_nr)) -#define EXYNOS4_GPE2 (_nr) (EXYNOS4_GPIO_E2_START + (_nr)) -#define EXYNOS4_GPE3 (_nr) (EXYNOS4_GPIO_E3_START + (_nr)) -#define EXYNOS4_GPE4 (_nr) (EXYNOS4_GPIO_E4_START + (_nr)) +#define EXYNOS4210_GPE0 (_nr) (EXYNOS4210_GPIO_E0_START + (_nr)) +#define EXYNOS4210_GPE1 (_nr) (EXYNOS4210_GPIO_E1_START + (_nr)) +#define EXYNOS4210_GPE2 (_nr) (EXYNOS4210_GPIO_E2_START + (_nr)) +#define EXYNOS4210_GPE3 (_nr) (EXYNOS4210_GPIO_E3_START + (_nr)) +#define EXYNOS4210_GPE4 (_nr) (EXYNOS4210_GPIO_E4_START + (_nr))#define EXYNOS4_GPF0 (_nr) (EXYNOS4_GPIO_F0_START + (_nr))#define EXYNOS4_GPF1 (_nr) (EXYNOS4_GPIO_F1_START + (_nr))#define EXYNOS4_GPF2 (_nr) (EXYNOS4_GPIO_F2_START + (_nr))
arch/arm/mach-exynos/mach-nuri.c +8 -8
@@ -264,7 +264,7 @@ static struct s3c_fb_platdata nuri_fb_pdata __initdata = {static void nuri_lcd_power_on (struct plat_lcd_data *pd,unsigned int power) { -int gpio =EXYNOS4_GPE1 (5 ); +int gpio =EXYNOS4210_GPE1 (5 );gpio_request (gpio,"LVDS_nSHDN" );gpio_direction_output (gpio, power);
@@ -273,7 +273,7 @@ static void nuri_lcd_power_on(struct plat_lcd_data *pd, unsigned int power)static int nuri_bl_init (struct device *dev) { -return gpio_request_one (EXYNOS4_GPE2 (3 ),GPIOF_OUT_INIT_LOW , +return gpio_request_one (EXYNOS4210_GPE2 (3 ),GPIOF_OUT_INIT_LOW ,"LCD_LD0_EN" ); }
@@ -282,14 +282,14 @@ static int nuri_bl_notify(struct device *dev, int brightness)if (brightness <1 ) brightness =0 ; -gpio_set_value (EXYNOS4_GPE2 (3 ),1 ); +gpio_set_value (EXYNOS4210_GPE2 (3 ),1 );return brightness; }static void nuri_bl_exit (struct device *dev) { -gpio_free (EXYNOS4_GPE2 (3 )); +gpio_free (EXYNOS4210_GPE2 (3 )); }/* nuri pwm backlight */
@@ -1042,7 +1042,7 @@ static struct max8903_pdata nuri_max8903 = {*/ .dok = EXYNOS4_GPX1(4), /* TA_nCONNECTED *//* uok, usus: not connected */ - .chg = EXYNOS4_GPE2(0), /* TA_nCHG */ + .chg = EXYNOS4210_GPE2(0), /* TA_nCHG *//* flt: vcc_1.8V_pda */ .dcm = EXYNOS4_GPL0(1), /* CURR_ADJ */
@@ -1114,7 +1114,7 @@ static struct regulator_init_data cam_vt_cam15_reg_init_data = {static struct fixed_voltage_config cam_vt_cam15_fixed_voltage_cfg = { .supply_name ="VT_CAM_1.5V" , .microvolts =1500000 , - .gpio =EXYNOS4_GPE2 (2 ),/* VT_CAM_1.5V_EN */ + .gpio =EXYNOS4210_GPE2 (2 ),/* VT_CAM_1.5V_EN */ .enable_high =1 , .init_data = &cam_vt_cam15_reg_init_data, };
@@ -1138,7 +1138,7 @@ static struct regulator_init_data cam_vdda_reg_init_data = {static struct fixed_voltage_config cam_vdda_fixed_voltage_cfg = { .supply_name ="CAM_IO_EN" , .microvolts =2800000 , - .gpio =EXYNOS4_GPE2 (1 ),/* CAM_IO_EN */ + .gpio =EXYNOS4210_GPE2 (1 ),/* CAM_IO_EN */ .enable_high =1 , .init_data = &cam_vdda_reg_init_data, };
@@ -1162,7 +1162,7 @@ static struct regulator_init_data cam_8m_12v_reg_init_data = {static struct fixed_voltage_config cam_8m_12v_fixed_voltage_cfg = { .supply_name ="8M_1.2V" , .microvolts =1200000 , - .gpio =EXYNOS4_GPE2 (5 ),/* 8M_1.2V_EN */ + .gpio =EXYNOS4210_GPE2 (5 ),/* 8M_1.2V_EN */ .enable_high =1 , .init_data = &cam_8m_12v_reg_init_data, };
arch/arm/mach-exynos/mach-origen.c +3 -3
@@ -560,13 +560,13 @@ static void lcd_hv070wsa_set_power(struct plat_lcd_data *pd, unsigned int power)int ret;if (power) - ret =gpio_request_one (EXYNOS4_GPE3 (4 ), + ret =gpio_request_one (EXYNOS4210_GPE3 (4 ),GPIOF_OUT_INIT_HIGH ,"GPE3_4" );else - ret =gpio_request_one (EXYNOS4_GPE3 (4 ), + ret =gpio_request_one (EXYNOS4210_GPE3 (4 ),GPIOF_OUT_INIT_LOW ,"GPE3_4" ); -gpio_free (EXYNOS4_GPE3 (4 )); +gpio_free (EXYNOS4210_GPE3 (4 ));if (ret)pr_err ("failed to request gpio for LCD power: %d\n" , ret);
arch/arm/mach-exynos/mach-universal_c210.c +16 -16
@@ -545,7 +545,7 @@ static struct max8998_platform_data universal_lp3974_pdata = { .buck2_voltage1 = 1200000, /* G3D */ .buck2_voltage2 = 1100000, .buck1_default_idx = 0, - .buck2_set3 = EXYNOS4_GPE2(0), + .buck2_set3 = EXYNOS4210_GPE2(0), .buck2_default_idx = 0, .wakeup = true, };
@@ -574,7 +574,7 @@ static struct regulator_init_data hdmi_fixed_voltage_init_data = {static struct fixed_voltage_config hdmi_fixed_voltage_config = { .supply_name ="HDMI_EN1" , .microvolts =5000000 , - .gpio =EXYNOS4_GPE0 (1 ), + .gpio =EXYNOS4210_GPE0 (1 ), .enable_high = true, .init_data = &hdmi_fixed_voltage_init_data, };
@@ -623,12 +623,12 @@ static void __init universal_tsp_init(void)int gpio;/* TSP_LDO_ON: XMDMADDR_11 */ - gpio =EXYNOS4_GPE2 (3 ); + gpio =EXYNOS4210_GPE2 (3 );gpio_request_one (gpio,GPIOF_OUT_INIT_HIGH ,"TSP_LDO_ON" );gpio_export (gpio,0 );/* TSP_INT: XMDMADDR_7 */ - gpio =EXYNOS4_GPE1 (7 ); + gpio =EXYNOS4210_GPE1 (7 );gpio_request (gpio,"TSP_INT" );s5p_register_gpio_interrupt (gpio);
@@ -654,8 +654,8 @@ static struct mcs_platform_data touchkey_data = {/* GPIO I2C 3_TOUCH 2.8V */ #define I2C_GPIO_BUS_12 12static struct i2c_gpio_platform_data i2c_gpio12_data = { - .sda_pin =EXYNOS4_GPE4 (0 ),/* XMDMDATA_8 */ - .scl_pin =EXYNOS4_GPE4 (1 ),/* XMDMDATA_9 */ + .sda_pin =EXYNOS4210_GPE4 (0 ),/* XMDMDATA_8 */ + .scl_pin =EXYNOS4210_GPE4 (1 ),/* XMDMDATA_9 */ };static struct platform_device i2c_gpio12 = {
@@ -677,13 +677,13 @@ static void __init universal_touchkey_init(void) {int gpio; - gpio =EXYNOS4_GPE3 (7 );/* XMDMDATA_7 */ + gpio =EXYNOS4210_GPE3 (7 );/* XMDMDATA_7 */ gpio_request (gpio,"3_TOUCH_INT" );s5p_register_gpio_interrupt (gpio);s3c_gpio_cfgpin (gpio,S3C_GPIO_SFN (0xf )); i2c_gpio12_devs[0 ].irq =gpio_to_irq (gpio); - gpio =EXYNOS4_GPE3 (3 );/* XMDMDATA_3 */ + gpio =EXYNOS4210_GPE3 (3 );/* XMDMDATA_3 */ gpio_request_one (gpio,GPIOF_OUT_INIT_HIGH ,"3_TOUCH_EN" ); }
@@ -769,7 +769,7 @@ static struct regulator_init_data mmc0_fixed_voltage_init_data = {static struct fixed_voltage_config mmc0_fixed_voltage_config = { .supply_name ="MASSMEMORY_EN" , .microvolts =2800000 , - .gpio =EXYNOS4_GPE1 (3 ), + .gpio =EXYNOS4210_GPE1 (3 ), .enable_high = true, .init_data = &mmc0_fixed_voltage_init_data, };
@@ -876,7 +876,7 @@ static struct regulator_init_data cam_vt_dio_reg_init_data = {static struct fixed_voltage_config cam_vt_dio_fixed_voltage_cfg = { .supply_name ="CAM_VT_D_IO" , .microvolts =2800000 , - .gpio =EXYNOS4_GPE2 (1 ),/* CAM_PWR_EN2 */ + .gpio =EXYNOS4210_GPE2 (1 ),/* CAM_PWR_EN2 */ .enable_high =1 , .init_data = &cam_vt_dio_reg_init_data, };
@@ -898,7 +898,7 @@ static struct regulator_init_data cam_i_core_reg_init_data = {static struct fixed_voltage_config cam_i_core_fixed_voltage_cfg = { .supply_name ="CAM_I_CORE_1.2V" , .microvolts =1200000 , - .gpio =EXYNOS4_GPE2 (2 ),/* CAM_8M_CORE_EN */ + .gpio =EXYNOS4210_GPE2 (2 ),/* CAM_8M_CORE_EN */ .enable_high =1 , .init_data = &cam_i_core_reg_init_data, };
@@ -920,7 +920,7 @@ static struct regulator_init_data cam_s_if_reg_init_data = {static struct fixed_voltage_config cam_s_if_fixed_voltage_cfg = { .supply_name ="CAM_S_IF_1.8V" , .microvolts =1800000 , - .gpio =EXYNOS4_GPE3 (0 ),/* CAM_PWR_EN1 */ + .gpio =EXYNOS4210_GPE3 (0 ),/* CAM_PWR_EN1 */ .enable_high =1 , .init_data = &cam_s_if_reg_init_data, };
@@ -938,11 +938,11 @@ static struct s5p_platform_mipi_csis mipi_csis_platdata = { .phy_enable = s5p_csis_phy_enable, }; -#define GPIO_CAM_LEVEL_EN (n) EXYNOS4_GPE4(n + 3) +#define GPIO_CAM_LEVEL_EN (n) EXYNOS4210_GPE4(n + 3)#define GPIO_CAM_8M_ISP_INT EXYNOS4_GPX1(5)/* XEINT_13 */ -#define GPIO_CAM_MEGA_nRST EXYNOS4_GPE2(5) -#define GPIO_CAM_VGA_NRST EXYNOS4_GPE4(7) -#define GPIO_CAM_VGA_NSTBY EXYNOS4_GPE4(6) +#define GPIO_CAM_MEGA_nRST EXYNOS4210_GPE2(5) +#define GPIO_CAM_VGA_NRST EXYNOS4210_GPE4(7) +#define GPIO_CAM_VGA_NSTBY EXYNOS4210_GPE4(6)static int s5k6aa_set_power (int on) {
arch/arm/mach-exynos/setup-fimc.c +2 -2
@@ -26,8 +26,8 @@ int exynos4_fimc_setup_gpio(enum s5p_camport_id id)break ;case S5P_CAMPORT_B : - gpio8 =EXYNOS4_GPE0 (0 );/* DATA[0:7] */ - gpio5 =EXYNOS4_GPE1 (0 );/* PCLK, VSYNC, HREF, CLKOUT, FIELD */ + gpio8 =EXYNOS4210_GPE0 (0 );/* DATA[0:7] */ + gpio5 =EXYNOS4210_GPE1 (0 );/* PCLK, VSYNC, HREF, CLKOUT, FIELD */ sfn =S3C_GPIO_SFN (3 );break ;
drivers/gpio/gpio-samsung.c +10 -10
@@ -2171,32 +2171,32 @@ static struct samsung_gpio_chip exynos4_gpios_1[] = { }, }, { .chip = { - .base = EXYNOS4_GPE0(0), - .ngpio = EXYNOS4_GPIO_E0_NR, + .base = EXYNOS4210_GPE0(0), + .ngpio = EXYNOS4210_GPIO_E0_NR, .label = "GPE0", }, }, { .chip = { - .base = EXYNOS4_GPE1(0), - .ngpio = EXYNOS4_GPIO_E1_NR, + .base = EXYNOS4210_GPE1(0), + .ngpio = EXYNOS4210_GPIO_E1_NR, .label = "GPE1", }, }, { .chip = { - .base = EXYNOS4_GPE2(0), - .ngpio = EXYNOS4_GPIO_E2_NR, + .base = EXYNOS4210_GPE2(0), + .ngpio = EXYNOS4210_GPIO_E2_NR, .label = "GPE2", }, }, { .chip = { - .base = EXYNOS4_GPE3(0), - .ngpio = EXYNOS4_GPIO_E3_NR, + .base = EXYNOS4210_GPE3(0), + .ngpio = EXYNOS4210_GPIO_E3_NR, .label = "GPE3", }, }, { .chip = { - .base = EXYNOS4_GPE4(0), - .ngpio = EXYNOS4_GPIO_E4_NR, + .base = EXYNOS4210_GPE4(0), + .ngpio = EXYNOS4210_GPIO_E4_NR, .label = "GPE4", }, }, {
Signature · 1 line
1.7.5.4
PATCH 1/2 ARM: EXYYNOS: Use EXYNOS4210_GPEx instead of EXYNOS4_GPEx
Add to cc Grant Likely and Linus Walleij
Quoted 346 lines · Joonyoung Shim
Also use
EXYNOS4210_GPIO_Exinstead ofEXYNOS4_GPIO_Ex. The GPEx gpios exist only on Exynos4210 and there are no on Exynos4x12. Redefine them to exact SoC name.Signed-off-by Joonyoung Shim<[email protected]>Signed-off-by Kyungmin Park<[email protected]>--- arch/arm/mach-exynos/include/mach/gpio.h | 32 ++++++++++++++-------------- arch/arm/mach-exynos/mach-nuri.c | 16 +++++++------- arch/arm/mach-exynos/mach-origen.c | 6 ++-- arch/arm/mach-exynos/mach-universal_c210.c | 32 ++++++++++++++-------------- arch/arm/mach-exynos/setup-fimc.c | 4 +- drivers/gpio/gpio-samsung.c | 20 ++++++++-------- 6 files changed, 55 insertions(+), 55 deletions(-)arch/arm/mach-exynos/include/mach/gpio.h +16
-16@@ -26,11 +26,11 @@#define EXYNOS4_GPIO_C1_NR (5)#define EXYNOS4_GPIO_D0_NR (4)#define EXYNOS4_GPIO_D1_NR (4) -#define EXYNOS4_GPIO_E0_NR (5) -#define EXYNOS4_GPIO_E1_NR (8) -#define EXYNOS4_GPIO_E2_NR (6) -#define EXYNOS4_GPIO_E3_NR (8) -#define EXYNOS4_GPIO_E4_NR (8) +#define EXYNOS4210_GPIO_E0_NR (5) +#define EXYNOS4210_GPIO_E1_NR (8) +#define EXYNOS4210_GPIO_E2_NR (6) +#define EXYNOS4210_GPIO_E3_NR (8) +#define EXYNOS4210_GPIO_E4_NR (8)#define EXYNOS4_GPIO_F0_NR (8)#define EXYNOS4_GPIO_F1_NR (8)#define EXYNOS4_GPIO_F2_NR (8)@@ -67,12 +67,12 @@ enum exynos4_gpio_number {EXYNOS4_GPIO_C1_START =EXYNOS_GPIO_NEXT (EXYNOS4_GPIO_C0 ),EXYNOS4_GPIO_D0_START =EXYNOS_GPIO_NEXT (EXYNOS4_GPIO_C1 ),EXYNOS4_GPIO_D1_START =EXYNOS_GPIO_NEXT (EXYNOS4_GPIO_D0 ), -EXYNOS4_GPIO_E0_START =EXYNOS_GPIO_NEXT (EXYNOS4_GPIO_D1 ), -EXYNOS4_GPIO_E1_START =EXYNOS_GPIO_NEXT (EXYNOS4_GPIO_E0 ), -EXYNOS4_GPIO_E2_START =EXYNOS_GPIO_NEXT (EXYNOS4_GPIO_E1 ), -EXYNOS4_GPIO_E3_START =EXYNOS_GPIO_NEXT (EXYNOS4_GPIO_E2 ), -EXYNOS4_GPIO_E4_START =EXYNOS_GPIO_NEXT (EXYNOS4_GPIO_E3 ), -EXYNOS4_GPIO_F0_START =EXYNOS_GPIO_NEXT (EXYNOS4_GPIO_E4 ), +EXYNOS4210_GPIO_E0_START =EXYNOS_GPIO_NEXT (EXYNOS4_GPIO_D1 ), +EXYNOS4210_GPIO_E1_START =EXYNOS_GPIO_NEXT (EXYNOS4210_GPIO_E0 ), +EXYNOS4210_GPIO_E2_START =EXYNOS_GPIO_NEXT (EXYNOS4210_GPIO_E1 ), +EXYNOS4210_GPIO_E3_START =EXYNOS_GPIO_NEXT (EXYNOS4210_GPIO_E2 ), +EXYNOS4210_GPIO_E4_START =EXYNOS_GPIO_NEXT (EXYNOS4210_GPIO_E3 ), +EXYNOS4_GPIO_F0_START =EXYNOS_GPIO_NEXT (EXYNOS4210_GPIO_E4 ),EXYNOS4_GPIO_F1_START =EXYNOS_GPIO_NEXT (EXYNOS4_GPIO_F0 ),EXYNOS4_GPIO_F2_START =EXYNOS_GPIO_NEXT (EXYNOS4_GPIO_F1 ), EXYNOS4_GPIO_F3_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_F2),@@ -108,11 +108,11 @@ enum exynos4_gpio_number {#define EXYNOS4_GPC1 (_nr) (EXYNOS4_GPIO_C1_START + (_nr))#define EXYNOS4_GPD0 (_nr) (EXYNOS4_GPIO_D0_START + (_nr))#define EXYNOS4_GPD1 (_nr) (EXYNOS4_GPIO_D1_START + (_nr)) -#define EXYNOS4_GPE0 (_nr) (EXYNOS4_GPIO_E0_START + (_nr)) -#define EXYNOS4_GPE1 (_nr) (EXYNOS4_GPIO_E1_START + (_nr)) -#define EXYNOS4_GPE2 (_nr) (EXYNOS4_GPIO_E2_START + (_nr)) -#define EXYNOS4_GPE3 (_nr) (EXYNOS4_GPIO_E3_START + (_nr)) -#define EXYNOS4_GPE4 (_nr) (EXYNOS4_GPIO_E4_START + (_nr)) +#define EXYNOS4210_GPE0 (_nr) (EXYNOS4210_GPIO_E0_START + (_nr)) +#define EXYNOS4210_GPE1 (_nr) (EXYNOS4210_GPIO_E1_START + (_nr)) +#define EXYNOS4210_GPE2 (_nr) (EXYNOS4210_GPIO_E2_START + (_nr)) +#define EXYNOS4210_GPE3 (_nr) (EXYNOS4210_GPIO_E3_START + (_nr)) +#define EXYNOS4210_GPE4 (_nr) (EXYNOS4210_GPIO_E4_START + (_nr))#define EXYNOS4_GPF0 (_nr) (EXYNOS4_GPIO_F0_START + (_nr))#define EXYNOS4_GPF1 (_nr) (EXYNOS4_GPIO_F1_START + (_nr))#define EXYNOS4_GPF2 (_nr) (EXYNOS4_GPIO_F2_START + (_nr))arch/arm/mach-exynos/mach-nuri.c +8
-8@@ -264,7 +264,7 @@ static struct s3c_fb_platdata nuri_fb_pdata __initdata = {static void nuri_lcd_power_on (struct plat_lcd_data *pd,unsigned int power) { -int gpio =EXYNOS4_GPE1 (5 ); +int gpio =EXYNOS4210_GPE1 (5 );gpio_request (gpio,"LVDS_nSHDN" );gpio_direction_output (gpio, power);@@ -273,7 +273,7 @@ static void nuri_lcd_power_on(struct plat_lcd_data *pd, unsigned int power)static int nuri_bl_init (struct device *dev) { -return gpio_request_one (EXYNOS4_GPE2 (3 ),GPIOF_OUT_INIT_LOW , +return gpio_request_one (EXYNOS4210_GPE2 (3 ),GPIOF_OUT_INIT_LOW ,"LCD_LD0_EN" ); }@@ -282,14 +282,14 @@ static int nuri_bl_notify(struct device *dev, int brightness)if (brightness<1 ) brightness =0 ; -gpio_set_value (EXYNOS4_GPE2 (3 ),1 ); +gpio_set_value (EXYNOS4210_GPE2 (3 ),1 );return brightness; }static void nuri_bl_exit (struct device *dev) { -gpio_free (EXYNOS4_GPE2 (3 )); +gpio_free (EXYNOS4210_GPE2 (3 )); }/* nuri pwm backlight */ @@ -1042,7 +1042,7 @@ static struct max8903_pdata nuri_max8903 = {*/ .dok = EXYNOS4_GPX1(4), /* TA_nCONNECTED *//* uok, usus: not connected */ - .chg = EXYNOS4_GPE2(0), /* TA_nCHG */ + .chg = EXYNOS4210_GPE2(0), /* TA_nCHG *//* flt: vcc_1.8V_pda */ .dcm = EXYNOS4_GPL0(1), /* CURR_ADJ */@@ -1114,7 +1114,7 @@ static struct regulator_init_data cam_vt_cam15_reg_init_data = {static struct fixed_voltage_config cam_vt_cam15_fixed_voltage_cfg = { .supply_name ="VT_CAM_1.5V" , .microvolts =1500000 , - .gpio =EXYNOS4_GPE2 (2 ),/* VT_CAM_1.5V_EN */ + .gpio =EXYNOS4210_GPE2 (2 ),/* VT_CAM_1.5V_EN */ .enable_high =1 , .init_data =&cam_vt_cam15_reg_init_data, };@@ -1138,7 +1138,7 @@ static struct regulator_init_data cam_vdda_reg_init_data = {static struct fixed_voltage_config cam_vdda_fixed_voltage_cfg = { .supply_name ="CAM_IO_EN" , .microvolts =2800000 , - .gpio =EXYNOS4_GPE2 (1 ),/* CAM_IO_EN */ + .gpio =EXYNOS4210_GPE2 (1 ),/* CAM_IO_EN */ .enable_high =1 , .init_data =&cam_vdda_reg_init_data, };@@ -1162,7 +1162,7 @@ static struct regulator_init_data cam_8m_12v_reg_init_data = {static struct fixed_voltage_config cam_8m_12v_fixed_voltage_cfg = { .supply_name ="8M_1.2V" , .microvolts =1200000 , - .gpio =EXYNOS4_GPE2 (5 ),/* 8M_1.2V_EN */ + .gpio =EXYNOS4210_GPE2 (5 ),/* 8M_1.2V_EN */ .enable_high =1 , .init_data =&cam_8m_12v_reg_init_data, };arch/arm/mach-exynos/mach-origen.c +3
-3@@ -560,13 +560,13 @@ static void lcd_hv070wsa_set_power(struct plat_lcd_data *pd, unsigned int power)int ret;if (power) - ret =gpio_request_one (EXYNOS4_GPE3 (4 ), + ret =gpio_request_one (EXYNOS4210_GPE3 (4 ),GPIOF_OUT_INIT_HIGH ,"GPE3_4" );else - ret =gpio_request_one (EXYNOS4_GPE3 (4 ), + ret =gpio_request_one (EXYNOS4210_GPE3 (4 ),GPIOF_OUT_INIT_LOW ,"GPE3_4" ); -gpio_free (EXYNOS4_GPE3 (4 )); +gpio_free (EXYNOS4210_GPE3 (4 ));if (ret)pr_err ("failed to request gpio for LCD power: %d\n" , ret);arch/arm/mach-exynos/mach-universal_c210.c +16
-16@@ -545,7 +545,7 @@ static struct max8998_platform_data universal_lp3974_pdata = { .buck2_voltage1 = 1200000, /* G3D */ .buck2_voltage2 = 1100000, .buck1_default_idx = 0, - .buck2_set3 = EXYNOS4_GPE2(0), + .buck2_set3 = EXYNOS4210_GPE2(0), .buck2_default_idx = 0, .wakeup = true, };@@ -574,7 +574,7 @@ static struct regulator_init_data hdmi_fixed_voltage_init_data = {static struct fixed_voltage_config hdmi_fixed_voltage_config = { .supply_name ="HDMI_EN1" , .microvolts =5000000 , - .gpio =EXYNOS4_GPE0 (1 ), + .gpio =EXYNOS4210_GPE0 (1 ), .enable_high = true, .init_data =&hdmi_fixed_voltage_init_data, };@@ -623,12 +623,12 @@ static void __init universal_tsp_init(void)int gpio;/* TSP_LDO_ON: XMDMADDR_11 */ - gpio =EXYNOS4_GPE2 (3 ); + gpio =EXYNOS4210_GPE2 (3 );gpio_request_one (gpio,GPIOF_OUT_INIT_HIGH ,"TSP_LDO_ON" );gpio_export (gpio,0 );/* TSP_INT: XMDMADDR_7 */ - gpio =EXYNOS4_GPE1 (7 ); + gpio =EXYNOS4210_GPE1 (7 );gpio_request (gpio,"TSP_INT" );s5p_register_gpio_interrupt (gpio);@@ -654,8 +654,8 @@ static struct mcs_platform_data touchkey_data = {/* GPIO I2C 3_TOUCH 2.8V */ #define I2C_GPIO_BUS_12 12static struct i2c_gpio_platform_data i2c_gpio12_data = { - .sda_pin =EXYNOS4_GPE4 (0 ),/* XMDMDATA_8 */ - .scl_pin =EXYNOS4_GPE4 (1 ),/* XMDMDATA_9 */ + .sda_pin =EXYNOS4210_GPE4 (0 ),/* XMDMDATA_8 */ + .scl_pin =EXYNOS4210_GPE4 (1 ),/* XMDMDATA_9 */ };static struct platform_device i2c_gpio12 = {@@ -677,13 +677,13 @@ static void __init universal_touchkey_init(void) {int gpio; - gpio =EXYNOS4_GPE3 (7 );/* XMDMDATA_7 */ + gpio =EXYNOS4210_GPE3 (7 );/* XMDMDATA_7 */ gpio_request (gpio,"3_TOUCH_INT" );s5p_register_gpio_interrupt (gpio);s3c_gpio_cfgpin (gpio,S3C_GPIO_SFN (0xf )); i2c_gpio12_devs[0 ].irq =gpio_to_irq (gpio); - gpio =EXYNOS4_GPE3 (3 );/* XMDMDATA_3 */ + gpio =EXYNOS4210_GPE3 (3 );/* XMDMDATA_3 */ gpio_request_one (gpio,GPIOF_OUT_INIT_HIGH ,"3_TOUCH_EN" ); }@@ -769,7 +769,7 @@ static struct regulator_init_data mmc0_fixed_voltage_init_data = {static struct fixed_voltage_config mmc0_fixed_voltage_config = { .supply_name ="MASSMEMORY_EN" , .microvolts =2800000 , - .gpio =EXYNOS4_GPE1 (3 ), + .gpio =EXYNOS4210_GPE1 (3 ), .enable_high = true, .init_data =&mmc0_fixed_voltage_init_data, };@@ -876,7 +876,7 @@ static struct regulator_init_data cam_vt_dio_reg_init_data = {static struct fixed_voltage_config cam_vt_dio_fixed_voltage_cfg = { .supply_name ="CAM_VT_D_IO" , .microvolts =2800000 , - .gpio =EXYNOS4_GPE2 (1 ),/* CAM_PWR_EN2 */ + .gpio =EXYNOS4210_GPE2 (1 ),/* CAM_PWR_EN2 */ .enable_high =1 , .init_data =&cam_vt_dio_reg_init_data, };@@ -898,7 +898,7 @@ static struct regulator_init_data cam_i_core_reg_init_data = {static struct fixed_voltage_config cam_i_core_fixed_voltage_cfg = { .supply_name ="CAM_I_CORE_1.2V" , .microvolts =1200000 , - .gpio =EXYNOS4_GPE2 (2 ),/* CAM_8M_CORE_EN */ + .gpio =EXYNOS4210_GPE2 (2 ),/* CAM_8M_CORE_EN */ .enable_high =1 , .init_data =&cam_i_core_reg_init_data, };@@ -920,7 +920,7 @@ static struct regulator_init_data cam_s_if_reg_init_data = {static struct fixed_voltage_config cam_s_if_fixed_voltage_cfg = { .supply_name ="CAM_S_IF_1.8V" , .microvolts =1800000 , - .gpio =EXYNOS4_GPE3 (0 ),/* CAM_PWR_EN1 */ + .gpio =EXYNOS4210_GPE3 (0 ),/* CAM_PWR_EN1 */ .enable_high =1 , .init_data =&cam_s_if_reg_init_data, };@@ -938,11 +938,11 @@ static struct s5p_platform_mipi_csis mipi_csis_platdata = { .phy_enable = s5p_csis_phy_enable, }; -#define GPIO_CAM_LEVEL_EN (n) EXYNOS4_GPE4(n + 3) +#define GPIO_CAM_LEVEL_EN (n) EXYNOS4210_GPE4(n + 3)#define GPIO_CAM_8M_ISP_INT EXYNOS4_GPX1(5)/* XEINT_13 */ -#define GPIO_CAM_MEGA_nRST EXYNOS4_GPE2(5) -#define GPIO_CAM_VGA_NRST EXYNOS4_GPE4(7) -#define GPIO_CAM_VGA_NSTBY EXYNOS4_GPE4(6) +#define GPIO_CAM_MEGA_nRST EXYNOS4210_GPE2(5) +#define GPIO_CAM_VGA_NRST EXYNOS4210_GPE4(7) +#define GPIO_CAM_VGA_NSTBY EXYNOS4210_GPE4(6)static int s5k6aa_set_power (int on) {arch/arm/mach-exynos/setup-fimc.c +2
-2@@ -26,8 +26,8 @@ int exynos4_fimc_setup_gpio(enum s5p_camport_id id)break ;case S5P_CAMPORT_B : - gpio8 =EXYNOS4_GPE0 (0 );/* DATA[0:7] */ - gpio5 =EXYNOS4_GPE1 (0 );/* PCLK, VSYNC, HREF, CLKOUT, FIELD */ + gpio8 =EXYNOS4210_GPE0 (0 );/* DATA[0:7] */ + gpio5 =EXYNOS4210_GPE1 (0 );/* PCLK, VSYNC, HREF, CLKOUT, FIELD */ sfn =S3C_GPIO_SFN (3 );break ;drivers/gpio/gpio-samsung.c +10
-10@@ -2171,32 +2171,32 @@ static struct samsung_gpio_chip exynos4_gpios_1[] = { }, }, { .chip = { - .base = EXYNOS4_GPE0(0), - .ngpio = EXYNOS4_GPIO_E0_NR, + .base = EXYNOS4210_GPE0(0), + .ngpio = EXYNOS4210_GPIO_E0_NR, .label = "GPE0", }, }, { .chip = { - .base = EXYNOS4_GPE1(0), - .ngpio = EXYNOS4_GPIO_E1_NR, + .base = EXYNOS4210_GPE1(0), + .ngpio = EXYNOS4210_GPIO_E1_NR, .label = "GPE1", }, }, { .chip = { - .base = EXYNOS4_GPE2(0), - .ngpio = EXYNOS4_GPIO_E2_NR, + .base = EXYNOS4210_GPE2(0), + .ngpio = EXYNOS4210_GPIO_E2_NR, .label = "GPE2", }, }, { .chip = { - .base = EXYNOS4_GPE3(0), - .ngpio = EXYNOS4_GPIO_E3_NR, + .base = EXYNOS4210_GPE3(0), + .ngpio = EXYNOS4210_GPIO_E3_NR, .label = "GPE3", }, }, { .chip = { - .base = EXYNOS4_GPE4(0), - .ngpio = EXYNOS4_GPIO_E4_NR, + .base = EXYNOS4210_GPE4(0), + .ngpio = EXYNOS4210_GPIO_E4_NR, .label = "GPE4", }, }, {
PATCH 1/2 ARM: EXYYNOS: Use EXYNOS4210_GPEx instead of EXYNOS4_GPEx
Quoted 9 lines · Joonyoung Shim
Add to cc Grant Likely and Linus Walleij
Quoted 6 lines · Joonyoung Shim
Also use
EXYNOS4210_GPIO_Exinstead ofEXYNOS4_GPIO_Ex. The GPEx gpios exist only on Exynos4210 and there are no on Exynos4x12. Redefine them to exact SoC name.Signed-off-by Joonyoung Shim<[email protected]>Signed-off-by Kyungmin Park<[email protected]>
Reviewed-by Sylwester Nawrocki <[email protected]>
Tested-by Sylwester Nawrocki <[email protected]>
PATCH 1/2 ARM: EXYYNOS: Use EXYNOS4210_GPEx instead of EXYNOS4_GPEx
In reply to Joonyoung ShimQuoted 9 lines · Joonyoung Shim
Add to cc Grant Likely and Linus Walleij
Quoted 6 lines · Joonyoung Shim
Also use
EXYNOS4210_GPIO_Exinstead ofEXYNOS4_GPIO_Ex. The GPEx gpios exist only on Exynos4210 and there are no on Exynos4x12. Redefine them to exact SoC name.Signed-off-by Joonyoung Shim<[email protected]>Signed-off-by Kyungmin Park<[email protected]>
Nit: there is a typo in the patch summary line:
s/EXYYNOS/EXYNOS
--
Regards,
Sylwester
PATCH 1/2 ARM: EXYYNOS: Use EXYNOS4210_GPEx instead of EXYNOS4_GPEx
In reply to Joonyoung ShimQuoted 12 lines · Joonyoung Shim
Add to cc Grant Likely and Linus Walleij
Quoted 8 lines · Joonyoung Shim
Also use
EXYNOS4210_GPIO_Exinstead ofEXYNOS4_GPIO_Ex. The GPEx gpios exist only on Exynos4210 and there are no on Exynos4x12. Redefine them to exact SoC name.Signed-off-by Joonyoung Shim<[email protected]>Signed-off-by Kyungmin Park<[email protected]>--- arch/arm/mach-exynos/include/mach/gpio.h | 32
++++++++++++++--------
Quoted 4 lines
------
Quoted 3 lines
arch/arm/mach-exynos/mach-nuri.c | 16 +++++++------- arch/arm/mach-exynos/mach-origen.c | 6 ++-- arch/arm/mach-exynos/mach-universal_c210.c | 32
++++++++++++++-------
Quoted 16 lines
-------
arch/arm/mach-
Quoted 5 lines
arch/arm/mach-exynos/setup-fimc.c | 4 +- drivers/gpio/gpio-samsung.c | 20 ++++++++-------- 6 files changed, 55 insertions(+), 55 deletions(-)arch/arm/mach- renamed from arch/arm/mach-exynos/include/mach/gpio.h +0
-0
exynos/include/mach/gpio.hQuoted 9 lines
index eb24f1e..21c9bf1 100644
arch/arm/mach-exynos/include/mach/gpio.h +0
-2@@ -26,11 +26,11 @@#define EXYNOS4_GPIO_C1_NR (5)#define EXYNOS4_GPIO_D0_NR (4)#define EXYNOS4_GPIO_D1_NR (4) -#define EXYNOS4_GPIO_E0_NR (5) -#define EXYNOS4_GPIO_E1_NR (8)
Quoted 8 lines
arch/arm/mach-exynos/include/mach/gpio.h line 33
Quoted 8 lines
arch/arm/mach-exynos/include/mach/gpio.h +5
-3-#define EXYNOS4_GPIO_E2_NR (6) -#define EXYNOS4_GPIO_E3_NR (8) -#define EXYNOS4_GPIO_E4_NR (8) +#define EXYNOS4210_GPIO_E0_NR (5) +#define EXYNOS4210_GPIO_E1_NR (8) +#define EXYNOS4210_GPIO_E2_NR (6) +#define EXYNOS4210_GPIO_E3_NR (8) +#define EXYNOS4210_GPIO_E4_NR (8)
I think, splitting the gpios like following(common exynos4 and exynos4210 or exynos4x12). So please just put the definitions for EXYNOS4210 GPIO after EXYNOS4_GPIO_XXX.
(quoted diff) +0 -0
b/arch/arm/mach-exynos/include/mach/gpio.h
index eb24f1e..910b611 100644
arch/arm/mach-exynos/include/mach/gpio.h +9 -7
@@ -26,17 +26,10 @@#define EXYNOS4_GPIO_C1_NR (5)#define EXYNOS4_GPIO_D0_NR (4)#define EXYNOS4_GPIO_D1_NR (4) -#define EXYNOS4_GPIO_E0_NR (5) -#define EXYNOS4_GPIO_E1_NR (8) -#define EXYNOS4_GPIO_E2_NR (6) -#define EXYNOS4_GPIO_E3_NR (8) -#define EXYNOS4_GPIO_E4_NR (8)#define EXYNOS4_GPIO_F0_NR (8)#define EXYNOS4_GPIO_F1_NR (8)#define EXYNOS4_GPIO_F2_NR (8)#define EXYNOS4_GPIO_F3_NR (6) -#define EXYNOS4_GPIO_J0_NR (8) -#define EXYNOS4_GPIO_J1_NR (5)#define EXYNOS4_GPIO_K0_NR (7)#define EXYNOS4_GPIO_K1_NR (7)#define EXYNOS4_GPIO_K2_NR (7)
@@ -57,6 +50,31 @@#define EXYNOS4_GPIO_Y6_NR (8)#define EXYNOS4_GPIO_Z_NR (7) +/* For EXYNOS4210 GPIO bank sizes */ + +#define EXYNOS4210_GPIO_E0_NR (5) +#define EXYNOS4210_GPIO_E1_NR (8) +#define EXYNOS4210_GPIO_E2_NR (6) +#define EXYNOS4210_GPIO_E3_NR (8) +#define EXYNOS4210_GPIO_E4_NR (8) +#define EXYNOS4210_GPIO_J0_NR (8) +#define EXYNOS4210_GPIO_J1_NR (5)
[...]
And we can add EXYNOS4X12 GPIO like following in other patch.
+/* For EXYNOS4X12 GPIO bank sizes */
+
+#define EXYNOS4X12_GPIO_J0_NR (8)
+#define EXYNOS4X12_GPIO_J1_NR (5)
+#define EXYNOS4X12_GPIO_M0_NR (8)
+#define EXYNOS4X12_GPIO_M1_NR (7)
+#define EXYNOS4X12_GPIO_M2_NR (5)
+#define EXYNOS4X12_GPIO_M3_NR (8)
+#define EXYNOS4X12_GPIO_M4_NR (8)
+#define EXYNOS4X12_GPIO_V0_NR (8)
+#define EXYNOS4X12_GPIO_V1_NR (8)
+#define EXYNOS4X12_GPIO_V2_NR (8)
+#define EXYNOS4X12_GPIO_V3_NR (8)
+#define EXYNOS4X12_GPIO_V4_NR (2)
Quoted 7 lines
Quoted 7 lines
arch/arm/mach-exynos/include/mach/gpio.h +0
-0#define EXYNOS4_GPIO_F0_NR (8)#define EXYNOS4_GPIO_F1_NR (8)#define EXYNOS4_GPIO_F2_NR (8)@@ -67,12 +67,12 @@ enum exynos4_gpio_number {EXYNOS4_GPIO_C1_START =EXYNOS_GPIO_NEXT (EXYNOS4_GPIO_C0 ),EXYNOS4_GPIO_D0_START =EXYNOS_GPIO_NEXT (EXYNOS4_GPIO_C1 ), EXYNOS4_GPIO_D1_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_D0),
Quoted 8 lines
arch/arm/mach-exynos/include/mach/gpio.h enum exynos4_gpio_number { · line 71
Quoted 8 lines
arch/arm/mach-exynos/include/mach/gpio.h +2
-6-EXYNOS4_GPIO_E0_START =EXYNOS_GPIO_NEXT (EXYNOS4_GPIO_D1 ), -EXYNOS4_GPIO_E1_START =EXYNOS_GPIO_NEXT (EXYNOS4_GPIO_E0 ), -EXYNOS4_GPIO_E2_START =EXYNOS_GPIO_NEXT (EXYNOS4_GPIO_E1 ), -EXYNOS4_GPIO_E3_START =EXYNOS_GPIO_NEXT (EXYNOS4_GPIO_E2 ), -EXYNOS4_GPIO_E4_START =EXYNOS_GPIO_NEXT (EXYNOS4_GPIO_E3 ), - EXYNOS4_GPIO_F0_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_E4), +EXYNOS4210_GPIO_E0_START =EXYNOS_GPIO_NEXT (EXYNOS4_GPIO_D1 ), + EXYNOS4210_GPIO_E1_START =
EXYNOS_GPIO_NEXT(EXYNOS4210_GPIO_E0),
Quoted 1 line
arch/arm/mach-exynos/include/mach/gpio.h enum exynos4_gpio_number { · line 72
Quoted 1 line
arch/arm/mach-exynos/include/mach/gpio.h +1
-0+ EXYNOS4210_GPIO_E2_START =
EXYNOS_GPIO_NEXT(EXYNOS4210_GPIO_E1),
Quoted 1 line
arch/arm/mach-exynos/include/mach/gpio.h enum exynos4_gpio_number { · line 73
Quoted 1 line
arch/arm/mach-exynos/include/mach/gpio.h +1
-0+ EXYNOS4210_GPIO_E3_START =
EXYNOS_GPIO_NEXT(EXYNOS4210_GPIO_E2),
Quoted 1 line
arch/arm/mach-exynos/include/mach/gpio.h enum exynos4_gpio_number { · line 74
Quoted 1 line
arch/arm/mach-exynos/include/mach/gpio.h +1
-0+ EXYNOS4210_GPIO_E4_START =
EXYNOS_GPIO_NEXT(EXYNOS4210_GPIO_E3),
Quoted 4 lines
arch/arm/mach-exynos/include/mach/gpio.h enum exynos4_gpio_number { · line 78
Quoted 4 lines
arch/arm/mach-exynos/include/mach/gpio.h +1
-0+EXYNOS4_GPIO_F0_START =EXYNOS_GPIO_NEXT (EXYNOS4210_GPIO_E4 ),EXYNOS4_GPIO_F1_START =EXYNOS_GPIO_NEXT (EXYNOS4_GPIO_F0 ),EXYNOS4_GPIO_F2_START =EXYNOS_GPIO_NEXT (EXYNOS4_GPIO_F1 ), EXYNOS4_GPIO_F3_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_F2),
Same as above.
@@ -99,6 +117,31 @@ enum exynos4_gpio_number {
EXYNOS4_GPIO_Z_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_Y6),
};
+enum exynos4210_gpio_number {
+ EXYNOS4210_GPIO_E0_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_Z),
+ EXYNOS4210_GPIO_E1_START =EXYNOS4_GPIO_NEXT(EXYNOS4210_GPIO_E0),
+ EXYNOS4210_GPIO_E2_START =EXYNOS4_GPIO_NEXT(EXYNOS4210_GPIO_E1),
+ EXYNOS4210_GPIO_E3_START =EXYNOS4_GPIO_NEXT(EXYNOS4210_GPIO_E2),
+ EXYNOS4210_GPIO_E4_START =EXYNOS4_GPIO_NEXT(EXYNOS4210_GPIO_E3),
+ EXYNOS4210_GPIO_J0_START =EXYNOS4_GPIO_NEXT(EXYNOS4210_GPIO_E4),
+ EXYNOS4210_GPIO_J1_START =EXYNOS4_GPIO_NEXT(EXYNOS4210_GPIO_J0),
+};
[...]
And following is possible for EXYNOS4X12...
+enum exynos4x12_gpio_number {
+ EXYNOS4X12_GPIO_J0_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_Z),
+ EXYNOS4X12_GPIO_J1_START =EXYNOS4_GPIO_NEXT(EXYNOS4X12_GPIO_J0),
+ EXYNOS4X12_GPIO_M0_START =EXYNOS4_GPIO_NEXT(EXYNOS4X12_GPIO_J1),
+ EXYNOS4X12_GPIO_M1_START =EXYNOS4_GPIO_NEXT(EXYNOS4X12_GPIO_M0),
+ EXYNOS4X12_GPIO_M2_START =EXYNOS4_GPIO_NEXT(EXYNOS4X12_GPIO_M1),
+ EXYNOS4X12_GPIO_M3_START =EXYNOS4_GPIO_NEXT(EXYNOS4X12_GPIO_M2),
+ EXYNOS4X12_GPIO_M4_START =EXYNOS4_GPIO_NEXT(EXYNOS4X12_GPIO_M3),
+ EXYNOS4X12_GPIO_V0_START =EXYNOS4_GPIO_NEXT(EXYNOS4X12_GPIO_M4),
+ EXYNOS4X12_GPIO_V1_START =EXYNOS4_GPIO_NEXT(EXYNOS4X12_GPIO_V0),
+ EXYNOS4X12_GPIO_V2_START =EXYNOS4_GPIO_NEXT(EXYNOS4X12_GPIO_V1),
+ EXYNOS4X12_GPIO_V3_START =EXYNOS4_GPIO_NEXT(EXYNOS4X12_GPIO_V2),
+ EXYNOS4X12_GPIO_V4_START =EXYNOS4_GPIO_NEXT(EXYNOS4X12_GPIO_V3),
+};
+
/* EXYNOS4 GPIO number definitions */
#define EXYNOS4_GPA0(_nr) (EXYNOS4_GPIO_A0_START + (_nr))
[...]
Of course, need to update other regarding gpio part accordingly.
Thanks.
Best regards,
Kgene.
--
Kukjin Kim <[email protected]>, Senior Engineer, SW Solution Development Team, Samsung Electronics Co., Ltd.
PATCH 1/2 ARM: EXYYNOS: Use EXYNOS4210_GPEx instead of EXYNOS4_GPEx
In reply to Joonyoung ShimQuoted 6 lines · Kukjin Kim
Quoted 4 lines · Joonyoung Shim
Add to cc Grant Likely and Linus Walleij
On 05/18/2012 11:18 AM, Joonyoung Shim wrote:
Quoted 8 lines
Quoted 8 lines
Quoted 8 lines
Also use
EXYNOS4210_GPIO_Exinstead ofEXYNOS4_GPIO_Ex. The GPEx gpios exist only on Exynos4210 and there are no on Exynos4x12. Redefine them to exact SoC name.Signed-off-by Joonyoung Shim<[email protected]>Signed-off-by Kyungmin Park<[email protected]>--- arch/arm/mach-exynos/include/mach/gpio.h | 32
++++++++++++++------
Quoted 5 lines
--
Quoted 4 lines
------
Quoted 3 lines
arch/arm/mach-exynos/mach-nuri.c | 16 +++++++------- arch/arm/mach-exynos/mach-origen.c | 6 ++-- arch/arm/mach-exynos/mach-universal_c210.c | 32
++++++++++++++-----
Quoted 86 lines
--
Quoted 16 lines
-------
arch/arm/mach-
Quoted 5 lines
arch/arm/mach-exynos/setup-fimc.c | 4 +- drivers/gpio/gpio-samsung.c | 20 ++++++++-------- 6 files changed, 55 insertions(+), 55 deletions(-)arch/arm/mach- renamed from arch/arm/mach-exynos/include/mach/gpio.h +0
-0
exynos/include/mach/gpio.hQuoted 9 lines
index eb24f1e..21c9bf1 100644
arch/arm/mach-exynos/include/mach/gpio.h +0
-2@@ -26,11 +26,11 @@#define EXYNOS4_GPIO_C1_NR (5)#define EXYNOS4_GPIO_D0_NR (4)#define EXYNOS4_GPIO_D1_NR (4) -#define EXYNOS4_GPIO_E0_NR (5) -#define EXYNOS4_GPIO_E1_NR (8)Quoted 8 lines
arch/arm/mach-exynos/include/mach/gpio.h line 33
Quoted 8 lines
arch/arm/mach-exynos/include/mach/gpio.h +5
-3-#define EXYNOS4_GPIO_E2_NR (6) -#define EXYNOS4_GPIO_E3_NR (8) -#define EXYNOS4_GPIO_E4_NR (8) +#define EXYNOS4210_GPIO_E0_NR (5) +#define EXYNOS4210_GPIO_E1_NR (8) +#define EXYNOS4210_GPIO_E2_NR (6) +#define EXYNOS4210_GPIO_E3_NR (8) +#define EXYNOS4210_GPIO_E4_NR (8)I think, splitting the gpios like following(common exynos4 and exynos4210 or exynos4x12). So please just put the definitions for EXYNOS4210 GPIO after
EXYNOS4_GPIO_XXX.arch/arm/mach- renamed from arch/arm/mach-exynos/include/mach/gpio.h +0
-0
exynos/include/mach/gpio.h
index eb24f1e..910b611 100644arch/arm/mach-exynos/include/mach/gpio.h +9
-7@@ -26,17 +26,10 @@#define EXYNOS4_GPIO_C1_NR (5)#define EXYNOS4_GPIO_D0_NR (4)#define EXYNOS4_GPIO_D1_NR (4) -#define EXYNOS4_GPIO_E0_NR (5) -#define EXYNOS4_GPIO_E1_NR (8) -#define EXYNOS4_GPIO_E2_NR (6) -#define EXYNOS4_GPIO_E3_NR (8) -#define EXYNOS4_GPIO_E4_NR (8)#define EXYNOS4_GPIO_F0_NR (8)#define EXYNOS4_GPIO_F1_NR (8)#define EXYNOS4_GPIO_F2_NR (8)#define EXYNOS4_GPIO_F3_NR (6) -#define EXYNOS4_GPIO_J0_NR (8) -#define EXYNOS4_GPIO_J1_NR (5)#define EXYNOS4_GPIO_K0_NR (7)#define EXYNOS4_GPIO_K1_NR (7)#define EXYNOS4_GPIO_K2_NR (7)@@ -57,6 +50,31 @@#define EXYNOS4_GPIO_Y6_NR (8)#define EXYNOS4_GPIO_Z_NR (7) +/* For EXYNOS4210 GPIO bank sizes */ + +#define EXYNOS4210_GPIO_E0_NR (5) +#define EXYNOS4210_GPIO_E1_NR (8) +#define EXYNOS4210_GPIO_E2_NR (6) +#define EXYNOS4210_GPIO_E3_NR (8) +#define EXYNOS4210_GPIO_E4_NR (8) +#define EXYNOS4210_GPIO_J0_NR (8) +#define EXYNOS4210_GPIO_J1_NR (5)And we can add EXYNOS4X12 GPIO like following in other patch.
arch/arm/mach-exynos/include/mach/gpio.h +14
-0+/* For EXYNOS4X12 GPIO bank sizes */ + +#define EXYNOS4X12_GPIO_J0_NR (8) +#define EXYNOS4X12_GPIO_J1_NR (5) +#define EXYNOS4X12_GPIO_M0_NR (8) +#define EXYNOS4X12_GPIO_M1_NR (7) +#define EXYNOS4X12_GPIO_M2_NR (5) +#define EXYNOS4X12_GPIO_M3_NR (8) +#define EXYNOS4X12_GPIO_M4_NR (8) +#define EXYNOS4X12_GPIO_V0_NR (8) +#define EXYNOS4X12_GPIO_V1_NR (8) +#define EXYNOS4X12_GPIO_V2_NR (8) +#define EXYNOS4X12_GPIO_V3_NR (8) +#define EXYNOS4X12_GPIO_V4_NR (2)
Quoted 15 lines
Quoted 7 lines
Quoted 7 lines
arch/arm/mach-exynos/include/mach/gpio.h +0
-0#define EXYNOS4_GPIO_F0_NR (8)#define EXYNOS4_GPIO_F1_NR (8)#define EXYNOS4_GPIO_F2_NR (8)@@ -67,12 +67,12 @@ enum exynos4_gpio_number {EXYNOS4_GPIO_C1_START =EXYNOS_GPIO_NEXT (EXYNOS4_GPIO_C0 ),EXYNOS4_GPIO_D0_START =EXYNOS_GPIO_NEXT (EXYNOS4_GPIO_C1 ), EXYNOS4_GPIO_D1_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_D0),Quoted 8 lines
arch/arm/mach-exynos/include/mach/gpio.h enum exynos4_gpio_number {
Quoted 8 lines
arch/arm/mach-exynos/include/mach/gpio.h +2
-6-EXYNOS4_GPIO_E0_START =EXYNOS_GPIO_NEXT (EXYNOS4_GPIO_D1 ), -EXYNOS4_GPIO_E1_START =EXYNOS_GPIO_NEXT (EXYNOS4_GPIO_E0 ), -EXYNOS4_GPIO_E2_START =EXYNOS_GPIO_NEXT (EXYNOS4_GPIO_E1 ), -EXYNOS4_GPIO_E3_START =EXYNOS_GPIO_NEXT (EXYNOS4_GPIO_E2 ), -EXYNOS4_GPIO_E4_START =EXYNOS_GPIO_NEXT (EXYNOS4_GPIO_E3 ), - EXYNOS4_GPIO_F0_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_E4), +EXYNOS4210_GPIO_E0_START =EXYNOS_GPIO_NEXT (EXYNOS4_GPIO_D1 ), + EXYNOS4210_GPIO_E1_START =
EXYNOS_GPIO_NEXT(EXYNOS4210_GPIO_E0),
Quoted 1 line
Quoted 1 line
arch/arm/mach-exynos/include/mach/gpio.h enum exynos4_gpio_number { · line 72
Quoted 1 line
arch/arm/mach-exynos/include/mach/gpio.h +1
-0+ EXYNOS4210_GPIO_E2_START =
EXYNOS_GPIO_NEXT(EXYNOS4210_GPIO_E1),
Quoted 1 line
Quoted 1 line
arch/arm/mach-exynos/include/mach/gpio.h enum exynos4_gpio_number { · line 73
Quoted 1 line
arch/arm/mach-exynos/include/mach/gpio.h +1
-0+ EXYNOS4210_GPIO_E3_START =
EXYNOS_GPIO_NEXT(EXYNOS4210_GPIO_E2),
Quoted 1 line
Quoted 1 line
arch/arm/mach-exynos/include/mach/gpio.h enum exynos4_gpio_number { · line 74
Quoted 1 line
arch/arm/mach-exynos/include/mach/gpio.h +1
-0+ EXYNOS4210_GPIO_E4_START =
EXYNOS_GPIO_NEXT(EXYNOS4210_GPIO_E3),
Quoted 8 lines
Quoted 4 lines
arch/arm/mach-exynos/include/mach/gpio.h enum exynos4_gpio_number { · line 78
Quoted 4 lines
arch/arm/mach-exynos/include/mach/gpio.h +1
-0+EXYNOS4_GPIO_F0_START =EXYNOS_GPIO_NEXT (EXYNOS4210_GPIO_E4 ),EXYNOS4_GPIO_F1_START =EXYNOS_GPIO_NEXT (EXYNOS4_GPIO_F0 ),EXYNOS4_GPIO_F2_START =EXYNOS_GPIO_NEXT (EXYNOS4_GPIO_F1 ), EXYNOS4_GPIO_F3_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_F2),Same as above.
arch/arm/mach-exynos/include/mach/gpio.h enum exynos4_gpio_number { · line 122
Quoted 6 lines
arch/arm/mach-exynos/include/mach/gpio.h +3
-0@@ -99,6 +117,31 @@ enum exynos4_gpio_number { EXYNOS4_GPIO_Z_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_Y6), }; +enum exynos4210_gpio_number { +EXYNOS4210_GPIO_E0_START =EXYNOS4_GPIO_NEXT (EXYNOS4_GPIO_Z ), + EXYNOS4210_GPIO_E1_START =
EXYNOS4_GPIO_NEXT(EXYNOS4210_GPIO_E0),
arch/arm/mach-exynos/include/mach/gpio.h enum exynos4_gpio_number { · line 123
Quoted 1 line
arch/arm/mach-exynos/include/mach/gpio.h +1
-0+ EXYNOS4210_GPIO_E2_START =
EXYNOS4_GPIO_NEXT(EXYNOS4210_GPIO_E1),
arch/arm/mach-exynos/include/mach/gpio.h enum exynos4_gpio_number { · line 124
Quoted 1 line
arch/arm/mach-exynos/include/mach/gpio.h +1
-0+ EXYNOS4210_GPIO_E3_START =
EXYNOS4_GPIO_NEXT(EXYNOS4210_GPIO_E2),
arch/arm/mach-exynos/include/mach/gpio.h enum exynos4_gpio_number { · line 125
Quoted 1 line
arch/arm/mach-exynos/include/mach/gpio.h +1
-0+ EXYNOS4210_GPIO_E4_START =
EXYNOS4_GPIO_NEXT(EXYNOS4210_GPIO_E3),
arch/arm/mach-exynos/include/mach/gpio.h enum exynos4_gpio_number { · line 126
Quoted 1 line
arch/arm/mach-exynos/include/mach/gpio.h +1
-0+ EXYNOS4210_GPIO_J0_START =
EXYNOS4_GPIO_NEXT(EXYNOS4210_GPIO_E4),
arch/arm/mach-exynos/include/mach/gpio.h enum exynos4_gpio_number { · line 127
Quoted 1 line
arch/arm/mach-exynos/include/mach/gpio.h +1
-0+ EXYNOS4210_GPIO_J1_START =
EXYNOS4_GPIO_NEXT(EXYNOS4210_GPIO_J0),
arch/arm/mach-exynos/include/mach/gpio.h
Quoted 9 lines
arch/arm/mach-exynos/include/mach/gpio.h +1
-0+};And following is possible for EXYNOS4X12...
arch/arm/mach-exynos/include/mach/gpio.h +3
-0+enum exynos4x12_gpio_number { +EXYNOS4X12_GPIO_J0_START =EXYNOS4_GPIO_NEXT (EXYNOS4_GPIO_Z ), + EXYNOS4X12_GPIO_J1_START =
EXYNOS4_GPIO_NEXT(EXYNOS4X12_GPIO_J0),
arch/arm/mach-exynos/include/mach/gpio.h
Quoted 1 line
arch/arm/mach-exynos/include/mach/gpio.h +1
-0+ EXYNOS4X12_GPIO_M0_START =
EXYNOS4_GPIO_NEXT(EXYNOS4X12_GPIO_J1),
arch/arm/mach-exynos/include/mach/gpio.h
Quoted 1 line
arch/arm/mach-exynos/include/mach/gpio.h +1
-0+ EXYNOS4X12_GPIO_M1_START =
EXYNOS4_GPIO_NEXT(EXYNOS4X12_GPIO_M0),
arch/arm/mach-exynos/include/mach/gpio.h
Quoted 1 line
arch/arm/mach-exynos/include/mach/gpio.h +1
-0+ EXYNOS4X12_GPIO_M2_START =
EXYNOS4_GPIO_NEXT(EXYNOS4X12_GPIO_M1),
arch/arm/mach-exynos/include/mach/gpio.h
Quoted 1 line
arch/arm/mach-exynos/include/mach/gpio.h +1
-0+ EXYNOS4X12_GPIO_M3_START =
EXYNOS4_GPIO_NEXT(EXYNOS4X12_GPIO_M2),
arch/arm/mach-exynos/include/mach/gpio.h
Quoted 1 line
arch/arm/mach-exynos/include/mach/gpio.h +1
-0+ EXYNOS4X12_GPIO_M4_START =
EXYNOS4_GPIO_NEXT(EXYNOS4X12_GPIO_M3),
arch/arm/mach-exynos/include/mach/gpio.h
Quoted 1 line
arch/arm/mach-exynos/include/mach/gpio.h +1
-0+ EXYNOS4X12_GPIO_V0_START =
EXYNOS4_GPIO_NEXT(EXYNOS4X12_GPIO_M4),
arch/arm/mach-exynos/include/mach/gpio.h
Quoted 1 line
arch/arm/mach-exynos/include/mach/gpio.h +1
-0+ EXYNOS4X12_GPIO_V1_START =
EXYNOS4_GPIO_NEXT(EXYNOS4X12_GPIO_V0),
arch/arm/mach-exynos/include/mach/gpio.h
Quoted 1 line
arch/arm/mach-exynos/include/mach/gpio.h +1
-0+ EXYNOS4X12_GPIO_V2_START =
EXYNOS4_GPIO_NEXT(EXYNOS4X12_GPIO_V1),
arch/arm/mach-exynos/include/mach/gpio.h
Quoted 1 line
arch/arm/mach-exynos/include/mach/gpio.h +1
-0+ EXYNOS4X12_GPIO_V3_START =
EXYNOS4_GPIO_NEXT(EXYNOS4X12_GPIO_V2),
arch/arm/mach-exynos/include/mach/gpio.h
Quoted 1 line
arch/arm/mach-exynos/include/mach/gpio.h +1
-0+ EXYNOS4X12_GPIO_V4_START =
EXYNOS4_GPIO_NEXT(EXYNOS4X12_GPIO_V3),
Quoted 10 lines
arch/arm/mach-exynos/include/mach/gpio.h +2
-0+}; +/* EXYNOS4 GPIO number definitions */ #define EXYNOS4_GPA0 (_nr) (EXYNOS4_GPIO_A0_START + (_nr))Of course, need to update other regarding gpio part accordingly.
Joonyoung, any updates on this?
Thanks.
Best regards,
Kgene.
--
Kukjin Kim <[email protected]>, Senior Engineer, SW Solution Development Team, Samsung Electronics Co., Ltd.
PATCH 1/2 ARM: EXYYNOS: Use EXYNOS4210_GPEx instead of EXYNOS4_GPEx
Quoted 185 lines · Kukjin Kim
Quoted 4 lines · Kukjin Kim
Quoted 3 lines · Joonyoung Shim
Add to cc Grant Likely and Linus Walleij
On 05/18/2012 11:18 AM, Joonyoung Shim wrote:
Quoted 8 lines
Quoted 8 lines
Quoted 8 lines
Also use
EXYNOS4210_GPIO_Exinstead ofEXYNOS4_GPIO_Ex. The GPEx gpios exist only on Exynos4210 and there are no on Exynos4x12. Redefine them to exact SoC name.Signed-off-by Joonyoung Shim<[email protected]>Signed-off-by Kyungmin Park<[email protected]>--- arch/arm/mach-exynos/include/mach/gpio.h | 32++++++++++++++------
Quoted 5 lines
--
Quoted 4 lines
------
Quoted 3 lines
arch/arm/mach-exynos/mach-nuri.c | 16 +++++++------- arch/arm/mach-exynos/mach-origen.c | 6 ++-- arch/arm/mach-exynos/mach-universal_c210.c | 32++++++++++++++-----
Quoted 85 lines
--
Quoted 16 lines
-------
arch/arm/mach-
Quoted 5 lines
arch/arm/mach-exynos/setup-fimc.c | 4 +- drivers/gpio/gpio-samsung.c | 20 ++++++++-------- 6 files changed, 55 insertions(+), 55 deletions(-)arch/arm/mach- renamed from arch/arm/mach-exynos/include/mach/gpio.h +0
-0
exynos/include/mach/gpio.hQuoted 9 lines
index eb24f1e..21c9bf1 100644
arch/arm/mach-exynos/include/mach/gpio.h +0
-2@@ -26,11 +26,11 @@#define EXYNOS4_GPIO_C1_NR (5)#define EXYNOS4_GPIO_D0_NR (4)#define EXYNOS4_GPIO_D1_NR (4) -#define EXYNOS4_GPIO_E0_NR (5) -#define EXYNOS4_GPIO_E1_NR (8)Quoted 8 lines
arch/arm/mach-exynos/include/mach/gpio.h line 33
Quoted 8 lines
arch/arm/mach-exynos/include/mach/gpio.h +5
-3-#define EXYNOS4_GPIO_E2_NR (6) -#define EXYNOS4_GPIO_E3_NR (8) -#define EXYNOS4_GPIO_E4_NR (8) +#define EXYNOS4210_GPIO_E0_NR (5) +#define EXYNOS4210_GPIO_E1_NR (8) +#define EXYNOS4210_GPIO_E2_NR (6) +#define EXYNOS4210_GPIO_E3_NR (8) +#define EXYNOS4210_GPIO_E4_NR (8)I think, splitting the gpios like following(common exynos4 and exynos4210 or exynos4x12). So please just put the definitions for EXYNOS4210 GPIO after
EXYNOS4_GPIO_XXX.arch/arm/mach- renamed from arch/arm/mach-exynos/include/mach/gpio.h +0
-0
exynos/include/mach/gpio.h
index eb24f1e..910b611 100644arch/arm/mach-exynos/include/mach/gpio.h +9
-7@@ -26,17 +26,10 @@#define EXYNOS4_GPIO_C1_NR (5)#define EXYNOS4_GPIO_D0_NR (4)#define EXYNOS4_GPIO_D1_NR (4) -#define EXYNOS4_GPIO_E0_NR (5) -#define EXYNOS4_GPIO_E1_NR (8) -#define EXYNOS4_GPIO_E2_NR (6) -#define EXYNOS4_GPIO_E3_NR (8) -#define EXYNOS4_GPIO_E4_NR (8)#define EXYNOS4_GPIO_F0_NR (8)#define EXYNOS4_GPIO_F1_NR (8)#define EXYNOS4_GPIO_F2_NR (8)#define EXYNOS4_GPIO_F3_NR (6) -#define EXYNOS4_GPIO_J0_NR (8) -#define EXYNOS4_GPIO_J1_NR (5)#define EXYNOS4_GPIO_K0_NR (7)#define EXYNOS4_GPIO_K1_NR (7)#define EXYNOS4_GPIO_K2_NR (7)@@ -57,6 +50,31 @@#define EXYNOS4_GPIO_Y6_NR (8)#define EXYNOS4_GPIO_Z_NR (7) +/* For EXYNOS4210 GPIO bank sizes */ + +#define EXYNOS4210_GPIO_E0_NR (5) +#define EXYNOS4210_GPIO_E1_NR (8) +#define EXYNOS4210_GPIO_E2_NR (6) +#define EXYNOS4210_GPIO_E3_NR (8) +#define EXYNOS4210_GPIO_E4_NR (8) +#define EXYNOS4210_GPIO_J0_NR (8) +#define EXYNOS4210_GPIO_J1_NR (5)And we can add EXYNOS4X12 GPIO like following in other patch.
arch/arm/mach-exynos/include/mach/gpio.h +14
-0+/* For EXYNOS4X12 GPIO bank sizes */ + +#define EXYNOS4X12_GPIO_J0_NR (8) +#define EXYNOS4X12_GPIO_J1_NR (5) +#define EXYNOS4X12_GPIO_M0_NR (8) +#define EXYNOS4X12_GPIO_M1_NR (7) +#define EXYNOS4X12_GPIO_M2_NR (5) +#define EXYNOS4X12_GPIO_M3_NR (8) +#define EXYNOS4X12_GPIO_M4_NR (8) +#define EXYNOS4X12_GPIO_V0_NR (8) +#define EXYNOS4X12_GPIO_V1_NR (8) +#define EXYNOS4X12_GPIO_V2_NR (8) +#define EXYNOS4X12_GPIO_V3_NR (8) +#define EXYNOS4X12_GPIO_V4_NR (2)Quoted 15 lines
Quoted 7 lines
Quoted 7 lines
arch/arm/mach-exynos/include/mach/gpio.h +0
-0#define EXYNOS4_GPIO_F0_NR (8)#define EXYNOS4_GPIO_F1_NR (8)#define EXYNOS4_GPIO_F2_NR (8)@@ -67,12 +67,12 @@ enum exynos4_gpio_number {EXYNOS4_GPIO_C1_START =EXYNOS_GPIO_NEXT (EXYNOS4_GPIO_C0 ),EXYNOS4_GPIO_D0_START =EXYNOS_GPIO_NEXT (EXYNOS4_GPIO_C1 ), EXYNOS4_GPIO_D1_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_D0),Quoted 8 lines
arch/arm/mach-exynos/include/mach/gpio.h enum exynos4_gpio_number {
Quoted 8 lines
arch/arm/mach-exynos/include/mach/gpio.h +2
-6-EXYNOS4_GPIO_E0_START =EXYNOS_GPIO_NEXT (EXYNOS4_GPIO_D1 ), -EXYNOS4_GPIO_E1_START =EXYNOS_GPIO_NEXT (EXYNOS4_GPIO_E0 ), -EXYNOS4_GPIO_E2_START =EXYNOS_GPIO_NEXT (EXYNOS4_GPIO_E1 ), -EXYNOS4_GPIO_E3_START =EXYNOS_GPIO_NEXT (EXYNOS4_GPIO_E2 ), -EXYNOS4_GPIO_E4_START =EXYNOS_GPIO_NEXT (EXYNOS4_GPIO_E3 ), - EXYNOS4_GPIO_F0_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_E4), +EXYNOS4210_GPIO_E0_START =EXYNOS_GPIO_NEXT (EXYNOS4_GPIO_D1 ), + EXYNOS4210_GPIO_E1_START =
EXYNOS_GPIO_NEXT(EXYNOS4210_GPIO_E0),Quoted 1 line
Quoted 1 line
arch/arm/mach-exynos/include/mach/gpio.h enum exynos4_gpio_number { · line 72
Quoted 1 line
arch/arm/mach-exynos/include/mach/gpio.h +1
-0+ EXYNOS4210_GPIO_E2_START =
EXYNOS_GPIO_NEXT(EXYNOS4210_GPIO_E1),Quoted 1 line
Quoted 1 line
arch/arm/mach-exynos/include/mach/gpio.h enum exynos4_gpio_number { · line 73
Quoted 1 line
arch/arm/mach-exynos/include/mach/gpio.h +1
-0+ EXYNOS4210_GPIO_E3_START =
EXYNOS_GPIO_NEXT(EXYNOS4210_GPIO_E2),Quoted 1 line
Quoted 1 line
arch/arm/mach-exynos/include/mach/gpio.h enum exynos4_gpio_number { · line 74
Quoted 1 line
arch/arm/mach-exynos/include/mach/gpio.h +1
-0+ EXYNOS4210_GPIO_E4_START =
EXYNOS_GPIO_NEXT(EXYNOS4210_GPIO_E3),arch/arm/mach-exynos/include/mach/gpio.h enum exynos4_gpio_number { · line 122
Quoted 13 lines
Quoted 4 lines
arch/arm/mach-exynos/include/mach/gpio.h enum exynos4_gpio_number { · line 78
Quoted 4 lines
arch/arm/mach-exynos/include/mach/gpio.h +1
-0+EXYNOS4_GPIO_F0_START =EXYNOS_GPIO_NEXT (EXYNOS4210_GPIO_E4 ),EXYNOS4_GPIO_F1_START =EXYNOS_GPIO_NEXT (EXYNOS4_GPIO_F0 ),EXYNOS4_GPIO_F2_START =EXYNOS_GPIO_NEXT (EXYNOS4_GPIO_F1 ), EXYNOS4_GPIO_F3_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_F2),Same as above.
arch/arm/mach-exynos/include/mach/gpio.h +3
-0@@ -99,6 +117,31 @@ enum exynos4_gpio_number { EXYNOS4_GPIO_Z_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_Y6), }; +enum exynos4210_gpio_number { +EXYNOS4210_GPIO_E0_START =EXYNOS4_GPIO_NEXT (EXYNOS4_GPIO_Z ), + EXYNOS4210_GPIO_E1_START =
EXYNOS4_GPIO_NEXT(EXYNOS4210_GPIO_E0),arch/arm/mach-exynos/include/mach/gpio.h enum exynos4_gpio_number { · line 123
Quoted 1 line
arch/arm/mach-exynos/include/mach/gpio.h +1
-0+ EXYNOS4210_GPIO_E2_START =
EXYNOS4_GPIO_NEXT(EXYNOS4210_GPIO_E1),arch/arm/mach-exynos/include/mach/gpio.h enum exynos4_gpio_number { · line 124
Quoted 1 line
arch/arm/mach-exynos/include/mach/gpio.h +1
-0+ EXYNOS4210_GPIO_E3_START =
EXYNOS4_GPIO_NEXT(EXYNOS4210_GPIO_E2),arch/arm/mach-exynos/include/mach/gpio.h enum exynos4_gpio_number { · line 125
Quoted 1 line
arch/arm/mach-exynos/include/mach/gpio.h +1
-0+ EXYNOS4210_GPIO_E4_START =
EXYNOS4_GPIO_NEXT(EXYNOS4210_GPIO_E3),arch/arm/mach-exynos/include/mach/gpio.h enum exynos4_gpio_number { · line 126
Quoted 1 line
arch/arm/mach-exynos/include/mach/gpio.h +1
-0+ EXYNOS4210_GPIO_J0_START =
EXYNOS4_GPIO_NEXT(EXYNOS4210_GPIO_E4),arch/arm/mach-exynos/include/mach/gpio.h enum exynos4_gpio_number { · line 127
Quoted 1 line
arch/arm/mach-exynos/include/mach/gpio.h +1
-0+ EXYNOS4210_GPIO_J1_START =
EXYNOS4_GPIO_NEXT(EXYNOS4210_GPIO_J0),arch/arm/mach-exynos/include/mach/gpio.h
Quoted 9 lines
arch/arm/mach-exynos/include/mach/gpio.h +1
-0+};And following is possible for EXYNOS4X12...
arch/arm/mach-exynos/include/mach/gpio.h +3
-0+enum exynos4x12_gpio_number { +EXYNOS4X12_GPIO_J0_START =EXYNOS4_GPIO_NEXT (EXYNOS4_GPIO_Z ), + EXYNOS4X12_GPIO_J1_START =
EXYNOS4_GPIO_NEXT(EXYNOS4X12_GPIO_J0),arch/arm/mach-exynos/include/mach/gpio.h
Quoted 1 line
arch/arm/mach-exynos/include/mach/gpio.h +1
-0+ EXYNOS4X12_GPIO_M0_START =
EXYNOS4_GPIO_NEXT(EXYNOS4X12_GPIO_J1),arch/arm/mach-exynos/include/mach/gpio.h
Quoted 1 line
arch/arm/mach-exynos/include/mach/gpio.h +1
-0+ EXYNOS4X12_GPIO_M1_START =
EXYNOS4_GPIO_NEXT(EXYNOS4X12_GPIO_M0),arch/arm/mach-exynos/include/mach/gpio.h
Quoted 1 line
arch/arm/mach-exynos/include/mach/gpio.h +1
-0+ EXYNOS4X12_GPIO_M2_START =
EXYNOS4_GPIO_NEXT(EXYNOS4X12_GPIO_M1),arch/arm/mach-exynos/include/mach/gpio.h
Quoted 1 line
arch/arm/mach-exynos/include/mach/gpio.h +1
-0+ EXYNOS4X12_GPIO_M3_START =
EXYNOS4_GPIO_NEXT(EXYNOS4X12_GPIO_M2),arch/arm/mach-exynos/include/mach/gpio.h
Quoted 1 line
arch/arm/mach-exynos/include/mach/gpio.h +1
-0+ EXYNOS4X12_GPIO_M4_START =
EXYNOS4_GPIO_NEXT(EXYNOS4X12_GPIO_M3),arch/arm/mach-exynos/include/mach/gpio.h
Quoted 1 line
arch/arm/mach-exynos/include/mach/gpio.h +1
-0+ EXYNOS4X12_GPIO_V0_START =
EXYNOS4_GPIO_NEXT(EXYNOS4X12_GPIO_M4),arch/arm/mach-exynos/include/mach/gpio.h
Quoted 1 line
arch/arm/mach-exynos/include/mach/gpio.h +1
-0+ EXYNOS4X12_GPIO_V1_START =
EXYNOS4_GPIO_NEXT(EXYNOS4X12_GPIO_V0),arch/arm/mach-exynos/include/mach/gpio.h
Quoted 1 line
arch/arm/mach-exynos/include/mach/gpio.h +1
-0+ EXYNOS4X12_GPIO_V2_START =
EXYNOS4_GPIO_NEXT(EXYNOS4X12_GPIO_V1),arch/arm/mach-exynos/include/mach/gpio.h
Quoted 1 line
arch/arm/mach-exynos/include/mach/gpio.h +1
-0+ EXYNOS4X12_GPIO_V3_START =
EXYNOS4_GPIO_NEXT(EXYNOS4X12_GPIO_V2),arch/arm/mach-exynos/include/mach/gpio.h
Quoted 1 line
arch/arm/mach-exynos/include/mach/gpio.h +1
-0+ EXYNOS4X12_GPIO_V4_START =
EXYNOS4_GPIO_NEXT(EXYNOS4X12_GPIO_V3),Quoted 4 lines
arch/arm/mach-exynos/include/mach/gpio.h +2
-0+}; +/* EXYNOS4 GPIO number definitions */
Quoted 7 lines
Quoted 6 lines
#define EXYNOS4_GPA0(_nr) (EXYNOS4_GPIO_A0_START + (_nr))[...]
Of course, need to update other regarding gpio part accordingly.
Joonyoung, any updates on this?
Sorry for late response, but i don't have any progress for this.
Thanks.
PATCH 2/2 gpio/exynos: Add support for Exynos4x12 SoC
In reply to Joonyoung ShimExynos4x12 GPIO part1 and part2 layouts are different with that of Exynos4210. So, it needs to support gpios for Exynos4x12 SoC. This doesn't support GPVx Exynos4x12 GPIO part4 yet.
In the Exynos4x12 GPIO part1 and part2, the interval of base register offset is 0x20 but GPF0, GPJ0, GPK0 and GPM0 ignore the 0x20 interval and have new value. The interrupt reg offset also is about GPF0 and GPK0 too. Refer the below layout.
- Exynos4x12 GPIO Part1
GPIO Base offset Interrupt reg offset
GPA0 0x000 0x00
GPA1 0x020 0x04
GPB 0x040 0x08
GPC0 0x060 0x0C
GPC1 0x080 0x10
GPD0 0x0A0 0x14
GPD1 0x0C0 0x18
...
GPF0 0x180 0x30
GPF1 0x1A0 0x34
GPF2 0x1C0 0x38
GPF3 0x1E0 0x3C
...
GPJ0 0x240 0x40
GPJ1 0x260 0x44- Exynos4x12 GPIO Part2
...
GPK0 0x040 0x08
GPK1 0x060 0x0C
GPK2 0x080 0x10
GPK3 0x0A0 0x14
GPL0 0x0C0 0x18
GPL1 0x0E0 0x1C
GPL2 0x100 0x20
GPY0 0x120 x
GPY1 0x140 x
GPY2 0x160 x
GPY3 0x180 x
GPY4 0x1A0 x
GPY5 0x1C0 x
GPY6 0x1E0 x
...
GPM0 0x260 0x24
GPM1 0x280 0x28
GPM2 0x2A0 0x2C
GPM3 0x2C0 0x30
GPM4 0x2E0 0x34
GPX0 0xC00 x
GPX1 0xC20 x
GPX2 0xC40 x
GPX3 0xC60 xSigned-off-by Joonyoung Shim <[email protected]>
Signed-off-by Kyungmin Park <[email protected]>
--- arch/arm/mach-exynos/include/mach/gpio.h | 28 +++- arch/arm/mach-exynos/include/mach/irqs.h | 6 - drivers/gpio/gpio-samsung.c | 334 +++++++++++++++++++++++++++--- 3 files changed, 327 insertions(+), 41 deletions(-)
arch/arm/mach-exynos/include/mach/gpio.h +27 -1
@@ -26,11 +26,13 @@#define EXYNOS4_GPIO_C1_NR (5)#define EXYNOS4_GPIO_D0_NR (4)#define EXYNOS4_GPIO_D1_NR (4) +#define EXYNOS4210_GPIO_E0_NR (5)#define EXYNOS4210_GPIO_E1_NR (8)#define EXYNOS4210_GPIO_E2_NR (6)#define EXYNOS4210_GPIO_E3_NR (8)#define EXYNOS4210_GPIO_E4_NR (8) +#define EXYNOS4_GPIO_F0_NR (8)#define EXYNOS4_GPIO_F1_NR (8)#define EXYNOS4_GPIO_F2_NR (8)
@@ -44,6 +46,13 @@#define EXYNOS4_GPIO_L0_NR (8)#define EXYNOS4_GPIO_L1_NR (3)#define EXYNOS4_GPIO_L2_NR (8) + +#define EXYNOS4X12_GPIO_M0_NR (8) +#define EXYNOS4X12_GPIO_M1_NR (7) +#define EXYNOS4X12_GPIO_M2_NR (5) +#define EXYNOS4X12_GPIO_M3_NR (8) +#define EXYNOS4X12_GPIO_M4_NR (8) +#define EXYNOS4_GPIO_X0_NR (8)#define EXYNOS4_GPIO_X1_NR (8)#define EXYNOS4_GPIO_X2_NR (8)
@@ -67,12 +76,20 @@ enum exynos4_gpio_number {EXYNOS4_GPIO_C1_START =EXYNOS_GPIO_NEXT (EXYNOS4_GPIO_C0 ),EXYNOS4_GPIO_D0_START =EXYNOS_GPIO_NEXT (EXYNOS4_GPIO_C1 ),EXYNOS4_GPIO_D1_START =EXYNOS_GPIO_NEXT (EXYNOS4_GPIO_D0 ), +EXYNOS4210_GPIO_E0_START =EXYNOS_GPIO_NEXT (EXYNOS4_GPIO_D1 ),EXYNOS4210_GPIO_E1_START =EXYNOS_GPIO_NEXT (EXYNOS4210_GPIO_E0 ),EXYNOS4210_GPIO_E2_START =EXYNOS_GPIO_NEXT (EXYNOS4210_GPIO_E1 ),EXYNOS4210_GPIO_E3_START =EXYNOS_GPIO_NEXT (EXYNOS4210_GPIO_E2 ),EXYNOS4210_GPIO_E4_START =EXYNOS_GPIO_NEXT (EXYNOS4210_GPIO_E3 ), -EXYNOS4_GPIO_F0_START =EXYNOS_GPIO_NEXT (EXYNOS4210_GPIO_E4 ), + +EXYNOS4X12_GPIO_M0_START =EXYNOS_GPIO_NEXT (EXYNOS4_GPIO_D1 ), +EXYNOS4X12_GPIO_M1_START =EXYNOS_GPIO_NEXT (EXYNOS4X12_GPIO_M0 ), +EXYNOS4X12_GPIO_M2_START =EXYNOS_GPIO_NEXT (EXYNOS4X12_GPIO_M1 ), +EXYNOS4X12_GPIO_M3_START =EXYNOS_GPIO_NEXT (EXYNOS4X12_GPIO_M2 ), +EXYNOS4X12_GPIO_M4_START =EXYNOS_GPIO_NEXT (EXYNOS4X12_GPIO_M3 ), + +EXYNOS4_GPIO_F0_START =EXYNOS_GPIO_NEXT (EXYNOS4X12_GPIO_M4 ),EXYNOS4_GPIO_F1_START =EXYNOS_GPIO_NEXT (EXYNOS4_GPIO_F0 ),EXYNOS4_GPIO_F2_START =EXYNOS_GPIO_NEXT (EXYNOS4_GPIO_F1 ), EXYNOS4_GPIO_F3_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_F2),
@@ -108,11 +125,13 @@ enum exynos4_gpio_number {#define EXYNOS4_GPC1 (_nr) (EXYNOS4_GPIO_C1_START + (_nr))#define EXYNOS4_GPD0 (_nr) (EXYNOS4_GPIO_D0_START + (_nr))#define EXYNOS4_GPD1 (_nr) (EXYNOS4_GPIO_D1_START + (_nr)) +#define EXYNOS4210_GPE0 (_nr) (EXYNOS4210_GPIO_E0_START + (_nr))#define EXYNOS4210_GPE1 (_nr) (EXYNOS4210_GPIO_E1_START + (_nr))#define EXYNOS4210_GPE2 (_nr) (EXYNOS4210_GPIO_E2_START + (_nr))#define EXYNOS4210_GPE3 (_nr) (EXYNOS4210_GPIO_E3_START + (_nr))#define EXYNOS4210_GPE4 (_nr) (EXYNOS4210_GPIO_E4_START + (_nr)) +#define EXYNOS4_GPF0 (_nr) (EXYNOS4_GPIO_F0_START + (_nr))#define EXYNOS4_GPF1 (_nr) (EXYNOS4_GPIO_F1_START + (_nr))#define EXYNOS4_GPF2 (_nr) (EXYNOS4_GPIO_F2_START + (_nr))
@@ -126,6 +145,13 @@ enum exynos4_gpio_number {#define EXYNOS4_GPL0 (_nr) (EXYNOS4_GPIO_L0_START + (_nr))#define EXYNOS4_GPL1 (_nr) (EXYNOS4_GPIO_L1_START + (_nr))#define EXYNOS4_GPL2 (_nr) (EXYNOS4_GPIO_L2_START + (_nr)) + +#define EXYNOS4X12_GPM0 (_nr) (EXYNOS4X12_GPIO_M0_START + (_nr)) +#define EXYNOS4X12_GPM1 (_nr) (EXYNOS4X12_GPIO_M1_START + (_nr)) +#define EXYNOS4X12_GPM2 (_nr) (EXYNOS4X12_GPIO_M2_START + (_nr)) +#define EXYNOS4X12_GPM3 (_nr) (EXYNOS4X12_GPIO_M3_START + (_nr)) +#define EXYNOS4X12_GPM4 (_nr) (EXYNOS4X12_GPIO_M4_START + (_nr)) +#define EXYNOS4_GPX0 (_nr) (EXYNOS4_GPIO_X0_START + (_nr))#define EXYNOS4_GPX1 (_nr) (EXYNOS4_GPIO_X1_START + (_nr))#define EXYNOS4_GPX2 (_nr) (EXYNOS4_GPIO_X2_START + (_nr))
arch/arm/mach-exynos/include/mach/irqs.h +0 -6
@@ -167,9 +167,6 @@#define EXYNOS4_MAX_COMBINER_NR 16 -#define EXYNOS4_IRQ_GPIO1_NR_GROUPS 16 -#define EXYNOS4_IRQ_GPIO2_NR_GROUPS 9 -/* * For Compatibility: * the default is for EXYNOS4, and
@@ -231,9 +228,6 @@#define IRQ_FIMD0_VSYNC EXYNOS4_IRQ_FIMD0_VSYNC#define IRQ_FIMD0_SYSTEM EXYNOS4_IRQ_FIMD0_SYSTEM -#define IRQ_GPIO1_NR_GROUPS EXYNOS4_IRQ_GPIO1_NR_GROUPS -#define IRQ_GPIO2_NR_GROUPS EXYNOS4_IRQ_GPIO2_NR_GROUPS -/* For EXYNOS5 SoCs */ #define EXYNOS5_IRQ_MDMA0 IRQ_SPI(33)
drivers/gpio/gpio-samsung.c +300 -34
411 lines not on this page · raw message
Signature · 1 line
1.7.5.4
PATCH 2/2 gpio/exynos: Add support for Exynos4x12 SoC
Add to cc Grant Likely and Linus Walleij
Quoted 593 lines · Joonyoung Shim
Exynos4x12 GPIO part1 and part2 layouts are different with that of Exynos4210. So, it needs to support gpios for Exynos4x12 SoC. This doesn't support GPVx Exynos4x12 GPIO part4 yet.
In the Exynos4x12 GPIO part1 and part2, the interval of base register offset is
0x20but GPF0, GPJ0, GPK0 and GPM0 ignore the0x20interval and have new value. The interrupt reg offset also is about GPF0 and GPK0 too. Refer the below layout.- Exynos4x12 GPIO Part1
GPIO Base offset Interrupt reg offset GPA0 0x000 0x00 GPA1 0x020 0x04 GPB 0x040 0x08 GPC0 0x060 0x0C GPC1 0x080 0x10 GPD0 0x0A0 0x14 GPD1 0x0C0 0x18 ... GPF0 0x180 0x30 GPF1 0x1A0 0x34 GPF2 0x1C0 0x38 GPF3 0x1E0 0x3C ... GPJ0 0x240 0x40 GPJ1 0x260 0x44- Exynos4x12 GPIO Part2
... GPK0 0x040 0x08 GPK1 0x060 0x0C GPK2 0x080 0x10 GPK3 0x0A0 0x14 GPL0 0x0C0 0x18 GPL1 0x0E0 0x1C GPL2 0x100 0x20 GPY0 0x120 x GPY1 0x140 x GPY2 0x160 x GPY3 0x180 x GPY4 0x1A0 x GPY5 0x1C0 x GPY6 0x1E0 x ... GPM0 0x260 0x24 GPM1 0x280 0x28 GPM2 0x2A0 0x2C GPM3 0x2C0 0x30 GPM4 0x2E0 0x34 GPX0 0xC00 x GPX1 0xC20 x GPX2 0xC40 x GPX3 0xC60 xSigned-off-by Joonyoung Shim<[email protected]>Signed-off-by Kyungmin Park<[email protected]>--- arch/arm/mach-exynos/include/mach/gpio.h | 28 +++- arch/arm/mach-exynos/include/mach/irqs.h | 6 - drivers/gpio/gpio-samsung.c | 334 +++++++++++++++++++++++++++--- 3 files changed, 327 insertions(+), 41 deletions(-)arch/arm/mach-exynos/include/mach/gpio.h +27
-1@@ -26,11 +26,13 @@#define EXYNOS4_GPIO_C1_NR (5)#define EXYNOS4_GPIO_D0_NR (4)#define EXYNOS4_GPIO_D1_NR (4) +#define EXYNOS4210_GPIO_E0_NR (5)#define EXYNOS4210_GPIO_E1_NR (8)#define EXYNOS4210_GPIO_E2_NR (6)#define EXYNOS4210_GPIO_E3_NR (8)#define EXYNOS4210_GPIO_E4_NR (8) +#define EXYNOS4_GPIO_F0_NR (8)#define EXYNOS4_GPIO_F1_NR (8)#define EXYNOS4_GPIO_F2_NR (8)@@ -44,6 +46,13 @@#define EXYNOS4_GPIO_L0_NR (8)#define EXYNOS4_GPIO_L1_NR (3)#define EXYNOS4_GPIO_L2_NR (8) + +#define EXYNOS4X12_GPIO_M0_NR (8) +#define EXYNOS4X12_GPIO_M1_NR (7) +#define EXYNOS4X12_GPIO_M2_NR (5) +#define EXYNOS4X12_GPIO_M3_NR (8) +#define EXYNOS4X12_GPIO_M4_NR (8) +#define EXYNOS4_GPIO_X0_NR (8)#define EXYNOS4_GPIO_X1_NR (8)#define EXYNOS4_GPIO_X2_NR (8)@@ -67,12 +76,20 @@ enum exynos4_gpio_number {EXYNOS4_GPIO_C1_START =EXYNOS_GPIO_NEXT (EXYNOS4_GPIO_C0 ),EXYNOS4_GPIO_D0_START =EXYNOS_GPIO_NEXT (EXYNOS4_GPIO_C1 ),EXYNOS4_GPIO_D1_START =EXYNOS_GPIO_NEXT (EXYNOS4_GPIO_D0 ), +EXYNOS4210_GPIO_E0_START =EXYNOS_GPIO_NEXT (EXYNOS4_GPIO_D1 ),EXYNOS4210_GPIO_E1_START =EXYNOS_GPIO_NEXT (EXYNOS4210_GPIO_E0 ),EXYNOS4210_GPIO_E2_START =EXYNOS_GPIO_NEXT (EXYNOS4210_GPIO_E1 ),EXYNOS4210_GPIO_E3_START =EXYNOS_GPIO_NEXT (EXYNOS4210_GPIO_E2 ),EXYNOS4210_GPIO_E4_START =EXYNOS_GPIO_NEXT (EXYNOS4210_GPIO_E3 ), -EXYNOS4_GPIO_F0_START =EXYNOS_GPIO_NEXT (EXYNOS4210_GPIO_E4 ), + +EXYNOS4X12_GPIO_M0_START =EXYNOS_GPIO_NEXT (EXYNOS4_GPIO_D1 ), +EXYNOS4X12_GPIO_M1_START =EXYNOS_GPIO_NEXT (EXYNOS4X12_GPIO_M0 ), +EXYNOS4X12_GPIO_M2_START =EXYNOS_GPIO_NEXT (EXYNOS4X12_GPIO_M1 ), +EXYNOS4X12_GPIO_M3_START =EXYNOS_GPIO_NEXT (EXYNOS4X12_GPIO_M2 ), +EXYNOS4X12_GPIO_M4_START =EXYNOS_GPIO_NEXT (EXYNOS4X12_GPIO_M3 ), + +EXYNOS4_GPIO_F0_START =EXYNOS_GPIO_NEXT (EXYNOS4X12_GPIO_M4 ),EXYNOS4_GPIO_F1_START =EXYNOS_GPIO_NEXT (EXYNOS4_GPIO_F0 ),EXYNOS4_GPIO_F2_START =EXYNOS_GPIO_NEXT (EXYNOS4_GPIO_F1 ), EXYNOS4_GPIO_F3_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_F2),@@ -108,11 +125,13 @@ enum exynos4_gpio_number {#define EXYNOS4_GPC1 (_nr) (EXYNOS4_GPIO_C1_START + (_nr))#define EXYNOS4_GPD0 (_nr) (EXYNOS4_GPIO_D0_START + (_nr))#define EXYNOS4_GPD1 (_nr) (EXYNOS4_GPIO_D1_START + (_nr)) +#define EXYNOS4210_GPE0 (_nr) (EXYNOS4210_GPIO_E0_START + (_nr))#define EXYNOS4210_GPE1 (_nr) (EXYNOS4210_GPIO_E1_START + (_nr))#define EXYNOS4210_GPE2 (_nr) (EXYNOS4210_GPIO_E2_START + (_nr))#define EXYNOS4210_GPE3 (_nr) (EXYNOS4210_GPIO_E3_START + (_nr))#define EXYNOS4210_GPE4 (_nr) (EXYNOS4210_GPIO_E4_START + (_nr)) +#define EXYNOS4_GPF0 (_nr) (EXYNOS4_GPIO_F0_START + (_nr))#define EXYNOS4_GPF1 (_nr) (EXYNOS4_GPIO_F1_START + (_nr))#define EXYNOS4_GPF2 (_nr) (EXYNOS4_GPIO_F2_START + (_nr))@@ -126,6 +145,13 @@ enum exynos4_gpio_number {#define EXYNOS4_GPL0 (_nr) (EXYNOS4_GPIO_L0_START + (_nr))#define EXYNOS4_GPL1 (_nr) (EXYNOS4_GPIO_L1_START + (_nr))#define EXYNOS4_GPL2 (_nr) (EXYNOS4_GPIO_L2_START + (_nr)) + +#define EXYNOS4X12_GPM0 (_nr) (EXYNOS4X12_GPIO_M0_START + (_nr)) +#define EXYNOS4X12_GPM1 (_nr) (EXYNOS4X12_GPIO_M1_START + (_nr)) +#define EXYNOS4X12_GPM2 (_nr) (EXYNOS4X12_GPIO_M2_START + (_nr)) +#define EXYNOS4X12_GPM3 (_nr) (EXYNOS4X12_GPIO_M3_START + (_nr)) +#define EXYNOS4X12_GPM4 (_nr) (EXYNOS4X12_GPIO_M4_START + (_nr)) +#define EXYNOS4_GPX0 (_nr) (EXYNOS4_GPIO_X0_START + (_nr))#define EXYNOS4_GPX1 (_nr) (EXYNOS4_GPIO_X1_START + (_nr))#define EXYNOS4_GPX2 (_nr) (EXYNOS4_GPIO_X2_START + (_nr))arch/arm/mach-exynos/include/mach/irqs.h +0
-6@@ -167,9 +167,6 @@#define EXYNOS4_MAX_COMBINER_NR 16 -#define EXYNOS4_IRQ_GPIO1_NR_GROUPS 16 -#define EXYNOS4_IRQ_GPIO2_NR_GROUPS 9 -/* * For Compatibility: * the default is for EXYNOS4, and @@ -231,9 +228,6 @@#define IRQ_FIMD0_VSYNC EXYNOS4_IRQ_FIMD0_VSYNC#define IRQ_FIMD0_SYSTEM EXYNOS4_IRQ_FIMD0_SYSTEM -#define IRQ_GPIO1_NR_GROUPS EXYNOS4_IRQ_GPIO1_NR_GROUPS -#define IRQ_GPIO2_NR_GROUPS EXYNOS4_IRQ_GPIO2_NR_GROUPS -/* For EXYNOS5 SoCs */ #define EXYNOS5_IRQ_MDMA0 IRQ_SPI(33)drivers/gpio/gpio-samsung.c +300
-34@@ -2126,7 +2126,7 @@ static struct samsung_gpio_chip s5pv210_gpios_4bit[] = {*/ #ifdef CONFIG_ARCH_EXYNOS4 -static struct samsung_gpio_chip exynos4_gpios_1[] = { +static struct samsung_gpio_chip exynos4210_gpios_1[] = { { .chip = { .base = EXYNOS4_GPA0(0),@@ -2225,10 +2225,93 @@ static struct samsung_gpio_chip exynos4_gpios_1[] = { }, }, }; -#endif -#ifdef CONFIG_ARCH_EXYNOS4 -static struct samsung_gpio_chip exynos4_gpios_2[] = { +static struct samsung_gpio_chip exynos4x12_gpios_1[] = { + { + .chip = { + .base =EXYNOS4_GPA0 (0 ), + .ngpio =EXYNOS4_GPIO_A0_NR , + .label ="GPA0" , + }, + }, { + .chip = { + .base =EXYNOS4_GPA1 (0 ), + .ngpio =EXYNOS4_GPIO_A1_NR , + .label ="GPA1" , + }, + }, { + .chip = { + .base =EXYNOS4_GPB (0 ), + .ngpio =EXYNOS4_GPIO_B_NR , + .label ="GPB" , + }, + }, { + .chip = { + .base =EXYNOS4_GPC0 (0 ), + .ngpio =EXYNOS4_GPIO_C0_NR , + .label ="GPC0" , + }, + }, { + .chip = { + .base =EXYNOS4_GPC1 (0 ), + .ngpio =EXYNOS4_GPIO_C1_NR , + .label ="GPC1" , + }, + }, { + .chip = { + .base =EXYNOS4_GPD0 (0 ), + .ngpio =EXYNOS4_GPIO_D0_NR , + .label ="GPD0" , + }, + }, { + .chip = { + .base =EXYNOS4_GPD1 (0 ), + .ngpio =EXYNOS4_GPIO_D1_NR , + .label ="GPD1" , + }, + }, { + .base = (void *)0x180 , + .group =12 , + .chip = { + .base =EXYNOS4_GPF0 (0 ), + .ngpio =EXYNOS4_GPIO_F0_NR , + .label ="GPF0" , + }, + }, { + .chip = { + .base =EXYNOS4_GPF1 (0 ), + .ngpio =EXYNOS4_GPIO_F1_NR , + .label ="GPF1" , + }, + }, { + .chip = { + .base =EXYNOS4_GPF2 (0 ), + .ngpio =EXYNOS4_GPIO_F2_NR , + .label ="GPF2" , + }, + }, { + .chip = { + .base =EXYNOS4_GPF3 (0 ), + .ngpio =EXYNOS4_GPIO_F3_NR , + .label ="GPF3" , + }, + }, { + .base = (void *)0x240 , + .chip = { + .base =EXYNOS4_GPJ0 (0 ), + .ngpio =EXYNOS4_GPIO_J0_NR , + .label ="GPJ0" , + }, + }, { + .chip = { + .base =EXYNOS4_GPJ1 (0 ), + .ngpio =EXYNOS4_GPIO_J1_NR , + .label ="GPJ1" , + }, + }, +}; + +static struct samsung_gpio_chip exynos4210_gpios_2[] = { { .chip = { .base =EXYNOS4_GPJ0 (0 ),@@ -2333,6 +2416,172 @@ static struct samsung_gpio_chip exynos4_gpios_2[] = { .label = "GPY6", }, }, { + .base = (void *)0xC00, + .config =&samsung_gpio_cfgs[9], + .irq_base = IRQ_EINT(0), + .chip = { + .base = EXYNOS4_GPX0(0), + .ngpio = EXYNOS4_GPIO_X0_NR, + .label = "GPX0", + .to_irq = samsung_gpiolib_to_irq, + }, + }, { + .config =&samsung_gpio_cfgs[9], + .irq_base = IRQ_EINT(8), + .chip = { + .base = EXYNOS4_GPX1(0), + .ngpio = EXYNOS4_GPIO_X1_NR, + .label = "GPX1", + .to_irq = samsung_gpiolib_to_irq, + }, + }, { + .config =&samsung_gpio_cfgs[9], + .irq_base = IRQ_EINT(16), + .chip = { + .base = EXYNOS4_GPX2(0), + .ngpio = EXYNOS4_GPIO_X2_NR, + .label = "GPX2", + .to_irq = samsung_gpiolib_to_irq, + }, + }, { + .config =&samsung_gpio_cfgs[9], + .irq_base = IRQ_EINT(24), + .chip = { + .base = EXYNOS4_GPX3(0), + .ngpio = EXYNOS4_GPIO_X3_NR, + .label = "GPX3", + .to_irq = samsung_gpiolib_to_irq, + }, + }, +}; + +static struct samsung_gpio_chip exynos4x12_gpios_2[] = { + { + .base = (void *)0x040, + .group = 20, + .chip = { + .base = EXYNOS4_GPK0(0), + .ngpio = EXYNOS4_GPIO_K0_NR, + .label = "GPK0", + }, + }, { + .chip = { + .base = EXYNOS4_GPK1(0), + .ngpio = EXYNOS4_GPIO_K1_NR, + .label = "GPK1", + }, + }, { + .chip = { + .base = EXYNOS4_GPK2(0), + .ngpio = EXYNOS4_GPIO_K2_NR, + .label = "GPK2", + }, + }, { + .chip = { + .base = EXYNOS4_GPK3(0), + .ngpio = EXYNOS4_GPIO_K3_NR, + .label = "GPK3", + }, + }, { + .chip = { + .base = EXYNOS4_GPL0(0), + .ngpio = EXYNOS4_GPIO_L0_NR, + .label = "GPL0", + }, + }, { + .chip = { + .base = EXYNOS4_GPL1(0), + .ngpio = EXYNOS4_GPIO_L1_NR, + .label = "GPL1", + }, + }, { + .chip = { + .base = EXYNOS4_GPL2(0), + .ngpio = EXYNOS4_GPIO_L2_NR, + .label = "GPL2", + }, + }, { + .config =&samsung_gpio_cfgs[8], + .chip = { + .base = EXYNOS4_GPY0(0), + .ngpio = EXYNOS4_GPIO_Y0_NR, + .label = "GPY0", + }, + }, { + .config =&samsung_gpio_cfgs[8], + .chip = { + .base = EXYNOS4_GPY1(0), + .ngpio = EXYNOS4_GPIO_Y1_NR, + .label = "GPY1", + }, + }, { + .config =&samsung_gpio_cfgs[8], + .chip = { + .base = EXYNOS4_GPY2(0), + .ngpio = EXYNOS4_GPIO_Y2_NR, + .label = "GPY2", + }, + }, { + .config =&samsung_gpio_cfgs[8], + .chip = { + .base = EXYNOS4_GPY3(0), + .ngpio = EXYNOS4_GPIO_Y3_NR, + .label = "GPY3", + }, + }, { + .config =&samsung_gpio_cfgs[8], + .chip = { + .base = EXYNOS4_GPY4(0), + .ngpio = EXYNOS4_GPIO_Y4_NR, + .label = "GPY4", + }, + }, { + .config =&samsung_gpio_cfgs[8], + .chip = { + .base = EXYNOS4_GPY5(0), + .ngpio = EXYNOS4_GPIO_Y5_NR, + .label = "GPY5", + }, + }, { + .config =&samsung_gpio_cfgs[8], + .chip = { + .base = EXYNOS4_GPY6(0), + .ngpio = EXYNOS4_GPIO_Y6_NR, + .label = "GPY6", + }, + }, { + .base = (void *)0x260, + .chip = { + .base = EXYNOS4X12_GPM0(0), + .ngpio = EXYNOS4X12_GPIO_M0_NR, + .label = "GPM0", + }, + }, { + .chip = { + .base = EXYNOS4X12_GPM1(0), + .ngpio = EXYNOS4X12_GPIO_M1_NR, + .label = "GPM1", + }, + }, { + .chip = { + .base = EXYNOS4X12_GPM2(0), + .ngpio = EXYNOS4X12_GPIO_M2_NR, + .label = "GPM2", + }, + }, { + .chip = { + .base = EXYNOS4X12_GPM3(0), + .ngpio = EXYNOS4X12_GPIO_M3_NR, + .label = "GPM3", + }, + }, { + .chip = { + .base = EXYNOS4X12_GPM4(0), + .ngpio = EXYNOS4X12_GPIO_M4_NR, + .label = "GPM4", + }, + }, { + .base = (void *)0xC00, .config =&samsung_gpio_cfgs[9], .irq_base = IRQ_EINT(0), .chip = {@@ -2370,9 +2619,7 @@ static struct samsung_gpio_chip exynos4_gpios_2[] = { }, }, }; -#endif -#ifdef CONFIG_ARCH_EXYNOS4static struct samsung_gpio_chip exynos4_gpios_3[] = { { .chip = {@@ -2727,7 +2974,7 @@ static __init int samsung_gpiolib_init(void) {struct samsung_gpio_chip *chip;int i, nr_chips; -#if defined(CONFIG_CPU_EXYNOS4210 ) || defined(CONFIG_SOC_EXYNOS5250 ) +#if defined(CONFIG_ARCH_EXYNOS4 ) || defined(CONFIG_SOC_EXYNOS5250 )void __iomem *gpio_base1, *gpio_base2, *gpio_base3, *gpio_base4;#endif int group =0 ;@@ -2794,9 +3041,12 @@ static __init int samsung_gpiolib_init(void)#if defined(CONFIG_CPU_S5PV210 )&& defined(CONFIG_S5P_GPIO_INT )s5p_register_gpioint_bank (IRQ_GPIOINT ,0 ,S5P_GPIOINT_GROUP_MAXNR );#endif - }else if (soc_is_exynos4210 ()) { -#ifdef CONFIG_CPU_EXYNOS4210 -void __iomem *gpx_base; + }else if (soc_is_exynos4210 () ||soc_is_exynos4212 () || +soc_is_exynos4412 ()) { +#ifdef CONFIG_ARCH_EXYNOS4 +struct samsung_gpio_chip *chip_p; +int offset =0 ; +int group1 =0 ;/* gpio part1 */ gpio_base1 =ioremap (EXYNOS4_PA_GPIO1 ,SZ_4K );@@ -2805,19 +3055,31 @@ static __init int samsung_gpiolib_init(void) goto err_ioremap1; } - chip = exynos4_gpios_1; - nr_chips =ARRAY_SIZE (exynos4_gpios_1); +if (soc_is_exynos4210 ()) { + chip = chip_p = exynos4210_gpios_1; + nr_chips =ARRAY_SIZE (exynos4210_gpios_1); + }else { + chip = chip_p = exynos4x12_gpios_1; + nr_chips =ARRAY_SIZE (exynos4x12_gpios_1); + }for (i =0 ; i< nr_chips; i++, chip++) {if (!chip->config) { chip->config =&exynos_gpio_cfg; +if (chip->group) + group = chip->group; chip->group = group++; } -exynos_gpiolib_attach_ofnode (chip, -EXYNOS4_PA_GPIO1 , i *0x20 ); + +if (chip->base) + offset = (u32 )chip->base; + chip->base = gpio_base1 + offset; + offset +=0x20 ; + +exynos_gpiolib_attach_ofnode (chip,EXYNOS4_PA_GPIO1 ,0 ); } -samsung_gpiolib_add_4bit_chips (exynos4_gpios_1, - nr_chips, gpio_base1); +samsung_gpiolib_add_4bit_chips (chip_p, nr_chips, gpio_base1); + group1 = group;/* gpio part2 */ gpio_base2 =ioremap (EXYNOS4_PA_GPIO2 ,SZ_4K );@@ -2826,25 +3088,32 @@ static __init int samsung_gpiolib_init(void) goto err_ioremap2; } -/* need to set base address for gpx */ - chip =&exynos4_gpios_2[16 ]; - gpx_base = gpio_base2 +0xC00 ; -for (i =0 ; i<4 ; i++, chip++, gpx_base +=0x20 ) - chip->base = gpx_base; +if (soc_is_exynos4210 ()) { + chip = chip_p = exynos4210_gpios_2; + nr_chips =ARRAY_SIZE (exynos4210_gpios_2); + }else { + chip = chip_p = exynos4x12_gpios_2; + nr_chips =ARRAY_SIZE (exynos4x12_gpios_2); + } - chip = exynos4_gpios_2; - nr_chips =ARRAY_SIZE (exynos4_gpios_2); + offset =0 ;for (i =0 ; i< nr_chips; i++, chip++) {if (!chip->config) { chip->config =&exynos_gpio_cfg; +if (chip->group) + group = chip->group; chip->group = group++; } -exynos_gpiolib_attach_ofnode (chip, -EXYNOS4_PA_GPIO2 , i *0x20 ); + +if (chip->base) + offset = (u32 )chip->base; + chip->base = gpio_base2 + offset; + offset +=0x20 ; + +exynos_gpiolib_attach_ofnode (chip,EXYNOS4_PA_GPIO2 ,0 ); } -samsung_gpiolib_add_4bit_chips (exynos4_gpios_2, - nr_chips, gpio_base2); +samsung_gpiolib_add_4bit_chips (chip_p, nr_chips, gpio_base2);/* gpio part3 */ gpio_base3 =ioremap (EXYNOS4_PA_GPIO3 ,SZ_256 );@@ -2867,12 +3136,9 @@ static __init int samsung_gpiolib_init(void)samsung_gpiolib_add_4bit_chips (exynos4_gpios_3, nr_chips, gpio_base3); -#if defined(CONFIG_CPU_EXYNOS4210 )&& defined(CONFIG_S5P_GPIO_INT ) -s5p_register_gpioint_bank (IRQ_GPIO_XA ,0 ,IRQ_GPIO1_NR_GROUPS ); -s5p_register_gpioint_bank (IRQ_GPIO_XB ,IRQ_GPIO1_NR_GROUPS ,IRQ_GPIO2_NR_GROUPS ); -#endif - -#endif /* CONFIG_CPU_EXYNOS4210 */ +s5p_register_gpioint_bank (IRQ_GPIO_XA ,0 , group1); +s5p_register_gpioint_bank (IRQ_GPIO_XB , group1, group - group1); +#endif /* CONFIG_ARCH_EXYNOS4 */ }else if (soc_is_exynos5250 ()) {#ifdef CONFIG_SOC_EXYNOS5250 void __iomem *gpx_base;@@ -2984,7 +3250,7 @@ static __init int samsung_gpiolib_init(void)return 0 ; -#if defined(CONFIG_CPU_EXYNOS4210 ) || defined(CONFIG_SOC_EXYNOS5250 ) +#if defined(CONFIG_ARCH_EXYNOS4 ) || defined(CONFIG_SOC_EXYNOS5250 ) err_ioremap4:iounmap (gpio_base3); err_ioremap3:
PATCH 2/2 gpio/exynos: Add support for Exynos4x12 SoC
Quoted 59 lines · Joonyoung Shim
Add to cc Grant Likely and Linus Walleij
Quoted 56 lines · Joonyoung Shim
Exynos4x12 GPIO part1 and part2 layouts are different with that of Exynos4210. So, it needs to support gpios for Exynos4x12 SoC. This doesn't support GPVx Exynos4x12 GPIO part4 yet.
In the Exynos4x12 GPIO part1 and part2, the interval of base register offset is
0x20but GPF0, GPJ0, GPK0 and GPM0 ignore the0x20interval and have new value. The interrupt reg offset also is about GPF0 and GPK0 too. Refer the below layout.- Exynos4x12 GPIO Part1
GPIO Base offset Interrupt reg offset GPA0 0x000 0x00 GPA1 0x020 0x04 GPB 0x040 0x08 GPC0 0x060 0x0C GPC1 0x080 0x10 GPD0 0x0A0 0x14 GPD1 0x0C0 0x18 ... GPF0 0x180 0x30 GPF1 0x1A0 0x34 GPF2 0x1C0 0x38 GPF3 0x1E0 0x3C ... GPJ0 0x240 0x40 GPJ1 0x260 0x44- Exynos4x12 GPIO Part2
... GPK0 0x040 0x08 GPK1 0x060 0x0C GPK2 0x080 0x10 GPK3 0x0A0 0x14 GPL0 0x0C0 0x18 GPL1 0x0E0 0x1C GPL2 0x100 0x20 GPY0 0x120 x GPY1 0x140 x GPY2 0x160 x GPY3 0x180 x GPY4 0x1A0 x GPY5 0x1C0 x GPY6 0x1E0 x ... GPM0 0x260 0x24 GPM1 0x280 0x28 GPM2 0x2A0 0x2C GPM3 0x2C0 0x30 GPM4 0x2E0 0x34 GPX0 0xC00 x GPX1 0xC20 x GPX2 0xC40 x GPX3 0xC60 xSigned-off-by Joonyoung Shim<[email protected]>Signed-off-by Kyungmin Park<[email protected]>
Reviewed-by Sylwester Nawrocki <[email protected]>
Tested-by Sylwester Nawrocki <[email protected]>
PATCH 2/2 gpio/exynos: Add support for Exynos4x12 SoC
In reply to Joonyoung ShimQuoted 58 lines · Joonyoung Shim
Add to cc Grant Likely and Linus Walleij
Quoted 54 lines · Joonyoung Shim
Exynos4x12 GPIO part1 and part2 layouts are different with that of Exynos4210. So, it needs to support gpios for Exynos4x12 SoC. This doesn't support GPVx Exynos4x12 GPIO part4 yet.
In the Exynos4x12 GPIO part1 and part2, the interval of base register offset is
0x20but GPF0, GPJ0, GPK0 and GPM0 ignore the0x20interval and have new value. The interrupt reg offset also is about GPF0 and GPK0 too. Refer the below layout.- Exynos4x12 GPIO Part1
GPIO Base offset Interrupt reg offset GPA0 0x000 0x00 GPA1 0x020 0x04 GPB 0x040 0x08 GPC0 0x060 0x0C GPC1 0x080 0x10 GPD0 0x0A0 0x14 GPD1 0x0C0 0x18 ... GPF0 0x180 0x30 GPF1 0x1A0 0x34 GPF2 0x1C0 0x38 GPF3 0x1E0 0x3C ... GPJ0 0x240 0x40 GPJ1 0x260 0x44- Exynos4x12 GPIO Part2
... GPK0 0x040 0x08 GPK1 0x060 0x0C GPK2 0x080 0x10 GPK3 0x0A0 0x14 GPL0 0x0C0 0x18 GPL1 0x0E0 0x1C GPL2 0x100 0x20 GPY0 0x120 x GPY1 0x140 x GPY2 0x160 x GPY3 0x180 x GPY4 0x1A0 x GPY5 0x1C0 x GPY6 0x1E0 x ... GPM0 0x260 0x24 GPM1 0x280 0x28 GPM2 0x2A0 0x2C GPM3 0x2C0 0x30 GPM4 0x2E0 0x34 GPX0 0xC00 x GPX1 0xC20 x GPX2 0xC40 x GPX3 0xC60 x
Quoted 8 lines
Quoted 6 lines
Signed-off-by Joonyoung Shim<[email protected]>Signed-off-by Kyungmin Park<[email protected]>--- arch/arm/mach-exynos/include/mach/gpio.h | 28 +++- arch/arm/mach-exynos/include/mach/irqs.h | 6 - drivers/gpio/gpio-samsung.c | 334+++++++++++++++++++++++++++---
Quoted 1 line
3 files changed, 327 insertions(+), 41 deletions(-)
See my comments on 1/2 patch.
Thanks.
Best regards,
Kgene.
--
Kukjin Kim <[email protected]>, Senior Engineer, SW Solution Development Team, Samsung Electronics Co., Ltd.