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powerpc/p1022ds: add support for SPI and SD boot

PATCH New Timur Tabi 4 participants 8 messages May 18, 2012 – Aug 9, 2012

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Timur Tabi

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#0 lore raw

PATCH 1/2 powerpc/p1022ds: add support for SPI and SD boot

From: Matthew McClintock <[email protected]>

Add TLB mappings, board target options, and configuration items need for SPI/SD boot.

Since P1022DS RevB board, the NOR flash have been changed to 16 bit/28bit address flash, therefore, when SDHC/ESPI booting and access to eLBC, the PMUXCR[0~1] must be set to 10b, and PMUXCR[9~10] must be set to 00b for them.

Configure the PX_BRDCFG0[0~1] to 10b which is connected to SPI devices as SPI_CS(0:3)_B.

Signed-off-by Matthew McClintock <[email protected]>
Signed-off-by Jerry Huang <[email protected]>
Signed-off-by Jiang Yutang <[email protected]>
---
 board/freescale/p1022ds/p1022ds.c |    4 +++
 board/freescale/p1022ds/tlb.c     |   14 ++++++++++
 boards.cfg                        |    4 +++
 include/configs/P1022DS.h         |   51 ++++++++++++++++++++++++++++++++++--
 4 files changed, 70 insertions(+), 3 deletions(-)
board/freescale/p1022ds/p1022ds.c +4 -0
index aca30f3..37531b4 100644
@@ -39,6 +39,10 @@ int board_early_init_f(void)
 
 	/* Set pmuxcr to allow both i2c1 and i2c2 */
 	setbits_be32(&gur->pmuxcr, 0x1000);
+#ifdef CONFIG_SYS_RAMBOOT
+	setbits_be32(&gur->pmuxcr,
+		in_be32(&gur->pmuxcr) | MPC85xx_PMUXCR_SD_DATA);
+#endif
 
 	/* Read back the register to synchronize the write. */
 	in_be32(&gur->pmuxcr);
board/freescale/p1022ds/tlb.c +14 -0
index e620112..71e71f7 100644
@@ -71,6 +71,20 @@ struct fsl_e_tlb_entry tlb_table[] = {
 	SET_TLB_ENTRY(1, PIXIS_BASE, PIXIS_BASE_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 7, BOOKE_PAGESZ_4K, 1),
+
+#ifdef CONFIG_SYS_RAMBOOT
+	/* *I*G - eSDHC/eSPI/NAND boot */
+	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
+			MAS3_SX|MAS3_SW|MAS3_SR, 0,
+			0, 8, BOOKE_PAGESZ_1G, 1),
+
+	/* map the second 1G */
+	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
+			CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
+			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+			0, 9, BOOKE_PAGESZ_1G, 1),
+#endif
+#
 };
 
 int num_tlb_entries = ARRAY_SIZE(tlb_table);
boards.cfg +4 -0
index 7194e08..42e5ae0 100644
@@ -699,6 +699,10 @@ P1021RDB-PC_NAND             powerpc     mpc85xx     p1_p2_rdb_pc        freesca
 P1021RDB-PC_SDCARD           powerpc     mpc85xx     p1_p2_rdb_pc        freescale      -           p1_p2_rdb_pc:P1021RDB,SDCARD
 P1021RDB-PC_SPIFLASH         powerpc     mpc85xx     p1_p2_rdb_pc        freescale      -           p1_p2_rdb_pc:P1021RDB,SPIFLASH
 P1022DS                      powerpc     mpc85xx     p1022ds             freescale
+P1022DS_SPIFLASH             powerpc     mpc85xx     p1022ds             freescale	-	    P1022DS:SPIFLASH
+P1022DS_36BIT_SPIFLASH       powerpc     mpc85xx     p1022ds             freescale	-	    P1022DS:36BIT,SPIFLASH
+P1022DS_SDCARD               powerpc     mpc85xx     p1022ds             freescale	-	    P1022DS:SDCARD
+P1022DS_36BIT_SDCARD         powerpc     mpc85xx     p1022ds             freescale	-	    P1022DS:36BIT,SDCARD
 P1022DS_36BIT                powerpc     mpc85xx     p1022ds             freescale      -           P1022DS:36BIT
 P1023RDS                     powerpc     mpc85xx     p1023rds            freescale      -           P1023RDS
 P1023RDS_NAND                powerpc     mpc85xx     p1023rds            freescale      -           P1023RDS:NAND
include/configs/P1022DS.h +48 -3

65 lines not on this page · raw message

Signature · 1 line
1.7.3.4
author
#1 lore raw

PATCH 2/2 powerpc/p1022ds: Add support for NAND and NAND boot

From: Matthew McClintock <[email protected]>

Add defines needed to access NAND, remove second flash bank that is actually connected to NAND.

Add nand booting support for P1022DS with hardcoded DDR config

Signed-off-by Matthew McClintock <[email protected]>
Signed-off-by Jerry Huang <[email protected]>
Signed-off-by Jiang Yutang <[email protected]>
---
 board/freescale/p1022ds/law.c                |    3 +
 board/freescale/p1022ds/tlb.c                |   25 +++--
 boards.cfg                                   |    2 +
 include/configs/P1022DS.h                    |  121 +++++++++++++++++++++--
 nand_spl/board/freescale/p1022ds/Makefile    |  137 ++++++++++++++++++++++++++
 nand_spl/board/freescale/p1022ds/nand_boot.c |  132 +++++++++++++++++++++++++
 6 files changed, 401 insertions(+), 19 deletions(-)
 create mode 100644 nand_spl/board/freescale/p1022ds/Makefile
 create mode 100644 nand_spl/board/freescale/p1022ds/nand_boot.c
board/freescale/p1022ds/law.c +3 -0
index b23b8f9..476069c 100644
@@ -16,6 +16,9 @@
 struct law_entry law_table[] = {
 	SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
 	SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC),
+#ifdef CONFIG_SYS_NAND_BASE_PHYS
+	SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
+#endif
 };
 
 int num_law_entries = ARRAY_SIZE(law_table);
board/freescale/p1022ds/tlb.c +16 -9
index 71e71f7..1301c78 100644
@@ -41,6 +41,18 @@ struct fsl_e_tlb_entry tlb_table[] = {
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 1, BOOKE_PAGESZ_1M, 1),
 
+#ifdef CONFIG_SYS_NAND_BASE
+	/* *I*G - NAND */
+	SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
+			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+			0, 10, BOOKE_PAGESZ_1M, 1),
+#endif
+
+	SET_TLB_ENTRY(1, PIXIS_BASE, PIXIS_BASE_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 7, BOOKE_PAGESZ_4K, 1),
+
+#ifndef CONFIG_NAND_SPL
 	/* W**G* - Flash/promjet, localbus */
 	/* This will be changed to *I*G* after relocation to RAM. */
 	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,

@@ -67,24 +79,19 @@ struct fsl_e_tlb_entry tlb_table[] = {
 	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_IO_VIRT, CONFIG_SYS_PCIE3_IO_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 6, BOOKE_PAGESZ_256K, 1),
-
-	SET_TLB_ENTRY(1, PIXIS_BASE, PIXIS_BASE_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 7, BOOKE_PAGESZ_4K, 1),
+#endif
 
 #ifdef CONFIG_SYS_RAMBOOT
 	/* *I*G - eSDHC/eSPI/NAND boot */
 	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
 			MAS3_SX|MAS3_SW|MAS3_SR, 0,
 			0, 8, BOOKE_PAGESZ_1G, 1),
-
-	/* map the second 1G */
+	/* *I*G - eSDHC/eSPI/NAND boot - second 1GB of memory */
 	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
-			CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
-			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+			 CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
+			MAS3_SX|MAS3_SW|MAS3_SR, 0,
 			0, 9, BOOKE_PAGESZ_1G, 1),
 #endif
-#
 };
 
 int num_tlb_entries = ARRAY_SIZE(tlb_table);
boards.cfg +2 -0
index 42e5ae0..418e5fe 100644
@@ -699,6 +699,8 @@ P1021RDB-PC_NAND             powerpc     mpc85xx     p1_p2_rdb_pc        freesca
 P1021RDB-PC_SDCARD           powerpc     mpc85xx     p1_p2_rdb_pc        freescale      -           p1_p2_rdb_pc:P1021RDB,SDCARD
 P1021RDB-PC_SPIFLASH         powerpc     mpc85xx     p1_p2_rdb_pc        freescale      -           p1_p2_rdb_pc:P1021RDB,SPIFLASH
 P1022DS                      powerpc     mpc85xx     p1022ds             freescale
+P1022DS_NAND                 powerpc     mpc85xx     p1022ds             freescale	-	    P1022DS:NAND
+P1022DS_36BIT_NAND           powerpc     mpc85xx     p1022ds             freescale	-	    P1022DS:36BIT,NAND
 P1022DS_SPIFLASH             powerpc     mpc85xx     p1022ds             freescale	-	    P1022DS:SPIFLASH
 P1022DS_36BIT_SPIFLASH       powerpc     mpc85xx     p1022ds             freescale	-	    P1022DS:36BIT,SPIFLASH
 P1022DS_SDCARD               powerpc     mpc85xx     p1022ds             freescale	-	    P1022DS:SDCARD
include/configs/P1022DS.h +111 -10

185 lines not on this page · raw message

nand_spl/board/freescale/p1022ds/Makefile new file +137 -0

137 lines not on this page · raw message

nand_spl/board/freescale/p1022ds/nand_boot.c new file +132 -0

132 lines not on this page · raw message

Signature · 1 line
1.7.3.4
NAK
#2 lore raw

PATCH 2/2 powerpc/p1022ds: Add support for NAND and NAND boot

include/configs/P1022DS.h line 138

Quoted 11 lines · Timur Tabi
include/configs/P1022DS.h +11 -0
+/* These are used when DDR doesn't use SPD.  */
+#define CONFIG_SYS_SDRAM_SIZE		2048
+#define CONFIG_SYS_SDRAM_SIZE_LAW	LAW_SIZE_2G
+#define CONFIG_SYS_DDR_CS0_BNDS		0x0000003F
+#define CONFIG_SYS_DDR_CS0_CONFIG	0x80014202
+#define CONFIG_SYS_DDR_CS1_BNDS		0x0040007F
+#define CONFIG_SYS_DDR_CS1_CONFIG	0x80014202
+#define CONFIG_SYS_DDR_TIMING_3		0x00010000
+#define CONFIG_SYS_DDR_TIMING_0		0x40110104
+#define CONFIG_SYS_DDR_TIMING_1		0x5c5bd746
+#define CONFIG_SYS_DDR_TIMING_2		0x0fa8d4ca

NACK, please use SPD.

Also please use the new SPL infrastructure.

-Scott

author
#3 lore raw

PATCH 2/2 powerpc/p1022ds: Add support for NAND and NAND boot

Quoted 3 lines · Scott Wood

NACK, please use SPD.

Also please use the new SPL infrastructure.

I'm just taking the patches as they are on the SDK and posting them. I have no idea how the new SPL infrastructure works.

If you're going to NACK this patch set, then I'm just going to drop them and work on something else.

Signature · 2 lines
Timur Tabi
Linux kernel developer at Freescale
#4 lore raw

PATCH 2/2 powerpc/p1022ds: Add support for NAND and NAND boot

Quoted 10 lines · Timur Tabi
Quoted 3 lines · Scott Wood

NACK, please use SPD.

Also please use the new SPL infrastructure.

I'm just taking the patches as they are on the SDK and posting them. ?I have no idea how the new SPL infrastructure works.

If you're going to NACK this patch set, then I'm just going to drop them and work on something else.

Upstream would need these... it's not trivial task.

-M

#5 lore raw

PATCH 1/2 powerpc/p1022ds: add support for SPI and SD boot

In reply to Timur Tabi

include/configs/P1022DS.h line 434

Quoted 5 lines · Timur Tabi
include/configs/P1022DS.h +5 -0
+#elif defined(CONFIG_NAND_U_BOOT)
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_SIZE		CONFIG_SYS_NAND_BLOCK_SIZE
+#define CONFIG_ENV_OFFSET	((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
+#define CONFIG_ENV_RANGE	(3 * CONFIG_ENV_SIZE)

What's this doing in the SPI/SD patch?

-Scott

#6 lore raw

PATCH 1/2 powerpc/p1022ds: add support for SPI and SD boot

Quoted 8 lines · Scott Wood

Review

Quoted 5 lines · Timur Tabi
(quoted diff) +5 -0
+#elif defined(CONFIG_NAND_U_BOOT)
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_SIZE ? ? ? ? ? ? ?CONFIG_SYS_NAND_BLOCK_SIZE
+#define CONFIG_ENV_OFFSET ? ?((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
+#define CONFIG_ENV_RANGE ? ? (3 * CONFIG_ENV_SIZE)

What's this doing in the SPI/SD patch?

My best guess on a patch from months ago is just trying to keep things in sync with other boards.

-M

Applied
#7 lore raw

PATCH 1/2 powerpc/p1022ds: add support for SPI and SD boot

In reply to Timur Tabi
Quoted 10 lines · Timur Tabi

From: Matthew McClintock <[email protected]>

Add TLB mappings, board target options, and configuration items need for SPI/SD boot.

Since P1022DS RevB board, the NOR flash have been changed to 16 bit/28bit address flash, therefore, when SDHC/ESPI booting and access to eLBC, the PMUXCR[0~1] must be set to 10b, and PMUXCR[9~10] must be set to 00b for them.

Quoted 6 lines

Configure the PX_BRDCFG0[0~1] to 10b which is connected to SPI devices as SPI_CS(0:3)_B.

Signed-off-by Matthew McClintock <[email protected]>
Signed-off-by Jerry Huang <[email protected]>
Signed-off-by Jiang Yutang <[email protected]>

Applied, thanks