net/designware: Consecutive writes to the same register to be avoided
PATCH v2 1/1 net/designware: Consecutive writes to the same register to be avoided
This commit is an add-on to f6c4191f. There are a few registers where consecutive writes to the same location should be avoided or have a delay.
According to Synopsys, here is a list of the registers and bit(s) where consecutive writes should be avoided or a delay is required:
DMA Registers:
Register 0 Bit 7
Register 6 All bits except for 24, 16-13, 2-1.
GMAC Registers:
Registers 0-3 All bits Registers 6-7 All bits Register 10 All bits Register 11 All bits except for 5-6. Registers 16-47 All bits Register 48 All bits except for 18-16, 14. Register 448 Bit 4. Register 459 Bits 0-3.
--- drivers/net/designware.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
drivers/net/designware.c +2 -2
@@ -163,8 +163,8 @@ static int dw_eth_init(struct eth_device *dev, bd_t *bis)writel (FIXEDBURST |PRIORXTX_41 |BURST_16 , &dma_p->busmode); -writel (FLUSHTXFIFO |readl (&dma_p->opmode), &dma_p->opmode); -writel (STOREFORWARD |TXSECONDFRAME , &dma_p->opmode); +writel (readl (&dma_p->opmode) |FLUSHTXFIFO |STOREFORWARD | +TXSECONDFRAME , &dma_p->opmode); conf =FRAMEBURSTENABLE |DISABLERXOWN ;
Signature · 1 line
1.7.9.5
PATCH v2 1/1 net/designware: Consecutive writes to the same register to be avoided
Quoted 31 lines · Dinh Nguyen
This commit is an add-on to
f6c4191f. There are a few registers where consecutive writes to the same location should be avoided or have a delay.According to Synopsys, here is a list of the registers and bit(s) where consecutive writes should be avoided or a delay is required:
DMA Registers:
Register 0 Bit 7
Register 6 All bits except for 24, 16-13, 2-1.GMAC Registers:
Registers 0-3 All bits Registers 6-7 All bits Register 10 All bits Register 11 All bits except for 5-6. Registers 16-47 All bits Register 48 All bits except for 18-16, 14. Register 448 Bit 4. Register 459 Bits 0-3.Reviewd-by Matthew Gerlach<[email protected]>Signed-off-by Dinh Nguyen<[email protected]>--- drivers/net/designware.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)drivers/net/designware.c +0
-0
drivers/net/designware.c static int dw_eth_init(struct eth_device *dev, bd_t *bis) · line 170
Quoted 10 lines
drivers/net/designware.c +2
-2@@ -163,8 +163,8 @@ static int dw_eth_init(struct eth_device *dev, bd_t *bis)writel (FIXEDBURST |PRIORXTX_41 |BURST_16 , &dma_p->busmode); -writel (FLUSHTXFIFO |readl (&dma_p->opmode),&dma_p->opmode); -writel (STOREFORWARD |TXSECONDFRAME ,&dma_p->opmode); +writel (readl (&dma_p->opmode) |FLUSHTXFIFO |STOREFORWARD | +TXSECONDFRAME ,&dma_p->opmode); conf =FRAMEBURSTENABLE |DISABLERXOWN ;
Joe Hershberger
AppliedPATCH v2 1/1 net/designware: Consecutive writes to the same register to be avoided
In reply to Dinh NguyenHi Dinh Nguyen,
Quoted 20 lines · Dinh Nguyen
This commit is an add-on to
f6c4191f. There are a few registers where consecutive writes to the same location should be avoided or have a delay.According to Synopsys, here is a list of the registers and bit(s) where consecutive writes should be avoided or a delay is required:
DMA Registers:
Register 0 Bit 7
Register 6 All bits except for 24, 16-13, 2-1.GMAC Registers:
Registers 0-3 All bits Registers 6-7 All bits Register 10 All bits Register 11 All bits except for 5-6. Registers 16-47 All bits Register 48 All bits except for 18-16, 14. Register 448 Bit 4. Register 459 Bits 0-3.
Quoted 3 lines
Reviewd-by Matthew Gerlach <[email protected]>Signed-off-by Dinh Nguyen <[email protected]>---
Applied to next, thanks.
-Joe