mx6: Avoid writing to read-only bits in imximage.cfg

PATCH New Vikram Narayanan 6 participants 14 messages Jun 12, 2012 – Jun 15, 2012 Arm i.MX and Layerscape

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Vikram Narayanan

author

2012-06-12 14:50 UTC #0 lore raw

PATCH 1/1 mx6: Avoid writing to read-only bits in imximage.cfg

If in case this is valid according to the latest datasheet, ignore this patch.

--
According to REV C manual, the register IOMUXC_IOMUXC_GPR4 has bits 4 and 5 read-only and the value is always set as zero. So write '0' to these bits instead of writing '1'.

Signed-off-by Vikram Narayanan <[email protected]>

Cc Jason Liu <[email protected]>

Cc Dirk Behme <[email protected]>

---
 board/freescale/mx6qarm2/imximage.cfg      |    2 +-
 board/freescale/mx6qsabrelite/imximage.cfg |    2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

board/freescale/mx6qarm2/imximage.cfg +1 -1

index ceecbf9..bf941a3 100644
@@ -167,7 +167,7 @@ DATA 4 0x020c407c 0x0F0000C3
 DATA 4 0x020c4080 0x000003FF
 
 # enable AXI cache for VDOA/VPU/IPU
-DATA 4 0x020e0010 0xF00000FF
+DATA 4 0x020e0010 0xF00000CF
 # set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7
 DATA 4 0x020e0018 0x007F007F
 DATA 4 0x020e001c 0x007F007F

board/freescale/mx6qsabrelite/imximage.cfg +1 -1

index c389427..62498ab 100644
@@ -164,7 +164,7 @@ DATA 4 0x020c407c 0x0F0000C3
 DATA 4 0x020c4080 0x000003FF
 
 # enable AXI cache for VDOA/VPU/IPU
-DATA 4 0x020e0010 0xF00000FF
+DATA 4 0x020e0010 0xF00000CF
 # set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7
 DATA 4 0x020e0018 0x007F007F
 DATA 4 0x020e001c 0x007F007F

Signature · 1 line

1.7.4.1

Dirk Behme

2012-06-12 15:05 UTC #1 lore raw

PATCH 1/1 mx6: Avoid writing to read-only bits in imximage.cfg

Quoted 6 lines · Vikram Narayanan

If in case this is valid according to the latest datasheet, ignore this patch.
--
According to REV C manual, the register IOMUXC_IOMUXC_GPR4 has bits 4 and 5 read-only and the value is always set as zero. So write '0' to these bits instead of writing '1'.

Jason, Fabio: What do you think? You should be the datasheet 'masters' ;)

Best regards

Dirk

Quoted 34 lines

Signed-off-by Vikram Narayanan <[email protected]>

Cc Jason Liu <[email protected]>

Cc Dirk Behme <[email protected]>

---
 board/freescale/mx6qarm2/imximage.cfg      |    2 +-
 board/freescale/mx6qsabrelite/imximage.cfg |    2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

board/freescale/mx6qarm2/imximage.cfg +1 -1

index ceecbf9..bf941a3 100644
@@ -167,7 +167,7 @@ DATA 4 0x020c407c 0x0F0000C3
 DATA 4 0x020c4080 0x000003FF
 
 # enable AXI cache for VDOA/VPU/IPU
-DATA 4 0x020e0010 0xF00000FF
+DATA 4 0x020e0010 0xF00000CF
 # set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7
 DATA 4 0x020e0018 0x007F007F
 DATA 4 0x020e001c 0x007F007F

board/freescale/mx6qsabrelite/imximage.cfg +1 -1

index c389427..62498ab 100644
@@ -164,7 +164,7 @@ DATA 4 0x020c407c 0x0F0000C3
 DATA 4 0x020c4080 0x000003FF
 
 # enable AXI cache for VDOA/VPU/IPU
-DATA 4 0x020e0010 0xF00000FF
+DATA 4 0x020e0010 0xF00000CF
 # set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7
 DATA 4 0x020e0018 0x007F007F
 DATA 4 0x020e001c 0x007F007F

Liu Hui-R64343

2012-06-13 02:55 UTC #2 lore raw

PATCH 1/1 mx6: Avoid writing to read-only bits in imximage.cfg

Quoted 9 lines

-----Original Message-----
From: Dirk Behme [mailto:dirk.behme at de.bosch.com]
Sent: Tuesday, June 12, 2012 11:05 PM
To: Fabio Estevam; Liu Hui-R64343
Cc: Vikram Narayanan; u-boot at lists.denx.de
Subject: Re: [U-Boot] [PATCH] mx6: Avoid writing to read-only bits in imximage.cfg
On 12.06.2012 16:50, Vikram Narayanan wrote:

Quoted 8 lines

Quoted 6 lines
If in case this is valid according to the latest datasheet, ignore this patch.
--
According to REV C manual, the register IOMUXC_IOMUXC_GPR4 has bits 4 and 5 read-only and the value is always set as zero.
So write '0' to these bits instead of writing '1'.
Jason, Fabio: What do you think? You should be the datasheet 'masters' ;)

Yes, according to the RM,
5
Reserved
This read-only field is reserved and always has the value 0. 4
Reserved
This read-only field is reserved and always has the value 0.

So, write 1 should have no effect.

Quoted 42 lines

Best regards
Dirk
board/freescale/mx6qarm2/imximage.cfg DATA 4 0x020c407c 0x0F0000C3 DATA 4
Quoted 14 lines
Signed-off-by Vikram Narayanan <[email protected]>
Cc Jason Liu <[email protected]>
Cc Dirk Behme <[email protected]>
---
 board/freescale/mx6qarm2/imximage.cfg      |    2 +-
 board/freescale/mx6qsabrelite/imximage.cfg |    2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)
board/freescale/mx6qarm2/imximage.cfg +0 -0
index ceecbf9..bf941a3 100644
@@ -167,7 +167,7 @@ DATA 4 0x020c407c 0x0F0000C3  DATA 4
0x020c4080
board/freescale/mx6qsabrelite/imximage.cfg DATA 4 0x020c407c 0x0F0000C3 DATA 4
Quoted 13 lines
0x000003FF
 # enable AXI cache for VDOA/VPU/IPU
board/freescale/mx6qarm2/imximage.cfg +1 -1
-DATA 4 0x020e0010 0xF00000FF
+DATA 4 0x020e0010 0xF00000CF
 # set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7  DATA 4 0x020e0018
0x007F007F DATA 4 0x020e001c 0x007F007F diff --git a/board/freescale/mx6qsabrelite/imximage.cfg b/board/freescale/mx6qsabrelite/imximage.cfg index c389427..62498ab 100644
board/freescale/mx6qsabrelite/imximage.cfg +0 -0
@@ -164,7 +164,7 @@ DATA 4 0x020c407c 0x0F0000C3  DATA 4
0x020c4080
Quoted 7 lines
0x000003FF
 # enable AXI cache for VDOA/VPU/IPU
board/freescale/mx6qsabrelite/imximage.cfg +1 -1
-DATA 4 0x020e0010 0xF00000FF
+DATA 4 0x020e0010 0xF00000CF
 # set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7  DATA 4 0x020e0018
0x007F007F DATA 4 0x020e001c 0x007F007F

Marek Vasut

2012-06-13 11:18 UTC #3 lore raw

PATCH 1/1 mx6: Avoid writing to read-only bits in imximage.cfg

Dear Liu Hui-R64343,

Quoted 27 lines

Quoted 12 lines
-----Original Message-----
From: Dirk Behme [mailto:dirk.behme at de.bosch.com]
Sent: Tuesday, June 12, 2012 11:05 PM
To: Fabio Estevam; Liu Hui-R64343
Cc: Vikram Narayanan; u-boot at lists.denx.de
Subject: Re: [U-Boot] [PATCH] mx6: Avoid writing to read-only bits in imximage.cfg
Quoted 3 lines · Vikram Narayanan
If in case this is valid according to the latest datasheet, ignore this patch.
Quoted 6 lines
Quoted 4 lines
--
According to REV C manual, the register IOMUXC_IOMUXC_GPR4 has bits 4 and 5 read-only and the value is always set as zero.
So write '0' to these bits instead of writing '1'.
Jason, Fabio: What do you think? You should be the datasheet 'masters' ;)
Yes, according to the RM,
5
Reserved
This read-only field is reserved and always has the value 0. 4
Reserved
This read-only field is reserved and always has the value 0.

Quoted 1 line

So, write 1 should have no effect.

I really dislike how "write 1 should have no effect" sounds. Can you please check with HW people?

[..]

Best regards,
Marek Vasut

Fabio Estevam

reviewer

2012-06-13 11:28 UTC #4 lore raw

PATCH 1/1 mx6: Avoid writing to read-only bits in imximage.cfg

Quoted 3 lines · Marek Vasut

I really dislike how "write 1 should have no effect" sounds. Can you please check with HW people?

I agree.

Jason, please check this with the design team.

Vikram's patch look correct.

Regards,

Fabio Estevam

Liu Hui-R64343

2012-06-13 11:31 UTC #5 lore raw

PATCH 1/1 mx6: Avoid writing to read-only bits in imximage.cfg

In reply to Marek Vasut

Hi, Marek,

Quoted 38 lines

-----Original Message-----
From: Marek Vasut [mailto:marex at denx.de]
Sent: Wednesday, June 13, 2012 7:18 PM
To: u-boot at lists.denx.de
Cc: Liu Hui-R64343; Dirk Behme; Fabio Estevam
Subject: Re: [U-Boot] [PATCH] mx6: Avoid writing to read-only bits in imximage.cfg
Dear Liu Hui-R64343,
Quoted 28 lines
Quoted 12 lines
-----Original Message-----
From: Dirk Behme [mailto:dirk.behme at de.bosch.com]
Sent: Tuesday, June 12, 2012 11:05 PM
To: Fabio Estevam; Liu Hui-R64343
Cc: Vikram Narayanan; u-boot at lists.denx.de
Subject: Re: [U-Boot] [PATCH] mx6: Avoid writing to read-only bits in imximage.cfg
Quoted 3 lines · Vikram Narayanan
If in case this is valid according to the latest datasheet, ignore this patch.
Quoted 7 lines
Quoted 4 lines
--
According to REV C manual, the register IOMUXC_IOMUXC_GPR4 has bits 4 and 5 read-only and the value is always set as zero. So write '0' to these bits instead of writing '1'.
Jason, Fabio: What do you think? You should be the datasheet 'masters' ;)
Yes, according to the RM,
5
Reserved
This read-only field is reserved and always has the value 0. 4
Reserved
This read-only field is reserved and always has the value 0.

Quoted 4 lines

Quoted 1 line
So, write 1 should have no effect.
I really dislike how "write 1 should have no effect" sounds. Can you please check with HW people?

Since this is read-only bit, if you write 1 to it, it will have no effect.

Yes, to avoid the confusion, for example to do the read-back check, I agree with not writing '1' to the read-only bit.

Quoted 5 lines

[..]
Best regards,
Marek Vasut

Marek Vasut

2012-06-13 12:24 UTC #6 lore raw

PATCH 1/1 mx6: Avoid writing to read-only bits in imximage.cfg

Dear Liu Hui-R64343,

[...]

Quoted 15 lines

Quoted 15 lines
Quoted 15 lines
Quoted 6 lines
Quoted 3 lines
According to REV C manual, the register IOMUXC_IOMUXC_GPR4 has bits 4 and 5 read-only and the value is always set as zero. So write '0' to these bits instead of writing '1'.
Jason, Fabio: What do you think? You should be the datasheet 'masters' ;)
Yes, according to the RM,
5
Reserved
This read-only field is reserved and always has the value 0. 4
Reserved
This read-only field is reserved and always has the value 0.

Quoted 6 lines

Quoted 4 lines
Quoted 1 line
So, write 1 should have no effect.
I really dislike how "write 1 should have no effect" sounds. Can you please check with HW people?
Since this is read-only bit, if you write 1 to it, it will have no effect.

For how long do you work with hardware? Did it never occur to you that when you wrote 1 to an "reserved" bit, it either did something you didn't expect or you had to rework it later because the new CPU has that bit for something else?

Quoted 2 lines

Yes, to avoid the confusion, for example to do the read-back check, I agree with not writing '1' to the read-only bit.

Please, ask the hardware people about this.

Quoted 4 lines

Quoted 4 lines
[..]
Best regards,
Marek Vasut

Best regards,
Marek Vasut

Liu Hui-R64343

2012-06-13 13:15 UTC #7 lore raw

PATCH 1/1 mx6: Avoid writing to read-only bits in imximage.cfg

Hi, Marek,

Quoted 40 lines

-----Original Message-----
From: Marek Vasut [mailto:marex at denx.de]
Sent: Wednesday, June 13, 2012 8:25 PM
To: u-boot at lists.denx.de
Cc: Liu Hui-R64343; Dirk Behme
Subject: Re: [U-Boot] [PATCH] mx6: Avoid writing to read-only bits in imximage.cfg
Dear Liu Hui-R64343,
[...]
Quoted 16 lines
Quoted 16 lines
Quoted 16 lines
Quoted 7 lines
Quoted 4 lines
According to REV C manual, the register IOMUXC_IOMUXC_GPR4 has bits
4 and 5 read-only and the value is always set as zero. So write '0' to these bits instead of writing '1'.
Jason, Fabio: What do you think? You should be the datasheet 'masters' ;)
Yes, according to the RM,
5
Reserved
This read-only field is reserved and always has the value 0. 4
Reserved
This read-only field is reserved and always has the value 0.
Quoted 6 lines
Quoted 4 lines
Quoted 1 line
So, write 1 should have no effect.
I really dislike how "write 1 should have no effect" sounds. Can you please check with HW people?
Since this is read-only bit, if you write 1 to it, it will have no effect.
For how long do you work with hardware? Did it never occur to you that when you wrote 1 to an "reserved" bit, it either did something you didn't expect or you had to rework it later because the new CPU has that bit for something else?

Quoted 4 lines

Quoted 2 lines
Yes, to avoid the confusion, for example to do the read-back check, I agree with not writing '1' to the read-only bit.
Please, ask the hardware people about this.

Yes, I will and back to you.

Quoted 8 lines

Quoted 5 lines
Quoted 5 lines
[..]
Best regards,
Marek Vasut
Best regards,
Marek Vasut

Marek Vasut

2012-06-13 13:21 UTC #8 lore raw

PATCH 1/1 mx6: Avoid writing to read-only bits in imximage.cfg

Dear Liu Hui-R64343,

Quoted 43 lines

Hi, Marek,
Quoted 41 lines
-----Original Message-----
From: Marek Vasut [mailto:marex at denx.de]
Sent: Wednesday, June 13, 2012 8:25 PM
To: u-boot at lists.denx.de
Cc: Liu Hui-R64343; Dirk Behme
Subject: Re: [U-Boot] [PATCH] mx6: Avoid writing to read-only bits in imximage.cfg
Dear Liu Hui-R64343,
[...]
Quoted 16 lines
Quoted 16 lines
Quoted 16 lines
Quoted 7 lines
Quoted 4 lines
According to REV C manual, the register IOMUXC_IOMUXC_GPR4 has bits
4 and 5 read-only and the value is always set as zero. So write '0' to these bits instead of writing '1'.
Jason, Fabio: What do you think? You should be the datasheet 'masters' ;)
Yes, according to the RM,
5
Reserved
This read-only field is reserved and always has the value 0. 4
Reserved
This read-only field is reserved and always has the value 0.
Quoted 7 lines
Quoted 4 lines
Quoted 1 line
So, write 1 should have no effect.
I really dislike how "write 1 should have no effect" sounds. Can you please check with HW people?
Since this is read-only bit, if you write 1 to it, it will have no effect.
For how long do you work with hardware? Did it never occur to you that when you wrote 1 to an "reserved" bit, it either did something you didn't expect or you had to rework it later because the new CPU has that bit for something else?

Quoted 6 lines

Quoted 4 lines
Quoted 2 lines
Yes, to avoid the confusion, for example to do the read-back check, I agree with not writing '1' to the read-only bit.
Please, ask the hardware people about this.
Yes, I will and back to you.

Thanks!

btw. sorry, I didn't meant to offend you.

Best regards,
Marek Vasut

Marek Vasut

2012-06-13 12:27 UTC #9 lore raw

PATCH 1/1 mx6: Avoid writing to read-only bits in imximage.cfg

In reply to Vikram Narayanan

Dear Vikram Narayanan,

Quoted 7 lines

If in case this is valid according to the latest datasheet, ignore this patch.
--
According to REV C manual, the register IOMUXC_IOMUXC_GPR4 has bits 4 and 5 read-only and the value is always set as zero. So write '0' to these bits instead of writing '1'.

I'm acking this as writing 0 to read-only bits is the only rightous thing to do. btw. how did you find this? Good catch, praise on you :-)

Acked-by Marek Vasut <[email protected]>

Quoted 26 lines

Signed-off-by Vikram Narayanan <[email protected]>
Cc Jason Liu <[email protected]>
Cc Dirk Behme <[email protected]>
---
 board/freescale/mx6qarm2/imximage.cfg      |    2 +-
 board/freescale/mx6qsabrelite/imximage.cfg |    2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)
(quoted diff) +0 -0
b/board/freescale/mx6qarm2/imximage.cfg index ceecbf9..bf941a3 100644
board/freescale/mx6qarm2/imximage.cfg +1 -1
@@ -167,7 +167,7 @@ DATA 4 0x020c407c 0x0F0000C3
 DATA 4 0x020c4080 0x000003FF
 
 # enable AXI cache for VDOA/VPU/IPU
-DATA 4 0x020e0010 0xF00000FF
+DATA 4 0x020e0010 0xF00000CF
 # set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7
 DATA 4 0x020e0018 0x007F007F
 DATA 4 0x020e001c 0x007F007F
(quoted diff) +0 -0
b/board/freescale/mx6qsabrelite/imximage.cfg index c389427..62498ab 100644

board/freescale/mx6qsabrelite/imximage.cfg DATA 4 0x020c407c 0x0F0000C3 · line 170

Quoted 8 lines

board/freescale/mx6qsabrelite/imximage.cfg +1 -1

@@ -164,7 +164,7 @@ DATA 4 0x020c407c 0x0F0000C3
 DATA 4 0x020c4080 0x000003FF
 
 # enable AXI cache for VDOA/VPU/IPU
-DATA 4 0x020e0010 0xF00000FF
+DATA 4 0x020e0010 0xF00000CF
 # set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7
 DATA 4 0x020e0018 0x007F007F
 DATA 4 0x020e001c 0x007F007F

Best regards,
Marek Vasut

Vikram Narayanan

author

2012-06-13 16:38 UTC #10 lore raw

PATCH 1/1 mx6: Avoid writing to read-only bits in imximage.cfg

Hello Marek,

Quoted 5 lines · Marek Vasut

Dear Vikram Narayanan,
Quoted 3 lines
If in case this is valid according to the latest datasheet, ignore this patch.

Quoted 7 lines

Quoted 4 lines
--
According to REV C manual, the register IOMUXC_IOMUXC_GPR4 has bits 4 and 5 read-only and the value is always set as zero. So write '0' to these bits instead of writing '1'.
I'm acking this as writing 0 to read-only bits is the only rightous thing to do. btw. how did you find this? Good catch, praise on you :-)

:)
In the middle of writing a imximage.cfg file for a custom mx6 board.

Regards,
Vikram

Quoted 39 lines

Acked-by Marek Vasut<[email protected]>
Quoted 26 lines
Signed-off-by Vikram Narayanan<[email protected]>
Cc Jason Liu<[email protected]>
Cc Dirk Behme<[email protected]>
---
  board/freescale/mx6qarm2/imximage.cfg      |    2 +-
  board/freescale/mx6qsabrelite/imximage.cfg |    2 +-
  2 files changed, 2 insertions(+), 2 deletions(-)
(quoted diff) +0 -0
b/board/freescale/mx6qarm2/imximage.cfg index ceecbf9..bf941a3 100644
board/freescale/mx6qarm2/imximage.cfg +1 -1
@@ -167,7 +167,7 @@ DATA 4 0x020c407c 0x0F0000C3
  DATA 4 0x020c4080 0x000003FF
 
  # enable AXI cache for VDOA/VPU/IPU
-DATA 4 0x020e0010 0xF00000FF
+DATA 4 0x020e0010 0xF00000CF
  # set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7
  DATA 4 0x020e0018 0x007F007F
  DATA 4 0x020e001c 0x007F007F
(quoted diff) +0 -0
b/board/freescale/mx6qsabrelite/imximage.cfg index c389427..62498ab 100644
board/freescale/mx6qsabrelite/imximage.cfg DATA 4 0x020c407c 0x0F0000C3 · line 170
Quoted 8 lines
board/freescale/mx6qsabrelite/imximage.cfg +1 -1
@@ -164,7 +164,7 @@ DATA 4 0x020c407c 0x0F0000C3
  DATA 4 0x020c4080 0x000003FF
 
  # enable AXI cache for VDOA/VPU/IPU
-DATA 4 0x020e0010 0xF00000FF
+DATA 4 0x020e0010 0xF00000CF
  # set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7
  DATA 4 0x020e0018 0x007F007F
  DATA 4 0x020e001c 0x007F007F
Best regards,
Marek Vasut

Marek Vasut

2012-06-13 17:15 UTC #11 lore raw

PATCH 1/1 mx6: Avoid writing to read-only bits in imximage.cfg

Dear Vikram Narayanan,

Quoted 13 lines

Hello Marek,
Quoted 10 lines · Marek Vasut
Dear Vikram Narayanan,
Quoted 7 lines
If in case this is valid according to the latest datasheet, ignore this patch.
--
According to REV C manual, the register IOMUXC_IOMUXC_GPR4 has bits 4 and 5 read-only and the value is always set as zero. So write '0' to these bits instead of writing '1'.

Quoted 6 lines

Quoted 2 lines
I'm acking this as writing 0 to read-only bits is the only rightous thing to do. btw. how did you find this? Good catch, praise on you :-)
:
:)
In the middle of writing a imximage.cfg file for a custom mx6 board.

So it did manifest somehow?

Quoted 50 lines

Regards,
Vikram
Quoted 47 lines
Acked-by Marek Vasut<[email protected]>
Quoted 39 lines
Signed-off-by Vikram Narayanan<[email protected]>
Cc Jason Liu<[email protected]>
Cc Dirk Behme<[email protected]>
---
  board/freescale/mx6qarm2/imximage.cfg      |    2 +-
  board/freescale/mx6qsabrelite/imximage.cfg |    2 +-
  2 files changed, 2 insertions(+), 2 deletions(-)
(quoted diff) +0 -0
b/board/freescale/mx6qarm2/imximage.cfg index ceecbf9..bf941a3 100644
board/freescale/mx6qarm2/imximage.cfg +1 -1
@@ -167,7 +167,7 @@ DATA 4 0x020c407c 0x0F0000C3
 
  DATA 4 0x020c4080 0x000003FF
 
  # enable AXI cache for VDOA/VPU/IPU
 
-DATA 4 0x020e0010 0xF00000FF
+DATA 4 0x020e0010 0xF00000CF
 
  # set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7
  DATA 4 0x020e0018 0x007F007F
  DATA 4 0x020e001c 0x007F007F
(quoted diff) +0 -0
b/board/freescale/mx6qsabrelite/imximage.cfg index c389427..62498ab 100644 --- a/board/freescale/mx6qsabrelite/imximage.cfg +++ b/board/freescale/mx6qsabrelite/imximage.cfg
board/freescale/mx6qarm2/imximage.cfg +1 -1
@@ -164,7 +164,7 @@ DATA 4 0x020c407c 0x0F0000C3
 
  DATA 4 0x020c4080 0x000003FF
 
  # enable AXI cache for VDOA/VPU/IPU
 
-DATA 4 0x020e0010 0xF00000FF
+DATA 4 0x020e0010 0xF00000CF
 
Quoted 3 lines
  # set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7
  DATA 4 0x020e0018 0x007F007F
  DATA 4 0x020e001c 0x007F007F
Best regards,
Marek Vasut

Best regards,
Marek Vasut

Vikram Narayanan

author

2012-06-13 17:40 UTC #12 lore raw

PATCH 1/1 mx6: Avoid writing to read-only bits in imximage.cfg

Hello Marek,

Quoted 15 lines · Marek Vasut

Dear Vikram Narayanan,
Quoted 13 lines
Hello Marek,
Quoted 10 lines · Marek Vasut
Dear Vikram Narayanan,
Quoted 7 lines
If in case this is valid according to the latest datasheet, ignore this patch.
--
According to REV C manual, the register IOMUXC_IOMUXC_GPR4 has bits 4 and 5 read-only and the value is always set as zero. So write '0' to these bits instead of writing '1'.

Quoted 8 lines

Quoted 6 lines
Quoted 2 lines
I'm acking this as writing 0 to read-only bits is the only rightous thing to do. btw. how did you find this? Good catch, praise on you :-)
:
:)
In the middle of writing a imximage.cfg file for a custom mx6 board.
So it did manifest somehow?

Still in progress. :)

Regards,
Vikram

Stefano Babic

2012-06-15 14:27 UTC #13 lore raw

PATCH 1/1 mx6: Avoid writing to read-only bits in imximage.cfg

In reply to Vikram Narayanan

Quoted 11 lines · Vikram Narayanan

If in case this is valid according to the latest datasheet, ignore this patch.
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According to REV C manual, the register IOMUXC_IOMUXC_GPR4 has bits 4 and 5 read-only and the value is always set as zero. So write '0' to these bits instead of writing '1'.
Signed-off-by Vikram Narayanan <[email protected]>
Cc Jason Liu <[email protected]>
Cc Dirk Behme <[email protected]>
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Applied to u-boot-imx, thanks.

Best regards,
Stefano Babic

Signature · 5 lines

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