ARM: at91: moving at91 to the common clk framework

index 98a42f3..b2686c6 100644
@@ -489,6 +489,7 @@ comment "Generic Board Type"
 config MACH_AT91SAM_DT
 	bool "Atmel AT91SAM Evaluation Kits with device-tree support"
 	select USE_OF
+	select COMMON_CLK
 	help
 	  Select this if you want to experiment device-tree with
 	  an Atmel Evaluation Kit.

index 79d0f60..29f8812 100644
@@ -6,8 +6,11 @@ obj-y		:= irq.o gpio.o setup.o
 obj-m		:=
 obj-n		:=
 obj-		:=
-
+ifeq ($(CONFIG_COMMON_CLK),y)
+obj-$(CONFIG_AT91_PMC_UNIT)	+= pmc-osc.o pmc-pll.o pmc-master.o pmc-sys.o pmc-periph.o pmc-prog.o pmc.o
+else
 obj-$(CONFIG_AT91_PMC_UNIT)	+= clock.o
+endif
 obj-$(CONFIG_AT91_SAM9_ALT_RESET) += at91sam9_alt_reset.o
 obj-$(CONFIG_AT91_SAM9G45_RESET) += at91sam9g45_reset.o
 obj-$(CONFIG_SOC_AT91SAM9)	+= at91sam926x_time.o sam9_smc.o

index f4605ff..a5379cd 100644
@@ -64,8 +64,305 @@
 			};
 
 			pmc: pmc at fffffc00 {
-				compatible = "atmel,at91rm9200-pmc";
+				compatible = "atmel,at91-pmc";
+				#address-cells = <1>;
+				#size-cells = <0>;
 				reg = <0xfffffc00 0x100>;
+				interrupts = <1 4>;
+
+				capabilities = <0xf031f77 0x1>; /*	SC{ER,DR,SR}, PC{ER,DR,SR}, MOR,
+													MCFR, PLL{AR,BR}, MCKR, PCK{0,1},
+													I{ER,DR,SR,MR}, PLLICPR */
+
+
+				slow: osc at 0 {
+					compatible = "atmel,at91-pmc-slow", "fixed-rate";
+					reg = <0>;
+					clock-frequency = <32768>;
+					#clock-cells = <0>;
+					clock-output-names = "slow";
+
+					characteristics {
+						output = <22000 42000>;
+					};
+				};
+
+				main: osc at 1 {
+					compatible = "atmel,at91-pmc-main", "fixed-rate";
+					reg = <1>;
+
+					#clock-cells = <0>;
+					clock-output-names = "main";
+
+					characteristics {
+						output = <3000000 20000000>;
+					};
+				};
+
+				plla: pll at 0 {
+					compatible = "atmel,at91-pmc-pll";
+					reg = <0>;
+
+					#clock-cells = <0>;
+					clocks = <&main>;
+					clock-output-names = "plla";
+
+					mask = <0xf8000000>;
+
+					characteristics {
+						input = <1000000 32000000>;
+						output = <
+								0 0 /* icpll = 0, out = 0 => no such conf*/
+								0 0 /* icpll = 0, out = 1 => no such conf*/
+								0 0 /* icpll = 0, out = 2 => no such conf*/
+								0 0 /* icpll = 0, out = 3 => no such conf*/
+								80000000 160000000 /* icpll = 1, out = 0 => 80 to 160MHz */
+								0 0 /* icpll = 1, out = 1 => no such conf*/
+								150000000 240000000 /* icpll = 1, out = 2 => 80 to 160MHz */
+								0 0 /* icpll = 1, out = 3 => no such conf*/
+							 >;
+					};
+
+				};
+
+				pllb: pll at 1 {
+					compatible = "atmel,at91-pmc-pll";
+					reg = <1>;
+
+					#clock-cells = <0>;
+					clocks = <&main>;
+					clock-output-names = "pllb";
+
+					mask = <0xf8000000>;
+
+					characteristics {
+						input = <1000000 32000000>;
+						output = <
+								0 0 /* icpll = 0, out = 0 => no such conf*/
+								0 0 /* icpll = 0, out = 1 => no such conf*/
+								0 0 /* icpll = 0, out = 2 => no such conf*/
+								0 0 /* icpll = 0, out = 3 => no such conf*/
+								80000000 160000000 /* icpll = 1, out = 0 => 80 to 160MHz */
+								0 0 /* icpll = 1, out = 1 => no such conf*/
+								150000000 240000000 /* icpll = 1, out = 2 => 80 to 160MHz */
+								0 0 /* icpll = 0, out = 3 => no such conf*/
+							 >;
+					};
+
+				};
+
+				pres: master at 0 {
+					compatible = "atmel,at91-pmc-pres";
+					offset = <0x2>;
+
+					#clock-cells = <0>;
+					clocks = <&slow>, <&main>, <&plla>, <&pllb>;
+					clock-output-names = "pres";
+				};
+
+				master: master at 1 {
+					compatible = "atmel,at91-pmc-master";
+					divisors = <1 2 4 6>;
+
+					#clock-cells = <0>;
+					clocks = <&pres>;
+					clock-output-names = "mck";
+
+					lookup at 0 {
+						compatible = "clk-lookup";
+						conid = "mck";
+					};
+
+					lookup at 1 {
+						compatible = "clk-lookup";
+						condid = "usart";
+						devid = "fffff200.serial";
+					};
+
+					characteristics {
+						output = <0 94500000>; /* master clock range at 1.65V*/
+					};
+
+				};
+
+				proc: sys at 0 {
+					compatible = "atmel,at91-pmc-proc";
+					divisor;
+
+					#clock-cells = <0>;
+					clocks = <&pres>;
+					clock-output-names = "proc";
+
+					characteristics {
+						output = <0 189000000>; /* proc clock range at 1.65V*/
+					};
+
+				};
+
+				prog0: sys at 8 {
+					compatible = "atmel,at91-pmc-prog", "atmel,at91-pmc-sys";
+					reg = <8>;
+					css-length = <2>;
+					pres-offset = <2>;
+
+					#clock-cells = <0>;
+					clocks = <&slow>, <&main>, <&plla>, <&pllb>;
+					clock-output-names = "prog0";
+
+				};
+
+				prog1: sys at 9 {
+					compatible = "atmel,at91-pmc-prog", "atmel,at91-pmc-sys";
+					reg = <9>;
+					css-length = <2>;
+					pres-offset = <2>;
+
+					#clock-cells = <0>;
+					clocks = <&slow>, <&main>, <&plla>, <&pllb>;
+					clock-output-names = "prog1";
+
+				};
+
+				usart0ck: periph at 6 {
+					compatible = "atmel,at91-pmc-periph";
+					reg = <6>;
+
+					#clock-cells = <0>;
+					clocks = <&master>;
+
+					clock-output-names = "fffb0000.serial";
+
+					lookup at 0 {
+						compatible = "clk-lookup";
+						conid = "usart";
+						devid = "fffb0000.serial";
+					};
+				};
+
+				usart1ck: periph at 7 {
+					compatible = "atmel,at91-pmc-periph";
+					reg = <7>;
+
+					#clock-cells = <0>;
+					clocks = <&master>;
+
+					clock-output-names = "fffb4000.serial";
+
+					lookup at 0 {
+						compatible = "clk-lookup";
+						conid = "usart";
+						devid = "fffb4000.serial";
+					};
+				};
+
+				usart2ck: periph at 8 {
+					compatible = "atmel,at91-pmc-periph";
+					reg = <8>;
+
+					#clock-cells = <0>;
+					clocks = <&master>;
+
+					clock-output-names = "fffb8000.serial";
+
+					lookup at 0 {
+						compatible = "clk-lookup";
+						conid = "usart";
+						devid = "fffb8000.serial";
+					};
+				};
+
+				usart3ck: periph at 23 {
+					compatible = "atmel,at91-pmc-periph";
+					reg = <23>;
+
+					#clock-cells = <0>;
+					clocks = <&master>;
+
+					clock-output-names = "fffd0000.serial";
+
+					lookup at 0 {
+						compatible = "clk-lookup";
+						conid = "usart";
+						devid = "fffd0000.serial";
+					};
+				};
+
+				usart4ck: periph at 24 {
+					compatible = "atmel,at91-pmc-periph";
+					reg = <24>;
+
+					#clock-cells = <0>;
+					clocks = <&master>;
+
+					clock-output-names = "fffd4000.serial";
+
+					lookup at 0 {
+						compatible = "clk-lookup";
+						conid = "usart";
+						devid = "fffd4000.serial";
+					};
+				};
+
+				usart5ck: periph at 25 {
+					compatible = "atmel,at91-pmc-periph";
+					reg = <25>;
+
+					#clock-cells = <0>;
+					clocks = <&master>;
+
+					clock-output-names = "fffd8000.serial";
+
+					lookup at 0 {
+						compatible = "clk-lookup";
+						conid = "usart";
+						devid = "fffd8000.serial";
+					};
+				};
+
+				pioAck: periph at 2 {
+					compatible = "atmel,at91-pmc-periph";
+					reg = <2>;
+
+					#clock-cells = <0>;
+					clocks = <&master>;
+
+					clock-output-names = "pioA";
+
+					lookup at 0 {
+						compatible = "clk-lookup";
+						conid = "pioA";
+					};
+				};
+
+				pioBck: periph at 3 {
+					compatible = "atmel,at91-pmc-periph";
+					reg = <3>;
+
+					#clock-cells = <0>;
+					clocks = <&master>;
+
+					clock-output-names = "pioB";
+
+					lookup at 0 {
+						compatible = "clk-lookup";
+						conid = "pioB";
+					};
+				};
+
+				pioCck: periph at 4 {
+					compatible = "atmel,at91-pmc-periph";
+					reg = <4>;
+
+					#clock-cells = <0>;
+					clocks = <&master>;
+
+					clock-output-names = "pioC";
+
+					lookup at 0 {
+						compatible = "clk-lookup";
+						conid = "pioC";
+					};
+				};
 			};
 
 			rstc at fffffd00 {

48 lines not on this page · raw message