ARM:Orion5x: Fix panic at boot for PCI IO reservation

Orion5x, and all other orion based systems have a PCI(E) IO window size of 1Mbyte. Recent changes to mach/io.h mean that by default the kernel does not allow such large windows, it refuses to reserve that much resource space, triggering a panic.

Reduce the PCI(E) IO window size to the normal 64K.

---
 arch/arm/mach-orion5x/include/mach/orion5x.h |    6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

index 2745f5d..2cdb12c 100644
@@ -43,12 +43,12 @@
 #define ORION5X_PCIE_IO_PHYS_BASE	0xf2000000
 #define ORION5X_PCIE_IO_VIRT_BASE	0xfde00000
 #define ORION5X_PCIE_IO_BUS_BASE	0x00000000
-#define ORION5X_PCIE_IO_SIZE		SZ_1M
+#define ORION5X_PCIE_IO_SIZE		SZ_64K
 
 #define ORION5X_PCI_IO_PHYS_BASE	0xf2100000
 #define ORION5X_PCI_IO_VIRT_BASE	0xfdf00000
-#define ORION5X_PCI_IO_BUS_BASE		0x00100000
-#define ORION5X_PCI_IO_SIZE		SZ_1M
+#define ORION5X_PCI_IO_BUS_BASE		0x00010000
+#define ORION5X_PCI_IO_SIZE		SZ_64K
 
 #define ORION5X_SRAM_PHYS_BASE		(0xf2200000)
 #define ORION5X_SRAM_SIZE		SZ_8K

1.7.10

It turns out this patch does not work...

There are two PCI devices on Orion5x. So the first one takes all the available 64K IO space and the second one fails it allocation.

We need to put back parts of mach/io.h to increase the available size to 128Kbytes.

It has been said in another email, the plan is to put the IO window at one fixed address. How will this work for devices with multiple PCI busses? Most Orion chips for have two separate PCI busses.

Thanks
Andrew

It supports up to 16 64K windows mapped into a 1MB area. So IO_RESOURCE_LIMIT will be 1MB in that case.

If the h/w can support i/o at 0, then it would be good make __io(x) be the form of ((x) + <host phys base>). Unfortunately, it seems the only way to figure this out is change it and see if it breaks people which isn't very nice.

Rob