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Exynos5: DDR3: Adding the DDR3 memory setup for Exynos5250 Rev 1.0

PATCH Superseded Rajeshwari Shinde 4 participants 8 messages Jun 20, 2012 – Jun 26, 2012

Subsystems (2)
Arm (32-bit) Arm Samsung Exynos

v2 of 6 Superseded Latest is v6 →

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Rajeshwari Shinde

author
#0 lore raw

PATCH v2 6/9 Exynos5: DDR3: Adding the DDR3 memory setup for Exynos5250 Rev 1.0

The patch adds the memory initialization sequence of DDR3.

Signed-off-by Hatim Ali <[email protected]>
Signed-off-by Rajeshwari Shinde <[email protected]>

---
Chnages in V2:
- None

 arch/arm/include/asm/arch-exynos/dmc.h |   65 +++++
 board/samsung/smdk5250/Makefile        |    2 +-
 board/samsung/smdk5250/dmc_common.c    |  199 ++++++++++++++
 board/samsung/smdk5250/dmc_init.c      |  462 --------------------------------
 board/samsung/smdk5250/dmc_init_ddr3.c |  228 ++++++++++++++++
 board/samsung/smdk5250/setup.h         |   59 ++++-
 6 files changed, 551 insertions(+), 464 deletions(-)
 create mode 100644 board/samsung/smdk5250/dmc_common.c
 delete mode 100644 board/samsung/smdk5250/dmc_init.c
 create mode 100644 board/samsung/smdk5250/dmc_init_ddr3.c
arch/arm/include/asm/arch-exynos/dmc.h +65 -0
index bd52d16..f65c676 100644
@@ -251,5 +251,70 @@ struct exynos5_phy_control {
 	unsigned int phy_con41;
 	unsigned int phy_con42;
 };
+
+enum ddr_mode {
+	DDR_MODE_DDR2,
+	DDR_MODE_DDR3,
+	DDR_MODE_LPDDR2,
+	DDR_MODE_LPDDR3,
+
+	DDR_MODE_COUNT,
+};
+
+enum mem_manuf {
+	MEM_MANUF_AUTODETECT,
+	MEM_MANUF_ELPIDA,
+	MEM_MANUF_SAMSUNG,
+
+	MEM_MANUF_COUNT,
+};
+
+/* CONCONTROL register fields */
+#define CONCONTROL_DFI_INIT_START_SHIFT	28
+#define CONCONTROL_RD_FETCH_SHIFT	12
+#define CONCONTROL_RD_FETCH_MASK	(0x7 << CONCONTROL_RD_FETCH_SHIFT)
+#define CONCONTROL_AREF_EN_SHIFT	5
+
+/* PRECHCONFIG register field */
+#define PRECHCONFIG_TP_CNT_SHIFT	24
+
+/* PWRDNCONFIG register field */
+#define PWRDNCONFIG_DPWRDN_CYC_SHIFT	0
+#define PWRDNCONFIG_DSREF_CYC_SHIFT	16
+
+/* PHY_CON0 register fields */
+#define PHY_CON0_T_WRRDCMD_SHIFT	17
+#define PHY_CON0_T_WRRDCMD_MASK		(0x7 << PHY_CON0_T_WRRDCMD_SHIFT)
+#define PHY_CON0_CTRL_DDR_MODE_SHIFT	11
+
+/* PHY_CON1 register fields */
+#define PHY_CON1_RDLVL_RDDATA_ADJ_SHIFT	0
+
+/* PHY_CON12 register fields */
+#define PHY_CON12_CTRL_START_POINT_SHIFT	24
+#define PHY_CON12_CTRL_INC_SHIFT	16
+#define PHY_CON12_CTRL_FORCE_SHIFT	8
+#define PHY_CON12_CTRL_START_SHIFT	6
+#define PHY_CON12_CTRL_START_MASK	(1 << PHY_CON12_CTRL_START_SHIFT)
+#define PHY_CON12_CTRL_DLL_ON_SHIFT	5
+#define PHY_CON12_CTRL_DLL_ON_MASK	(1 << PHY_CON12_CTRL_DLL_ON_SHIFT)
+#define PHY_CON12_CTRL_REF_SHIFT	1
+
+/* PHY_CON16 register fields */
+#define PHY_CON16_ZQ_MODE_DDS_SHIFT	24
+#define PHY_CON16_ZQ_MODE_DDS_MASK	(0x7 << PHY_CON16_ZQ_MODE_DDS_SHIFT)
+
+#define PHY_CON16_ZQ_MODE_TERM_SHIFT 21
+#define PHY_CON16_ZQ_MODE_TERM_MASK	(0x7 << PHY_CON16_ZQ_MODE_TERM_SHIFT)
+
+#define PHY_CON16_ZQ_MODE_NOTERM_MASK	(1 << 19)
+
+/* PHY_CON42 register fields */
+#define PHY_CON42_CTRL_BSTLEN_SHIFT	8
+#define PHY_CON42_CTRL_BSTLEN_MASK	(0xff << PHY_CON42_CTRL_BSTLEN_SHIFT)
+
+#define PHY_CON42_CTRL_RDLAT_SHIFT	0
+#define PHY_CON42_CTRL_RDLAT_MASK	(0x1f << PHY_CON42_CTRL_RDLAT_SHIFT)
+
 #endif
 #endif
board/samsung/smdk5250/Makefile +1 -1
index 3675fad..1474fa8 100644
@@ -27,7 +27,7 @@ LIB	= $(obj)lib$(BOARD).o
 SOBJS	:= lowlevel_init.o
 
 COBJS	:= clock_init.o
-COBJS	+= dmc_init.o
+COBJS	+= dmc_common.o dmc_init_ddr3.o
 COBJS	+= tzpc_init.o
 COBJS	+= smdk5250_spl.o
board/samsung/smdk5250/dmc_common.c new file +199 -0

199 lines not on this page · raw message

board/samsung/smdk5250/dmc_init.c deleted +0 -462

462 lines not on this page · raw message

board/samsung/smdk5250/dmc_init_ddr3.c new file +228 -0

228 lines not on this page · raw message

board/samsung/smdk5250/setup.h +58 -1

66 lines not on this page · raw message

Signature · 1 line
1.7.4.4
author
#1 lore raw

PATCH v2 7/9 EXYNOS5: CLOCK: Modify MPLL clock out for Exynos5250 Rev 1.0

MPLL clock-out of Exynos5250 Rev 1.0 is always at 1.6GHz. Adjust the divisor value to get 800MHz as needed by devices like UART etc

Signed-off-by Hatim Ali <[email protected]>
Signed-off-by Rajeshwari Shinde <[email protected]>

---
Chnages in V2:
- None

 arch/arm/cpu/armv7/exynos/clock.c        |   12 +++++++++++-
 arch/arm/include/asm/arch-exynos/clock.h |    3 +++
 2 files changed, 14 insertions(+), 1 deletions(-)
arch/arm/cpu/armv7/exynos/clock.c +11 -1
index 330bd75..dbd5f11 100644
@@ -98,7 +98,7 @@ static unsigned long exynos5_get_pll_clk(int pllreg)
 	struct exynos5_clock *clk =
 		(struct exynos5_clock *)samsung_get_base_clock();
 	unsigned long r, m, p, s, k = 0, mask, fout;
-	unsigned int freq;
+	unsigned int freq, pll_div2_sel,  mpll_fout_sel;
 
 	switch (pllreg) {
 	case APLL:

@@ -155,6 +155,16 @@ static unsigned long exynos5_get_pll_clk(int pllreg)
 		fout = m * (freq / (p * (1 << (s - 1))));
 	}
 
+	/* According to the user manual, in EVT1 MPLL always gives
+	 * 1.6GHz clock, so divide by 2 to get 800MHz MPLL clock.*/
+	if (pllreg == MPLL) {
+		pll_div2_sel = readl(&clk->pll_div2_sel);
+		mpll_fout_sel = (pll_div2_sel >> MPLL_FOUT_SEL_SHIFT)
+				& MPLL_FOUT_SEL_MASK;
+		if (mpll_fout_sel == 0)
+			fout /= 2;
+	}
+
 	return fout;
 }
arch/arm/include/asm/arch-exynos/clock.h +3 -0
index 7cc3d5e..a34a3f0 100644
@@ -594,4 +594,7 @@ struct exynos5_clock {
 	unsigned char	res109b[0xf5e4];
 };
 #endif
+
+#define MPLL_FOUT_SEL_SHIFT	4
+#define MPLL_FOUT_SEL_MASK	0x1
 #endif
Signature · 1 line
1.7.4.4
#2 lore raw

PATCH v2 7/9 EXYNOS5: CLOCK: Modify MPLL clock out for Exynos5250 Rev 1.0

Dear Rajeshwari Shinde,

Quoted 27 lines · Rajeshwari Shinde

MPLL clock-out of Exynos5250 Rev 1.0 is always at 1.6GHz. Adjust the divisor value to get 800MHz as needed by devices like UART etc

Signed-off-by Hatim Ali <[email protected]>
Signed-off-by Rajeshwari Shinde <[email protected]>

---
Chnages in V2:
? ? ? ?- None
?arch/arm/cpu/armv7/exynos/clock.c ? ? ? ?| ? 12 +++++++++++- ?arch/arm/include/asm/arch-exynos/clock.h | ? ?3 +++ ?2 files changed, 14 insertions(+), 1 deletions(-)

arch/arm/cpu/armv7/exynos/clock.c +0 -0
index 330bd75..dbd5f11 100644
@@ -98,7 +98,7 @@ static unsigned long exynos5_get_pll_clk(int pllreg)

? ? ? ?struct exynos5_clock *clk =
? ? ? ? ? ? ? ?(struct exynos5_clock *)samsung_get_base_clock(); ? ? ? ?unsigned long r, m, p, s, k = 0, mask, fout;
- ? ? ? unsigned int freq;
+ ? ? ? unsigned int freq, pll_div2_sel, ?mpll_fout_sel;

? ? ? ?switch (pllreg) {
? ? ? ?case APLL:

arch/arm/cpu/armv7/exynos/clock.c static unsigned long exynos5_get_pll_clk(int pllreg) · line 159

Quoted 5 lines
arch/arm/cpu/armv7/exynos/clock.c +2 -0
@@ -155,6 +155,16 @@ static unsigned long exynos5_get_pll_clk(int pllreg)
 ? ? ? ? ? ? ? ?fout = m * (freq / (p * (1 << (s - 1))));
 ? ? ? ?}
 
+ ? ? ? /* According to the user manual, in EVT1 MPLL always gives
+ ? ? ? ?* 1.6GHz clock, so divide by 2 to get 800MHz MPLL clock.*/

Please fix multiline comment style.

arch/arm/cpu/armv7/exynos/clock.c static unsigned long exynos5_get_pll_clk(int pllreg) · line 170

Quoted 11 lines
arch/arm/cpu/armv7/exynos/clock.c +8 -0
+ ? ? ? if (pllreg == MPLL) {
+ ? ? ? ? ? ? ? pll_div2_sel = readl(&clk->pll_div2_sel);
+ ? ? ? ? ? ? ? mpll_fout_sel = (pll_div2_sel >> MPLL_FOUT_SEL_SHIFT)
+ ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? & MPLL_FOUT_SEL_MASK;
+ ? ? ? ? ? ? ? if (mpll_fout_sel == 0)
+ ? ? ? ? ? ? ? ? ? ? ? fout /= 2;
+ ? ? ? }
+
 ? ? ? ?return fout;
 ?}

Thanks.
Minkyu Kang.

Signature · 2 lines
from. prom.
www.promsoft.net
author
#3 lore raw

PATCH v2 8/9 EXYNOS5 : Modify pinnumx settings as per Exynos5250 Rev 1.0

In reply to Rajeshwari Shinde

This patch modifies the pinmux settings of MMC and UART as per Exynos5250 Rev 1.0

Signed-off-by Rajeshwari Shinde <[email protected]>

---
Chnages in V2:
- None

 arch/arm/cpu/armv7/exynos/pinmux.c |   18 +++++++++---------
 1 files changed, 9 insertions(+), 9 deletions(-)
arch/arm/cpu/armv7/exynos/pinmux.c +9 -9
index d2b7d2c..7611c7a 100644
@@ -40,8 +40,8 @@ static void exynos5_uart_config(int peripheral)
 		count = 4;
 		break;
 	case PERIPH_ID_UART1:
-		bank = &gpio1->a0;
-		start = 4;
+		bank = &gpio1->d0;
+		start = 0;
 		count = 4;
 		break;
 	case PERIPH_ID_UART2:

@@ -66,25 +66,25 @@ static int exynos5_mmc_config(int peripheral, int flags)
 	struct exynos5_gpio_part1 *gpio1 =
 		(struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
 	struct s5p_gpio_bank *bank, *bank_ext;
-	int i;
+	int i, start;
 
 	switch (peripheral) {
 	case PERIPH_ID_SDMMC0:
 		bank = &gpio1->c0;
 		bank_ext = &gpio1->c1;
+		start = 0;
 		break;
 	case PERIPH_ID_SDMMC1:
-		bank = &gpio1->c1;
+		bank = &gpio1->c2;
 		bank_ext = NULL;
 		break;
 	case PERIPH_ID_SDMMC2:
-		bank = &gpio1->c2;
-		bank_ext = &gpio1->c3;
-		break;
-	case PERIPH_ID_SDMMC3:
 		bank = &gpio1->c3;
 		bank_ext = NULL;
 		break;
+	case PERIPH_ID_SDMMC3:
+		debug("SDMMC3 not supported yet");
+		return -1;
 	}
 	if ((flags & PINMUX_FLAG_8BIT_MODE) && !bank_ext) {
 		debug("SDMMC device %d does not support 8bit mode",

@@ -92,7 +92,7 @@ static int exynos5_mmc_config(int peripheral, int flags)
 		return -1;
 	}
 	if (flags & PINMUX_FLAG_8BIT_MODE) {
-		for (i = 3; i <= 6; i++) {
+		for (i = start; i <= (start + 3); i++) {
 			s5p_gpio_cfg_pin(bank_ext, i, GPIO_FUNC(0x3));
 			s5p_gpio_set_pull(bank_ext, i, GPIO_PULL_UP);
 			s5p_gpio_set_drv(bank_ext, i, GPIO_DRV_4X);
Signature · 1 line
1.7.4.4
#4 lore raw

PATCH v2 8/9 EXYNOS5 : Modify pinnumx settings as per Exynos5250 Rev 1.0

Hi Rajeshwari,

Quoted 41 lines · Rajeshwari Shinde

This patch modifies the pinmux settings of MMC and UART as per Exynos5250 Rev 1.0

Signed-off-by Rajeshwari Shinde <[email protected]>

---
Chnages in V2:
- None

 arch/arm/cpu/armv7/exynos/pinmux.c |   18 +++++++++---------
 1 files changed, 9 insertions(+), 9 deletions(-)
arch/arm/cpu/armv7/exynos/pinmux.c +5 -4
index d2b7d2c..7611c7a 100644
@@ -40,8 +40,8 @@ static void exynos5_uart_config(int peripheral)
 		count = 4;
 		break;
 	case PERIPH_ID_UART1:
-		bank = &gpio1->a0;
-		start = 4;
+		bank = &gpio1->d0;
+		start = 0;
 		count = 4;
 		break;
 	case PERIPH_ID_UART2:

@@ -66,25 +66,25 @@ static int exynos5_mmc_config(int peripheral, int flags)
 	struct exynos5_gpio_part1 *gpio1 =
 		(struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
 	struct s5p_gpio_bank *bank, *bank_ext;
-	int i;
+	int i, start;
 
 	switch (peripheral) {
 	case PERIPH_ID_SDMMC0:
 		bank = &gpio1->c0;
 		bank_ext = &gpio1->c1;
+		start = 0;
 		break;
 	case PERIPH_ID_SDMMC1:
-		bank = &gpio1->c1;
+		bank = &gpio1->c2;

arch/arm/cpu/armv7/exynos/pinmux.c static int exynos5_mmc_config(int peripheral, int flags) · line 84

Quoted 10 lines
arch/arm/cpu/armv7/exynos/pinmux.c +0 -4
 		bank_ext = NULL;
 		break;
 	case PERIPH_ID_SDMMC2:
-		bank = &gpio1->c2;
-		bank_ext = &gpio1->c3;
-		break;
-	case PERIPH_ID_SDMMC3:
 		bank = &gpio1->c3;
 		bank_ext = NULL;
 		break;

if SDMMC2 is supported 8BIT_MODE. Need gpio1->c4,

Quoted 8 lines
arch/arm/cpu/armv7/exynos/pinmux.c +3 -0
+	case PERIPH_ID_SDMMC3:
+		debug("SDMMC3 not supported yet");
+		return -1;
 
 	}
 	if ((flags & PINMUX_FLAG_8BIT_MODE) && !bank_ext) {
arch/arm/cpu/armv7/exynos/pinmux.c +0 -0
 		debug("SDMMC device %d does not support 8bit mode",

arch/arm/cpu/armv7/exynos/pinmux.c static int exynos5_mmc_config(int peripheral, int flags) · line 96

Quoted 6 lines
arch/arm/cpu/armv7/exynos/pinmux.c +1 -1
@@ -92,7 +92,7 @@ static int exynos5_mmc_config(int peripheral, int flags)
 		return -1;
 	}
 	if (flags & PINMUX_FLAG_8BIT_MODE) {
-		for (i = 3; i <= 6; i++) {
+		for (i = start; i <= (start + 3); i++) {
 			s5p_gpio_cfg_pin(bank_ext, i, GPIO_FUNC(0x3));

At EVT1, i known GPIO_FUNC(0x3) is wrong.

Quoted 2 lines
arch/arm/cpu/armv7/exynos/pinmux.c +0 -0
 			s5p_gpio_set_pull(bank_ext, i, GPIO_PULL_UP);
 			s5p_gpio_set_drv(bank_ext, i, GPIO_DRV_4X);
#5 lore raw

PATCH v2 8/9 EXYNOS5 : Modify pinnumx settings as per Exynos5250 Rev 1.0

Hi Jaehoon Chung

Quoted 49 lines · Jaehoon Chung

Hi Rajeshwari,

Quoted 45 lines · Rajeshwari Shinde

This patch modifies the pinmux settings of MMC and UART as per Exynos5250 Rev 1.0

Signed-off-by Rajeshwari Shinde <[email protected]>

---
Chnages in V2:
? ? ? - None
?arch/arm/cpu/armv7/exynos/pinmux.c | ? 18 +++++++++--------- ?1 files changed, 9 insertions(+), 9 deletions(-)

arch/arm/cpu/armv7/exynos/pinmux.c +0 -0
index d2b7d2c..7611c7a 100644
@@ -40,8 +40,8 @@ static void exynos5_uart_config(int peripheral)
 ? ? ? ? ? ? ? count = 4;
 ? ? ? ? ? ? ? break;

? ? ? case PERIPH_ID_UART1:
- ? ? ? ? ? ? bank = &gpio1->a0;
- ? ? ? ? ? ? start = 4;
+ ? ? ? ? ? ? bank = &gpio1->d0;
+ ? ? ? ? ? ? start = 0;
? ? ? ? ? ? ? count = 4;
? ? ? ? ? ? ? break;
? ? ? case PERIPH_ID_UART2:

arch/arm/cpu/armv7/exynos/pinmux.c +0 -0
@@ -66,25 +66,25 @@ static int exynos5_mmc_config(int peripheral, int flags)

? ? ? struct exynos5_gpio_part1 *gpio1 =
? ? ? ? ? ? ? (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1(); ? ? ? struct s5p_gpio_bank *bank, *bank_ext;
- ? ? int i;
+ ? ? int i, start;

? ? ? switch (peripheral) {
? ? ? case PERIPH_ID_SDMMC0:
? ? ? ? ? ? ? bank = &gpio1->c0;
? ? ? ? ? ? ? bank_ext = &gpio1->c1;
+ ? ? ? ? ? ? start = 0;
? ? ? ? ? ? ? break;
? ? ? case PERIPH_ID_SDMMC1:
- ? ? ? ? ? ? bank = &gpio1->c1;
+ ? ? ? ? ? ? bank = &gpio1->c2;
? ? ? ? ? ? ? bank_ext = NULL;
? ? ? ? ? ? ? break;
? ? ? case PERIPH_ID_SDMMC2:
- ? ? ? ? ? ? bank = &gpio1->c2;

Quoted 8 lines
Quoted 6 lines

- ? ? ? ? ? ? bank_ext = &gpio1->c3;
- ? ? ? ? ? ? break;
- ? ? case PERIPH_ID_SDMMC3:
? ? ? ? ? ? ? bank = &gpio1->c3;
? ? ? ? ? ? ? bank_ext = NULL;
? ? ? ? ? ? ? break;

if SDMMC2 is supported 8BIT_MODE. Need gpio1->c4,

-- ohh ok the manual which I have does not have gpio1->c4. I possible can you send me the user manual which you are referring to.

Quoted 5 lines
Quoted 4 lines

+ ? ? case PERIPH_ID_SDMMC3:
+ ? ? ? ? ? ? debug("SDMMC3 not supported yet");
+ ? ? ? ? ? ? return -1;

Quoted 12 lines

arch/arm/cpu/armv7/exynos/pinmux.c static int exynos5_mmc_config(int peripheral, int flags) · line 96

Quoted 10 lines

? ? ? }
? ? ? if ((flags & PINMUX_FLAG_8BIT_MODE) && !bank_ext) { ? ? ? ? ? ? ? debug("SDMMC device %d does not support 8bit mode",

arch/arm/cpu/armv7/exynos/pinmux.c +1 -1
@@ -92,7 +92,7 @@ static int exynos5_mmc_config(int peripheral, int flags)
 ? ? ? ? ? ? ? return -1;
 ? ? ? }
 ? ? ? if (flags & PINMUX_FLAG_8BIT_MODE) {
- ? ? ? ? ? ? for (i = 3; i <= 6; i++) {
+ ? ? ? ? ? ? for (i = start; i <= (start + 3); i++) {
 ? ? ? ? ? ? ? ? ? ? ? s5p_gpio_cfg_pin(bank_ext, i, GPIO_FUNC(0x3));

At EVT1, i known GPIO_FUNC(0x3) is wrong.

-- Ohh ok

Quoted 9 lines

arch/arm/cpu/armv7/exynos/pinmux.c static int exynos5_mmc_config(int peripheral, int flags) · line 98

Quoted 3 lines
arch/arm/cpu/armv7/exynos/pinmux.c +0 -0
 ? ? ? ? ? ? ? ? ? ? ? s5p_gpio_set_pull(bank_ext, i, GPIO_PULL_UP);
 ? ? ? ? ? ? ? ? ? ? ? s5p_gpio_set_drv(bank_ext, i, GPIO_DRV_4X);

_______________________________________________
U-Boot mailing list
U-Boot at lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Regards,
Rajeshwari Shinde.

author
#6 lore raw

PATCH v2 9/9 SMDK5250: Enable UART and MMC for Exynos5250 Rev 1.0

In reply to Rajeshwari Shinde

This patch sets UART3 and MMC channle 0 for Exynos5250 Rev 1.0

Signed-off-by Rajeshwari Shinde <[email protected]>

---
Chnages in V2:
- None

 board/samsung/smdk5250/smdk5250.c |    6 +++---
 include/configs/smdk5250.h        |    2 +-
 2 files changed, 4 insertions(+), 4 deletions(-)
board/samsung/smdk5250/smdk5250.c +3 -3
index 3b078da..b593325 100644
@@ -130,13 +130,13 @@ int board_mmc_init(bd_t *bis)
 {
 	int err;
 
-	err = exynos_pinmux_config(PERIPH_ID_SDMMC2, PINMUX_FLAG_NONE);
+	err = exynos_pinmux_config(PERIPH_ID_SDMMC0, PINMUX_FLAG_8BIT_MODE);
 	if (err) {
-		debug("SDMMC2 not configured\n");
+		debug("SDMMC0 not configured\n");
 		return err;
 	}
 
-	err = s5p_mmc_init(2, 4);
+	err = s5p_mmc_init(0, 8);
 	return err;
 }
 #endif
include/configs/smdk5250.h +1 -1
index 405abd5..d4d370f 100644
@@ -69,7 +69,7 @@
 
 /* select serial console configuration */
 #define CONFIG_SERIAL_MULTI
-#define CONFIG_SERIAL1			/* use SERIAL 1 */
+#define CONFIG_SERIAL3			/* use SERIAL 3 */
 #define CONFIG_BAUDRATE			115200
 #define EXYNOS5_DEFAULT_UART_OFFSET	0x010000
Signature · 1 line
1.7.4.4
#7 lore raw

PATCH v2 9/9 SMDK5250: Enable UART and MMC for Exynos5250 Rev 1.0

Quoted 1 line · Rajeshwari Shinde

This patch sets UART3 and MMC channle 0 for Exynos5250 Rev 1.0

Please fix typo channle -> channel.

Quoted 29 lines
Signed-off-by Rajeshwari Shinde <[email protected]>

---
Chnages in V2:
? ? ? ?- None
?board/samsung/smdk5250/smdk5250.c | ? ?6 +++---
?include/configs/smdk5250.h ? ? ? ?| ? ?2 +-
?2 files changed, 4 insertions(+), 4 deletions(-)

board/samsung/smdk5250/smdk5250.c +3 -3
index 3b078da..b593325 100644
@@ -130,13 +130,13 @@ int board_mmc_init(bd_t *bis)
 ?{
 ? ? ? ?int err;
 
- ? ? ? err = exynos_pinmux_config(PERIPH_ID_SDMMC2, PINMUX_FLAG_NONE);
+ ? ? ? err = exynos_pinmux_config(PERIPH_ID_SDMMC0, PINMUX_FLAG_8BIT_MODE);
 ? ? ? ?if (err) {
- ? ? ? ? ? ? ? debug("SDMMC2 not configured\n");
+ ? ? ? ? ? ? ? debug("SDMMC0 not configured\n");
 ? ? ? ? ? ? ? ?return err;
 ? ? ? ?}
 
- ? ? ? err = s5p_mmc_init(2, 4);
+ ? ? ? err = s5p_mmc_init(0, 8);
 ? ? ? ?return err;
 ?}
Quoted 1 line

?#endif

Thanks.
Minkyu Kang.

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