EXYNOS5: Support for Exynos5250 Rev 1.0

new file mode 100644
index 0000000..1d79239
@@ -0,0 +1,95 @@
+/*
+ * Copyright (c) 2012 The Chromium OS Authors.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ASM_ARCH_EXYNOS_SPL_H__
+#define __ASM_ARCH_EXYNOS_SPL_H__
+
+#include <asm/arch-exynos/dmc.h>
+
+enum boot_mode {
+	/*
+	 * Assign the OM pin values for respective boot modes.
+	 * Exynos4 does not support spi boot and the mmc boot OM
+	 * pin values are the same across Exynos4 and Exynos5.
+	 */
+	BOOT_MODE_MMC = 4,
+	BOOT_MODE_SERIAL = 20,
+	/* Boot based on Operating Mode pin settings */
+	BOOT_MODE_OM = 32,
+	BOOT_MODE_USB,	/* Boot using USB download */
+};
+
+/* Parameters of early board initialization in SPL */
+struct spl_machine_param {
+	/* Add fields as and when required */
+	u32		signature;
+	u32		version;	/* Version number */
+	u32		size;		/* Size of block */
+	/**
+	 * Parameters we expect, in order, terminated with \0. Each parameter
+	 * is a single character representing one 32-bit word in this
+	 * structure.
+	 *
+	 * Valid characters in this string are:
+	 *
+	 * Code		Name
+	 * v		mem_iv_size
+	 * m		mem_type
+	 * u		uboot_size
+	 * b		boot_source
+	 * f		frequency_mhz (memory frequency in MHz)
+	 * a		ARM clock frequency in MHz
+	 * s		serial base address
+	 * i		i2c base address for early access (meant for PMIC)
+	 * r		board rev GPIO numbers used to read board revision
+	 *			(lower halfword=bit 0, upper=bit 1)
+	 * M		Memory Manufacturer name
+	 * \0		termination
+	 */
+	char		params[12];	/* Length must be word-aligned */
+	u32		mem_iv_size;	/* Memory channel interleaving size */
+	enum ddr_mode	mem_type;	/* Type of on-board memory */
+	/*
+	 * U-boot size - The iROM mmc copy function used by the SPL takes a
+	 * block count paramter to describe the u-boot size unlike the spi
+	 * boot copy function which just uses the u-boot size directly. Align
+	 * the u-boot size to block size (512 bytes) when populating the SPL
+	 * table only for mmc boot.
+	 */
+	u32		uboot_size;
+	enum boot_mode	boot_source;	/* Boot device */
+	enum mem_manuf	mem_manuf;	/* Memory Manufacturer */
+	unsigned	frequency_mhz;	/* Frequency of memory in MHz */
+	unsigned	arm_freq_mhz;	/* ARM Frequency in MHz */
+	u32		serial_base;	/* Serial base address */
+	u32		i2c_base;	/* i2c base address */
+} __attribute__((__packed__));
+
+/**
+ * Validate signature and return a pointer to the parameter table.  If the
+ * signature is invalid, call panic() and never return.
+ *
+ * @return pointer to the parameter table if signature matched or never return.
+ */
+struct spl_machine_param *spl_get_machine_params(void);
+
+#endif /* __ASM_ARCH_EXYNOS_SPL_H__ */

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index 9659f9e..405abd5 100644
@@ -105,6 +105,11 @@
 #define CONFIG_SPL
 #define COPY_BL2_FNPTR_ADDR	0x02020030
 
+/* specific .lds file */
+#define CONFIG_SPL_LDSCRIPT	"board/samsung/smdk5250/smdk5250-uboot-spl.lds"
+#define CONFIG_SPL_TEXT_BASE	0x02023400
+#define CONFIG_SPL_MAX_SIZE	(14 * 1024)
+
 #define CONFIG_BOOTCOMMAND	"mmc read 40007000 451 2000; bootm 40007000"
 
 /* Miscellaneous configurable options */

index 50da958..7cc3d5e 100644
@@ -272,7 +272,7 @@ struct exynos5_clock {
 	unsigned int	clkout_cmu_cpu;
 	unsigned int	clkout_cmu_cpu_div_stat;
 	unsigned char	res8[0x5f8];
-	unsigned int	armclk_stopctrl;
+	unsigned int	armclk_stopctrl;	/* base + 0x1000 */
 	unsigned int	atclk_stopctrl;
 	unsigned char	res9[0x8];
 	unsigned int	parityfail_status;

@@ -323,10 +323,12 @@ struct exynos5_clock {
 	unsigned char	res19[0xf8];
 	unsigned int	div_core0;
 	unsigned int	div_core1;
-	unsigned char	res20[0xf8];
+	unsigned int	div_sysrgt;
+	unsigned char	res20[0xf4];
 	unsigned int	div_stat_core0;
 	unsigned int	div_stat_core1;
-	unsigned char	res21[0x2f8];
+	unsigned int	div_stat_sysrgt;
+	unsigned char	res21[0x2f4];
 	unsigned int	gate_ip_core;
 	unsigned char	res22[0xfc];
 	unsigned int	clkout_cmu_core;

@@ -352,7 +354,11 @@ struct exynos5_clock {
 	unsigned int	div_stat_acp;
 	unsigned char	res30[0x1fc];
 	unsigned int	gate_ip_acp;
-	unsigned char	res31[0x1fc];
+	unsigned char	res31a[0xfc];
+	unsigned int	div_syslft;
+	unsigned char	res31b[0xc];
+	unsigned int	div_stat_syslft;
+	unsigned char	res31c[0xec];
 	unsigned int	clkout_cmu_acp;
 	unsigned int	clkout_cmu_acp_div_stat;
 	unsigned char	res32[0x38f8];

@@ -379,7 +385,9 @@ struct exynos5_clock {
 	unsigned int	epll_lock;
 	unsigned char	res40[0xc];
 	unsigned int	vpll_lock;
-	unsigned char	res41[0xdc];
+	unsigned char	res41a[0xc];
+	unsigned int	gpll_lock;
+	unsigned char	res41b[0xcc];
 	unsigned int	cpll_con0;
 	unsigned int	cpll_con1;
 	unsigned char	res42[0x8];

@@ -390,7 +398,10 @@ struct exynos5_clock {
 	unsigned int	vpll_con0;
 	unsigned int	vpll_con1;
 	unsigned int	vpll_con2;
-	unsigned char	res44[0xc4];
+	unsigned char	res44a[0x4];
+	unsigned int	gpll_con0;
+	unsigned int	gpll_con1;
+	unsigned char	res44b[0xb8];
 	unsigned int	src_top0;
 	unsigned int	src_top1;
 	unsigned int	src_top2;

@@ -521,7 +532,9 @@ struct exynos5_clock {
 	unsigned int	clkout_cmu_top_div_stat;
 	unsigned char	res84[0x37f8];
 	unsigned int	src_lex;
-	unsigned char	res85[0x2fc];
+	unsigned char	res85[0x1fc];
+	unsigned int	mux_stat_lex;
+	unsigned char	res85b[0xfc];
 	unsigned int	div_lex;
 	unsigned char	res86[0xfc];
 	unsigned int	div_stat_lex;

@@ -549,7 +562,8 @@ struct exynos5_clock {
 	unsigned int	clkout_cmu_r1x;
 	unsigned int	clkout_cmu_r1x_div_stat;
 	unsigned char	res98[0x3608];
-	unsigned int	bpll_lock;
+
+	unsigned int	bpll_lock;		/* base + 0x2000c */
 	unsigned char	res99[0xfc];
 	unsigned int	bpll_con0;
 	unsigned int	bpll_con1;

@@ -574,8 +588,10 @@ struct exynos5_clock {
 	unsigned int	clkout_cmu_cdrex_div_stat;
 	unsigned char	res108[0x8];
 	unsigned int	lpddr3phy_ctrl;
-	unsigned char	res109[0xf5f8];
+	unsigned char	res109a[0xc];
+	unsigned int	lpddr3phy_con3;
+	unsigned int	pll_div2_sel;
+	unsigned char	res109b[0xf5e4];
 };
 #endif
-
 #endif

index 305842d..2eba397 100644
@@ -22,181 +22,643 @@
  * MA 02111-1307 USA
  */
 
+#include <common.h>
 #include <config.h>
-#include <version.h>
 #include <asm/io.h>
+#include <asm/arch/clk.h>
 #include <asm/arch/clock.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/gpio.h>
+#include <asm/arch/spl.h>
+
+#include "clock_init.h"
 #include "setup.h"
 
-void system_clock_init()
+DECLARE_GLOBAL_DATA_PTR;
+
+struct arm_clk_ratios arm_clk_ratios[] = {
+	{
+		.arm_freq_mhz = 600,
+
+		.apll_mdiv = 0xc8,
+		.apll_pdiv = 0x4,
+		.apll_sdiv = 0x1,
+
+		.arm2_ratio = 0x0,
+		.apll_ratio = 0x1,
+		.pclk_dbg_ratio = 0x1,
+		.atb_ratio = 0x2,
+		.periph_ratio = 0x7,
+		.acp_ratio = 0x7,
+		.cpud_ratio = 0x1,
+		.arm_ratio = 0x0,
+	}, {
+		.arm_freq_mhz = 800,
+
+		.apll_mdiv = 0x64,
+		.apll_pdiv = 0x3,
+		.apll_sdiv = 0x0,
+
+		.arm2_ratio = 0x0,
+		.apll_ratio = 0x1,
+		.pclk_dbg_ratio = 0x1,
+		.atb_ratio = 0x3,
+		.periph_ratio = 0x7,
+		.acp_ratio = 0x7,
+		.cpud_ratio = 0x2,
+		.arm_ratio = 0x0,
+	}, {
+		.arm_freq_mhz = 1000,
+
+		.apll_mdiv = 0x7d,
+		.apll_pdiv = 0x3,
+		.apll_sdiv = 0x0,
+
+		.arm2_ratio = 0x0,
+		.apll_ratio = 0x1,
+		.pclk_dbg_ratio = 0x1,
+		.atb_ratio = 0x4,
+		.periph_ratio = 0x7,
+		.acp_ratio = 0x7,
+		.cpud_ratio = 0x2,
+		.arm_ratio = 0x0,
+	}, {
+		.arm_freq_mhz = 1200,
+
+		.apll_mdiv = 0x96,
+		.apll_pdiv = 0x3,
+		.apll_sdiv = 0x0,
+
+		.arm2_ratio = 0x0,
+		.apll_ratio = 0x3,
+		.pclk_dbg_ratio = 0x1,
+		.atb_ratio = 0x5,
+		.periph_ratio = 0x7,
+		.acp_ratio = 0x7,
+		.cpud_ratio = 0x3,
+		.arm_ratio = 0x0,
+	}, {
+		.arm_freq_mhz = 1400,
+
+		.apll_mdiv = 0xaf,
+		.apll_pdiv = 0x3,
+		.apll_sdiv = 0x0,
+
+		.arm2_ratio = 0x0,
+		.apll_ratio = 0x3,
+		.pclk_dbg_ratio = 0x1,
+		.atb_ratio = 0x6,
+		.periph_ratio = 0x7,
+		.acp_ratio = 0x7,
+		.cpud_ratio = 0x3,
+		.arm_ratio = 0x0,
+	}, {
+		.arm_freq_mhz = 1700,
+
+		.apll_mdiv = 0x1a9,
+		.apll_pdiv = 0x6,
+		.apll_sdiv = 0x0,
+
+		.arm2_ratio = 0x0,
+		.apll_ratio = 0x3,
+		.pclk_dbg_ratio = 0x1,
+		.atb_ratio = 0x6,
+		.periph_ratio = 0x7,
+		.acp_ratio = 0x7,
+		.cpud_ratio = 0x3,
+		.arm_ratio = 0x0,
+	}
+};
+struct mem_timings mem_timings[] = {
+	{
+		.mem_manuf = MEM_MANUF_ELPIDA,
+		.mem_type = DDR_MODE_DDR3,
+		.frequency_mhz = 800,
+		.mpll_mdiv = 0xc8,
+		.mpll_pdiv = 0x3,
+		.mpll_sdiv = 0x0,
+		.cpll_mdiv = 0xde,
+		.cpll_pdiv = 0x4,
+		.cpll_sdiv = 0x2,
+		.gpll_mdiv = 0x215,
+		.gpll_pdiv = 0xc,
+		.gpll_sdiv = 0x1,
+		.epll_mdiv = 0x60,
+		.epll_pdiv = 0x3,
+		.epll_sdiv = 0x3,
+		.vpll_mdiv = 0x96,
+		.vpll_pdiv = 0x3,
+		.vpll_sdiv = 0x2,
+
+		.bpll_mdiv = 0x64,
+		.bpll_pdiv = 0x3,
+		.bpll_sdiv = 0x0,
+		.pclk_cdrex_ratio = 0x5,
+		.direct_cmd_msr = {
+			0x00020018, 0x00030000, 0x00010042, 0x00000d70
+		},
+		.timing_ref = 0x000000bb,
+		.timing_row = 0x8c36650e,
+		.timing_data = 0x3630580b,
+		.timing_power = 0x41000a44,
+		.phy0_dqs = 0x08080808,
+		.phy1_dqs = 0x08080808,
+		.phy0_dq = 0x08080808,
+		.phy1_dq = 0x08080808,
+		.phy0_tFS = 0x4,
+		.phy1_tFS = 0x4,
+		.phy0_pulld_dqs = 0xf,
+		.phy1_pulld_dqs = 0xf,
+
+		.lpddr3_ctrl_phy_reset = 0x1,
+		.ctrl_start_point = 0x10,
+		.ctrl_inc = 0x10,
+		.ctrl_start = 0x1,
+		.ctrl_dll_on = 0x1,
+		.ctrl_ref = 0x8,
+
+		.ctrl_force = 0x1a,
+		.ctrl_rdlat = 0x0b,
+		.ctrl_bstlen = 0x08,
+
+		.fp_resync = 0x8,
+		.iv_size = 0x7,
+		.dfi_init_start = 1,
+		.aref_en = 1,
+
+		.rd_fetch = 0x3,
+
+		.zq_mode_dds = 0x7,
+		.zq_mode_term = 0x1,
+		.zq_mode_noterm = 0,
+
+		/*
+		* Dynamic Clock: Always Running
+		* Memory Burst length: 8
+		* Number of chips: 1
+		* Memory Bus width: 32 bit
+		* Memory Type: DDR3
+		* Additional Latancy for PLL: 0 Cycle
+		*/
+		.memcontrol = DMC_MEMCONTROL_CLK_STOP_DISABLE |
+			DMC_MEMCONTROL_DPWRDN_DISABLE |
+			DMC_MEMCONTROL_DPWRDN_ACTIVE_PRECHARGE |
+			DMC_MEMCONTROL_TP_DISABLE |
+			DMC_MEMCONTROL_DSREF_ENABLE |
+			DMC_MEMCONTROL_ADD_LAT_PALL_CYCLE(0) |
+			DMC_MEMCONTROL_MEM_TYPE_DDR3 |
+			DMC_MEMCONTROL_MEM_WIDTH_32BIT |
+			DMC_MEMCONTROL_NUM_CHIP_1 |
+			DMC_MEMCONTROL_BL_8 |
+			DMC_MEMCONTROL_PZQ_DISABLE |
+			DMC_MEMCONTROL_MRR_BYTE_7_0,
+		.memconfig = DMC_MEMCONFIGx_CHIP_MAP_INTERLEAVED |
+			DMC_MEMCONFIGx_CHIP_COL_10 |
+			DMC_MEMCONFIGx_CHIP_ROW_15 |
+			DMC_MEMCONFIGx_CHIP_BANK_8,
+		.membaseconfig0 = DMC_MEMBASECONFIG_VAL(0x40),
+		.membaseconfig1 = DMC_MEMBASECONFIG_VAL(0x80),
+		.prechconfig_tp_cnt = 0xff,
+		.dpwrdn_cyc = 0xff,
+		.dsref_cyc = 0xffff,
+		.concontrol = DMC_CONCONTROL_DFI_INIT_START_DISABLE |
+			DMC_CONCONTROL_TIMEOUT_LEVEL0 |
+			DMC_CONCONTROL_RD_FETCH_DISABLE |
+			DMC_CONCONTROL_EMPTY_DISABLE |
+			DMC_CONCONTROL_AREF_EN_DISABLE |
+			DMC_CONCONTROL_IO_PD_CON_DISABLE,
+		.dmc_channels = 2,
+		.chips_per_channel = 2,
+		.chips_to_configure = 1,
+		.send_zq_init = 1,
+		.impedance = IMP_OUTPUT_DRV_30_OHM,
+		.gate_leveling_enable = 0,
+	}, {
+		.mem_manuf = MEM_MANUF_SAMSUNG,
+		.mem_type = DDR_MODE_DDR3,
+		.frequency_mhz = 800,
+		.mpll_mdiv = 0xc8,
+		.mpll_pdiv = 0x3,
+		.mpll_sdiv = 0x0,
+		.cpll_mdiv = 0xde,
+		.cpll_pdiv = 0x4,
+		.cpll_sdiv = 0x2,
+		.gpll_mdiv = 0x215,
+		.gpll_pdiv = 0xc,
+		.gpll_sdiv = 0x1,
+		.epll_mdiv = 0x60,
+		.epll_pdiv = 0x3,
+		.epll_sdiv = 0x3,
+		.vpll_mdiv = 0x96,
+		.vpll_pdiv = 0x3,
+		.vpll_sdiv = 0x2,
+
+		.bpll_mdiv = 0x64,
+		.bpll_pdiv = 0x3,
+		.bpll_sdiv = 0x0,
+		.pclk_cdrex_ratio = 0x5,
+		.direct_cmd_msr = {
+			0x00020018, 0x00030000, 0x00010000, 0x00000d70
+		},
+		.timing_ref = 0x000000bb,
+		.timing_row = 0x8c36650e,
+		.timing_data = 0x3630580b,
+		.timing_power = 0x41000a44,
+		.phy0_dqs = 0x08080808,
+		.phy1_dqs = 0x08080808,
+		.phy0_dq = 0x08080808,
+		.phy1_dq = 0x08080808,
+		.phy0_tFS = 0x8,
+		.phy1_tFS = 0x8,
+		.phy0_pulld_dqs = 0xf,
+		.phy1_pulld_dqs = 0xf,
+
+		.lpddr3_ctrl_phy_reset = 0x1,
+		.ctrl_start_point = 0x10,
+		.ctrl_inc = 0x10,
+		.ctrl_start = 0x1,
+		.ctrl_dll_on = 0x1,
+		.ctrl_ref = 0x8,
+
+		.ctrl_force = 0x1a,
+		.ctrl_rdlat = 0x0b,
+		.ctrl_bstlen = 0x08,
+
+		.fp_resync = 0x8,
+		.iv_size = 0x7,
+		.dfi_init_start = 1,
+		.aref_en = 1,
+
+		.rd_fetch = 0x3,
+
+		.zq_mode_dds = 0x5,
+		.zq_mode_term = 0x1,
+		.zq_mode_noterm = 1,
+
+		/*
+		* Dynamic Clock: Always Running
+		* Memory Burst length: 8
+		* Number of chips: 1
+		* Memory Bus width: 32 bit
+		* Memory Type: DDR3
+		* Additional Latancy for PLL: 0 Cycle
+		*/
+		.memcontrol = DMC_MEMCONTROL_CLK_STOP_DISABLE |
+			DMC_MEMCONTROL_DPWRDN_DISABLE |
+			DMC_MEMCONTROL_DPWRDN_ACTIVE_PRECHARGE |
+			DMC_MEMCONTROL_TP_DISABLE |
+			DMC_MEMCONTROL_DSREF_ENABLE |
+			DMC_MEMCONTROL_ADD_LAT_PALL_CYCLE(0) |
+			DMC_MEMCONTROL_MEM_TYPE_DDR3 |
+			DMC_MEMCONTROL_MEM_WIDTH_32BIT |
+			DMC_MEMCONTROL_NUM_CHIP_1 |
+			DMC_MEMCONTROL_BL_8 |
+			DMC_MEMCONTROL_PZQ_DISABLE |
+			DMC_MEMCONTROL_MRR_BYTE_7_0,
+		.memconfig = DMC_MEMCONFIGx_CHIP_MAP_INTERLEAVED |
+			DMC_MEMCONFIGx_CHIP_COL_10 |
+			DMC_MEMCONFIGx_CHIP_ROW_15 |
+			DMC_MEMCONFIGx_CHIP_BANK_8,
+		.membaseconfig0 = DMC_MEMBASECONFIG_VAL(0x40),
+		.membaseconfig1 = DMC_MEMBASECONFIG_VAL(0x80),
+		.prechconfig_tp_cnt = 0xff,
+		.dpwrdn_cyc = 0xff,
+		.dsref_cyc = 0xffff,
+		.concontrol = DMC_CONCONTROL_DFI_INIT_START_DISABLE |
+			DMC_CONCONTROL_TIMEOUT_LEVEL0 |
+			DMC_CONCONTROL_RD_FETCH_DISABLE |
+			DMC_CONCONTROL_EMPTY_DISABLE |
+			DMC_CONCONTROL_AREF_EN_DISABLE |
+			DMC_CONCONTROL_IO_PD_CON_DISABLE,
+		.dmc_channels = 2,
+		.chips_per_channel = 2,
+		.chips_to_configure = 1,
+		.send_zq_init = 1,
+		.impedance = IMP_OUTPUT_DRV_40_OHM,
+		.gate_leveling_enable = 1,
+	}
+};
+
+/**
+ * Get the required memory type and speed (SPL version).
+ *
+ * In SPL we have no device tree, so we use the machine parameters
+ *
+ * @param mem_type	Returns memory type
+ * @param frequency_mhz	Returns memory speed in MHz
+ * @param arm_freq	Returns ARM clock speed in MHz
+ * @param mem_manuf	Return Memory Manufacturer name
+ * @return 0 if all ok
+ */
+static int clock_get_mem_selection(enum ddr_mode *mem_type,
+		unsigned *frequency_mhz, unsigned *arm_freq,
+		enum mem_manuf *mem_manuf)
 {
-	struct exynos5_clock *clk = (struct exynos5_clock *)EXYNOS5_CLOCK_BASE;
+	struct spl_machine_param *params;
 
-	/*
-	 * MUX_APLL_SEL[0]: FINPLL = 0
-	 * MUX_CPU_SEL[6]: MOUTAPLL = 0
-	 * MUX_HPM_SEL[20]: MOUTAPLL = 0
-	 */
-	writel(0x0, &clk->src_cpu);
+	params = spl_get_machine_params();
+	*mem_type = params->mem_type;
+	*frequency_mhz = params->frequency_mhz;
+	*arm_freq = params->arm_freq_mhz;
+	*mem_manuf = params->mem_manuf;
 
-	/* MUX_MPLL_SEL[8]: FINPLL = 0 */
-	writel(0x0, &clk->src_core1);
+	return 0;
+}
 
-	/*
-	 * VPLLSRC_SEL[0]: FINPLL = 0
-	 * MUX_{CPLL[8]}|{EPLL[12]}|{VPLL[16]}_SEL: FINPLL = 0
-	 */
-	writel(0x0, &clk->src_top2);
+/* Get the ratios for setting ARM clock */
+struct arm_clk_ratios *get_arm_ratios(void)
+{
+	struct arm_clk_ratios *arm_ratio;
+	enum ddr_mode mem_type;
+	enum mem_manuf mem_manuf;
+	unsigned frequency_mhz, arm_freq;
+	int i;
+
+	if (clock_get_mem_selection(&mem_type, &frequency_mhz,
+					&arm_freq, &mem_manuf))
+		;
+	for (i = 0, arm_ratio = arm_clk_ratios; i < ARRAY_SIZE(arm_clk_ratios);
+		i++, arm_ratio++) {
+		if (arm_ratio->arm_freq_mhz == arm_freq)
+			return arm_ratio;
+	}
+
+	/* will hang if failed to find clock ratio */
+	while (1)
+		;
+
+	return NULL;
+}
 
-	/* MUX_BPLL_SEL[0]: FINPLL = 0 */
-	writel(0x0, &clk->src_cdrex);
+struct mem_timings *clock_get_mem_timings(void)
+{
+	struct mem_timings *mem;
+	enum ddr_mode mem_type;
+	enum mem_manuf mem_manuf;
+	unsigned frequency_mhz, arm_freq;
+	int i;
+
+	if (!clock_get_mem_selection(&mem_type, &frequency_mhz,
+						&arm_freq, &mem_manuf)) {
+		for (i = 0, mem = mem_timings; i < ARRAY_SIZE(mem_timings);
+				i++, mem++) {
+			if (mem->mem_type == mem_type &&
+					mem->frequency_mhz == frequency_mhz &&
+					mem->mem_manuf == mem_manuf)
+				return mem;
+		}
+	}
+
+	/* will hang if failed to find memory timings */
+	while (1)
+		;
+
+	return NULL;
+}
 
-	/* MUX_ACLK_* Clock Selection */
-	writel(CLK_SRC_TOP0_VAL, &clk->src_top0);
+void system_clock_init()
+{
+	struct exynos5_clock *clk = (struct exynos5_clock *)EXYNOS5_CLOCK_BASE;
+	struct mem_timings *mem;
+	struct arm_clk_ratios *arm_clk_ratio;
+	u32 val, tmp;
+
+	mem = clock_get_mem_timings();
+	arm_clk_ratio = get_arm_ratios();
+
+	clrbits_le32(&clk->src_cpu, MUX_APLL_SEL_MASK);
+	do {
+		val = readl(&clk->mux_stat_cpu);
+	} while ((val | MUX_APLL_SEL_MASK) != val);
+
+	clrbits_le32(&clk->src_core1, MUX_MPLL_SEL_MASK);
+	do {
+		val = readl(&clk->mux_stat_core1);
+	} while ((val | MUX_MPLL_SEL_MASK) != val);
+
+	clrbits_le32(&clk->src_core1, MUX_CPLL_SEL_MASK);
+	clrbits_le32(&clk->src_core1, MUX_EPLL_SEL_MASK);
+	clrbits_le32(&clk->src_core1, MUX_VPLL_SEL_MASK);
+	clrbits_le32(&clk->src_core1, MUX_GPLL_SEL_MASK);
+	tmp = MUX_CPLL_SEL_MASK | MUX_EPLL_SEL_MASK | MUX_VPLL_SEL_MASK
+		| MUX_GPLL_SEL_MASK;
+	do {
+		val = readl(&clk->mux_stat_top2);
+	} while ((val | tmp) != val);
+
+	clrbits_le32(&clk->src_cdrex, MUX_BPLL_SEL_MASK);
+	do {
+		val = readl(&clk->mux_stat_cdrex);
+	} while ((val | MUX_BPLL_SEL_MASK) != val);
 
-	/* MUX_ACLK_* Clock Selection */
-	writel(CLK_SRC_TOP1_VAL, &clk->src_top1);
+	/* PLL locktime */
+	writel(APLL_LOCK_VAL, &clk->apll_lock);
 
-	/* MUX_ACLK_* Clock Selection */
-	writel(CLK_SRC_TOP3_VAL, &clk->src_top3);
+	writel(MPLL_LOCK_VAL, &clk->mpll_lock);
 
-	/* MUX_PWI_SEL[19:16]: SCLKMPLL = 6 */
-	writel(CLK_SRC_CORE0_VAL, &clk->src_core0);
+	writel(BPLL_LOCK_VAL, &clk->bpll_lock);
 
-	/* MUX_ATCLK_LEX[0]: ACLK_200 = 0 */
-	writel(CLK_SRC_LEX_VAL, &clk->src_lex);
+	writel(CPLL_LOCK_VAL, &clk->cpll_lock);
 
-	/* UART [0-5]: SCLKMPLL = 6 */
-	writel(CLK_SRC_PERIC0_VAL, &clk->src_peric0);
+	writel(GPLL_LOCK_VAL, &clk->gpll_lock);
 
-	/* Set Clock Ratios */
-	writel(CLK_DIV_CPU0_VAL, &clk->div_cpu0);
+	writel(EPLL_LOCK_VAL, &clk->epll_lock);
 
-	/* Set COPY and HPM Ratio */
-	writel(CLK_DIV_CPU1_VAL, &clk->div_cpu1);
+	writel(VPLL_LOCK_VAL, &clk->vpll_lock);
 
-	/* CORED_RATIO, COREP_RATIO */
-	writel(CLK_DIV_CORE0_VAL, &clk->div_core0);
+	writel(CLK_REG_DISABLE, &clk->pll_div2_sel);
+
+	writel(MUX_HPM_SEL_MASK, &clk->src_cpu);
+	do {
+		val = readl(&clk->mux_stat_cpu);
+	} while ((val | HPM_SEL_SCLK_MPLL) != val);
+
+	val = arm_clk_ratio->arm2_ratio << 28
+		| arm_clk_ratio->apll_ratio << 24
+		| arm_clk_ratio->pclk_dbg_ratio << 20
+		| arm_clk_ratio->atb_ratio << 16
+		| arm_clk_ratio->periph_ratio << 12
+		| arm_clk_ratio->acp_ratio << 8
+		| arm_clk_ratio->cpud_ratio << 4
+		| arm_clk_ratio->arm_ratio;
+	writel(val, &clk->div_cpu0);
+	do {
+		val = readl(&clk->div_stat_cpu0);
+	} while (0 != val);
 
-	/* PWI_RATIO[11:8], DVSEM_RATIO[22:16], DPM_RATIO[24:20] */
-	writel(CLK_DIV_CORE1_VAL, &clk->div_core1);
+	writel(CLK_DIV_CPU1_VAL, &clk->div_cpu1);
+	do {
+		val = readl(&clk->div_stat_cpu1);
+	} while (0 != val);
 
-	/* ACLK_*_RATIO */
-	writel(CLK_DIV_TOP0_VAL, &clk->div_top0);
+	/* Set APLL */
+	writel(APLL_CON1_VAL, &clk->apll_con1);
+	val = set_pll(arm_clk_ratio->apll_mdiv, arm_clk_ratio->apll_pdiv,
+			arm_clk_ratio->apll_sdiv);
+	writel(val, &clk->apll_con0);
+	while (readl(&clk->apll_con0) & APLL_CON0_LOCKED)
+		;
 
-	/* ACLK_*_RATIO */
-	writel(CLK_DIV_TOP1_VAL, &clk->div_top1);
+	/* Set MPLL */
+	writel(MPLL_CON1_VAL, &clk->mpll_con1);
+	val = set_pll(mem->mpll_mdiv, mem->mpll_pdiv, mem->mpll_sdiv);
+	writel(val, &clk->mpll_con0);
+	while (readl(&clk->mpll_con0) & MPLL_CON0_LOCKED)
+		;
 
-	/* CDREX Ratio */
-	writel(CLK_DIV_CDREX_INIT_VAL, &clk->div_cdrex);
+	/* Set BPLL */
+	writel(BPLL_CON1_VAL, &clk->bpll_con1);
+	val = set_pll(mem->bpll_mdiv, mem->bpll_pdiv, mem->bpll_sdiv);
+	writel(val, &clk->bpll_con0);
+	while (readl(&clk->bpll_con0) & BPLL_CON0_LOCKED)
+		;
 
-	/* MCLK_EFPHY_RATIO[3:0] */
-	writel(CLK_DIV_CDREX2_VAL, &clk->div_cdrex2);
+	/* Set CPLL */
+	writel(CPLL_CON1_VAL, &clk->cpll_con1);
+	val = set_pll(mem->cpll_mdiv, mem->cpll_pdiv, mem->cpll_sdiv);
+	writel(val, &clk->cpll_con0);
+	while (readl(&clk->cpll_con0) & CPLL_CON0_LOCKED)
+		;
+
+	/* Set GPLL */
+	writel(GPLL_CON1_VAL, &clk->gpll_con1);
+	val = set_pll(mem->gpll_mdiv, mem->gpll_pdiv, mem->gpll_sdiv);
+	writel(val, &clk->gpll_con0);
+	while (readl(&clk->gpll_con0) & GPLL_CON0_LOCKED)
+		;
 
-	/* {PCLK[4:6]|ATCLK[10:8]}_RATIO */
-	writel(CLK_DIV_LEX_VAL, &clk->div_lex);
+	/* Set EPLL */
+	writel(EPLL_CON2_VAL, &clk->epll_con2);
+	writel(EPLL_CON1_VAL, &clk->epll_con1);
+	val = set_pll(mem->epll_mdiv, mem->epll_pdiv, mem->epll_sdiv);
+	writel(val, &clk->epll_con0);
+	while (readl(&clk->epll_con0) & EPLL_CON0_LOCKED)
+		;
 
-	/* PCLK_R0X_RATIO[3:0] */
-	writel(CLK_DIV_R0X_VAL, &clk->div_r0x);
+	/* Set VPLL */
+	writel(VPLL_CON2_VAL, &clk->vpll_con2);
+	writel(VPLL_CON1_VAL, &clk->vpll_con1);
+	val = set_pll(mem->vpll_mdiv, mem->vpll_pdiv, mem->vpll_sdiv);
+	writel(val, &clk->vpll_con0);
+	while (readl(&clk->vpll_con0) & VPLL_CON0_LOCKED)
+		;
 
-	/* PCLK_R1X_RATIO[3:0] */
-	writel(CLK_DIV_R1X_VAL, &clk->div_r1x);
+	writel(CLK_SRC_CORE0_VAL, &clk->src_core0);
+	writel(CLK_DIV_CORE0_VAL, &clk->div_core0);
+	while (readl(&clk->div_stat_core0) != 0)
+		;
 
-	/* SATA[24]: SCLKMPLL=0, MMC[0-4]: SCLKMPLL = 6 */
-	writel(CLK_SRC_FSYS_VAL, &clk->src_fsys);
+	writel(CLK_DIV_CORE1_VAL, &clk->div_core1);
+	while (readl(&clk->div_stat_core1) != 0)
+		;
 
-	/* UART[0-4] */
-	writel(CLK_DIV_PERIC0_VAL, &clk->div_peric0);
+	writel(CLK_DIV_SYSRGT_VAL, &clk->div_sysrgt);
+	while (readl(&clk->div_stat_sysrgt) != 0)
+		;
 
-	/* PWM_RATIO[3:0] */
-	writel(CLK_DIV_PERIC3_VAL, &clk->div_peric3);
+	writel(CLK_DIV_ACP_VAL, &clk->div_acp);
+	while (readl(&clk->div_stat_acp) != 0)
+		;
 
-	/* SATA_RATIO, USB_DRD_RATIO */
-	writel(CLK_DIV_FSYS0_VAL, &clk->div_fsys0);
+	writel(CLK_DIV_SYSLFT_VAL, &clk->div_syslft);
+	while (readl(&clk->div_stat_syslft) != 0)
+		;
 
-	/* MMC[0-1] */
-	writel(CLK_DIV_FSYS1_VAL, &clk->div_fsys1);
+	writel(CLK_SRC_TOP0_VAL, &clk->src_top0);
+	writel(CLK_SRC_TOP1_VAL, &clk->src_top1);
+	writel(TOP2_VAL, &clk->src_top2);
+	writel(CLK_SRC_TOP3_VAL, &clk->src_top3);
 
-	/* MMC[2-3] */
-	writel(CLK_DIV_FSYS2_VAL, &clk->div_fsys2);
+	writel(CLK_DIV_TOP0_VAL, &clk->div_top0);
+	while (readl(&clk->div_stat_top0))
+		;
 
-	/* MMC[4] */
-	writel(CLK_DIV_FSYS3_VAL, &clk->div_fsys3);
+	writel(CLK_DIV_TOP1_VAL, &clk->div_top1);
+	while (readl(&clk->div_stat_top1))
+		;
 
-	/* ACLK|PLCK_ACP_RATIO */
-	writel(CLK_DIV_ACP_VAL, &clk->div_acp);
+	writel(CLK_SRC_LEX_VAL, &clk->src_lex);
+	while (1) {
+		val = readl(&clk->mux_stat_lex);
+		if (val == (val | 1))
+			break;
+	}
 
-	/* ISPDIV0_RATIO, ISPDIV1_RATIO */
-	writel(CLK_DIV_ISP0_VAL, &clk->div_isp0);
+	writel(CLK_DIV_LEX_VAL, &clk->div_lex);
+	while (readl(&clk->div_stat_lex))
+		;
 
-	/* MCUISPDIV0_RATIO, MCUISPDIV1_RATIO */
-	writel(CLK_DIV_ISP1_VAL, &clk->div_isp1);
+	writel(CLK_DIV_R0X_VAL, &clk->div_r0x);
+	while (readl(&clk->div_stat_r0x))
+		;
 
-	/* MPWMDIV_RATIO */
-	writel(CLK_DIV_ISP2_VAL, &clk->div_isp2);
+	writel(CLK_DIV_R0X_VAL, &clk->div_r0x);
+	while (readl(&clk->div_stat_r0x))
+		;
 
-	/* PLL locktime */
-	writel(APLL_LOCK_VAL, &clk->apll_lock);
+	writel(CLK_DIV_R1X_VAL, &clk->div_r1x);
+	while (readl(&clk->div_stat_r1x))
+		;
 
-	writel(MPLL_LOCK_VAL, &clk->mpll_lock);
+	writel(CLK_REG_DISABLE, &clk->src_cdrex);
 
-	writel(BPLL_LOCK_VAL, &clk->bpll_lock);
+	writel(CLK_DIV_CDREX_VAL, &clk->div_cdrex);
+	while (readl(&clk->div_stat_cdrex))
+		;
 
-	writel(CPLL_LOCK_VAL, &clk->cpll_lock);
+	val = readl(&clk->src_cpu);
+	val |= CLK_SRC_CPU_VAL;
+	writel(val, &clk->src_cpu);
 
-	writel(EPLL_LOCK_VAL, &clk->epll_lock);
+	val = readl(&clk->src_top2);
+	val |= CLK_SRC_TOP2_VAL;
+	writel(val, &clk->src_top2);
 
-	writel(VPLL_LOCK_VAL, &clk->vpll_lock);
+	val = readl(&clk->src_core1);
+	val |= CLK_SRC_CORE1_VAL;
+	writel(val, &clk->src_core1);
 
-	sdelay(0x10000);
+	writel(CLK_SRC_FSYS0_VAL, &clk->src_fsys);
+	writel(CLK_DIV_FSYS0_VAL, &clk->div_fsys0);
+	while (readl(&clk->div_stat_fsys0))
+		;
+
+	writel(CLK_REG_DISABLE, &clk->clkout_cmu_cpu);
+	writel(CLK_REG_DISABLE, &clk->clkout_cmu_core);
+	writel(CLK_REG_DISABLE, &clk->clkout_cmu_acp);
+	writel(CLK_REG_DISABLE, &clk->clkout_cmu_top);
+	writel(CLK_REG_DISABLE, &clk->clkout_cmu_lex);
+	writel(CLK_REG_DISABLE, &clk->clkout_cmu_r0x);
+	writel(CLK_REG_DISABLE, &clk->clkout_cmu_r1x);
+	writel(CLK_REG_DISABLE, &clk->clkout_cmu_cdrex);
 
-	/* Set APLL */
-	writel(APLL_CON1_VAL, &clk->apll_con1);
-	writel(APLL_CON0_VAL, &clk->apll_con0);
-	sdelay(0x30000);
+	writel(CLK_SRC_PERIC0_VAL, &clk->src_peric0);
+	writel(CLK_DIV_PERIC0_VAL, &clk->div_peric0);
 
-	/* Set MPLL */
-	writel(MPLL_CON1_VAL, &clk->mpll_con1);
-	writel(MPLL_CON0_VAL, &clk->mpll_con0);
-	sdelay(0x30000);
-	writel(BPLL_CON1_VAL, &clk->bpll_con1);
-	writel(BPLL_CON0_VAL, &clk->bpll_con0);
-	sdelay(0x30000);
+	writel(CLK_SRC_PERIC1_VAL, &clk->src_peric1);
+	writel(CLK_DIV_PERIC1_VAL, &clk->div_peric1);
+	writel(CLK_DIV_PERIC2_VAL, &clk->div_peric2);
+	writel(SCLK_SRC_ISP_VAL, &clk->sclk_src_isp);
+	writel(SCLK_DIV_ISP_VAL, &clk->sclk_div_isp);
+	writel(CLK_DIV_ISP0_VAL, &clk->div_isp0);
+	writel(CLK_DIV_ISP1_VAL, &clk->div_isp1);
+	writel(CLK_DIV_ISP2_VAL, &clk->div_isp2);
 
-	/* Set CPLL */
-	writel(CPLL_CON1_VAL, &clk->cpll_con1);
-	writel(CPLL_CON0_VAL, &clk->cpll_con0);
-	sdelay(0x30000);
+	/* FIMD1 SRC CLK SELECTION */
+	writel(CLK_SRC_DISP1_0_VAL, &clk->src_disp1_0);
 
-	/* Set EPLL */
-	writel(EPLL_CON2_VAL, &clk->epll_con2);
-	writel(EPLL_CON1_VAL, &clk->epll_con1);
-	writel(EPLL_CON0_VAL, &clk->epll_con0);
-	sdelay(0x30000);
+	val = MMC2_PRE_RATIO_VAL << MMC2_PRE_RATIO_OFFSET
+		| MMC2_RATIO_VAL << MMC2_RATIO_OFFSET
+		| MMC3_PRE_RATIO_VAL << MMC3_PRE_RATIO_OFFSET
+		| MMC3_RATIO_VAL << MMC3_RATIO_OFFSET;
+	writel(val, &clk->div_fsys2);
+}
 
-	/* Set VPLL */
-	writel(VPLL_CON2_VAL, &clk->vpll_con2);
-	writel(VPLL_CON1_VAL, &clk->vpll_con1);
-	writel(VPLL_CON0_VAL, &clk->vpll_con0);
-	sdelay(0x30000);
+void clock_init_dp_clock(void)
+{
+	struct exynos5_clock *clk = (struct exynos5_clock *)EXYNOS5_CLOCK_BASE;
 
-	/* Set MPLL */
-	/* After Initiallising th PLL select the sources accordingly */
-	/* MUX_APLL_SEL[0]: MOUTAPLLFOUT = 1 */
-	writel(CLK_SRC_CPU_VAL, &clk->src_cpu);
-
-	/* MUX_MPLL_SEL[8]: MOUTMPLLFOUT = 1 */
-	writel(CLK_SRC_CORE1_VAL, &clk->src_core1);
-
-	/* MUX_BPLL_SEL[0]: FOUTBPLL = 1*/
-	writel(CLK_SRC_CDREX_INIT_VAL, &clk->src_cdrex);
-
-	/*
-	 * VPLLSRC_SEL[0]: FINPLL = 0
-	 * MUX_{CPLL[8]}|{EPLL[12]}|{VPLL[16]}_SEL: MOUT{CPLL|EPLL|VPLL} = 1
-	 * MUX_{MPLL[20]}|{BPLL[24]}_USER_SEL: FOUT{MPLL|BPLL} = 1
-	 */
-	writel(CLK_SRC_TOP2_VAL, &clk->src_top2);
+	/* DP clock enable */
+	setbits_le32(&clk->gate_ip_disp1, CLK_GATE_DP1_ALLOW);
+
+	/* We run DP at 267 Mhz */
+	setbits_le32(&clk->div_disp1_0, CLK_DIV_DISP1_0_FIMD1);
 }

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index bd52d16..f65c676 100644
@@ -251,5 +251,70 @@ struct exynos5_phy_control {
 	unsigned int phy_con41;
 	unsigned int phy_con42;
 };
+
+enum ddr_mode {
+	DDR_MODE_DDR2,
+	DDR_MODE_DDR3,
+	DDR_MODE_LPDDR2,
+	DDR_MODE_LPDDR3,
+
+	DDR_MODE_COUNT,
+};
+
+enum mem_manuf {
+	MEM_MANUF_AUTODETECT,
+	MEM_MANUF_ELPIDA,
+	MEM_MANUF_SAMSUNG,
+
+	MEM_MANUF_COUNT,
+};
+
+/* CONCONTROL register fields */
+#define CONCONTROL_DFI_INIT_START_SHIFT	28
+#define CONCONTROL_RD_FETCH_SHIFT	12
+#define CONCONTROL_RD_FETCH_MASK	(0x7 << CONCONTROL_RD_FETCH_SHIFT)
+#define CONCONTROL_AREF_EN_SHIFT	5
+
+/* PRECHCONFIG register field */
+#define PRECHCONFIG_TP_CNT_SHIFT	24
+
+/* PWRDNCONFIG register field */
+#define PWRDNCONFIG_DPWRDN_CYC_SHIFT	0
+#define PWRDNCONFIG_DSREF_CYC_SHIFT	16
+
+/* PHY_CON0 register fields */
+#define PHY_CON0_T_WRRDCMD_SHIFT	17
+#define PHY_CON0_T_WRRDCMD_MASK		(0x7 << PHY_CON0_T_WRRDCMD_SHIFT)
+#define PHY_CON0_CTRL_DDR_MODE_SHIFT	11
+
+/* PHY_CON1 register fields */
+#define PHY_CON1_RDLVL_RDDATA_ADJ_SHIFT	0
+
+/* PHY_CON12 register fields */
+#define PHY_CON12_CTRL_START_POINT_SHIFT	24
+#define PHY_CON12_CTRL_INC_SHIFT	16
+#define PHY_CON12_CTRL_FORCE_SHIFT	8
+#define PHY_CON12_CTRL_START_SHIFT	6
+#define PHY_CON12_CTRL_START_MASK	(1 << PHY_CON12_CTRL_START_SHIFT)
+#define PHY_CON12_CTRL_DLL_ON_SHIFT	5
+#define PHY_CON12_CTRL_DLL_ON_MASK	(1 << PHY_CON12_CTRL_DLL_ON_SHIFT)
+#define PHY_CON12_CTRL_REF_SHIFT	1
+
+/* PHY_CON16 register fields */
+#define PHY_CON16_ZQ_MODE_DDS_SHIFT	24
+#define PHY_CON16_ZQ_MODE_DDS_MASK	(0x7 << PHY_CON16_ZQ_MODE_DDS_SHIFT)
+
+#define PHY_CON16_ZQ_MODE_TERM_SHIFT 21
+#define PHY_CON16_ZQ_MODE_TERM_MASK	(0x7 << PHY_CON16_ZQ_MODE_TERM_SHIFT)
+
+#define PHY_CON16_ZQ_MODE_NOTERM_MASK	(1 << 19)
+
+/* PHY_CON42 register fields */
+#define PHY_CON42_CTRL_BSTLEN_SHIFT	8
+#define PHY_CON42_CTRL_BSTLEN_MASK	(0xff << PHY_CON42_CTRL_BSTLEN_SHIFT)
+
+#define PHY_CON42_CTRL_RDLAT_SHIFT	0
+#define PHY_CON42_CTRL_RDLAT_MASK	(0x1f << PHY_CON42_CTRL_RDLAT_SHIFT)
+
 #endif
 #endif

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index 330bd75..dbd5f11 100644
@@ -98,7 +98,7 @@ static unsigned long exynos5_get_pll_clk(int pllreg)
 	struct exynos5_clock *clk =
 		(struct exynos5_clock *)samsung_get_base_clock();
 	unsigned long r, m, p, s, k = 0, mask, fout;
-	unsigned int freq;
+	unsigned int freq, pll_div2_sel,  mpll_fout_sel;
 
 	switch (pllreg) {
 	case APLL:

@@ -155,6 +155,16 @@ static unsigned long exynos5_get_pll_clk(int pllreg)
 		fout = m * (freq / (p * (1 << (s - 1))));
 	}
 
+	/* According to the user manual, in EVT1 MPLL always gives
+	 * 1.6GHz clock, so divide by 2 to get 800MHz MPLL clock.*/
+	if (pllreg == MPLL) {
+		pll_div2_sel = readl(&clk->pll_div2_sel);
+		mpll_fout_sel = (pll_div2_sel >> MPLL_FOUT_SEL_SHIFT)
+				& MPLL_FOUT_SEL_MASK;
+		if (mpll_fout_sel == 0)
+			fout /= 2;
+	}
+
 	return fout;
 }
 

index 7cc3d5e..a34a3f0 100644
@@ -594,4 +594,7 @@ struct exynos5_clock {
 	unsigned char	res109b[0xf5e4];
 };
 #endif
+
+#define MPLL_FOUT_SEL_SHIFT	4
+#define MPLL_FOUT_SEL_MASK	0x1
 #endif

index d2b7d2c..7611c7a 100644
@@ -40,8 +40,8 @@ static void exynos5_uart_config(int peripheral)
 		count = 4;
 		break;
 	case PERIPH_ID_UART1:
-		bank = &gpio1->a0;
-		start = 4;
+		bank = &gpio1->d0;
+		start = 0;
 		count = 4;
 		break;
 	case PERIPH_ID_UART2:

@@ -66,25 +66,25 @@ static int exynos5_mmc_config(int peripheral, int flags)
 	struct exynos5_gpio_part1 *gpio1 =
 		(struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
 	struct s5p_gpio_bank *bank, *bank_ext;
-	int i;
+	int i, start;
 
 	switch (peripheral) {
 	case PERIPH_ID_SDMMC0:
 		bank = &gpio1->c0;
 		bank_ext = &gpio1->c1;
+		start = 0;
 		break;
 	case PERIPH_ID_SDMMC1:
-		bank = &gpio1->c1;
+		bank = &gpio1->c2;
 		bank_ext = NULL;
 		break;
 	case PERIPH_ID_SDMMC2:
-		bank = &gpio1->c2;
-		bank_ext = &gpio1->c3;
-		break;
-	case PERIPH_ID_SDMMC3:
 		bank = &gpio1->c3;
 		bank_ext = NULL;
 		break;
+	case PERIPH_ID_SDMMC3:
+		debug("SDMMC3 not supported yet");
+		return -1;
 	}
 	if ((flags & PINMUX_FLAG_8BIT_MODE) && !bank_ext) {
 		debug("SDMMC device %d does not support 8bit mode",

@@ -92,7 +92,7 @@ static int exynos5_mmc_config(int peripheral, int flags)
 		return -1;
 	}
 	if (flags & PINMUX_FLAG_8BIT_MODE) {
-		for (i = 3; i <= 6; i++) {
+		for (i = start; i <= (start + 3); i++) {
 			s5p_gpio_cfg_pin(bank_ext, i, GPIO_FUNC(0x3));
 			s5p_gpio_set_pull(bank_ext, i, GPIO_PULL_UP);
 			s5p_gpio_set_drv(bank_ext, i, GPIO_DRV_4X);

index 3b078da..b593325 100644
@@ -130,13 +130,13 @@ int board_mmc_init(bd_t *bis)
 {
 	int err;
 
-	err = exynos_pinmux_config(PERIPH_ID_SDMMC2, PINMUX_FLAG_NONE);
+	err = exynos_pinmux_config(PERIPH_ID_SDMMC0, PINMUX_FLAG_8BIT_MODE);
 	if (err) {
-		debug("SDMMC2 not configured\n");
+		debug("SDMMC0 not configured\n");
 		return err;
 	}
 
-	err = s5p_mmc_init(2, 4);
+	err = s5p_mmc_init(0, 8);
 	return err;
 }
 #endif

index 405abd5..d4d370f 100644
@@ -69,7 +69,7 @@
 
 /* select serial console configuration */
 #define CONFIG_SERIAL_MULTI
-#define CONFIG_SERIAL1			/* use SERIAL 1 */
+#define CONFIG_SERIAL3			/* use SERIAL 3 */
 #define CONFIG_BAUDRATE			115200
 #define EXYNOS5_DEFAULT_UART_OFFSET	0x010000