updates for Keymile Marvell boards

-----Original Message-----
From: Valentin Longchamp [mailto:valentin.longchamp at keymile.com]
Sent: 07 June 2012 15:37
To: prafulla at mavell.com
Cc: Valentin Longchamp; holger.brunck at keymile.com; u- boot at lists.denx.de; Gerlando Falauto; Prafulla Wadaskar
Subject: [PATCH 02/20] arm/km: use correct kw_gpio function for NAND/SPI switching

This used to be done with registers direct access, which is not clear and optimal.

Signed-off-by Valentin Longchamp <[email protected]>

Signed-off-by Holger Brunck <[email protected]>

cc Gerlando Falauto <[email protected]>

cc Prafulla Wadaskar <[email protected]>

---
 board/keymile/km_arm/km_arm.c |   53 +++++++++++++++++++++-----------
--------
 include/configs/km/km_arm.h   |    1 +
 2 files changed, 29 insertions(+), 25 deletions(-)

board/keymile/km_arm/km_arm.c +8 -6

index ed12b5c..e4ae1fb 100644
@@ -247,15 +247,12 @@ int board_early_init_f(void)
 	kirkwood_mpp_conf(kwmpp_config, NULL);
 
 	/*
-	 * The FLASH_GPIO_PIN switches between using a
+	 * The KM_FLASH_GPIO_PIN switches between using a
 	 * NAND or a SPI FLASH. Set this pin on start
 	 * to NAND mode.
 	 */
-	tmp = readl(KW_GPIO0_BASE);
-	writel(tmp | FLASH_GPIO_PIN , KW_GPIO0_BASE);
-	tmp = readl(KW_GPIO0_BASE + 4);
-	writel(tmp & (~FLASH_GPIO_PIN) , KW_GPIO0_BASE + 4);
-
+	kw_gpio_set_valid(KM_FLASH_GPIO_PIN, 1);
+	kw_gpio_direction_output(KM_FLASH_GPIO_PIN, 1);
 #if defined(CONFIG_SOFT_I2C)
 	/* init the GPIO for I2C Bitbang driver */
 	kw_gpio_set_valid(KM_KIRKWOOD_SDA_PIN, 1);

@@ -284,35 +281,41 @@ int board_init(void)
 	return 0;
 }
 
+int km_hw_spi_bus_claim(int on)
+{
+	int gpio_value = !on;
+
+	if (on) {

Quoted 61 lines

-----Original Message-----
From: Valentin Longchamp [mailto:valentin.longchamp at keymile.com]
Sent: 07 June 2012 15:37
To: prafulla at mavell.com
Cc: Valentin Longchamp; holger.brunck at keymile.com; u- boot at lists.denx.de; Gerlando Falauto; Prafulla Wadaskar
Subject: [PATCH 02/20] arm/km: use correct kw_gpio function for NAND/SPI switching

This used to be done with registers direct access, which is not clear and optimal.

Signed-off-by Valentin Longchamp <[email protected]>

Signed-off-by Holger Brunck <[email protected]>

cc Gerlando Falauto <[email protected]>

cc Prafulla Wadaskar <[email protected]>

---
 board/keymile/km_arm/km_arm.c |   53 +++++++++++++++++++++-----------
--------
 include/configs/km/km_arm.h   |    1 +
 2 files changed, 29 insertions(+), 25 deletions(-)

board/keymile/km_arm/km_arm.c +12 -6

index ed12b5c..e4ae1fb 100644
@@ -247,15 +247,12 @@ int board_early_init_f(void)
 	kirkwood_mpp_conf(kwmpp_config, NULL);
 
 	/*
-	 * The FLASH_GPIO_PIN switches between using a
+	 * The KM_FLASH_GPIO_PIN switches between using a
 	 * NAND or a SPI FLASH. Set this pin on start
 	 * to NAND mode.
 	 */
-	tmp = readl(KW_GPIO0_BASE);
-	writel(tmp | FLASH_GPIO_PIN , KW_GPIO0_BASE);
-	tmp = readl(KW_GPIO0_BASE + 4);
-	writel(tmp & (~FLASH_GPIO_PIN) , KW_GPIO0_BASE + 4);
-
+	kw_gpio_set_valid(KM_FLASH_GPIO_PIN, 1);
+	kw_gpio_direction_output(KM_FLASH_GPIO_PIN, 1);
 #if defined(CONFIG_SOFT_I2C)
 	/* init the GPIO for I2C Bitbang driver */
 	kw_gpio_set_valid(KM_KIRKWOOD_SDA_PIN, 1);

@@ -284,35 +281,41 @@ int board_init(void)
 	return 0;
 }
 
+int km_hw_spi_bus_claim(int on)
+{
+	int gpio_value = !on;
+
+	if (on) {
+		kwmpp_config[0] = MPP0_SPI_SCn;
+		kwmpp_config[1] = MPP1_SPI_MOSI;
+		kwmpp_config[2] = MPP2_SPI_SCK;
+		kwmpp_config[3] = MPP3_SPI_MISO;

board/keymile/km_arm/km_arm.c int board_init(void) · line 298

Quoted 6 lines

board/keymile/km_arm/km_arm.c +6 -0

+	} else {
+		kwmpp_config[0] = MPP0_NF_IO2;
+		kwmpp_config[1] = MPP1_NF_IO3;
+		kwmpp_config[2] = MPP2_NF_IO4;
+		kwmpp_config[3] = MPP3_NF_IO5;
+	}

NACK...

-----Original Message-----
From: Holger Brunck [mailto:holger.brunck at keymile.com]
Sent: 12 June 2012 14:08
To: Prafulla Wadaskar
Cc: Valentin Longchamp; prafulla at mavell.com; u-boot at lists.denx.de; Gerlando Falauto
Subject: Re: [PATCH 02/20] arm/km: use correct kw_gpio function for NAND/SPI switching

Quoted 11 lines · Prafulla Wadaskar

Quoted 11 lines

-----Original Message-----
From: Valentin Longchamp [mailto:valentin.longchamp at keymile.com]
Sent: 07 June 2012 15:37
To: prafulla at mavell.com
Cc: Valentin Longchamp; holger.brunck at keymile.com; u- boot at lists.denx.de; Gerlando Falauto; Prafulla Wadaskar
Subject: [PATCH 02/20] arm/km: use correct kw_gpio function for NAND/SPI switching

Quoted 1 line

Quoted 1 line

This used to be done with registers direct access, which is not

clear

Quoted 8 lines

Quoted 8 lines

and optimal.

Signed-off-by Valentin Longchamp <[email protected]>

Signed-off-by Holger Brunck <[email protected]>

cc Gerlando Falauto <[email protected]>

cc Prafulla Wadaskar <[email protected]>

---
 board/keymile/km_arm/km_arm.c |   53 +++++++++++++++++++++--------

---

Quoted 41 lines

Quoted 41 lines

--------

 include/configs/km/km_arm.h   |    1 +
 2 files changed, 29 insertions(+), 25 deletions(-)

board/keymile/km_arm/km_arm.c +12 -6

index ed12b5c..e4ae1fb 100644
@@ -247,15 +247,12 @@ int board_early_init_f(void)
 	kirkwood_mpp_conf(kwmpp_config, NULL);
 
 	/*
-	 * The FLASH_GPIO_PIN switches between using a
+	 * The KM_FLASH_GPIO_PIN switches between using a
 	 * NAND or a SPI FLASH. Set this pin on start
 	 * to NAND mode.
 	 */
-	tmp = readl(KW_GPIO0_BASE);
-	writel(tmp | FLASH_GPIO_PIN , KW_GPIO0_BASE);
-	tmp = readl(KW_GPIO0_BASE + 4);
-	writel(tmp & (~FLASH_GPIO_PIN) , KW_GPIO0_BASE + 4);
-
+	kw_gpio_set_valid(KM_FLASH_GPIO_PIN, 1);
+	kw_gpio_direction_output(KM_FLASH_GPIO_PIN, 1);
 #if defined(CONFIG_SOFT_I2C)
 	/* init the GPIO for I2C Bitbang driver */
 	kw_gpio_set_valid(KM_KIRKWOOD_SDA_PIN, 1);

@@ -284,35 +281,41 @@ int board_init(void)
 	return 0;
 }
 
+int km_hw_spi_bus_claim(int on)
+{
+	int gpio_value = !on;
+
+	if (on) {
+		kwmpp_config[0] = MPP0_SPI_SCn;
+		kwmpp_config[1] = MPP1_SPI_MOSI;
+		kwmpp_config[2] = MPP2_SPI_SCK;
+		kwmpp_config[3] = MPP3_SPI_MISO;

Quoted 9 lines

board/keymile/km_arm/km_arm.c int board_init(void) · line 298

Quoted 6 lines

board/keymile/km_arm/km_arm.c +6 -0

+	} else {
+		kwmpp_config[0] = MPP0_NF_IO2;
+		kwmpp_config[1] = MPP1_NF_IO3;
+		kwmpp_config[2] = MPP2_NF_IO4;
+		kwmpp_config[3] = MPP3_NF_IO5;
+	}

NACK...

Could you please be a bit more verbose. Why do you NACK this? This code is only
related to our boards...

Quoted 85 lines

-----Original Message-----
From: Holger Brunck [mailto:holger.brunck at keymile.com]
Sent: 12 June 2012 14:08
To: Prafulla Wadaskar
Cc: Valentin Longchamp; prafulla at mavell.com; u-boot at lists.denx.de; Gerlando Falauto
Subject: Re: [PATCH 02/20] arm/km: use correct kw_gpio function for NAND/SPI switching

Quoted 11 lines · Prafulla Wadaskar

Quoted 11 lines

-----Original Message-----
From: Valentin Longchamp [mailto:valentin.longchamp at keymile.com]
Sent: 07 June 2012 15:37
To: prafulla at mavell.com
Cc: Valentin Longchamp; holger.brunck at keymile.com; u- boot at lists.denx.de; Gerlando Falauto; Prafulla Wadaskar
Subject: [PATCH 02/20] arm/km: use correct kw_gpio function for NAND/SPI switching

Quoted 1 line

Quoted 1 line

This used to be done with registers direct access, which is not

clear

Quoted 8 lines

Quoted 8 lines

and optimal.

Signed-off-by Valentin Longchamp <[email protected]>

Signed-off-by Holger Brunck <[email protected]>

cc Gerlando Falauto <[email protected]>

cc Prafulla Wadaskar <[email protected]>

---
 board/keymile/km_arm/km_arm.c |   53 +++++++++++++++++++++--------

---

Quoted 41 lines

Quoted 41 lines

--------

 include/configs/km/km_arm.h   |    1 +
 2 files changed, 29 insertions(+), 25 deletions(-)

board/keymile/km_arm/km_arm.c +12 -6

index ed12b5c..e4ae1fb 100644
@@ -247,15 +247,12 @@ int board_early_init_f(void)
 	kirkwood_mpp_conf(kwmpp_config, NULL);
 
 	/*
-	 * The FLASH_GPIO_PIN switches between using a
+	 * The KM_FLASH_GPIO_PIN switches between using a
 	 * NAND or a SPI FLASH. Set this pin on start
 	 * to NAND mode.
 	 */
-	tmp = readl(KW_GPIO0_BASE);
-	writel(tmp | FLASH_GPIO_PIN , KW_GPIO0_BASE);
-	tmp = readl(KW_GPIO0_BASE + 4);
-	writel(tmp & (~FLASH_GPIO_PIN) , KW_GPIO0_BASE + 4);
-
+	kw_gpio_set_valid(KM_FLASH_GPIO_PIN, 1);
+	kw_gpio_direction_output(KM_FLASH_GPIO_PIN, 1);
 #if defined(CONFIG_SOFT_I2C)
 	/* init the GPIO for I2C Bitbang driver */
 	kw_gpio_set_valid(KM_KIRKWOOD_SDA_PIN, 1);

@@ -284,35 +281,41 @@ int board_init(void)
 	return 0;
 }
 
+int km_hw_spi_bus_claim(int on)
+{
+	int gpio_value = !on;
+
+	if (on) {
+		kwmpp_config[0] = MPP0_SPI_SCn;
+		kwmpp_config[1] = MPP1_SPI_MOSI;
+		kwmpp_config[2] = MPP2_SPI_SCK;
+		kwmpp_config[3] = MPP3_SPI_MISO;

Quoted 9 lines

board/keymile/km_arm/km_arm.c int board_init(void) · line 298

Quoted 6 lines

board/keymile/km_arm/km_arm.c +6 -0

+	} else {
+		kwmpp_config[0] = MPP0_NF_IO2;
+		kwmpp_config[1] = MPP1_NF_IO3;
+		kwmpp_config[2] = MPP2_NF_IO4;
+		kwmpp_config[3] = MPP3_NF_IO5;
+	}

NACK...

Quoted 3 lines

Could you please be a bit more verbose. Why do you NACK this? This code is only
related to our boards...

Dear Holger
We have already patches for Kirkwood-spi in place that address this. So we have to use this framework.

Ref: http://lists.denx.de/pipermail/u-boot/2012-June/125574.html

Quoted 93 lines · Prafulla Wadaskar

Quoted 85 lines

-----Original Message-----
From: Holger Brunck [mailto:holger.brunck at keymile.com]
Sent: 12 June 2012 14:08
To: Prafulla Wadaskar
Cc: Valentin Longchamp; prafulla at mavell.com; u-boot at lists.denx.de; Gerlando Falauto
Subject: Re: [PATCH 02/20] arm/km: use correct kw_gpio function for NAND/SPI switching

Quoted 11 lines · Prafulla Wadaskar

Quoted 11 lines

-----Original Message-----
From: Valentin Longchamp [mailto:valentin.longchamp at keymile.com]
Sent: 07 June 2012 15:37
To: prafulla at mavell.com
Cc: Valentin Longchamp; holger.brunck at keymile.com; u- boot at lists.denx.de; Gerlando Falauto; Prafulla Wadaskar
Subject: [PATCH 02/20] arm/km: use correct kw_gpio function for NAND/SPI switching

Quoted 1 line

Quoted 1 line

This used to be done with registers direct access, which is not

clear

Quoted 8 lines

Quoted 8 lines

and optimal.

Signed-off-by Valentin Longchamp <[email protected]>

Signed-off-by Holger Brunck <[email protected]>

cc Gerlando Falauto <[email protected]>

cc Prafulla Wadaskar <[email protected]>

---
 board/keymile/km_arm/km_arm.c |   53 +++++++++++++++++++++--------

---

Quoted 41 lines

Quoted 41 lines

--------

 include/configs/km/km_arm.h   |    1 +
 2 files changed, 29 insertions(+), 25 deletions(-)

board/keymile/km_arm/km_arm.c +12 -6

index ed12b5c..e4ae1fb 100644
@@ -247,15 +247,12 @@ int board_early_init_f(void)
 	kirkwood_mpp_conf(kwmpp_config, NULL);
 
 	/*
-	 * The FLASH_GPIO_PIN switches between using a
+	 * The KM_FLASH_GPIO_PIN switches between using a
 	 * NAND or a SPI FLASH. Set this pin on start
 	 * to NAND mode.
 	 */
-	tmp = readl(KW_GPIO0_BASE);
-	writel(tmp | FLASH_GPIO_PIN , KW_GPIO0_BASE);
-	tmp = readl(KW_GPIO0_BASE + 4);
-	writel(tmp & (~FLASH_GPIO_PIN) , KW_GPIO0_BASE + 4);
-
+	kw_gpio_set_valid(KM_FLASH_GPIO_PIN, 1);
+	kw_gpio_direction_output(KM_FLASH_GPIO_PIN, 1);
 #if defined(CONFIG_SOFT_I2C)
 	/* init the GPIO for I2C Bitbang driver */
 	kw_gpio_set_valid(KM_KIRKWOOD_SDA_PIN, 1);

@@ -284,35 +281,41 @@ int board_init(void)
 	return 0;
 }
 
+int km_hw_spi_bus_claim(int on)
+{
+	int gpio_value = !on;
+
+	if (on) {
+		kwmpp_config[0] = MPP0_SPI_SCn;
+		kwmpp_config[1] = MPP1_SPI_MOSI;
+		kwmpp_config[2] = MPP2_SPI_SCK;
+		kwmpp_config[3] = MPP3_SPI_MISO;

Quoted 9 lines

board/keymile/km_arm/km_arm.c int board_init(void) · line 298

Quoted 6 lines

board/keymile/km_arm/km_arm.c +6 -0

+	} else {
+		kwmpp_config[0] = MPP0_NF_IO2;
+		kwmpp_config[1] = MPP1_NF_IO3;
+		kwmpp_config[2] = MPP2_NF_IO4;
+		kwmpp_config[3] = MPP3_NF_IO5;
+	}

NACK...

Quoted 3 lines

Could you please be a bit more verbose. Why do you NACK this? This code is only
related to our boards...

Dear Holger
We have already patches for Kirkwood-spi in place that address this. So we have to use this framework.

Quoted 2 lines

Ref: http://lists.denx.de/pipermail/u-boot/2012-June/125574.html

ok I see what you mean. We make use of it later on:
[PATCH 18/20] arm/km: implement weak function board_spi_clam_bus/release I'll squash this one together with 02/20 then it is more clear.

-----Original Message-----
From: Valentin Longchamp [mailto:valentin.longchamp at keymile.com]
Sent: 07 June 2012 15:37
To: prafulla at mavell.com
Cc: Holger Brunck; u-boot at lists.denx.de; Valentin Longchamp; Gerlando Falauto; Prafulla Wadaskar
Subject: [PATCH 04/20] arm/km: add kmnusa board support

From: Holger Brunck <[email protected]>

This board is similar to portl2, but it has the u-boot environment in a SPI NOR flash and not in an i2c eeprom like portl2 have.

Some other details:
- IVM EEPROM is at adress: pca9547:70:9
- PCI is enabled
- PIGGY4 is connected via MV88E6352 simple switch. There is no phy between the simple switch and the kirkwood.

Signed-off-by Holger Brunck <[email protected]>

Signed-off-by Valentin Longchamp <[email protected]>

cc Gerlando Falauto <[email protected]>

cc Prafulla Wadaskar <[email protected]>

---
 MAINTAINERS                       |    1 +
 board/keymile/km_arm/128M16-1.cfg |  294

+++++++++++++++++++++++++++++++++++++

 board/keymile/km_arm/km_arm.c     |    9 +-
 boards.cfg                        |    1 +
 include/configs/km/km_arm.h       |   44 +++++-
 include/configs/km_kirkwood.h     |   67 +++++++--
 6 files changed, 392 insertions(+), 24 deletions(-)
 create mode 100644 board/keymile/km_arm/128M16-1.cfg

MAINTAINERS +0 -0

index 0445539..aa11268 100644

MAINTAINERS +0 -0

      mgcoge3un       ARM926EJS (Kirkwood SoC)
      portl2          ARM926EJS (Kirkwood SoC)
 

board/keymile/km_arm/128M16-1.cfg new file +142 -0

new file mode 100644
index 0000000..bcce907
@@ -0,0 +1,294 @@
+#
+# (C) Copyright 2010
+# Heiko Schocher, DENX Software Engineering, hs at denx.de.
+#
+# (C) Copyright 2012
+# Valentin Longchamp, Keymile AG, valentin.longchamp at keymile.com
+# Stefan Bigler, Keymile AG, stefan.bigler at keymile.com
+#
+# (C) Copyright 2012
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+# Refer docs/README.kwimage for more details about how-to configure
+# and create kirkwood boot image
+#
+
+# Boot Media configurations
+BOOT_FROM    spi     # Boot from SPI flash
+
+DATA 0xFFD10000 0x01112222   # MPP Control 0 Register
+# bit 3-0:   2, MPPSel0  SPI_CSn  (1=NF_IO[2])
+# bit 7-4:   2, MPPSel1  SPI_SI   (1=NF_IO[3])
+# bit 12-8:  2, MPPSel2  SPI_SCK  (1=NF_IO[4])
+# bit 15-12: 2, MPPSel3  SPI_SO   (1=NF_IO[5])
+# bit 19-16: 1, MPPSel4  NF_IO[6]
+# bit 23-20: 1, MPPSel5  NF_IO[7]
+# bit 27-24: 1, MPPSel6  SYSRST_O
+# bit 31-28: 0, MPPSel7  GPO[7]
+
+DATA 0xFFD10004 0x03303300   # MPP Control 1 Register
+# bit 3-0:   0, MPPSel8       GPIO[8]
+# bit 7-4:   0, MPPSel9  GPIO[9]
+# bit 12-8:  3, MPPSel10 UA0_TXD
+# bit 15-12: 3, MPPSel11 UA0_RXD
+# bit 19-16: 0, MPPSel12 not connected
+# bit 23-20: 3, MPPSel13 UA1_TXD
+# bit 27-24: 3, MPPSel14 UA1_RXD
+# bit 31-28: 0, MPPSel15 GPIO[15]
+
+DATA 0xFFD10008 0x00001100   # MPP Control 2 Register
+# bit 3-0:   0, MPPSel16 GPIO[16]
+# bit 7-4:   0, MPPSel17 not connected
+# bit 12-8:  1, MPPSel18 NF_IO[0]
+# bit 15-12: 1, MPPSel19 NF_IO[1]
+# bit 19-16: 0, MPPSel20 GPIO[20]
+# bit 23-20: 0, MPPSel21 GPIO[21]
+# bit 27-24: 0, MPPSel22 GPIO[22]
+# bit 31-28: 0, MPPSel23 GPIO[23]
+
+# MPP Control 3-6 Register untouched (MPP24-49)
+
+DATA 0xFFD100E0 0x1B1B1B1B   # IO Configuration 0 Register
+# bit 2-0:   3, Reserved
+# bit 5-3:   3, Reserved
+# bit 6:     0, Reserved
+# bit 7:     0, RGMII-pads voltage = 3.3V
+# bit 10-8:  3, Reserved
+# bit 13-11: 3, Reserved
+# bit 14:    0, Reserved
+# bit 15:    0, MPP RGMII-pads voltage = 3.3V
+# bit 31-16  0x1B1B, Reserved
+
+DATA 0xFFD20134 0x66666666   # L2 RAM Timing 0 Register
+# bit 0-1:   2, Tag RAM RTC RAM0
+# bit 3-2:   1, Tag RAM WTC RAM0
+# bit 7-4:   6, Reserve
+# bit 9-8:   2, Valid RAM RTC RAM
+# bit 11-10: 1, Valid RAM WTC RAM
+# bit 13-12: 2, Dirty RAM RTC RAM
+# bit 15-14: 1, Dirty RAM WTC RAM
+# bit 17-16: 2, Data RAM RTC RAM0
+# bit 19-18: 1, Data RAM WTC RAM0
+# bit 21-20: 2, Data RAM RTC RAM1
+# bit 23-22: 1, Data RAM WTC RAM1
+# bit 25-24: 2, Data RAM RTC RAM2
+# bit 27-26: 1, Data RAM WTC RAM2
+# bit 29-28: 2, Data RAM RTC RAM3
+# bit 31-30: 1, Data RAM WTC RAM4
+
+DATA 0xFFD20138 0x66666666   # L2 RAM Timing 1 Register
+# bit 15-0:  ???, Reserve
+# bit 17-16: 2, ECC RAM RTC RAM0
+# bit 19-18: 1, ECC RAM WTC RAM0
+# bit 31-20: ???,Reserve
+
+DATA 0xFFD20154 0x00000200   # CPU RAM Management Control3 Register
+# bit 23-0:  0x000200, Addr Config tuning
+# bit 31-24: 0,        Reserved
+
+# ??? Missing register # CPU RAM Management Control2 Register
+
+DATA 0xFFD2014C 0x00001C00   # CPU RAM Management Control1 Register
+# bit 15-0:  0x1C00, Opmux Tuning
+# bit 31-16: 0,      Pc Dp Tuning
+
+DATA 0xFFD20148 0x00000001   # CPU RAM Management Control0 Register
+# bit 1-0:   1, addr clk tune
+# bit 3-2:   0, reserved
+# bit 5-4:   0, dtcmp clk tune
+# bit 7-6:   0, reserved
+# bit 9-8:   0, macdrv clk tune
+# bit 11-10: 0, opmuxgm2 clk tune
+# bit 15-14: 0, rf clk tune
+# bit 17-16: 0, rfbypass clk tune
+# bit 19-18: 0, pc dp clk tune
+# bit 23-20: 0, icache clk tune
+# bit 27:24: 0, dcache clk tune
+# bit 31:28: 0, regfile tunin
+
+# SDRAM initalization
+DATA 0xFFD01400 0x430004E0   # SDRAM Configuration Register
+# bit 13-0:  0x4E0, DDR2 clks refresh rate
+# bit 14:    0, reserved
+# bit 15:    0, reserved
+# bit 16:    0, CPU to Dram Write buffer policy
+# bit 17:    0, Enable Registered DIMM or Equivalent Sampling Logic
+# bit 19-18: 0, reserved
+# bit 23-20: 0, reserved
+# bit 24:    1, enable exit self refresh mode on DDR access
+# bit 25:    1, required
+# bit 29-26: 0, reserved
+# bit 31-30: 1, reserved
+
+DATA 0xFFD01404 0x36543000   # DDR Controller Control Low
+# bit 3-0:   0, reserved
+# bit 4:     0, 2T mode =addr/cmd in same cycle
+# bit 5:     0, clk is driven during self refresh, we don't care for

APX

board/keymile/km_arm/128M16-1.cfg new file +8 -0

+# bit 6:     0, use recommended falling edge of clk for addr/cmd
+# bit 7-11:  0, reserved
+# bit 12-13: 1, reserved, required 1
+# bit 14:    0, input buffer always powered up
+# bit 17-15: 0, reserved
+# bit 18:    1, cpu lock transaction enabled
+# bit 19:    0, reserved
+# bit 23-20: 5, recommended value for CL=4 and STARTBURST_DEL

disabled bit31=0
+# bit 27-24: 6, CL+1, STARTBURST sample stages, for freqs 200-399MHz, unbuffered DIMM

board/keymile/km_arm/128M16-1.cfg new file +95 -0

+# bit 30-28: 3, required
+# bit 31:    0,no additional STARTBURST delay
+
+DATA 0xFFD01408 0x2302444e   # DDR Timing (Low) (active cycles value
+1)
+# bit 3-0:   0xE, TRAS, 15 clk (45 ns)
+# bit 7-4:   0x4, TRCD, 5 clk (15 ns)
+# bit 11-8:  0x4, TRP, 5 clk (15 ns)
+# bit 15-12: 0x4, TWR, 5 clk (15 ns)
+# bit 19-16: 0x2, TWTR, 3 clk (7.5 ns)
+# bit 20:      0, extended TRAS msb
+# bit 23-21:   0, reserved
+# bit 27-24: 0x3, TRRD, 4 clk (10 ns)
+# bit 31-28: 0x2, TRTP, 3 clk (7.5 ns)
+
+DATA 0xFFD0140C 0x0000003e   #  DDR Timing (High)
+# bit 6-0:   0x3E, TRFC, 63 clk (195 ns)
+# bit 8-7:      0, TR2R
+# bit 10-9:     0, TR2W
+# bit 12-11:    0, TW2W
+# bit 31-13:    0, reserved
+
+DATA 0xFFD01410 0x00000001   #  DDR Address Control
+# bit 1-0:    1, Cs0width=x16
+# bit 3-2:    0, Cs0size=2Gb
+# bit 5-4:    0, Cs1width=nonexistent
+# bit 7-6:    0, Cs1size =nonexistent
+# bit 9-8:    0, Cs2width=nonexistent
+# bit 11-10:  0, Cs2size =nonexistent
+# bit 13-12:  0, Cs3width=nonexistent
+# bit 15-14:  0, Cs3size =nonexistent
+# bit 16:     0, Cs0AddrSel
+# bit 17:     0, Cs1AddrSel
+# bit 18:     0, Cs2AddrSel
+# bit 19:     0, Cs3AddrSel
+# bit 31-20:  0, required
+
+DATA 0xFFD01414 0x00000000   #  DDR Open Pages Control
+# bit 0:      0,  OpenPage enabled
+# bit 31-1:   0, required
+
+DATA 0xFFD01418 0x00000000   #  DDR Operation
+# bit 3-0:    0, DDR cmd
+# bit 31-4:   0, required
+
+DATA 0xFFD0141C 0x00000652   #  DDR Mode
+# bit 2-0:    2, Burst Length = 4
+# bit 3:      0, Burst Type
+# bit 6-4:    5, CAS Latency = 5
+# bit 7:      0, Test mode
+# bit 8:      0, DLL Reset
+# bit 11-9:   3, Write recovery for auto-precharge must be 3
+# bit 12:     0, Active power down exit time, fast exit
+# bit 14-13:  0, reserved
+# bit 31-15:  0, reserved
+
+DATA 0xFFD01420 0x00000006   #  DDR Extended Mode
+# bit 0:      0, DDR DLL enabled
+# bit 1:      1,  DDR drive strength reduced
+# bit 2:      1,  DDR ODT control lsb, 75 ohm termination [RTT0]
+# bit 5-3:    0, required
+# bit 6:      0, DDR ODT control msb, 75 ohm termination [RTT1]
+# bit 9-7:    0, required
+# bit 10:     0, differential DQS enabled
+# bit 11:     0, required
+# bit 12:     0, DDR output buffer enabled
+# bit 31-13:  0 required
+
+DATA 0xFFD01424 0x0000F17F   #  DDR Controller Control High
+# bit 2-0:    7, required
+# bit 3:      1, MBUS Burst Chop disabled
+# bit 6-4:    7, required
+# bit 7:      0, reserved
+# bit 8:      1, add sample stage required for f > 266 MHz
+# bit 9:      0, no half clock cycle addition to dataout
+# bit 10:     0, 1/4 clock cycle skew enabled for addr/ctl signals
+# bit 11:     0, 1/4 clock cycle skew disabled for write mesh
+# bit 15-12:0xf, required
+# bit 31-16:  0, required
+
+DATA 0xFFD01428 0x00084520   # DDR2 SDRAM Timing Low
+# bit 3-0:    0, required
+# bit 7-4:    2, M_ODT assertion 2 cycles after read start command
+# bit 11-8:   5, M_ODT de-assertion 5 cycles after read start command
+#                (ODT turn off delay 2,5 clk cycles)
+# bit 15-12:  4, internal ODT time based on bit 7-4
+#                with the considered SDRAM internal delay
+# bit 19-16:  8, internal ODT de-assertion based on bit 11-8
+#                with the considered SDRAM internal delay
+# bit 31-20:  0, required
+
+DATA 0xFFD0147c 0x00008452   # DDR2 SDRAM Timing High
+# bit 3-0:    2, M_ODT assertion same as bit 11-8
+# bit 7-4:    5, M_ODT de-assertion same as bit 15-12
+# bit 11-8:   4, internal ODT assertion 2 cycles after write start

command

board/keymile/km_arm/128M16-1.cfg new file +2 -0

+#                with the considered SDRAM internal delay
+# bit 15-12:  8, internal ODT de-assertion 5 cycles after write start

command

board/keymile/km_arm/128M16-1.cfg new file +19 -0

+#                with the considered SDRAM internal delay
+
+DATA 0xFFD01500 0x00000000   # CS[0]n Base address to 0x0
+# bit 23-0:   0, reserved
+# bit 31-24:  0, CPU CS Window0 Base Address, addr bits [31:24]
+
+DATA 0xFFD01504 0x0FFFFFF1   # CS[0]n Size
+# bit 0:      1, Window enabled
+# bit 1:      0, Write Protect disabled
+# bit 3-2:    0, CS0 hit selected
+# bit 23-4:ones, required
+# bit 31-24: 0x0F, Size (i.e. 256MB)
+
+DATA 0xFFD0150C 0x00000000   # CS[1]n Size, window disabled
+DATA 0xFFD01514 0x00000000   # CS[2]n Size, window disabled
+DATA 0xFFD0151C 0x00000000   # CS[3]n Size, window disabled
+
+DATA 0xFFD01494 0x00010000   #  DDR ODT Control (Low)
+# bit 3-0:     0, ODT0Rd, MODT[0] not asserted during read from DRAM

CS0

board/keymile/km_arm/128M16-1.cfg new file +15 -0

+# bit 7-4:     0, ODT0Rd, MODT[1] not asserted
+# bit 11-8:    0, required
+# big 15-11:   0, required
+# bit 19-16:   1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
+# bit 23-20:   0, ODT0Wr, MODT[1] not asserted
+# bit 27-24:   0, required
+# bit 31-28:   0, required
+
+DATA 0xFFD01498 0x00000000   #  DDR ODT Control (High)
+# bit 1-0:     0, ODT0 controlled by ODT Control (low) register above
+# bit 3-2:     0, ODT1 controlled by register
+# bit 31-4:    0, required
+
+DATA 0xFFD0149C 0x0000E801   # CPU ODT Control
+# bit 3-0:     1, ODTRd, Internal ODT asserted during read from DRAM

bank0
+# bit 7-4: 0, ODTWr, Internal ODT not asserted during write to
DRAM

board/keymile/km_arm/128M16-1.cfg new file +1 -0

+# bit 9-8:     0, ODTEn, controlled by ODTRd and ODTWr

board/keymile/km_arm/128M16-1.cfg new file +1 -0

+DATA 0x0 0x0

board/keymile/km_arm/km_arm.c +2 -2

index e4ae1fb..ffe13cd 100644
@@ -133,10 +133,11 @@ int startup_allowed(void)
 }
 #endif
 
-#if (defined(CONFIG_MGCOGE3UN)|defined(CONFIG_PORTL2))
+#if (defined(CONFIG_MGCOGE3UN)|defined(CONFIG_PORTL2)| \
+     defined(CONFIG_KM_PIGGY4_88E6352))
 /*
- * These two boards have always ethernet present. Its connected to

the mv
- * switch.
+ * All boards with PIGGY4 connected via a simple switch have ethernet always
+ * present.
*/
int ethernet_present(void)
{

board/keymile/km_arm/km_arm.c +1 -1

@@ -384,7 +385,7 @@ void reset_phy(void)
      /* reset the phy */
      miiphy_reset(name, CONFIG_PHY_BASE_ADR);
 }
-#else
+#elif !defined(CONFIG_KM_PIGGY4_88E6352)
 /* Configure and enable MV88E1118 PHY on the piggy*/
 void reset_phy(void)
 {

boards.cfg +0 -1

index b711e0d..1a4c2ad 100644
@@ -140,6 +140,7 @@ pogo_e02                     arm         arm926ejs
-                   clouden
 dns325                       arm         arm926ejs   -

d-link kirkwood
km_kirkwood arm arm926ejs km_arm
keymile kirkwood km_kirkwood:KM_KIRKWOOD,KM_DISABLE_PCI
km_kirkwood_pci arm arm926ejs km_arm
keymile kirkwood km_kirkwood:KM_KIRKWOOD_PCI,KM_RECONFIG_XLX
+kmnusa arm arm926ejs km_arm

keymile kirkwood km_kirkwood:KM_NUSA
mgcoge3un arm arm926ejs km_arm
keymile kirkwood
portl2 arm arm926ejs km_arm
keymile kirkwood
inetspace_v2 arm arm926ejs netspace_v2
LaCie kirkwood lacie_kw:INETSPACE_V2

include/configs/km/km_arm.h +0 -0

index 28b5021..a35ef61 100644

include/configs/km/km_arm.h +0 -0

 #include "asm/arch/config.h"
 
 #define CONFIG_SYS_TEXT_BASE 0x07d00000      /* code address before reloc

*/

include/configs/km/km_arm.h +2 -0

@@ -211,6 +218,15 @@ int get_scl(void);
 /*
  *  Environment variables configurations
  */
+#if defined CONFIG_KM_ENV_IS_IN_SPI_NOR
+#define CONFIG_ENV_IS_IN_SPI_FLASH  /* use SPI-Flash for environment

vars */

include/configs/km/km_arm.h +2 -0

+#define CONFIG_ENV_OFFSET            0xc0000     /* no bracets! */
+#define CONFIG_ENV_SIZE                      0x02000     /* Size of Environment

*/

include/configs/km/km_arm.h +5 -0

+#define CONFIG_ENV_SECT_SIZE         0x10000
+#define CONFIG_ENV_OFFSET_REDUND     (CONFIG_ENV_OFFSET + \
+                                     CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_TOTAL_SIZE                0x20000     /* no bracets! */
+#else
 #define CONFIG_ENV_IS_IN_EEPROM              /* use EEPROM for environment

vars */
#define CONFIG_SYS_DEF_EEPROM_ADDR 0x50
#define CONFIG_ENV_EEPROM_IS_ON_I2C

include/configs/km/km_arm.h +19 -9

@@ -218,11 +234,11 @@ int get_scl(void);
 #define CONFIG_ENV_OFFSET            0x0 /* no bracets! */
 #define CONFIG_ENV_SIZE                      (0x2000 - CONFIG_ENV_OFFSET)
 #define CONFIG_I2C_ENV_EEPROM_BUS    KM_ENV_BUS "\0"
-
-/* offset redund: (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) */
-#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
 #define CONFIG_ENV_OFFSET_REDUND     0x2000 /* no bracets! */
 #define CONFIG_ENV_SIZE_REDUND               (CONFIG_ENV_SIZE)
+#endif
+
+#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
 
 #define CONFIG_SPI_FLASH
 #define CONFIG_SPI_FLASH_STMICRO

@@ -245,17 +261,27 @@ int get_scl(void);
              "sf write ${load_addr_r} 0 ${filesize};"                \
              "spi off\0"
 
-/*
- * Default environment variables
- */
-#define CONFIG_EXTRA_ENV_SETTINGS                                    \
-     CONFIG_KM_DEF_ENV                                               \
+#if defined CONFIG_KM_ENV_IS_IN_SPI_NOR
+#define CONFIG_KM_NEW_ENV                                            \
+     "newenv=sf probe 0;"                                            \
+             "sf erase " xstr(CONFIG_ENV_OFFSET) " "                 \
+             xstr(CONFIG_ENV_TOTAL_SIZE)"\0"
+#else
+#define CONFIG_KM_NEW_ENV                                            \
      "newenv=setenv addr 0x100000 && "                               \
              "i2c dev 1; mw.b ${addr} 0 4 && "                       \
              "eeprom write " xstr(CONFIG_SYS_DEF_EEPROM_ADDR)        \
              " ${addr} " xstr(CONFIG_ENV_OFFSET) " 4 && "            \
              "eeprom write " xstr(CONFIG_SYS_DEF_EEPROM_ADDR)        \
-             " ${addr} " xstr(CONFIG_ENV_OFFSET_REDUND) " 4\0"       \
+             " ${addr} " xstr(CONFIG_ENV_OFFSET_REDUND) " 4\0"
+#endif
+
+/*
+ * Default environment variables
+ */
+#define CONFIG_EXTRA_ENV_SETTINGS                                    \
+     CONFIG_KM_DEF_ENV                                               \
+     CONFIG_KM_NEW_ENV                                               \
      "arch=arm\0"                                                    \
      "EEprom_ivm=" KM_IVM_BUS "\0"                                   \
      ""

include/configs/km_kirkwood.h +29 -11

index f639edc..97aa617 100644
@@ -6,8 +6,9 @@
  * (C) Copyright 2009
  * Stefan Roese, DENX Software Engineering, sr at denx.de.
  *
- * (C) Copyright 2011
- * Holger Brunck, Keymile GmbH Hannover, holger.brunck at keymile.de
+ * (C) Copyright 2011-2012
+ * Holger Brunck, Keymile GmbH Hannover, holger.brunck at keymile.com
+ * Valentin Longchamp, Keymile AG, valentin.longchamp at keymile.com
  *
  * See file CREDITS for list of people who contributed to this
  * project.

@@ -36,23 +37,67 @@
 #ifndef _CONFIG_KM_KIRKWOOD_H
 #define _CONFIG_KM_KIRKWOOD_H
 
-/* include common defines/options for all arm based Keymile boards */
-#include "km/km_arm.h"
-
-/*
- * Version number information
- */
 #if defined(CONFIG_KM_KIRKWOOD)
-#define CONFIG_IDENT_STRING  "\nKeymile Kirkwood"
+#define CONFIG_IDENT_STRING          "\nKeymile Kirkwood"
 #undef  CONFIG_KIRKWOOD_PCIE_INIT
+#define KM_IVM_BUS                   "pca9544a:70:9" /* I2C2 (Mux-Port 1)*/
 #elif defined(CONFIG_KM_KIRKWOOD_PCI)
-#define CONFIG_IDENT_STRING  "\nKeymile Kirkwood PCI"
+#define CONFIG_IDENT_STRING          "\nKeymile Kirkwood PCI"
+#define KM_IVM_BUS                   "pca9544a:70:9" /* I2C2 (Mux-Port 1)*/
+/* KM_NUSA */
+#elif defined(CONFIG_KM_NUSA)
+#define KM_IVM_BUS                   "pca9547:70:9"  /* I2C2 (Mux-Port 1)*/
+#define CONFIG_IDENT_STRING          "\nKeymile NUSA"
+#undef CONFIG_SYS_KWD_CONFIG
+#define CONFIG_SYS_KWD_CONFIG \
+             $(SRCTREE)/$(CONFIG_BOARDDIR)/128M16-1.cfg
+#define CONFIG_KM_ENV_IS_IN_SPI_NOR
+#define CONFIG_KM_FPGA_CONFIG
+#define CONFIG_KM_PIGGY4_88E6352
+
+#else
+#error ("Board unsupported")
 #endif
 
+/* include common defines/options for all arm based Keymile boards */
+#include "km/km_arm.h"
+
 #define CONFIG_HOSTNAME                      km_kirkwood
 
-#define KM_IVM_BUS   "pca9544a:70:9" /* I2C2 (Mux-Port 1)*/
+#ifndef CONFIG_KM_ENV_IS_IN_SPI_NOR
 #define KM_ENV_BUS   "pca9544a:70:d" /* I2C2 (Mux-Port 5)*/
+#endif
+
+#if defined(CONFIG_KM_PIGGY4_88E6352)
+/*
+ * Some keymile boards like mgcoge5un & nusa1 have their PIGGY4

connected via
+ * an Marvell 88E6352 simple switch.
+ * In this case we have to change the default settings for the etherent mac.
+ * There is NO ethernet phy. The ARM and Switch are conencted directly over
+ * RGMII in MAC-MAC mode
+ * In this case 1GBit full duplex and autoneg off
+ */

include/configs/km_kirkwood.h +21 -0

+#define PORT_SERIAL_CONTROL_VALUE            ( \
+     MVGBE_FORCE_LINK_PASS                       | \
+     MVGBE_DIS_AUTO_NEG_FOR_DUPLX            | \
+     MVGBE_DIS_AUTO_NEG_FOR_FLOW_CTRL        | \
+     MVGBE_ADV_NO_FLOW_CTRL                      | \
+     MVGBE_FORCE_FC_MODE_NO_PAUSE_DIS_TX     | \
+     MVGBE_FORCE_BP_MODE_NO_JAM                  | \
+     (1 << 9) /* Reserved bit has to be 1 */ | \
+     MVGBE_DO_NOT_FORCE_LINK_FAIL            | \
+     MVGBE_DIS_AUTO_NEG_SPEED_GMII           | \
+     MVGBE_DTE_ADV_0                                 | \
+     MVGBE_MIIPHY_MAC_MODE                       | \
+     MVGBE_AUTO_NEG_NO_CHANGE                    | \
+     MVGBE_MAX_RX_PACKET_1552BYTE            | \
+     MVGBE_CLR_EXT_LOOPBACK                      | \
+     MVGBE_SET_FULL_DUPLEX_MODE                  | \
+     MVGBE_EN_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX |\
+     MVGBE_SET_GMII_SPEED_TO_1000        |\
+     MVGBE_SET_MII_SPEED_TO_100)
+
+#endif
 
 /* GPIO Pin from kirkwood connected to PROGRAM_B pin of the xilinx

FPGA */
#define KM_XLX_PROGRAM_B_PIN 39
--
1.7.1

Quoted 21 lines

-----Original Message-----
From: Valentin Longchamp [mailto:valentin.longchamp at keymile.com]
Sent: 07 June 2012 15:37
To: prafulla at mavell.com
Cc: Holger Brunck; u-boot at lists.denx.de; Valentin Longchamp; Gerlando Falauto; Prafulla Wadaskar
Subject: [PATCH 04/20] arm/km: add kmnusa board support

From: Holger Brunck <[email protected]>

This board is similar to portl2, but it has the u-boot environment in a SPI NOR flash and not in an i2c eeprom like portl2 have.

Some other details:
- IVM EEPROM is at adress: pca9547:70:9
- PCI is enabled
- PIGGY4 is connected via MV88E6352 simple switch. There is no phy between the simple switch and the kirkwood.

Quoted 8 lines

Signed-off-by Holger Brunck <[email protected]>

Signed-off-by Valentin Longchamp <[email protected]>

cc Gerlando Falauto <[email protected]>

cc Prafulla Wadaskar <[email protected]>

---
 MAINTAINERS                       |    1 +
 board/keymile/km_arm/128M16-1.cfg |  294

+++++++++++++++++++++++++++++++++++++

Please avoid file names starting with numbers.

Quoted 14 lines

 board/keymile/km_arm/km_arm.c     |    9 +-
 boards.cfg                        |    1 +
 include/configs/km/km_arm.h       |   44 +++++-
 include/configs/km_kirkwood.h     |   67 +++++++--
 6 files changed, 392 insertions(+), 24 deletions(-)
 create mode 100644 board/keymile/km_arm/128M16-1.cfg

MAINTAINERS +0 -0

index 0445539..aa11268 100644
@@ -738,6 +738,7 @@ Sergey Lapin <[email protected]>
 Valentin Longchamp <[email protected]>
 

MAINTAINERS Sergey Lapin <[email protected]> · line 741

Quoted 2 lines

MAINTAINERS +1 -0

      km_kirkwood     ARM926EJS (Kirkwood SoC)
+     kmnusa          ARM926EJS (Kirkwood SoC)

Again.... I would like to suggest to separate out new boards addition, bugfixes/updates specific to km_*boards and generic kirkwood specific patches.

It's always faster to merger small patch series that big one.

Quoted 302 lines

MAINTAINERS +0 -0

      mgcoge3un       ARM926EJS (Kirkwood SoC)
      portl2          ARM926EJS (Kirkwood SoC)
 

board/keymile/km_arm/128M16-1.cfg new file +142 -0

new file mode 100644
index 0000000..bcce907
@@ -0,0 +1,294 @@
+#
+# (C) Copyright 2010
+# Heiko Schocher, DENX Software Engineering, hs at denx.de.
+#
+# (C) Copyright 2012
+# Valentin Longchamp, Keymile AG, valentin.longchamp at keymile.com
+# Stefan Bigler, Keymile AG, stefan.bigler at keymile.com
+#
+# (C) Copyright 2012
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+# Refer docs/README.kwimage for more details about how-to configure
+# and create kirkwood boot image
+#
+
+# Boot Media configurations
+BOOT_FROM    spi     # Boot from SPI flash
+
+DATA 0xFFD10000 0x01112222   # MPP Control 0 Register
+# bit 3-0:   2, MPPSel0  SPI_CSn  (1=NF_IO[2])
+# bit 7-4:   2, MPPSel1  SPI_SI   (1=NF_IO[3])
+# bit 12-8:  2, MPPSel2  SPI_SCK  (1=NF_IO[4])
+# bit 15-12: 2, MPPSel3  SPI_SO   (1=NF_IO[5])
+# bit 19-16: 1, MPPSel4  NF_IO[6]
+# bit 23-20: 1, MPPSel5  NF_IO[7]
+# bit 27-24: 1, MPPSel6  SYSRST_O
+# bit 31-28: 0, MPPSel7  GPO[7]
+
+DATA 0xFFD10004 0x03303300   # MPP Control 1 Register
+# bit 3-0:   0, MPPSel8       GPIO[8]
+# bit 7-4:   0, MPPSel9  GPIO[9]
+# bit 12-8:  3, MPPSel10 UA0_TXD
+# bit 15-12: 3, MPPSel11 UA0_RXD
+# bit 19-16: 0, MPPSel12 not connected
+# bit 23-20: 3, MPPSel13 UA1_TXD
+# bit 27-24: 3, MPPSel14 UA1_RXD
+# bit 31-28: 0, MPPSel15 GPIO[15]
+
+DATA 0xFFD10008 0x00001100   # MPP Control 2 Register
+# bit 3-0:   0, MPPSel16 GPIO[16]
+# bit 7-4:   0, MPPSel17 not connected
+# bit 12-8:  1, MPPSel18 NF_IO[0]
+# bit 15-12: 1, MPPSel19 NF_IO[1]
+# bit 19-16: 0, MPPSel20 GPIO[20]
+# bit 23-20: 0, MPPSel21 GPIO[21]
+# bit 27-24: 0, MPPSel22 GPIO[22]
+# bit 31-28: 0, MPPSel23 GPIO[23]
+
+# MPP Control 3-6 Register untouched (MPP24-49)
+
+DATA 0xFFD100E0 0x1B1B1B1B   # IO Configuration 0 Register
+# bit 2-0:   3, Reserved
+# bit 5-3:   3, Reserved
+# bit 6:     0, Reserved
+# bit 7:     0, RGMII-pads voltage = 3.3V
+# bit 10-8:  3, Reserved
+# bit 13-11: 3, Reserved
+# bit 14:    0, Reserved
+# bit 15:    0, MPP RGMII-pads voltage = 3.3V
+# bit 31-16  0x1B1B, Reserved
+
+DATA 0xFFD20134 0x66666666   # L2 RAM Timing 0 Register
+# bit 0-1:   2, Tag RAM RTC RAM0
+# bit 3-2:   1, Tag RAM WTC RAM0
+# bit 7-4:   6, Reserve
+# bit 9-8:   2, Valid RAM RTC RAM
+# bit 11-10: 1, Valid RAM WTC RAM
+# bit 13-12: 2, Dirty RAM RTC RAM
+# bit 15-14: 1, Dirty RAM WTC RAM
+# bit 17-16: 2, Data RAM RTC RAM0
+# bit 19-18: 1, Data RAM WTC RAM0
+# bit 21-20: 2, Data RAM RTC RAM1
+# bit 23-22: 1, Data RAM WTC RAM1
+# bit 25-24: 2, Data RAM RTC RAM2
+# bit 27-26: 1, Data RAM WTC RAM2
+# bit 29-28: 2, Data RAM RTC RAM3
+# bit 31-30: 1, Data RAM WTC RAM4
+
+DATA 0xFFD20138 0x66666666   # L2 RAM Timing 1 Register
+# bit 15-0:  ???, Reserve
+# bit 17-16: 2, ECC RAM RTC RAM0
+# bit 19-18: 1, ECC RAM WTC RAM0
+# bit 31-20: ???,Reserve
+
+DATA 0xFFD20154 0x00000200   # CPU RAM Management Control3 Register
+# bit 23-0:  0x000200, Addr Config tuning
+# bit 31-24: 0,        Reserved
+
+# ??? Missing register # CPU RAM Management Control2 Register
+
+DATA 0xFFD2014C 0x00001C00   # CPU RAM Management Control1 Register
+# bit 15-0:  0x1C00, Opmux Tuning
+# bit 31-16: 0,      Pc Dp Tuning
+
+DATA 0xFFD20148 0x00000001   # CPU RAM Management Control0 Register
+# bit 1-0:   1, addr clk tune
+# bit 3-2:   0, reserved
+# bit 5-4:   0, dtcmp clk tune
+# bit 7-6:   0, reserved
+# bit 9-8:   0, macdrv clk tune
+# bit 11-10: 0, opmuxgm2 clk tune
+# bit 15-14: 0, rf clk tune
+# bit 17-16: 0, rfbypass clk tune
+# bit 19-18: 0, pc dp clk tune
+# bit 23-20: 0, icache clk tune
+# bit 27:24: 0, dcache clk tune
+# bit 31:28: 0, regfile tunin
+
+# SDRAM initalization
+DATA 0xFFD01400 0x430004E0   # SDRAM Configuration Register
+# bit 13-0:  0x4E0, DDR2 clks refresh rate
+# bit 14:    0, reserved
+# bit 15:    0, reserved
+# bit 16:    0, CPU to Dram Write buffer policy
+# bit 17:    0, Enable Registered DIMM or Equivalent Sampling Logic
+# bit 19-18: 0, reserved
+# bit 23-20: 0, reserved
+# bit 24:    1, enable exit self refresh mode on DDR access
+# bit 25:    1, required
+# bit 29-26: 0, reserved
+# bit 31-30: 1, reserved
+
+DATA 0xFFD01404 0x36543000   # DDR Controller Control Low
+# bit 3-0:   0, reserved
+# bit 4:     0, 2T mode =addr/cmd in same cycle
+# bit 5:     0, clk is driven during self refresh, we don't care for

APX

board/keymile/km_arm/128M16-1.cfg new file +8 -0

+# bit 6:     0, use recommended falling edge of clk for addr/cmd
+# bit 7-11:  0, reserved
+# bit 12-13: 1, reserved, required 1
+# bit 14:    0, input buffer always powered up
+# bit 17-15: 0, reserved
+# bit 18:    1, cpu lock transaction enabled
+# bit 19:    0, reserved
+# bit 23-20: 5, recommended value for CL=4 and STARTBURST_DEL

disabled bit31=0
+# bit 27-24: 6, CL+1, STARTBURST sample stages, for freqs 200-399MHz, unbuffered DIMM

board/keymile/km_arm/128M16-1.cfg new file +95 -0

+# bit 30-28: 3, required
+# bit 31:    0,no additional STARTBURST delay
+
+DATA 0xFFD01408 0x2302444e   # DDR Timing (Low) (active cycles value
+1)
+# bit 3-0:   0xE, TRAS, 15 clk (45 ns)
+# bit 7-4:   0x4, TRCD, 5 clk (15 ns)
+# bit 11-8:  0x4, TRP, 5 clk (15 ns)
+# bit 15-12: 0x4, TWR, 5 clk (15 ns)
+# bit 19-16: 0x2, TWTR, 3 clk (7.5 ns)
+# bit 20:      0, extended TRAS msb
+# bit 23-21:   0, reserved
+# bit 27-24: 0x3, TRRD, 4 clk (10 ns)
+# bit 31-28: 0x2, TRTP, 3 clk (7.5 ns)
+
+DATA 0xFFD0140C 0x0000003e   #  DDR Timing (High)
+# bit 6-0:   0x3E, TRFC, 63 clk (195 ns)
+# bit 8-7:      0, TR2R
+# bit 10-9:     0, TR2W
+# bit 12-11:    0, TW2W
+# bit 31-13:    0, reserved
+
+DATA 0xFFD01410 0x00000001   #  DDR Address Control
+# bit 1-0:    1, Cs0width=x16
+# bit 3-2:    0, Cs0size=2Gb
+# bit 5-4:    0, Cs1width=nonexistent
+# bit 7-6:    0, Cs1size =nonexistent
+# bit 9-8:    0, Cs2width=nonexistent
+# bit 11-10:  0, Cs2size =nonexistent
+# bit 13-12:  0, Cs3width=nonexistent
+# bit 15-14:  0, Cs3size =nonexistent
+# bit 16:     0, Cs0AddrSel
+# bit 17:     0, Cs1AddrSel
+# bit 18:     0, Cs2AddrSel
+# bit 19:     0, Cs3AddrSel
+# bit 31-20:  0, required
+
+DATA 0xFFD01414 0x00000000   #  DDR Open Pages Control
+# bit 0:      0,  OpenPage enabled
+# bit 31-1:   0, required
+
+DATA 0xFFD01418 0x00000000   #  DDR Operation
+# bit 3-0:    0, DDR cmd
+# bit 31-4:   0, required
+
+DATA 0xFFD0141C 0x00000652   #  DDR Mode
+# bit 2-0:    2, Burst Length = 4
+# bit 3:      0, Burst Type
+# bit 6-4:    5, CAS Latency = 5
+# bit 7:      0, Test mode
+# bit 8:      0, DLL Reset
+# bit 11-9:   3, Write recovery for auto-precharge must be 3
+# bit 12:     0, Active power down exit time, fast exit
+# bit 14-13:  0, reserved
+# bit 31-15:  0, reserved
+
+DATA 0xFFD01420 0x00000006   #  DDR Extended Mode
+# bit 0:      0, DDR DLL enabled
+# bit 1:      1,  DDR drive strength reduced
+# bit 2:      1,  DDR ODT control lsb, 75 ohm termination [RTT0]
+# bit 5-3:    0, required
+# bit 6:      0, DDR ODT control msb, 75 ohm termination [RTT1]
+# bit 9-7:    0, required
+# bit 10:     0, differential DQS enabled
+# bit 11:     0, required
+# bit 12:     0, DDR output buffer enabled
+# bit 31-13:  0 required
+
+DATA 0xFFD01424 0x0000F17F   #  DDR Controller Control High
+# bit 2-0:    7, required
+# bit 3:      1, MBUS Burst Chop disabled
+# bit 6-4:    7, required
+# bit 7:      0, reserved
+# bit 8:      1, add sample stage required for f > 266 MHz
+# bit 9:      0, no half clock cycle addition to dataout
+# bit 10:     0, 1/4 clock cycle skew enabled for addr/ctl signals
+# bit 11:     0, 1/4 clock cycle skew disabled for write mesh
+# bit 15-12:0xf, required
+# bit 31-16:  0, required
+
+DATA 0xFFD01428 0x00084520   # DDR2 SDRAM Timing Low
+# bit 3-0:    0, required
+# bit 7-4:    2, M_ODT assertion 2 cycles after read start command
+# bit 11-8:   5, M_ODT de-assertion 5 cycles after read start command
+#                (ODT turn off delay 2,5 clk cycles)
+# bit 15-12:  4, internal ODT time based on bit 7-4
+#                with the considered SDRAM internal delay
+# bit 19-16:  8, internal ODT de-assertion based on bit 11-8
+#                with the considered SDRAM internal delay
+# bit 31-20:  0, required
+
+DATA 0xFFD0147c 0x00008452   # DDR2 SDRAM Timing High
+# bit 3-0:    2, M_ODT assertion same as bit 11-8
+# bit 7-4:    5, M_ODT de-assertion same as bit 15-12
+# bit 11-8:   4, internal ODT assertion 2 cycles after write start

command

board/keymile/km_arm/128M16-1.cfg new file +2 -0

+#                with the considered SDRAM internal delay
+# bit 15-12:  8, internal ODT de-assertion 5 cycles after write start

command

board/keymile/km_arm/128M16-1.cfg new file +19 -0

+#                with the considered SDRAM internal delay
+
+DATA 0xFFD01500 0x00000000   # CS[0]n Base address to 0x0
+# bit 23-0:   0, reserved
+# bit 31-24:  0, CPU CS Window0 Base Address, addr bits [31:24]
+
+DATA 0xFFD01504 0x0FFFFFF1   # CS[0]n Size
+# bit 0:      1, Window enabled
+# bit 1:      0, Write Protect disabled
+# bit 3-2:    0, CS0 hit selected
+# bit 23-4:ones, required
+# bit 31-24: 0x0F, Size (i.e. 256MB)
+
+DATA 0xFFD0150C 0x00000000   # CS[1]n Size, window disabled
+DATA 0xFFD01514 0x00000000   # CS[2]n Size, window disabled
+DATA 0xFFD0151C 0x00000000   # CS[3]n Size, window disabled
+
+DATA 0xFFD01494 0x00010000   #  DDR ODT Control (Low)
+# bit 3-0:     0, ODT0Rd, MODT[0] not asserted during read from DRAM

CS0

board/keymile/km_arm/128M16-1.cfg new file +15 -0

+# bit 7-4:     0, ODT0Rd, MODT[1] not asserted
+# bit 11-8:    0, required
+# big 15-11:   0, required
+# bit 19-16:   1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
+# bit 23-20:   0, ODT0Wr, MODT[1] not asserted
+# bit 27-24:   0, required
+# bit 31-28:   0, required
+
+DATA 0xFFD01498 0x00000000   #  DDR ODT Control (High)
+# bit 1-0:     0, ODT0 controlled by ODT Control (low) register above
+# bit 3-2:     0, ODT1 controlled by register
+# bit 31-4:    0, required
+
+DATA 0xFFD0149C 0x0000E801   # CPU ODT Control
+# bit 3-0:     1, ODTRd, Internal ODT asserted during read from DRAM

bank0
+# bit 7-4: 0, ODTWr, Internal ODT not asserted during write to
DRAM

board/keymile/km_arm/128M16-1.cfg new file +1 -0

+# bit 9-8:     0, ODTEn, controlled by ODTRd and ODTWr

board/keymile/km_arm/128M16-1.cfg line 293

Quoted 10 lines

board/keymile/km_arm/128M16-1.cfg new file +10 -0

+# bit 11-10:   2, DQ_ODTSel. ODT select turned on, 75 ohm
+# bit 13-12:   2, STARTBURST ODT buffer selected, 75 ohm
+# bit 14:      1, STARTBURST ODT enabled
+# bit 15:      1, Use ODT Block
+
+DATA 0xFFD01480 0x00000001   # DDR Initialization Control
+# bit 0:       1, enable DDR init upon this register write
+# bit 31-1:    0, reserved
+
+# End of Header extension

Is this configuration similar to any other board already mainlined? if there is small delta like RAM/flash sizes then you can manage it through board_init()

Just think of it.

Quoted 39 lines

board/keymile/km_arm/128M16-1.cfg new file +1 -0

+DATA 0x0 0x0

board/keymile/km_arm/km_arm.c +2 -2

index e4ae1fb..ffe13cd 100644
@@ -133,10 +133,11 @@ int startup_allowed(void)
 }
 #endif
 
-#if (defined(CONFIG_MGCOGE3UN)|defined(CONFIG_PORTL2))
+#if (defined(CONFIG_MGCOGE3UN)|defined(CONFIG_PORTL2)| \
+     defined(CONFIG_KM_PIGGY4_88E6352))
 /*
- * These two boards have always ethernet present. Its connected to

the mv
- * switch.
+ * All boards with PIGGY4 connected via a simple switch have ethernet always
+ * present.
*/
int ethernet_present(void)
{

board/keymile/km_arm/km_arm.c +1 -1

@@ -384,7 +385,7 @@ void reset_phy(void)
      /* reset the phy */
      miiphy_reset(name, CONFIG_PHY_BASE_ADR);
 }
-#else
+#elif !defined(CONFIG_KM_PIGGY4_88E6352)
 /* Configure and enable MV88E1118 PHY on the piggy*/
 void reset_phy(void)
 {

boards.cfg +0 -1

index b711e0d..1a4c2ad 100644
@@ -140,6 +140,7 @@ pogo_e02                     arm         arm926ejs
-                   clouden
 dns325                       arm         arm926ejs   -

Quoted 6 lines

d-link kirkwood
km_kirkwood arm arm926ejs km_arm
keymile kirkwood km_kirkwood:KM_KIRKWOOD,KM_DISABLE_PCI
km_kirkwood_pci arm arm926ejs km_arm
keymile kirkwood km_kirkwood:KM_KIRKWOOD_PCI,KM_RECONFIG_XLX
+kmnusa arm arm926ejs km_arm

Why name is not km_nusa?

Quoted 15 lines

keymile kirkwood km_kirkwood:KM_NUSA
mgcoge3un arm arm926ejs km_arm
keymile kirkwood
portl2 arm arm926ejs km_arm
keymile kirkwood
inetspace_v2 arm arm926ejs netspace_v2
LaCie kirkwood lacie_kw:INETSPACE_V2

include/configs/km/km_arm.h +0 -0

index 28b5021..a35ef61 100644
@@ -57,6 +57,13 @@
 #define CONFIG_CMD_SF
 #define CONFIG_SOFT_I2C              /* I2C bit-banged       */
 

include/configs/km/km_arm.h line 66

Quoted 7 lines

include/configs/km/km_arm.h +7 -0

+#if defined CONFIG_KM_ENV_IS_IN_SPI_NOR
+#define CONFIG_ENV_SPI_BUS           0
+#define CONFIG_ENV_SPI_CS            0
+#define CONFIG_ENV_SPI_MAX_HZ                5000000
+#define CONFIG_ENV_SPI_MODE          SPI_MODE_3
+#endif
+

Do you still need this? Your patch 03/20 takes care of this.

-----Original Message-----
From: Holger Brunck [mailto:holger.brunck at keymile.com]
Sent: 12 June 2012 14:04
To: Prafulla Wadaskar
Cc: Valentin Longchamp; prafulla at mavell.com; u-boot at lists.denx.de; Gerlando Falauto
Subject: Re: [PATCH 04/20] arm/km: add kmnusa board support

Quoted 7 lines · Prafulla Wadaskar

Quoted 7 lines

-----Original Message-----
From: Valentin Longchamp [mailto:valentin.longchamp at keymile.com]
Sent: 07 June 2012 15:37
To: prafulla at mavell.com
Cc: Holger Brunck; u-boot at lists.denx.de; Valentin Longchamp;

Gerlando

Quoted 23 lines

Quoted 22 lines

Falauto; Prafulla Wadaskar
Subject: [PATCH 04/20] arm/km: add kmnusa board support

From: Holger Brunck <[email protected]>

This board is similar to portl2, but it has the u-boot environment in a SPI NOR flash and not in an i2c eeprom like portl2 have.

Some other details:
- IVM EEPROM is at adress: pca9547:70:9
- PCI is enabled
- PIGGY4 is connected via MV88E6352 simple switch. There is no phy between the simple switch and the kirkwood.

Signed-off-by Holger Brunck <[email protected]>

Signed-off-by Valentin Longchamp <[email protected]>

cc Gerlando Falauto <[email protected]>

cc Prafulla Wadaskar <[email protected]>

---
 MAINTAINERS                       |    1 +
 board/keymile/km_arm/128M16-1.cfg |  294

+++++++++++++++++++++++++++++++++++++

Quoted 2 lines

Please avoid file names starting with numbers.

would sdram128M16-1.cfg be ok? The reason for this numbering is to have a chance
to know which organisation this RAM has.

Quoted 15 lines

Quoted 15 lines

 board/keymile/km_arm/km_arm.c     |    9 +-
 boards.cfg                        |    1 +
 include/configs/km/km_arm.h       |   44 +++++-
 include/configs/km_kirkwood.h     |   67 +++++++--
 6 files changed, 392 insertions(+), 24 deletions(-)
 create mode 100644 board/keymile/km_arm/128M16-1.cfg

MAINTAINERS +0 -0

index 0445539..aa11268 100644
@@ -738,6 +738,7 @@ Sergey Lapin <[email protected]>
 Valentin Longchamp <[email protected]>
 

Quoted 4 lines

MAINTAINERS Sergey Lapin <[email protected]> · line 741

Quoted 2 lines

MAINTAINERS +1 -0

      km_kirkwood     ARM926EJS (Kirkwood SoC)
+     kmnusa          ARM926EJS (Kirkwood SoC)

Again.... I would like to suggest to separate out new boards

addition, bugfixes/updates specific to km_*boards and generic kirkwood specific patches.

Quoted 3 lines

It's always faster to merger small patch series that big one.

Yes ok, but was has this to do with this patch? What is meant to be kirkwood
specific? This is all board related code.

Quoted 25 lines

Quoted 25 lines

MAINTAINERS +0 -0

      mgcoge3un       ARM926EJS (Kirkwood SoC)
      portl2          ARM926EJS (Kirkwood SoC)
 

board/keymile/km_arm/128M16-1.cfg new file +15 -0

new file mode 100644
index 0000000..bcce907
@@ -0,0 +1,294 @@
+#
+# (C) Copyright 2010
+# Heiko Schocher, DENX Software Engineering, hs at denx.de.
+#
+# (C) Copyright 2012
+# Valentin Longchamp, Keymile AG, valentin.longchamp at keymile.com
+# Stefan Bigler, Keymile AG, stefan.bigler at keymile.com
+#
+# (C) Copyright 2012
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of

Quoted 8 lines

board/keymile/km_arm/128M16-1.cfg

Quoted 8 lines

board/keymile/km_arm/128M16-1.cfg new file +8 -0

+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public

License

Quoted 5 lines

board/keymile/km_arm/128M16-1.cfg

Quoted 5 lines

board/keymile/km_arm/128M16-1.cfg new file +5 -0

+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+# Refer docs/README.kwimage for more details about how-to

configure

Quoted 65 lines

Quoted 65 lines

board/keymile/km_arm/128M16-1.cfg new file +65 -0

+# and create kirkwood boot image
+#
+
+# Boot Media configurations
+BOOT_FROM    spi     # Boot from SPI flash
+
+DATA 0xFFD10000 0x01112222   # MPP Control 0 Register
+# bit 3-0:   2, MPPSel0  SPI_CSn  (1=NF_IO[2])
+# bit 7-4:   2, MPPSel1  SPI_SI   (1=NF_IO[3])
+# bit 12-8:  2, MPPSel2  SPI_SCK  (1=NF_IO[4])
+# bit 15-12: 2, MPPSel3  SPI_SO   (1=NF_IO[5])
+# bit 19-16: 1, MPPSel4  NF_IO[6]
+# bit 23-20: 1, MPPSel5  NF_IO[7]
+# bit 27-24: 1, MPPSel6  SYSRST_O
+# bit 31-28: 0, MPPSel7  GPO[7]
+
+DATA 0xFFD10004 0x03303300   # MPP Control 1 Register
+# bit 3-0:   0, MPPSel8       GPIO[8]
+# bit 7-4:   0, MPPSel9  GPIO[9]
+# bit 12-8:  3, MPPSel10 UA0_TXD
+# bit 15-12: 3, MPPSel11 UA0_RXD
+# bit 19-16: 0, MPPSel12 not connected
+# bit 23-20: 3, MPPSel13 UA1_TXD
+# bit 27-24: 3, MPPSel14 UA1_RXD
+# bit 31-28: 0, MPPSel15 GPIO[15]
+
+DATA 0xFFD10008 0x00001100   # MPP Control 2 Register
+# bit 3-0:   0, MPPSel16 GPIO[16]
+# bit 7-4:   0, MPPSel17 not connected
+# bit 12-8:  1, MPPSel18 NF_IO[0]
+# bit 15-12: 1, MPPSel19 NF_IO[1]
+# bit 19-16: 0, MPPSel20 GPIO[20]
+# bit 23-20: 0, MPPSel21 GPIO[21]
+# bit 27-24: 0, MPPSel22 GPIO[22]
+# bit 31-28: 0, MPPSel23 GPIO[23]
+
+# MPP Control 3-6 Register untouched (MPP24-49)
+
+DATA 0xFFD100E0 0x1B1B1B1B   # IO Configuration 0 Register
+# bit 2-0:   3, Reserved
+# bit 5-3:   3, Reserved
+# bit 6:     0, Reserved
+# bit 7:     0, RGMII-pads voltage = 3.3V
+# bit 10-8:  3, Reserved
+# bit 13-11: 3, Reserved
+# bit 14:    0, Reserved
+# bit 15:    0, MPP RGMII-pads voltage = 3.3V
+# bit 31-16  0x1B1B, Reserved
+
+DATA 0xFFD20134 0x66666666   # L2 RAM Timing 0 Register
+# bit 0-1:   2, Tag RAM RTC RAM0
+# bit 3-2:   1, Tag RAM WTC RAM0
+# bit 7-4:   6, Reserve
+# bit 9-8:   2, Valid RAM RTC RAM
+# bit 11-10: 1, Valid RAM WTC RAM
+# bit 13-12: 2, Dirty RAM RTC RAM
+# bit 15-14: 1, Dirty RAM WTC RAM
+# bit 17-16: 2, Data RAM RTC RAM0
+# bit 19-18: 1, Data RAM WTC RAM0
+# bit 21-20: 2, Data RAM RTC RAM1
+# bit 23-22: 1, Data RAM WTC RAM1
+# bit 25-24: 2, Data RAM RTC RAM2
+# bit 27-26: 1, Data RAM WTC RAM2
+# bit 29-28: 2, Data RAM RTC RAM3
+# bit 31-30: 1, Data RAM WTC RAM4

Quoted 8 lines

board/keymile/km_arm/128M16-1.cfg

Quoted 8 lines

board/keymile/km_arm/128M16-1.cfg new file +8 -0

+
+DATA 0xFFD20138 0x66666666   # L2 RAM Timing 1 Register
+# bit 15-0:  ???, Reserve
+# bit 17-16: 2, ECC RAM RTC RAM0
+# bit 19-18: 1, ECC RAM WTC RAM0
+# bit 31-20: ???,Reserve
+
+DATA 0xFFD20154 0x00000200   # CPU RAM Management Control3

Register

Quoted 6 lines

board/keymile/km_arm/128M16-1.cfg

Quoted 6 lines

board/keymile/km_arm/128M16-1.cfg new file +6 -0

+# bit 23-0:  0x000200, Addr Config tuning
+# bit 31-24: 0,        Reserved
+
+# ??? Missing register # CPU RAM Management Control2 Register
+
+DATA 0xFFD2014C 0x00001C00   # CPU RAM Management Control1

Register

Quoted 4 lines

board/keymile/km_arm/128M16-1.cfg

Quoted 4 lines

board/keymile/km_arm/128M16-1.cfg new file +4 -0

+# bit 15-0:  0x1C00, Opmux Tuning
+# bit 31-16: 0,      Pc Dp Tuning
+
+DATA 0xFFD20148 0x00000001   # CPU RAM Management Control0

Register

Quoted 12 lines

Quoted 12 lines

board/keymile/km_arm/128M16-1.cfg new file +12 -0

+# bit 1-0:   1, addr clk tune
+# bit 3-2:   0, reserved
+# bit 5-4:   0, dtcmp clk tune
+# bit 7-6:   0, reserved
+# bit 9-8:   0, macdrv clk tune
+# bit 11-10: 0, opmuxgm2 clk tune
+# bit 15-14: 0, rf clk tune
+# bit 17-16: 0, rfbypass clk tune
+# bit 19-18: 0, pc dp clk tune
+# bit 23-20: 0, icache clk tune
+# bit 27:24: 0, dcache clk tune
+# bit 31:28: 0, regfile tunin

Quoted 8 lines

board/keymile/km_arm/128M16-1.cfg

Quoted 8 lines

board/keymile/km_arm/128M16-1.cfg new file +8 -0

+
+# SDRAM initalization
+DATA 0xFFD01400 0x430004E0   # SDRAM Configuration Register
+# bit 13-0:  0x4E0, DDR2 clks refresh rate
+# bit 14:    0, reserved
+# bit 15:    0, reserved
+# bit 16:    0, CPU to Dram Write buffer policy
+# bit 17:    0, Enable Registered DIMM or Equivalent Sampling

Logic

Quoted 11 lines

board/keymile/km_arm/128M16-1.cfg

Quoted 11 lines

board/keymile/km_arm/128M16-1.cfg new file +11 -0

+# bit 19-18: 0, reserved
+# bit 23-20: 0, reserved
+# bit 24:    1, enable exit self refresh mode on DDR access
+# bit 25:    1, required
+# bit 29-26: 0, reserved
+# bit 31-30: 1, reserved
+
+DATA 0xFFD01404 0x36543000   # DDR Controller Control Low
+# bit 3-0:   0, reserved
+# bit 4:     0, 2T mode =addr/cmd in same cycle
+# bit 5:     0, clk is driven during self refresh, we don't care

for

Quoted 11 lines

Quoted 11 lines

APX

board/keymile/km_arm/128M16-1.cfg new file +8 -0

+# bit 6:     0, use recommended falling edge of clk for addr/cmd
+# bit 7-11:  0, reserved
+# bit 12-13: 1, reserved, required 1
+# bit 14:    0, input buffer always powered up
+# bit 17-15: 0, reserved
+# bit 18:    1, cpu lock transaction enabled
+# bit 19:    0, reserved
+# bit 23-20: 5, recommended value for CL=4 and STARTBURST_DEL

disabled bit31=0
+# bit 27-24: 6, CL+1, STARTBURST sample stages, for freqs 200-

399MHz,

Quoted 5 lines

board/keymile/km_arm/128M16-1.cfg

Quoted 5 lines

unbuffered DIMM

board/keymile/km_arm/128M16-1.cfg new file +4 -0

+# bit 30-28: 3, required
+# bit 31:    0,no additional STARTBURST delay
+
+DATA 0xFFD01408 0x2302444e   # DDR Timing (Low) (active cycles

value

Quoted 72 lines

Quoted 72 lines

+1)

board/keymile/km_arm/128M16-1.cfg new file +71 -0

+# bit 3-0:   0xE, TRAS, 15 clk (45 ns)
+# bit 7-4:   0x4, TRCD, 5 clk (15 ns)
+# bit 11-8:  0x4, TRP, 5 clk (15 ns)
+# bit 15-12: 0x4, TWR, 5 clk (15 ns)
+# bit 19-16: 0x2, TWTR, 3 clk (7.5 ns)
+# bit 20:      0, extended TRAS msb
+# bit 23-21:   0, reserved
+# bit 27-24: 0x3, TRRD, 4 clk (10 ns)
+# bit 31-28: 0x2, TRTP, 3 clk (7.5 ns)
+
+DATA 0xFFD0140C 0x0000003e   #  DDR Timing (High)
+# bit 6-0:   0x3E, TRFC, 63 clk (195 ns)
+# bit 8-7:      0, TR2R
+# bit 10-9:     0, TR2W
+# bit 12-11:    0, TW2W
+# bit 31-13:    0, reserved
+
+DATA 0xFFD01410 0x00000001   #  DDR Address Control
+# bit 1-0:    1, Cs0width=x16
+# bit 3-2:    0, Cs0size=2Gb
+# bit 5-4:    0, Cs1width=nonexistent
+# bit 7-6:    0, Cs1size =nonexistent
+# bit 9-8:    0, Cs2width=nonexistent
+# bit 11-10:  0, Cs2size =nonexistent
+# bit 13-12:  0, Cs3width=nonexistent
+# bit 15-14:  0, Cs3size =nonexistent
+# bit 16:     0, Cs0AddrSel
+# bit 17:     0, Cs1AddrSel
+# bit 18:     0, Cs2AddrSel
+# bit 19:     0, Cs3AddrSel
+# bit 31-20:  0, required
+
+DATA 0xFFD01414 0x00000000   #  DDR Open Pages Control
+# bit 0:      0,  OpenPage enabled
+# bit 31-1:   0, required
+
+DATA 0xFFD01418 0x00000000   #  DDR Operation
+# bit 3-0:    0, DDR cmd
+# bit 31-4:   0, required
+
+DATA 0xFFD0141C 0x00000652   #  DDR Mode
+# bit 2-0:    2, Burst Length = 4
+# bit 3:      0, Burst Type
+# bit 6-4:    5, CAS Latency = 5
+# bit 7:      0, Test mode
+# bit 8:      0, DLL Reset
+# bit 11-9:   3, Write recovery for auto-precharge must be 3
+# bit 12:     0, Active power down exit time, fast exit
+# bit 14-13:  0, reserved
+# bit 31-15:  0, reserved
+
+DATA 0xFFD01420 0x00000006   #  DDR Extended Mode
+# bit 0:      0, DDR DLL enabled
+# bit 1:      1,  DDR drive strength reduced
+# bit 2:      1,  DDR ODT control lsb, 75 ohm termination [RTT0]
+# bit 5-3:    0, required
+# bit 6:      0, DDR ODT control msb, 75 ohm termination [RTT1]
+# bit 9-7:    0, required
+# bit 10:     0, differential DQS enabled
+# bit 11:     0, required
+# bit 12:     0, DDR output buffer enabled
+# bit 31-13:  0 required
+
+DATA 0xFFD01424 0x0000F17F   #  DDR Controller Control High
+# bit 2-0:    7, required
+# bit 3:      1, MBUS Burst Chop disabled
+# bit 6-4:    7, required
+# bit 7:      0, reserved
+# bit 8:      1, add sample stage required for f > 266 MHz
+# bit 9:      0, no half clock cycle addition to dataout
+# bit 10:     0, 1/4 clock cycle skew enabled for addr/ctl signals

Quoted 8 lines

board/keymile/km_arm/128M16-1.cfg

Quoted 8 lines

board/keymile/km_arm/128M16-1.cfg new file +8 -0

+# bit 11:     0, 1/4 clock cycle skew disabled for write mesh
+# bit 15-12:0xf, required
+# bit 31-16:  0, required
+
+DATA 0xFFD01428 0x00084520   # DDR2 SDRAM Timing Low
+# bit 3-0:    0, required
+# bit 7-4:    2, M_ODT assertion 2 cycles after read start command
+# bit 11-8:   5, M_ODT de-assertion 5 cycles after read start

command

Quoted 6 lines

Quoted 6 lines

board/keymile/km_arm/128M16-1.cfg new file +6 -0

+#                (ODT turn off delay 2,5 clk cycles)
+# bit 15-12:  4, internal ODT time based on bit 7-4
+#                with the considered SDRAM internal delay
+# bit 19-16:  8, internal ODT de-assertion based on bit 11-8
+#                with the considered SDRAM internal delay
+# bit 31-20:  0, required

Quoted 8 lines

board/keymile/km_arm/128M16-1.cfg

Quoted 8 lines

board/keymile/km_arm/128M16-1.cfg new file +5 -0

+
+DATA 0xFFD0147c 0x00008452   # DDR2 SDRAM Timing High
+# bit 3-0:    2, M_ODT assertion same as bit 11-8
+# bit 7-4:    5, M_ODT de-assertion same as bit 15-12
+# bit 11-8:   4, internal ODT assertion 2 cycles after write start

command

board/keymile/km_arm/128M16-1.cfg new file +2 -0

+#                with the considered SDRAM internal delay
+# bit 15-12:  8, internal ODT de-assertion 5 cycles after write

start

Quoted 12 lines

Quoted 12 lines

command

board/keymile/km_arm/128M16-1.cfg new file +11 -0

+#                with the considered SDRAM internal delay
+
+DATA 0xFFD01500 0x00000000   # CS[0]n Base address to 0x0
+# bit 23-0:   0, reserved
+# bit 31-24:  0, CPU CS Window0 Base Address, addr bits [31:24]
+
+DATA 0xFFD01504 0x0FFFFFF1   # CS[0]n Size
+# bit 0:      1, Window enabled
+# bit 1:      0, Write Protect disabled
+# bit 3-2:    0, CS0 hit selected
+# bit 23-4:ones, required

Quoted 8 lines

board/keymile/km_arm/128M16-1.cfg

Quoted 8 lines

board/keymile/km_arm/128M16-1.cfg new file +8 -0

+# bit 31-24: 0x0F, Size (i.e. 256MB)
+
+DATA 0xFFD0150C 0x00000000   # CS[1]n Size, window disabled
+DATA 0xFFD01514 0x00000000   # CS[2]n Size, window disabled
+DATA 0xFFD0151C 0x00000000   # CS[3]n Size, window disabled
+
+DATA 0xFFD01494 0x00010000   #  DDR ODT Control (Low)
+# bit 3-0:     0, ODT0Rd, MODT[0] not asserted during read from

DRAM

Quoted 5 lines

board/keymile/km_arm/128M16-1.cfg

Quoted 5 lines

CS0

board/keymile/km_arm/128M16-1.cfg new file +4 -0

+# bit 7-4:     0, ODT0Rd, MODT[1] not asserted
+# bit 11-8:    0, required
+# big 15-11:   0, required
+# bit 19-16:   1, ODT0Wr, MODT[0] asserted during write to DRAM

CS0

Quoted 6 lines

board/keymile/km_arm/128M16-1.cfg

Quoted 6 lines

board/keymile/km_arm/128M16-1.cfg new file +6 -0

+# bit 23-20:   0, ODT0Wr, MODT[1] not asserted
+# bit 27-24:   0, required
+# bit 31-28:   0, required
+
+DATA 0xFFD01498 0x00000000   #  DDR ODT Control (High)
+# bit 1-0:     0, ODT0 controlled by ODT Control (low) register

above

Quoted 5 lines

board/keymile/km_arm/128M16-1.cfg

Quoted 5 lines

board/keymile/km_arm/128M16-1.cfg new file +5 -0

+# bit 3-2:     0, ODT1 controlled by register
+# bit 31-4:    0, required
+
+DATA 0xFFD0149C 0x0000E801   # CPU ODT Control
+# bit 3-0:     1, ODTRd, Internal ODT asserted during read from

DRAM

Quoted 8 lines

Quoted 8 lines

bank0
+# bit 7-4: 0, ODTWr, Internal ODT not asserted during write to
DRAM

board/keymile/km_arm/128M16-1.cfg new file +5 -0

+# bit 9-8:     0, ODTEn, controlled by ODTRd and ODTWr
+# bit 11-10:   2, DQ_ODTSel. ODT select turned on, 75 ohm
+# bit 13-12:   2, STARTBURST ODT buffer selected, 75 ohm
+# bit 14:      1, STARTBURST ODT enabled
+# bit 15:      1, Use ODT Block

Quoted 8 lines

board/keymile/km_arm/128M16-1.cfg line 293

Quoted 6 lines

board/keymile/km_arm/128M16-1.cfg new file +6 -0

+
+DATA 0xFFD01480 0x00000001   # DDR Initialization Control
+# bit 0:       1, enable DDR init upon this register write
+# bit 31-1:    0, reserved
+
+# End of Header extension

Is this configuration similar to any other board already mainlined?

if there is small delta like RAM/flash sizes then you can manage it through board_init()

Quoted 3 lines

Just think of it.

I would like to keep it as it is.

Quoted 10 lines

Quoted 10 lines

board/keymile/km_arm/128M16-1.cfg new file +1 -0

+DATA 0x0 0x0

board/keymile/km_arm/km_arm.c +0 -0

index e4ae1fb..ffe13cd 100644
@@ -133,10 +133,11 @@ int startup_allowed(void)
 }
 #endif
 

Quoted 8 lines

Quoted 8 lines

board/keymile/km_arm/km_arm.c +2 -2

-#if (defined(CONFIG_MGCOGE3UN)|defined(CONFIG_PORTL2))
+#if (defined(CONFIG_MGCOGE3UN)|defined(CONFIG_PORTL2)| \
+     defined(CONFIG_KM_PIGGY4_88E6352))
 /*
- * These two boards have always ethernet present. Its connected to

the mv
- * switch.
+ * All boards with PIGGY4 connected via a simple switch have

ethernet

Quoted 11 lines

Quoted 11 lines

always
+ * present.
*/
int ethernet_present(void)
{

board/keymile/km_arm/km_arm.c +1 -1

@@ -384,7 +385,7 @@ void reset_phy(void)
      /* reset the phy */
      miiphy_reset(name, CONFIG_PHY_BASE_ADR);
 }
-#else
+#elif !defined(CONFIG_KM_PIGGY4_88E6352)

Quoted 8 lines

boards.cfg pogo_e02 arm

Quoted 8 lines

board/keymile/km_arm/km_arm.c +0 -0

 /* Configure and enable MV88E1118 PHY on the piggy*/
 void reset_phy(void)
 {

boards.cfg +0 -0

index b711e0d..1a4c2ad 100644
@@ -140,6 +140,7 @@ pogo_e02                     arm

arm926ejs

Quoted 7 lines

Quoted 7 lines

boards.cfg +0 -1

-                   clouden
 dns325                       arm         arm926ejs   -

d-link kirkwood
km_kirkwood arm arm926ejs km_arm
keymile kirkwood km_kirkwood:KM_KIRKWOOD,KM_DISABLE_PCI
km_kirkwood_pci arm arm926ejs km_arm
keymile kirkwood

km_kirkwood:KM_KIRKWOOD_PCI,KM_RECONFIG_XLX

Quoted 4 lines

Quoted 1 line

+kmnusa arm arm926ejs km_arm

Why name is not km_nusa?

Could be also km_nusa. But isn't it up to us how we name our boards?

Quoted 8 lines

Review

Quoted 8 lines

keymile kirkwood km_kirkwood:KM_NUSA
mgcoge3un arm arm926ejs km_arm
keymile kirkwood
portl2 arm arm926ejs km_arm
keymile kirkwood
inetspace_v2 arm arm926ejs netspace_v2
LaCie kirkwood lacie_kw:INETSPACE_V2

(quoted diff) +0 -0

b/include/configs/km/km_arm.h

Quoted 7 lines

Quoted 7 lines

index 28b5021..a35ef61 100644

include/configs/km/km_arm.h +0 -0

@@ -57,6 +57,13 @@
 #define CONFIG_CMD_SF
 #define CONFIG_SOFT_I2C              /* I2C bit-banged       */
 

Quoted 10 lines

include/configs/km/km_arm.h line 66

Quoted 7 lines

include/configs/km/km_arm.h +7 -0

+#if defined CONFIG_KM_ENV_IS_IN_SPI_NOR
+#define CONFIG_ENV_SPI_BUS           0
+#define CONFIG_ENV_SPI_CS            0
+#define CONFIG_ENV_SPI_MAX_HZ                5000000
+#define CONFIG_ENV_SPI_MODE          SPI_MODE_3
+#endif
+

Do you still need this? Your patch 03/20 takes care of this.

Yes we need it. Patch 03/20 makes it possible to overwrite these default values.
And in this patch we use 5MHz as max frequency rather than 50MHz which is the
default setting.

Regards
Holger

Quoted 45 lines

-----Original Message-----
From: Holger Brunck [mailto:holger.brunck at keymile.com]
Sent: 12 June 2012 14:04
To: Prafulla Wadaskar
Cc: Valentin Longchamp; prafulla at mavell.com; u-boot at lists.denx.de; Gerlando Falauto
Subject: Re: [PATCH 04/20] arm/km: add kmnusa board support

Quoted 7 lines · Prafulla Wadaskar

Quoted 7 lines

-----Original Message-----
From: Valentin Longchamp [mailto:valentin.longchamp at keymile.com]
Sent: 07 June 2012 15:37
To: prafulla at mavell.com
Cc: Holger Brunck; u-boot at lists.denx.de; Valentin Longchamp;

Gerlando

Quoted 25 lines

Quoted 14 lines

Falauto; Prafulla Wadaskar
Subject: [PATCH 04/20] arm/km: add kmnusa board support

From: Holger Brunck <[email protected]>

This board is similar to portl2, but it has the u-boot environment in a SPI NOR flash and not in an i2c eeprom like portl2 have.

Some other details:
- IVM EEPROM is at adress: pca9547:70:9
- PCI is enabled
- PIGGY4 is connected via MV88E6352 simple switch. There is no phy between the simple switch and the kirkwood.

Quoted 8 lines

Signed-off-by Holger Brunck <[email protected]>

Signed-off-by Valentin Longchamp <[email protected]>

cc Gerlando Falauto <[email protected]>

cc Prafulla Wadaskar <[email protected]>

---
 MAINTAINERS                       |    1 +
 board/keymile/km_arm/128M16-1.cfg |  294

+++++++++++++++++++++++++++++++++++++

Please avoid file names starting with numbers.

Quoted 3 lines

would sdram128M16-1.cfg be ok? The reason for this numbering is to have a chance
to know which organisation this RAM has.

I think kwbimage_128M16_1.cfg should be okay,
BTW: if the configuration is similar to any other already supported board, may you think to reuse the same.

-----Original Message-----
From: Holger Brunck [mailto:holger.brunck at keymile.com]
Sent: 12 June 2012 14:04
To: Prafulla Wadaskar
Cc: Valentin Longchamp; prafulla at mavell.com; u-boot at lists.denx.de; Gerlando Falauto
Subject: Re: [PATCH 04/20] arm/km: add kmnusa board support

On 06/12/2012 06:39 AM, Prafulla Wadaskar wrote:

Quoted 4 lines

Review

Quoted 2 lines

(quoted diff) +2 -0

+
+# End of Header extension

Is this configuration similar to any other board already mainlined?

if there is small delta like RAM/flash sizes then you can manage it through board_init()

Quoted 3 lines

Just think of it.

I would like to keep it as it is.

Quoted 10 lines

Quoted 10 lines

board/keymile/km_arm/128M16-1.cfg new file +1 -0

+DATA 0x0 0x0

board/keymile/km_arm/km_arm.c +0 -0

index e4ae1fb..ffe13cd 100644
@@ -133,10 +133,11 @@ int startup_allowed(void)
 }
 #endif
 

Quoted 8 lines

Quoted 8 lines

board/keymile/km_arm/km_arm.c +2 -2

-#if (defined(CONFIG_MGCOGE3UN)|defined(CONFIG_PORTL2))
+#if (defined(CONFIG_MGCOGE3UN)|defined(CONFIG_PORTL2)| \
+     defined(CONFIG_KM_PIGGY4_88E6352))
 /*
- * These two boards have always ethernet present. Its connected to

the mv
- * switch.
+ * All boards with PIGGY4 connected via a simple switch have

ethernet

Quoted 11 lines

Quoted 11 lines

always
+ * present.
*/
int ethernet_present(void)
{

board/keymile/km_arm/km_arm.c +1 -1

@@ -384,7 +385,7 @@ void reset_phy(void)
      /* reset the phy */
      miiphy_reset(name, CONFIG_PHY_BASE_ADR);
 }
-#else
+#elif !defined(CONFIG_KM_PIGGY4_88E6352)

Quoted 8 lines

boards.cfg pogo_e02 arm

Quoted 8 lines

board/keymile/km_arm/km_arm.c +0 -0

 /* Configure and enable MV88E1118 PHY on the piggy*/
 void reset_phy(void)
 {

boards.cfg +0 -0

index b711e0d..1a4c2ad 100644
@@ -140,6 +140,7 @@ pogo_e02                     arm

arm926ejs

Quoted 7 lines

Quoted 7 lines

boards.cfg +0 -1

-                   clouden
 dns325                       arm         arm926ejs   -

d-link kirkwood
km_kirkwood arm arm926ejs km_arm
keymile kirkwood km_kirkwood:KM_KIRKWOOD,KM_DISABLE_PCI
km_kirkwood_pci arm arm926ejs km_arm
keymile kirkwood

km_kirkwood:KM_KIRKWOOD_PCI,KM_RECONFIG_XLX

Quoted 4 lines

Quoted 1 line

+kmnusa arm arm926ejs km_arm

Why name is not km_nusa?

Could be also km_nusa. But isn't it up to us how we name our boards?

Quoted 9 lines

Review

Quoted 9 lines

keymile kirkwood km_kirkwood:KM_NUSA
mgcoge3un arm arm926ejs km_arm
keymile kirkwood
portl2 arm arm926ejs km_arm
keymile kirkwood
inetspace_v2 arm arm926ejs netspace_v2
LaCie kirkwood lacie_kw:INETSPACE_V2

(quoted diff) +0 -0

b/include/configs/km/km_arm.h

Quoted 7 lines

Quoted 7 lines

index 28b5021..a35ef61 100644

include/configs/km/km_arm.h +0 -0

@@ -57,6 +57,13 @@
 #define CONFIG_CMD_SF
 #define CONFIG_SOFT_I2C              /* I2C bit-banged       */
 

Quoted 10 lines

include/configs/km/km_arm.h line 66

Quoted 7 lines

include/configs/km/km_arm.h +7 -0

+#if defined CONFIG_KM_ENV_IS_IN_SPI_NOR
+#define CONFIG_ENV_SPI_BUS           0
+#define CONFIG_ENV_SPI_CS            0
+#define CONFIG_ENV_SPI_MAX_HZ                5000000
+#define CONFIG_ENV_SPI_MODE          SPI_MODE_3
+#endif
+

Do you still need this? Your patch 03/20 takes care of this.

Yes we need it. Patch 03/20 makes it possible to overwrite these default values.
And in this patch we use 5MHz as max frequency rather than 50MHz which is the
default setting.

-----Original Message-----
From: Holger Brunck [mailto:holger.brunck at keymile.com]
Sent: 12 June 2012 14:04
To: Prafulla Wadaskar
Cc: Valentin Longchamp; prafulla at mavell.com; u-boot at lists.denx.de; Gerlando Falauto
Subject: Re: [PATCH 04/20] arm/km: add kmnusa board support

Quoted 7 lines · Prafulla Wadaskar

Quoted 7 lines

-----Original Message-----
From: Valentin Longchamp [mailto:valentin.longchamp at keymile.com]
Sent: 07 June 2012 15:37
To: prafulla at mavell.com
Cc: Holger Brunck; u-boot at lists.denx.de; Valentin Longchamp;

Gerlando

Quoted 23 lines

Quoted 14 lines

Falauto; Prafulla Wadaskar
Subject: [PATCH 04/20] arm/km: add kmnusa board support

From: Holger Brunck <[email protected]>

This board is similar to portl2, but it has the u-boot environment in a SPI NOR flash and not in an i2c eeprom like portl2 have.

Some other details:
- IVM EEPROM is at adress: pca9547:70:9
- PCI is enabled
- PIGGY4 is connected via MV88E6352 simple switch. There is no phy between the simple switch and the kirkwood.

Quoted 8 lines

Signed-off-by Holger Brunck <[email protected]>

Signed-off-by Valentin Longchamp <[email protected]>

cc Gerlando Falauto <[email protected]>

cc Prafulla Wadaskar <[email protected]>

---
 MAINTAINERS                       |    1 +
 board/keymile/km_arm/128M16-1.cfg |  294

+++++++++++++++++++++++++++++++++++++

Quoted 2 lines

Please avoid file names starting with numbers.

would sdram128M16-1.cfg be ok? The reason for this numbering is to have a chance
to know which organisation this RAM has.

Quoted 14 lines

Quoted 14 lines

 board/keymile/km_arm/km_arm.c     |    9 +-
 boards.cfg                        |    1 +
 include/configs/km/km_arm.h       |   44 +++++-
 include/configs/km_kirkwood.h     |   67 +++++++--
 6 files changed, 392 insertions(+), 24 deletions(-)
 create mode 100644 board/keymile/km_arm/128M16-1.cfg

MAINTAINERS +0 -0

index 0445539..aa11268 100644
@@ -738,6 +738,7 @@ Sergey Lapin <[email protected]>
 Valentin Longchamp <[email protected]>
 

Quoted 4 lines

MAINTAINERS Sergey Lapin <[email protected]> · line 741

Quoted 2 lines

MAINTAINERS +1 -0

      km_kirkwood     ARM926EJS (Kirkwood SoC)
+     kmnusa          ARM926EJS (Kirkwood SoC)

Again.... I would like to suggest to separate out new boards

addition, bugfixes/updates specific to km_*boards and generic kirkwood specific patches.

Quoted 1 line

Quoted 2 lines

It's always faster to merger small patch series that big one.

Yes ok, but was has this to do with this patch? What is meant to be kirkwood
specific? This is all board related code.

Quoted 21 lines

Quoted 14 lines

Quoted 14 lines

 board/keymile/km_arm/km_arm.c     |    9 +-
 boards.cfg                        |    1 +
 include/configs/km/km_arm.h       |   44 +++++-
 include/configs/km_kirkwood.h     |   67 +++++++--
 6 files changed, 392 insertions(+), 24 deletions(-)
 create mode 100644 board/keymile/km_arm/128M16-1.cfg

MAINTAINERS +0 -0

index 0445539..aa11268 100644
@@ -738,6 +738,7 @@ Sergey Lapin <[email protected]>
 Valentin Longchamp <[email protected]>
 

Quoted 4 lines

MAINTAINERS Sergey Lapin <[email protected]> · line 741

Quoted 2 lines

MAINTAINERS +1 -0

      km_kirkwood     ARM926EJS (Kirkwood SoC)
+     kmnusa          ARM926EJS (Kirkwood SoC)

Again.... I would like to suggest to separate out new boards

addition, bugfixes/updates specific to km_*boards and generic kirkwood specific patches.

Quoted 1 line

Quoted 6 lines

Quoted 2 lines

It's always faster to merger small patch series that big one.

Yes ok, but was has this to do with this patch? What is meant to be kirkwood
specific? This is all board related code.

I agree, let's separate out -
1. bugfix/updates patch series to current code
2. "Kirkwood specific" means the changes to the Kirkwood related file that may affects other boards, for ex arch/arm/cpu/arm926ejs/mach-kirkwood/*
3. Additional board supports

And if possible these patches should be independent so that can be pulled independently

-----Original Message-----
From: Holger Brunck [mailto:holger.brunck at keymile.com]
Sent: 12 June 2012 16:07
To: Prafulla Wadaskar
Cc: Valentin Longchamp; prafulla at mavell.com; u-boot at lists.denx.de; Gerlando Falauto
Subject: Re: [PATCH 04/20] arm/km: add kmnusa board support

Quoted 14 lines · Prafulla Wadaskar

Quoted 14 lines

Quoted 14 lines

Quoted 14 lines

 board/keymile/km_arm/km_arm.c     |    9 +-
 boards.cfg                        |    1 +
 include/configs/km/km_arm.h       |   44 +++++-
 include/configs/km_kirkwood.h     |   67 +++++++--
 6 files changed, 392 insertions(+), 24 deletions(-)
 create mode 100644 board/keymile/km_arm/128M16-1.cfg

MAINTAINERS +0 -0

index 0445539..aa11268 100644
@@ -738,6 +738,7 @@ Sergey Lapin <[email protected]>
 Valentin Longchamp <[email protected]>
 

Quoted 5 lines

Quoted 5 lines

Quoted 4 lines

MAINTAINERS Sergey Lapin <[email protected]> · line 741

Quoted 2 lines

MAINTAINERS +1 -0

      km_kirkwood     ARM926EJS (Kirkwood SoC)
+     kmnusa          ARM926EJS (Kirkwood SoC)

Again.... I would like to suggest to separate out new boards

addition, bugfixes/updates specific to km_*boards and generic

kirkwood

Quoted 5 lines

Quoted 5 lines

specific patches.

Quoted 3 lines

It's always faster to merger small patch series that big one.

Quoted 7 lines

Quoted 3 lines

Yes ok, but was has this to do with this patch? What is meant to be kirkwood
specific? This is all board related code.

I agree, let's separate out -
1. bugfix/updates patch series to current code
2. "Kirkwood specific" means the changes to the Kirkwood related

file that may affects other boards, for ex
arch/arm/cpu/arm926ejs/mach-kirkwood/*

Quoted 3 lines

3. Additional board supports

And if possible these patches should be independent so that can be

pulled independently

Quoted 1 line

the only patch in the serie which modifies common Kirkwood related files are:
[PATCH 03/20] arm/kirkwood: protect the ENV_SPI #defines

Do you want me to send this one seperately? I can do that. So then we resend
again a new patch serie I guess...

The other stuff is only related to our boards and I would like to keep it as it
is. It would cause a lot of rebasing and reorganisation and in the end the
result is the same.

Quoted 55 lines

-----Original Message-----
From: Holger Brunck [mailto:holger.brunck at keymile.com]
Sent: 12 June 2012 16:07
To: Prafulla Wadaskar
Cc: Valentin Longchamp; prafulla at mavell.com; u-boot at lists.denx.de; Gerlando Falauto
Subject: Re: [PATCH 04/20] arm/km: add kmnusa board support

Quoted 14 lines · Prafulla Wadaskar

Quoted 14 lines

Quoted 14 lines

Quoted 14 lines

 board/keymile/km_arm/km_arm.c     |    9 +-
 boards.cfg                        |    1 +
 include/configs/km/km_arm.h       |   44 +++++-
 include/configs/km_kirkwood.h     |   67 +++++++--
 6 files changed, 392 insertions(+), 24 deletions(-)
 create mode 100644 board/keymile/km_arm/128M16-1.cfg

MAINTAINERS +0 -0

index 0445539..aa11268 100644
@@ -738,6 +738,7 @@ Sergey Lapin <[email protected]>
 Valentin Longchamp <[email protected]>
 

Quoted 5 lines

Quoted 5 lines

Quoted 4 lines

MAINTAINERS Sergey Lapin <[email protected]> · line 741

Quoted 2 lines

MAINTAINERS +1 -0

      km_kirkwood     ARM926EJS (Kirkwood SoC)
+     kmnusa          ARM926EJS (Kirkwood SoC)

Again.... I would like to suggest to separate out new boards

addition, bugfixes/updates specific to km_*boards and generic

kirkwood

Quoted 5 lines

Quoted 5 lines

specific patches.

Quoted 3 lines

It's always faster to merger small patch series that big one.

Quoted 7 lines

Quoted 3 lines

Yes ok, but was has this to do with this patch? What is meant to be kirkwood
specific? This is all board related code.

I agree, let's separate out -
1. bugfix/updates patch series to current code
2. "Kirkwood specific" means the changes to the Kirkwood related

file that may affects other boards, for ex
arch/arm/cpu/arm926ejs/mach-kirkwood/*

Quoted 3 lines

3. Additional board supports

And if possible these patches should be independent so that can be

pulled independently

Quoted 1 line

the only patch in the serie which modifies common Kirkwood related files are:
[PATCH 03/20] arm/kirkwood: protect the ENV_SPI #defines

Quoted 3 lines

Do you want me to send this one seperately? I can do that. So then we resend
again a new patch serie I guess...

It would be a great you can split 20 patches in to smaller patch series as per above suggestion.

-----Original Message-----
From: Holger Brunck [mailto:holger.brunck at keymile.com]
Sent: 12 June 2012 17:13
To: Prafulla Wadaskar
Cc: Valentin Longchamp; prafulla at mavell.com; u-boot at lists.denx.de; Gerlando Falauto
Subject: Re: [PATCH 04/20] arm/km: add kmnusa board support

Quoted 29 lines · Prafulla Wadaskar

Quoted 29 lines

-----Original Message-----
From: Holger Brunck [mailto:holger.brunck at keymile.com]
Sent: 12 June 2012 16:07
To: Prafulla Wadaskar
Cc: Valentin Longchamp; prafulla at mavell.com; u-boot at lists.denx.de; Gerlando Falauto
Subject: Re: [PATCH 04/20] arm/km: add kmnusa board support

Quoted 18 lines · Prafulla Wadaskar

Quoted 18 lines

Quoted 18 lines

Quoted 12 lines

 board/keymile/km_arm/km_arm.c     |    9 +-
 boards.cfg                        |    1 +
 include/configs/km/km_arm.h       |   44 +++++-
 include/configs/km_kirkwood.h     |   67 +++++++--
 6 files changed, 392 insertions(+), 24 deletions(-)
 create mode 100644 board/keymile/km_arm/128M16-1.cfg

MAINTAINERS +0 -0

index 0445539..aa11268 100644

MAINTAINERS Sergey Lapin <[email protected]> · line 741

Quoted 4 lines

MAINTAINERS +1 -0

@@ -738,6 +738,7 @@ Sergey Lapin <[email protected]>
 Valentin Longchamp <[email protected]>
 
      km_kirkwood     ARM926EJS (Kirkwood SoC)
+     kmnusa          ARM926EJS (Kirkwood SoC)

Again.... I would like to suggest to separate out new boards

Quoted 8 lines

Quoted 8 lines

Quoted 1 line

Quoted 1 line

addition, bugfixes/updates specific to km_*boards and generic

kirkwood

Quoted 6 lines

Quoted 6 lines

specific patches.

Quoted 3 lines

It's always faster to merger small patch series that big one.

Yes ok, but was has this to do with this patch? What is meant to

be

Quoted 11 lines

Quoted 11 lines

Quoted 6 lines

Quoted 2 lines

kirkwood
specific? This is all board related code.

I agree, let's separate out -
1. bugfix/updates patch series to current code
2. "Kirkwood specific" means the changes to the Kirkwood related

file that may affects other boards, for ex
arch/arm/cpu/arm926ejs/mach-kirkwood/*

Quoted 3 lines

3. Additional board supports

And if possible these patches should be independent so that can be

Quoted 8 lines

Quoted 8 lines

pulled independently

Quoted 1 line

the only patch in the serie which modifies common Kirkwood related files are:
[PATCH 03/20] arm/kirkwood: protect the ENV_SPI #defines

Do you want me to send this one seperately? I can do that. So then

we

Quoted 3 lines

Quoted 2 lines

resend
again a new patch serie I guess...

Quoted 1 line

It would be a great you can split 20 patches in to smaller patch

series as per above suggestion.

Quoted 1 line

Again, the only patch wich is common Kirkwood related is the above mentioned
patch. I can extract this one if you want me to.

All others are somehow interconnected and therefore it makes sense to have it
in one patch serie.

Quoted 73 lines

-----Original Message-----
From: Holger Brunck [mailto:holger.brunck at keymile.com]
Sent: 12 June 2012 17:13
To: Prafulla Wadaskar
Cc: Valentin Longchamp; prafulla at mavell.com; u-boot at lists.denx.de; Gerlando Falauto
Subject: Re: [PATCH 04/20] arm/km: add kmnusa board support

Quoted 29 lines · Prafulla Wadaskar

Quoted 29 lines

-----Original Message-----
From: Holger Brunck [mailto:holger.brunck at keymile.com]
Sent: 12 June 2012 16:07
To: Prafulla Wadaskar
Cc: Valentin Longchamp; prafulla at mavell.com; u-boot at lists.denx.de; Gerlando Falauto
Subject: Re: [PATCH 04/20] arm/km: add kmnusa board support

Quoted 18 lines · Prafulla Wadaskar

Quoted 18 lines

Quoted 18 lines

Quoted 12 lines

 board/keymile/km_arm/km_arm.c     |    9 +-
 boards.cfg                        |    1 +
 include/configs/km/km_arm.h       |   44 +++++-
 include/configs/km_kirkwood.h     |   67 +++++++--
 6 files changed, 392 insertions(+), 24 deletions(-)
 create mode 100644 board/keymile/km_arm/128M16-1.cfg

MAINTAINERS +0 -0

index 0445539..aa11268 100644

MAINTAINERS Sergey Lapin <[email protected]> · line 741

Quoted 4 lines

MAINTAINERS +1 -0

@@ -738,6 +738,7 @@ Sergey Lapin <[email protected]>
 Valentin Longchamp <[email protected]>
 
      km_kirkwood     ARM926EJS (Kirkwood SoC)
+     kmnusa          ARM926EJS (Kirkwood SoC)

Again.... I would like to suggest to separate out new boards

Quoted 8 lines

Quoted 8 lines

Quoted 1 line

Quoted 1 line

addition, bugfixes/updates specific to km_*boards and generic

kirkwood

Quoted 6 lines

Quoted 6 lines

specific patches.

Quoted 3 lines

It's always faster to merger small patch series that big one.

Yes ok, but was has this to do with this patch? What is meant to

be

Quoted 11 lines

Quoted 11 lines

Quoted 6 lines

Quoted 2 lines

kirkwood
specific? This is all board related code.

I agree, let's separate out -
1. bugfix/updates patch series to current code
2. "Kirkwood specific" means the changes to the Kirkwood related

file that may affects other boards, for ex
arch/arm/cpu/arm926ejs/mach-kirkwood/*

Quoted 3 lines

3. Additional board supports

And if possible these patches should be independent so that can be

Quoted 8 lines

Quoted 8 lines

pulled independently

Quoted 1 line

the only patch in the serie which modifies common Kirkwood related files are:
[PATCH 03/20] arm/kirkwood: protect the ENV_SPI #defines

Do you want me to send this one seperately? I can do that. So then

we

Quoted 4 lines

Quoted 2 lines

resend
again a new patch serie I guess...

It would be a great you can split 20 patches in to smaller patch

Quoted 6 lines

series as per above suggestion.

Quoted 1 line

Again, the only patch wich is common Kirkwood related is the above mentioned
patch. I can extract this one if you want me to.

Yes, extract this and send it as standalone

Quoted 4 lines

All others are somehow interconnected and therefore it makes sense to have it
in one patch serie.

Send one patch series which are related to updates/fixes to already supported code.

Then send anther patch series for addition of new boards, mention the dependency if any.

-----Original Message-----
From: Valentin Longchamp [mailto:valentin.longchamp at keymile.com]
Sent: 07 June 2012 15:37
To: prafulla at mavell.com
Cc: Holger Brunck; u-boot at lists.denx.de; Valentin Longchamp; Gerlando Falauto; Prafulla Wadaskar
Subject: [PATCH 05/20] arm/km: add kmcoge5un board support

From: Holger Brunck <[email protected]>

For u-boot this board is similar to mgcoge3un. But some differences are present. We have a different SDRAM on it and therefore a new

SDRAM config file. Additionaly this board has a direct MAC/MAC connection from the kirkwood to a marvell simple switch without a phy inbetween, this needs a new configuration for the mvgbe driver.

Signed-off-by Holger Brunck <[email protected]>

Signed-off-by Valentin Longchamp <[email protected]>

cc Gerlando Falauto <[email protected]>

cc Prafulla Wadaskar <[email protected]>

---
 MAINTAINERS                      |    1 +
 board/keymile/km_arm/256M8-1.cfg |  296

++++++++++++++++++++++++++++++++++++++

 boards.cfg                       |    1 +
 include/configs/km_kirkwood.h    |   16 ++-
 4 files changed, 312 insertions(+), 2 deletions(-)
 create mode 100644 board/keymile/km_arm/256M8-1.cfg

MAINTAINERS +0 -0

index aa11268..ef57cd6 100644
@@ -740,6 +740,7 @@ Valentin Longchamp

<[email protected]>

      km_kirkwood     ARM926EJS (Kirkwood SoC)
      kmnusa          ARM926EJS (Kirkwood SoC)
      mgcoge3un       ARM926EJS (Kirkwood SoC)
+     kmcoge5un       ARM926EJS (Kirkwood SoC)

portl2 ARM926EJS (Kirkwood SoC)

Nishanth Menon <[email protected]>

board/keymile/km_arm/256M8-1.cfg new file +144 -0

new file mode 100644
index 0000000..3e1237b
@@ -0,0 +1,296 @@
+#
+# (C) Copyright 2012
+# Stefan Bigler, Keymile AG, stefan.bigler at keymile.com
+# Norbert Mayer, Keymile AG, norbert.mayer at keymile.com
+# Deepak Patel, XENTECH Limited, deepak.patel at xentech.co.uk
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+# Refer docs/README.kwimage for more details about how-to configure
+# and create kirkwood boot image
+#
+# This configuration applies to COGE5 design (ARM-part)
+# Two 8-Bit devices are connected on the 16-Bit bus on the same
+# chip-select. The supported devices are
+#   MT47H256M8EB-3IT:C
+#   MT47H256M8EB-25EIT:C
+
+# Boot Media configurations
+BOOT_FROM    spi     # Boot from SPI flash
+
+DATA 0xFFD10000 0x01112222   # MPP Control 0 Register
+# bit 3-0:   2, MPPSel0  SPI_CSn  (1=NF_IO[2])
+# bit 7-4:   2, MPPSel1  SPI_MOSI (1=NF_IO[3])
+# bit 12-8:  2, MPPSel2  SPI_SCK  (1=NF_IO[4])
+# bit 15-12: 2, MPPSel3  SPI_MISO (1=NF_IO[5])
+# bit 19-16: 1, MPPSel4  NF_IO[6]
+# bit 23-20: 1, MPPSel5  NF_IO[7]
+# bit 27-24: 1, MPPSel6  SYSRST_O
+# bit 31-28: 0, MPPSel7  GPO[7]
+
+DATA 0xFFD10004 0x03303300   # MPP Control 1 Register
+# bit 3-0:   0, MPPSel8       GPIO[8] CPU_SDA bitbanged
+# bit 7-4:   0, MPPSel9  GPIO[9] CPU_SCL bitbanged
+# bit 12-8:  3, MPPSel10 UA0_TXD
+# bit 15-12: 3, MPPSel11 UA0_RXD
+# bit 19-16: 0, MPPSel12 not connected
+# bit 23-20: 3, MPPSel13 GPIO[14]
+# bit 27-24: 3, MPPSel14 GPIO[15]
+# bit 31-28: 0, MPPSel15 GPIO[16] BOOT_FL_SEL (SPI-MUX Signal)
+
+DATA 0xFFD10008 0x00001100   # MPP Control 2 Register
+# bit 3-0:   0, MPPSel16 GPIO[16]
+# bit 7-4:   0, MPPSel17 not connected
+# bit 11-8:  1, MPPSel18 NF_IO[0]
+# bit 15-12: 1, MPPSel19 NF_IO[1]
+# bit 19-16: 0, MPPSel20 GPIO[20]
+# bit 23-20: 0, MPPSel21 GPIO[21]
+# bit 27-24: 0, MPPSel22 GPIO[22]
+# bit 31-28: 0, MPPSel23 GPIO[23]
+
+# MPP Control 3-6 Register untouched (MPP24-49)
+
+DATA 0xFFD100E0 0x1B1B1B1B   # IO Configuration 0 Register
+# bit 2-0:   3, Reserved
+# bit 5-3:   3, Reserved
+# bit 6:     0, Reserved
+# bit 7:     0, RGMII-pads voltage = 3.3V
+# bit 10-8:  3, Reserved
+# bit 13-11: 3, Reserved
+# bit 14:    0, Reserved
+# bit 15:    0, MPP RGMII-pads voltage = 3.3V
+# bit 31-16  0x1B1B, Reserved
+
+DATA 0xFFD20134 0x66666666   # L2 RAM Timing 0 Register
+# bit 0-1:   2, Tag RAM RTC RAM0
+# bit 3-2:   1, Tag RAM WTC RAM0
+# bit 7-4:   6, Reserved
+# bit 9-8:   2, Valid RAM RTC RAM
+# bit 11-10: 1, Valid RAM WTC RAM
+# bit 13-12: 2, Dirty RAM RTC RAM
+# bit 15-14: 1, Dirty RAM WTC RAM
+# bit 17-16: 2, Data RAM RTC RAM0
+# bit 19-18: 1, Data RAM WTC RAM0
+# bit 21-20: 2, Data RAM RTC RAM1
+# bit 23-22: 1, Data RAM WTC RAM1
+# bit 25-24: 2, Data RAM RTC RAM2
+# bit 27-26: 1, Data RAM WTC RAM2
+# bit 29-28: 2, Data RAM RTC RAM3
+# bit 31-30: 1, Data RAM WTC RAM4
+
+DATA 0xFFD20138 0x66666666   # L2 RAM Timing 1 Register
+# bit 15-0:  ?, Reserved
+# bit 17-16: 2, ECC RAM RTC RAM0
+# bit 19-18: 1, ECC RAM WTC RAM0
+# bit 31-20: ?,Reserved
+
+DATA 0xFFD20154 0x00000200   # CPU RAM Management Control3 Register
+# bit 23-0:  0x000200, Addr Config tuning
+# bit 31-24: 0,        Reserved
+
+# ??? Missing register # CPU RAM Management Control2 Register
+
+DATA 0xFFD2014C 0x00001C00   # CPU RAM Management Control1 Register
+# bit 15-0:  0x1C00, Opmux Tuning
+# bit 31-16: 0,      Pc Dp Tuning
+
+DATA 0xFFD20148 0x00000001   # CPU RAM Management Control0 Register
+# bit 1-0:   1, addr clk tune
+# bit 3-2:   0, reserved
+# bit 5-4:   0, dtcmp clk tune
+# bit 7-6:   0, reserved
+# bit 9-8:   0, macdrv clk tune
+# bit 11-10: 0, opmuxgm2 clk tune
+# bit 15-14: 0, rf clk tune
+# bit 17-16: 0, rfbypass clk tune
+# bit 19-18: 0, pc dp clk tune
+# bit 23-20: 0, icache clk tune
+# bit 27:24: 0, dcache clk tune
+# bit 31:28: 0, regfile tunin
+
+# SDRAM initalization
+DATA 0xFFD01400 0x430004E0   # SDRAM Configuration Register
+# bit 13-0:  0x4E0, DDR2 clks refresh rate
+# bit 14:    0, reserved
+# bit 15:    0, reserved
+# bit 16:    0, CPU to Dram Write buffer policy
+# bit 17:    0, Enable Registered DIMM or Equivalent Sampling Logic
+# bit 19-18: 0, reserved
+# bit 23-20: 0, reserved
+# bit 24:    1, enable exit self refresh mode on DDR access
+# bit 25:    1, required
+# bit 29-26: 0, reserved
+# bit 31-30: 1, reserved
+
+DATA 0xFFD01404 0x36543000   # DDR Controller Control Low
+# bit 3-0:   0, reserved
+# bit 4:     0, 2T mode =addr/cmd in same cycle
+# bit 5:     0, clk is driven during self refresh, we don't care for

APX

board/keymile/km_arm/256M8-1.cfg new file +8 -0

+# bit 6:     0, use recommended falling edge of clk for addr/cmd
+# bit 7-11:  0, reserved
+# bit 12-13: 1, reserved, required 1
+# bit 14:    0, input buffer always powered up
+# bit 17-15: 0, reserved
+# bit 18:    1, cpu lock transaction enabled
+# bit 19:    0, reserved
+# bit 23-20: 5, recommended value for CL=4 and STARTBURST_DEL

disabled bit31=0
+# bit 27-24: 6, CL+1, STARTBURST sample stages, freq 200-399MHz, unbuffer DIMM

board/keymile/km_arm/256M8-1.cfg new file +95 -0

+# bit 30-28: 3, required
+# bit 31:    0, no additional STARTBURST delay
+
+DATA 0xFFD01408 0x2202444E   # DDR Timing (Low) (active cycles value
+1)
+# bit 3-0:   0xe, TRAS = 45ns -> 15 clk cycles
+# bit 7-4:   0x4, TRCD = 15ns -> 5 clk cycles
+# bit 11-8:  0x4, TRP = 15ns -> 5 clk cycles
+# bit 15-12: 0x4, TWR = 15ns -> 5 clk cycles
+# bit 19-16: 0x2, TWTR = 7,5ns -> 3 clk cycles
+# bit 20:      0, extended TRAS msb
+# bit 23-21:   0, reserved
+# bit 27-24: 0x2, TRRD = 7,5ns -> 3 clk cycles
+# bit 31-28: 0x2, TRTP = 7,5ns -> 3 clk cycles
+
+DATA 0xFFD0140C 0x0000003E   #  DDR Timing (High)
+# bit 6-0:   0x3E, TRFC = 195ns -> 63 clk cycles
+# bit 8-7:      0, TR2R
+# bit 10-9:     0, TR2W
+# bit 12-11:    0, TW2W
+# bit 31-13:    0, reserved
+
+DATA 0xFFD01410 0x00000000   #  DDR Address Control
+# bit 1-0:    0, Cs0width=x8 (2 devices)
+# bit 3-2:    0, Cs0size=2Gb
+# bit 5-4:    0, Cs1width=nonexistent
+# bit 7-6:    0, Cs1size =nonexistent
+# bit 9-8:    0, Cs2width=nonexistent
+# bit 11-10:  0, Cs2size =nonexistent
+# bit 13-12:  0, Cs3width=nonexistent
+# bit 15-14:  0, Cs3size =nonexistent
+# bit 16:     0, Cs0AddrSel
+# bit 17:     0, Cs1AddrSel
+# bit 18:     0, Cs2AddrSel
+# bit 19:     0, Cs3AddrSel
+# bit 31-20:  0, required
+
+DATA 0xFFD01414 0x00000000   #  DDR Open Pages Control
+# bit 0:      0,  OpenPage enabled
+# bit 31-1:   0, required
+
+DATA 0xFFD01418 0x00000000   #  DDR Operation
+# bit 3-0:    0, DDR cmd
+# bit 31-4:   0, required
+
+DATA 0xFFD0141C 0x00000652   #  DDR Mode
+# bit 2-0:    2, Burst Length = 4
+# bit 3:      0, Burst Type
+# bit 6-4:    5, CAS Latency = 5
+# bit 7:      0, Test mode
+# bit 8:      0, DLL Reset
+# bit 11-9:   3, Write recovery for auto-precharge must be 3
+# bit 12:     0, Active power down exit time, fast exit
+# bit 14-13:  0, reserved
+# bit 31-15:  0, reserved
+
+DATA 0xFFD01420 0x00000006   #  DDR Extended Mode
+# bit 0:      0, DDR DLL enabled
+# bit 1:      1, DDR drive strenght reduced
+# bit 2:      1, DDR ODT control lsb, 75ohm termination [RTT0]
+# bit 5-3:    0, required
+# bit 6:      0, DDR ODT control msb, 75ohm termination [RTT1]
+# bit 9-7:    0, required
+# bit 10:     0, differential DQS enabled
+# bit 11:     0, required
+# bit 12:     0, DDR output buffer enabled
+# bit 31-13:  0 required
+
+DATA 0xFFD01424 0x0000F17F   #  DDR Controller Control High
+# bit 2-0:    7, required
+# bit 3:      1, MBUS Burst Chop disabled
+# bit 6-4:    7, required
+# bit 7:      0, reserved
+# bit 8:      1, add sample stage required for > 266Mhz
+# bit 9:      0, no half clock cycle addition to dataout
+# bit 10:     0, 1/4 clock cycle skew enabled for addr/ctl signals
+# bit 11:     0, 1/4 clock cycle skew disabled for write mesh
+# bit 15-12:0xf, required
+# bit 31-16:  0, required
+
+DATA 0xFFD01428 0x00084520   # DDR2 SDRAM Timing Low
+# bit 3-0:    0, required
+# bit 7-4:    2, M_ODT assertion 2 cycles after read start command
+# bit 11-8:   5, M_ODT de-assertion 5 cycles after read start command
+#                (ODT turn off delay 2,5 clk cycles)
+# bit 15-12:  4, internal ODT time based on bit 7-4
+#                with the considered SDRAM internal delay
+# bit 19-16:  8, internal ODT de-assertion based on bit 11-8
+#                with the considered SDRAM internal delay
+# bit 31-20:  0, required
+
+DATA 0xFFD0147c 0x00008452   # DDR2 SDRAM Timing High
+# bit 3-0:    2, M_ODT assertion same as bit 11-8
+# bit 7-4:    5, M_ODT de-assertion same as bit 15-12
+# bit 11-8:   4, internal ODT assertion 2 cycles after write start

command

board/keymile/km_arm/256M8-1.cfg new file +2 -0

+#                with the considered SDRAM internal delay
+# bit 15-12:  8, internal ODT de-assertion 5 cycles after write start

command

board/keymile/km_arm/256M8-1.cfg new file +19 -0

+#                with the considered SDRAM internal delay
+
+DATA 0xFFD01500 0x00000000   # CS[0]n Base address to 0x0
+# bit 23-0:   0, reserved
+# bit 31-24:  0, CPU CS Window0 Base Address, addr bits [31:24]
+
+DATA 0xFFD01504 0x1FFFFFF1   # CS[0]n Size
+# bit 0:      1, Window enabled
+# bit 1:      0, Write Protect disabled
+# bit 3-2:    0, CS0 hit selected
+# bit 23-4:ones, required
+# bit 31-24:0x1F, Size (i.e. 512MB)
+
+DATA 0xFFD0150C 0x00000000   # CS[1]n Size, window disabled
+DATA 0xFFD01514 0x00000000   # CS[2]n Size, window disabled
+DATA 0xFFD0151C 0x00000000   # CS[3]n Size, window disabled
+
+DATA 0xFFD01494 0x00010000   #  DDR ODT Control (Low)
+# bit 3-0:     0, ODT0Rd, MODT[0] not asserted during read from DRAM

CS0

board/keymile/km_arm/256M8-1.cfg new file +15 -0

+# bit 7-4:     0, ODT0Rd, MODT[1] not asserted
+# bit 11-8:    0, required
+# big 15-11:   0, required
+# bit 19-16:   1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
+# bit 23-20:   0, ODT0Wr, MODT[1] not asserted
+# bit 27-24:   0, required
+# bit 31-28:   0, required
+
+DATA 0xFFD01498 0x00000004   #  DDR ODT Control (High)
+# bit 1-0:     0, ODT0 controlled by ODT Control (low) register above
+# bit 3-2:     1, ODT1 never active
+# bit 31-4:    0, required
+
+DATA 0xFFD0149C 0x0000E801   # CPU ODT Control
+# bit 3-0:     1, ODT0Rd, Internal ODT asserted during read from DRAM

bank0
+# bit 7-4: 0, ODT0Wr, Internal ODT not asserted during write to
DRAM bank0

board/keymile/km_arm/256M8-1.cfg new file +12 -0

+# bit 9-8:     0, ODTEn, controlled by ODT0Rd and ODT0Wr
+# bit 11-10:   2, DQ_ODTSel. ODT select turned on, 75 ohm
+# bit 13-12:   2, STARTBURST ODT buffer selected, 75 ohm
+# bit 14:      1, STARTBURST ODT enabled
+# bit 15:      1, Use ODT Block
+
+DATA 0xFFD01480 0x00000001   # DDR Initialization Control
+# bit 0:       1, enable DDR init upon this register write
+# bit 31-1:    0, reserved
+
+# End of Header extension
+DATA 0x0 0x0

boards.cfg +0 -0

index 1a4c2ad..d174371 100644
@@ -142,6 +142,7 @@ km_kirkwood                  arm         arm926ejs

km_arm keymile
km_kirkwood_pci arm arm926ejs km_arm
keymile kirkwood km_kirkwood:KM_KIRKWOOD_PCI,KM_RECONFIG_XLX
kmnusa arm arm926ejs km_arm
keymile kirkwood km_kirkwood:KM_NUSA
mgcoge3un arm arm926ejs km_arm
keymile kirkwood
+kmcoge5un arm arm926ejs km_arm
keymile kirkwood km_kirkwood:KMCOGE5UN
portl2 arm arm926ejs km_arm
keymile kirkwood

 inetspace_v2                 arm         arm926ejs   netspace_v2
LaCie          kirkwood       lacie_kw:INETSPACE_V2
 net2big_v2                   arm         arm926ejs   net2big_v2
LaCie          kirkwood       lacie_kw:NET2BIG_V2

include/configs/km_kirkwood.h +3 -0

index 97aa617..e6f0e36 100644
@@ -39,15 +39,18 @@
 
 #if defined(CONFIG_KM_KIRKWOOD)
 #define CONFIG_IDENT_STRING          "\nKeymile Kirkwood"
+#define CONFIG_HOSTNAME                      km_kirkwood
 #undef  CONFIG_KIRKWOOD_PCIE_INIT
 #define KM_IVM_BUS                   "pca9544a:70:9" /* I2C2 (Mux-Port 1)*/
 #elif defined(CONFIG_KM_KIRKWOOD_PCI)
 #define CONFIG_IDENT_STRING          "\nKeymile Kirkwood PCI"
+#define CONFIG_HOSTNAME                      km_kirkwood_pci
 #define KM_IVM_BUS                   "pca9544a:70:9" /* I2C2 (Mux-Port 1)*/
 /* KM_NUSA */
 #elif defined(CONFIG_KM_NUSA)
 #define KM_IVM_BUS                   "pca9547:70:9"  /* I2C2 (Mux-Port 1)*/
 #define CONFIG_IDENT_STRING          "\nKeymile NUSA"
+#define CONFIG_HOSTNAME                      kmnusa
 #undef CONFIG_SYS_KWD_CONFIG
 #define CONFIG_SYS_KWD_CONFIG \
              $(SRCTREE)/$(CONFIG_BOARDDIR)/128M16-1.cfg

@@ -55,6 +58,17 @@
 #define CONFIG_KM_FPGA_CONFIG
 #define CONFIG_KM_PIGGY4_88E6352

-----Original Message-----
From: Valentin Longchamp [mailto:valentin.longchamp at keymile.com]
Sent: 07 June 2012 15:37
To: prafulla at mavell.com
Cc: Holger Brunck; u-boot at lists.denx.de; Valentin Longchamp; Gerlando Falauto; Prafulla Wadaskar
Subject: [PATCH 10/20] arm/km: cleanup km_kirkwood boards

From: Holger Brunck <[email protected]>

Remove config options from boards.cfg and simply add one switch per board and differ afterwards in km_kirkwood.h between the features. More boards are upcoming and therefore it's easier to have this at one place.

Signed-off-by Holger Brunck <[email protected]>

Signed-off-by Valentin Longchamp <[email protected]>

cc Gerlando Falauto <[email protected]>

cc Prafulla Wadaskar <[email protected]>

---
 boards.cfg                    |    4 ++--
 include/configs/km_kirkwood.h |    7 ++++++-
 2 files changed, 8 insertions(+), 3 deletions(-)

boards.cfg +0 -0

index 0fb8811..9569d1a 100644
@@ -138,8 +138,8 @@ enbw_cmc                     arm         arm926ejs

enbw_cmc enbw
calimain arm arm926ejs calimain
omicron davinci
pogo_e02 arm arm926ejs -
cloudengines kirkwood
dns325 arm arm926ejs -
d-link kirkwood
-km_kirkwood arm arm926ejs km_arm
keymile kirkwood km_kirkwood:KM_KIRKWOOD,KM_DISABLE_PCI
-km_kirkwood_pci arm arm926ejs km_arm
keymile kirkwood km_kirkwood:KM_KIRKWOOD_PCI,KM_FPGA_CONFIG
+km_kirkwood arm arm926ejs km_arm
keymile kirkwood km_kirkwood:KM_KIRKWOOD

+km_kirkwood_pci arm arm926ejs km_arm
keymile kirkwood km_kirkwood:KM_KIRKWOOD_PCI
kmnusa arm arm926ejs km_arm
keymile kirkwood km_kirkwood:KM_NUSA
mgcoge3un arm arm926ejs km_arm
keymile kirkwood km_kirkwood:KM_MGCOGE3UN
kmcoge5un arm arm926ejs km_arm
keymile kirkwood km_kirkwood:KMCOGE5UN

Quoted 46 lines

-----Original Message-----
From: Valentin Longchamp [mailto:valentin.longchamp at keymile.com]
Sent: 07 June 2012 15:37
To: prafulla at mavell.com
Cc: Holger Brunck; u-boot at lists.denx.de; Valentin Longchamp; Gerlando Falauto; Prafulla Wadaskar
Subject: [PATCH 10/20] arm/km: cleanup km_kirkwood boards

From: Holger Brunck <[email protected]>

Remove config options from boards.cfg and simply add one switch per board and differ afterwards in km_kirkwood.h between the features. More boards are upcoming and therefore it's easier to have this at one place.

Signed-off-by Holger Brunck <[email protected]>

Signed-off-by Valentin Longchamp <[email protected]>

cc Gerlando Falauto <[email protected]>

cc Prafulla Wadaskar <[email protected]>

---
 boards.cfg                    |    4 ++--
 include/configs/km_kirkwood.h |    7 ++++++-
 2 files changed, 8 insertions(+), 3 deletions(-)

boards.cfg +0 -0

index 0fb8811..9569d1a 100644
@@ -138,8 +138,8 @@ enbw_cmc                     arm         arm926ejs

enbw_cmc enbw
calimain arm arm926ejs calimain
omicron davinci
pogo_e02 arm arm926ejs -
cloudengines kirkwood
dns325 arm arm926ejs -
d-link kirkwood
-km_kirkwood arm arm926ejs km_arm
keymile kirkwood km_kirkwood:KM_KIRKWOOD,KM_DISABLE_PCI
-km_kirkwood_pci arm arm926ejs km_arm
keymile kirkwood km_kirkwood:KM_KIRKWOOD_PCI,KM_FPGA_CONFIG
+km_kirkwood arm arm926ejs km_arm
keymile kirkwood km_kirkwood:KM_KIRKWOOD
+km_kirkwood_pci arm arm926ejs km_arm
keymile kirkwood km_kirkwood:KM_KIRKWOOD_PCI

Quoted 6 lines

kmnusa arm arm926ejs km_arm
keymile kirkwood km_kirkwood:KM_NUSA
mgcoge3un arm arm926ejs km_arm
keymile kirkwood km_kirkwood:KM_MGCOGE3UN
kmcoge5un arm arm926ejs km_arm
keymile kirkwood km_kirkwood:KMCOGE5UN

Can you maintain uniform naming here KMCODE5SUN should be KM_CODE5UN?