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ARM: OMAP2+: hwmod: Add new sysc_type3 into omap_hwmod required for am33xx

PATCH New Vaibhav Hiremath 4 participants 7 messages Feb 17, 2012 – Jun 28, 2012

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#0 lore raw

PATCH 1/1 ARM: OMAP2+: hwmod: Add new sysc_type3 into omap_hwmod required for am33xx

In case of AM33xx family of devices (like cpsw) have different sysc bit field offsets defined,

sysc_type3:

|  3     2  |  1    0  |
| STDBYMODE | IDLEMODE |

So introduce new sysc_type3 in omap_hwmod common data.

---
 arch/arm/mach-omap2/omap_hwmod_common_data.c |    9 +++++++++
 arch/arm/plat-omap/include/plat/omap_hwmod.h |   10 ++++++++++
 2 files changed, 19 insertions(+), 0 deletions(-)
arch/arm/mach-omap2/omap_hwmod_common_data.c +9 -0
index 51e5418..6dd922e 100644
@@ -49,6 +49,15 @@ struct omap_hwmod_sysc_fields omap_hwmod_sysc_type2 = {
 	.srst_shift	= SYSC_TYPE2_SOFTRESET_SHIFT,
 };
 
+/**
+ * struct omap_hwmod_sysc_type3 - TYPE3 sysconfig scheme.
+ * Used by some IPs on AM33xx
+ */
+struct omap_hwmod_sysc_fields omap_hwmod_sysc_type3 = {
+	.midle_shift	= SYSC_TYPE3_MIDLEMODE_SHIFT,
+	.sidle_shift	= SYSC_TYPE3_SIDLEMODE_SHIFT,
+};
+
 struct omap_dss_dispc_dev_attr omap2_3_dss_dispc_dev_attr = {
 	.manager_count		= 2,
 	.has_framedonetv_irq	= 0
arch/arm/plat-omap/include/plat/omap_hwmod.h +10 -0
index 9db27aa..3128364 100644
@@ -41,6 +41,7 @@ struct omap_device;
 
 extern struct omap_hwmod_sysc_fields omap_hwmod_sysc_type1;
 extern struct omap_hwmod_sysc_fields omap_hwmod_sysc_type2;
+extern struct omap_hwmod_sysc_fields omap_hwmod_sysc_type3;
 
 /*
  * OCP SYSCONFIG bit shifts/masks TYPE1. These are for IPs compliant
@@ -70,6 +71,15 @@ extern struct omap_hwmod_sysc_fields omap_hwmod_sysc_type2;
 #define SYSC_TYPE2_MIDLEMODE_SHIFT	4
 #define SYSC_TYPE2_MIDLEMODE_MASK	(0x3 << SYSC_TYPE2_MIDLEMODE_SHIFT)
 
+/*
+ * OCP SYSCONFIG bit shifts/masks TYPE3.
+ * This is applicable for some IPs present in AM33XX
+ */
+#define SYSC_TYPE3_SIDLEMODE_SHIFT	0
+#define SYSC_TYPE3_SIDLEMODE_MASK	(0x3 << SYSC_TYPE3_SIDLEMODE_SHIFT)
+#define SYSC_TYPE3_MIDLEMODE_SHIFT	2
+#define SYSC_TYPE3_MIDLEMODE_MASK	(0x3 << SYSC_TYPE3_MIDLEMODE_SHIFT)
+
 /* OCP SYSSTATUS bit shifts/masks */
 #define SYSS_RESETDONE_SHIFT		0
 #define SYSS_RESETDONE_MASK		(1 << SYSS_RESETDONE_SHIFT)
Signature · 1 line
1.7.0.4
#1 lore raw

PATCH 1/1 ARM: OMAP2+: hwmod: Add new sysc_type3 into omap_hwmod required for am33xx

Hi Vaibhav,

Quoted 2 lines · Vaibhav Hiremath

In case of AM33xx family of devices (like cpsw) have different sysc bit field offsets defined,

It is really used by several IPs, or it is just an unique exception?

For an exception, you can just define the omap_hwmod_sysc_fields for that IP.
This is what SmartReflex is using for example.

Regards,
Benoit

Quoted 61 lines

sysc_type3:

|  3     2  |  1    0  |
| STDBYMODE | IDLEMODE |

So introduce new sysc_type3 in omap_hwmod common data.

---
  arch/arm/mach-omap2/omap_hwmod_common_data.c |    9 +++++++++
  arch/arm/plat-omap/include/plat/omap_hwmod.h |   10 ++++++++++
  2 files changed, 19 insertions(+), 0 deletions(-)
arch/arm/mach-omap2/omap_hwmod_common_data.c +9 -0
index 51e5418..6dd922e 100644
@@ -49,6 +49,15 @@ struct omap_hwmod_sysc_fields omap_hwmod_sysc_type2 = {
  	.srst_shift	= SYSC_TYPE2_SOFTRESET_SHIFT,
  };
 
+/**
+ * struct omap_hwmod_sysc_type3 - TYPE3 sysconfig scheme.
+ * Used by some IPs on AM33xx
+ */
+struct omap_hwmod_sysc_fields omap_hwmod_sysc_type3 = {
+	.midle_shift	= SYSC_TYPE3_MIDLEMODE_SHIFT,
+	.sidle_shift	= SYSC_TYPE3_SIDLEMODE_SHIFT,
+};
+
  struct omap_dss_dispc_dev_attr omap2_3_dss_dispc_dev_attr = {
  	.manager_count		= 2,
  	.has_framedonetv_irq	= 0
arch/arm/plat-omap/include/plat/omap_hwmod.h +10 -0
index 9db27aa..3128364 100644
@@ -41,6 +41,7 @@ struct omap_device;
 
  extern struct omap_hwmod_sysc_fields omap_hwmod_sysc_type1;
  extern struct omap_hwmod_sysc_fields omap_hwmod_sysc_type2;
+extern struct omap_hwmod_sysc_fields omap_hwmod_sysc_type3;
 
  /*
   * OCP SYSCONFIG bit shifts/masks TYPE1. These are for IPs compliant
@@ -70,6 +71,15 @@ extern struct omap_hwmod_sysc_fields omap_hwmod_sysc_type2;
  #define SYSC_TYPE2_MIDLEMODE_SHIFT	4
  #define SYSC_TYPE2_MIDLEMODE_MASK	(0x3<<  SYSC_TYPE2_MIDLEMODE_SHIFT)
 
+/*
+ * OCP SYSCONFIG bit shifts/masks TYPE3.
+ * This is applicable for some IPs present in AM33XX
+ */
+#define SYSC_TYPE3_SIDLEMODE_SHIFT	0
+#define SYSC_TYPE3_SIDLEMODE_MASK	(0x3<<  SYSC_TYPE3_SIDLEMODE_SHIFT)
+#define SYSC_TYPE3_MIDLEMODE_SHIFT	2
+#define SYSC_TYPE3_MIDLEMODE_MASK	(0x3<<  SYSC_TYPE3_MIDLEMODE_SHIFT)
+
  /* OCP SYSSTATUS bit shifts/masks */
  #define SYSS_RESETDONE_SHIFT		0
  #define SYSS_RESETDONE_MASK		(1<<  SYSS_RESETDONE_SHIFT)
#2 lore raw

PATCH 1/1 ARM: OMAP2+: hwmod: Add new sysc_type3 into omap_hwmod required for am33xx

Hi Benoit,

Quoted 12 lines · Benoit

Hi Vaibhav,

Quoted 2 lines · Vaibhav Hiremath

In case of AM33xx family of devices (like cpsw) have different sysc bit field offsets defined,

It is really used by several IPs, or it is just an unique exception?

For an exception, you can just define the omap_hwmod_sysc_fields for that IP.
This is what SmartReflex is using for example.

I haven't really check TI81xx code but we might need to share these SYSC types with a few IPs in that family also. How can the sharing of the sysc data be handled?

Regards,
Vaibhav B.

#3 lore raw

PATCH 1/1 ARM: OMAP2+: hwmod: Add new sysc_type3 into omap_hwmod required for am33xx

Quoted 11 lines · Vaibhav

Hi Benoit,

Quoted 8 lines · Benoit

Hi Vaibhav,

Quoted 2 lines · Vaibhav Hiremath

In case of AM33xx family of devices (like cpsw) have different sysc bit field offsets defined,

It is really used by several IPs, or it is just an unique exception?

Quoted 8 lines
Quoted 4 lines

For an exception, you can just define the omap_hwmod_sysc_fields for that IP.
This is what SmartReflex is using for example.

I haven't really check TI81xx code but we might need to share these SYSC types with a few IPs in that family also. How can the sharing of the sysc data be handled?

Benoit,

Any comments on this patch?

Thanks,
Vaibhav

Quoted 3 lines

Regards,
Vaibhav B.

maintainer
#4 lore raw

PATCH 1/1 ARM: OMAP2+: hwmod: Add new sysc_type3 into omap_hwmod required for am33xx

In reply to Vaibhav Hiremath
Quoted 11 lines · Vaibhav Hiremath

In case of AM33xx family of devices (like cpsw) have different sysc bit field offsets defined,

sysc_type3:

|  3     2  |  1    0  |
| STDBYMODE | IDLEMODE |

So introduce new sysc_type3 in omap_hwmod common data.

Thanks, queued for 3.5.

- Paul

#5 lore raw

PATCH 1/1 ARM: OMAP2+: hwmod: Add new sysc_type3 into omap_hwmod required for am33xx

Quoted 9 lines · Paul Walmsley
Quoted 7 lines · Vaibhav Hiremath

In case of AM33xx family of devices (like cpsw) have different sysc bit field offsets defined,

sysc_type3:

|  3     2  |  1    0  |
| STDBYMODE | IDLEMODE |
Quoted 7 lines
Quoted 4 lines

So introduce new sysc_type3 in omap_hwmod common data.

Thanks, queued for 3.5.

We missed this patch last time, can you pleas make sure to include it this time.

Thanks,
Vaibhav

#6 lore raw

PATCH 1/1 ARM: OMAP2+: hwmod: Add new sysc_type3 into omap_hwmod required for am33xx

Quoted 12 lines · Vaibhav
Quoted 11 lines · Paul Walmsley
Quoted 9 lines · Vaibhav Hiremath

In case of AM33xx family of devices (like cpsw) have different sysc bit field offsets defined,

sysc_type3:

|  3     2  |  1    0  |
| STDBYMODE | IDLEMODE |

So introduce new sysc_type3 in omap_hwmod common data.

Quoted 9 lines
Quoted 5 lines
Quoted 2 lines

Thanks, queued for 3.5.

We missed this patch last time, can you pleas make sure to include it this time.

Another patch which got missed from your last pull-request is,

ARM: OMAP3/4: omap_hwmod:Add rstst_off field to struct omap_hwmod_omap4_prcm

Can you please add it to your pull request?

Thanks,
Vaibhav