add gpmi support for imx6q

Add clocks for gpmi-nand.

Signed-off-by Huang Shijie <[email protected]>

---
 arch/arm/mach-imx/clk-imx6q.c |    8 +++++++-
 1 files changed, 7 insertions(+), 1 deletions(-)

arch/arm/mach-imx/clk-imx6q.c +2 -1

index 12d9040..a837528 100644
@@ -151,7 +151,7 @@ enum mx6q_clks {
 	esai, gpt_ipg, gpt_ipg_per, gpu2d_core, gpu3d_core, hdmi_iahb,
 	hdmi_isfr, i2c1, i2c2, i2c3, iim, enfc, ipu1, ipu1_di0, ipu1_di1, ipu2,
 	ipu2_di0, ldb_di0, ldb_di1, ipu2_di1, hsi_tx, mlb, mmdc_ch0_axi,
-	mmdc_ch1_axi, ocram, openvg_axi, pcie_axi, pwm1, pwm2, pwm3, pwm4,
+	mmdc_ch1_axi, ocram, openvg_axi, pcie_axi, pwm1, pwm2, pwm3, pwm4, per1_bch,
 	gpmi_bch_apb, gpmi_bch, gpmi_io, gpmi_apb, sata, sdma, spba, ssi1,
 	ssi2, ssi3, uart_ipg, uart_serial, usboh3, usdhc1, usdhc2, usdhc3,
 	usdhc4, vdo_axi, vpu_axi, cko1, pll1_sys, pll2_bus, pll3_usb_otg,

@@ -357,6 +357,7 @@ int __init mx6q_clocks_init(void)
 	clk[ocram]        = imx_clk_gate2("ocram",         "ahb",               base + 0x74, 28);
 	clk[openvg_axi]   = imx_clk_gate2("openvg_axi",    "axi",               base + 0x74, 30);
 	clk[pcie_axi]     = imx_clk_gate2("pcie_axi",      "pcie_axi_sel",      base + 0x78, 0);
+	clk[per1_bch]     = imx_clk_gate2("per1_bch",      "usdhc3",            base + 0x78, 12);
 	clk[pwm1]         = imx_clk_gate2("pwm1",          "ipg_per",           base + 0x78, 16);
 	clk[pwm2]         = imx_clk_gate2("pwm2",          "ipg_per",           base + 0x78, 18);
 	clk[pwm3]         = imx_clk_gate2("pwm3",          "ipg_per",           base + 0x78, 20);

arch/arm/mach-imx/clk-imx6q.c +0 -0

 	clk_register_clkdev(clk[uart_serial], "per", "2020000.serial");
 	clk_register_clkdev(clk[uart_ipg], "ipg", "2020000.serial");
 	clk_register_clkdev(clk[uart_serial], "per", "21e8000.serial");

Signature · 1 line

1.7.4.4

It's a little bit strange to me that this clock still gets NULL con_id while all other gpmi-nand clocks have proper con_id assigned.

Add the DT node for gpmi nand.
Add the pinmux support for gpmi nand.

The gpmi nand may conflicts with other modules, such as MMC. So we do not enable the gpmi nand for mx6q-arm2 board, just add the node for the board.

Acked-by Dong Aisheng <[email protected]>

Signed-off-by Huang Shijie <[email protected]>

The gpmi nand driver may needs several clocks(MX6Q needs five clocks).

In the old clock framework, all these clocks are chained together, all you need is to manipulate the first clock.

But the kernel uses the common clk framework now, which forces us to get the clocks one by one. When we use them, we have to enable them one by one too.

Signed-off-by Huang Shijie <[email protected]>

---
 arch/arm/boot/dts/imx6q-arm2.dts       |    2 +-
 drivers/mtd/nand/gpmi-nand/gpmi-lib.c  |   43 ++++++++++++++---
 drivers/mtd/nand/gpmi-nand/gpmi-nand.c |   82 ++++++++++++++++++++++++++++----
 drivers/mtd/nand/gpmi-nand/gpmi-nand.h |    3 +-
 4 files changed, 111 insertions(+), 19 deletions(-)

arch/arm/boot/dts/imx6q-arm2.dts +1 -1

index 14e72e2..027a2f8 100644
@@ -25,7 +25,7 @@
 		gpmi-nand at 00112000 {
 			pinctrl-names = "default";
 			pinctrl-0 = <&pinctrl_gpmi_nand_1>;
-			status = "disabled"; /* gpmi nand conflicts with SD */
+			status = "okay"; /* gpmi nand conflicts with SD */
 		};
 
 		aips-bus at 02100000 { /* AIPS2 */

drivers/mtd/nand/gpmi-nand/gpmi-lib.c +13 -0

index a1f4332..c3778c0 100644
@@ -124,12 +124,40 @@ error:
 	return -ETIMEDOUT;
 }
 
+static int __gpmi_enable_clk(struct gpmi_nand_data *this, bool v)
+{
+	struct clk *clk;
+	int ret;
+	int i;
+
+	for (i = 0; i < GPMI_CLK_MAX; i++) {
+		clk = this->resources.clock[i];
+		if (!clk)
+			break;
+
+		if (v) {
+			ret = clk_prepare_enable(clk);

drivers/mtd/nand/gpmi-nand/gpmi-lib.c +3 -0

+	return ret;
+}
+
 

Quoted 53 lines · Huang Shijie

The gpmi nand driver may needs several clocks(MX6Q needs five clocks).

In the old clock framework, all these clocks are chained together, all you need is to manipulate the first clock.

But the kernel uses the common clk framework now, which forces us to get the clocks one by one. When we use them, we have to enable them one by one too.

Signed-off-by Huang Shijie <[email protected]>

---
arch/arm/boot/dts/imx6q-arm2.dts | 2 +- drivers/mtd/nand/gpmi-nand/gpmi-lib.c | 43 ++++++++++++++--- drivers/mtd/nand/gpmi-nand/gpmi-nand.c | 82
++++++++++++++++++++++++++++----
drivers/mtd/nand/gpmi-nand/gpmi-nand.h | 3 +-

4 files changed, 111 insertions(+), 19 deletions(-)

arch/arm/boot/dts/imx6q-arm2.dts +1 -1

index 14e72e2..027a2f8 100644
@@ -25,7 +25,7 @@
 gpmi-nand at 00112000 {
 pinctrl-names = "default";
 pinctrl-0 = <&pinctrl_gpmi_nand_1>;
- status = "disabled"; /* gpmi nand conflicts with SD */
+ status = "okay"; /* gpmi nand conflicts with SD */
 };
 

aips-bus at 02100000 { /* AIPS2 */

drivers/mtd/nand/gpmi-nand/gpmi-lib.c +12 -0

index a1f4332..c3778c0 100644
@@ -124,12 +124,40 @@ error:
 return -ETIMEDOUT;
 }
 
+static int __gpmi_enable_clk(struct gpmi_nand_data *this, bool v)
+{
+ struct clk *clk;
+ int ret;
+ int i;
+
+ for (i = 0; i < GPMI_CLK_MAX; i++) {
+ clk = this->resources.clock[i];
+ if (!clk)
+ break;
+
+ if (v) {

drivers/mtd/nand/gpmi-nand/gpmi-lib.c error: · line 148

Quoted 10 lines

drivers/mtd/nand/gpmi-nand/gpmi-lib.c +10 -0

+ ret = clk_prepare_enable(clk);
+ if (ret)
+ goto err_clk;
+ } else {
+ clk_disable_unprepare(clk);
+ }
+ }
+ return 0;
+
+err_clk:

Doesn't this design introduce clk_enalbe/disable un-balance problems?

Suppose you successfully enabled 1st and 2nd clocks, and failed at the third clock, this function will return, then the caller function will check the return value and call

__gpmi_enable_clk(this, 0), in this function, it will unconditionally disable all five clocks.

Regards,
Hui.

drivers/mtd/nand/gpmi-nand/gpmi-lib.c error: · line 151

Quoted 3 lines

drivers/mtd/nand/gpmi-nand/gpmi-lib.c +3 -0

+ return ret;
+}
+

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