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clk: mxs: imx28: decrease the frequency of ref_io1 for SSP2 and SSP3

PATCH New Lauri Hintsala 4 participants 6 messages Jul 4, 2012 – Jul 5, 2012

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Arm i.MX and Layerscape Common clk
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Lauri Hintsala

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#0 lore raw

PATCH 1/1 clk: mxs: imx28: decrease the frequency of ref_io1 for SSP2 and SSP3

SSP0 and SSP1 use ref_io0 which has decreased frequency. Expand the frequency fix for ref_io1 to get SSP2 and SSP3 to work.

Signed-off-by Lauri Hintsala <[email protected]>
---
 drivers/clk/mxs/clk-imx28.c |    6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)
drivers/clk/mxs/clk-imx28.c +3 -3
index 2826a26..0097c3a 100644
@@ -112,11 +112,11 @@ static void __init clk_misc_init(void)
 
 	/*
 	 * 480 MHz seems too high to be ssp clock source directly,
-	 * so set frac0 to get a 288 MHz ref_io0.
+	 * so set frac0 to get a 288 MHz ref_io0 and ref_io1.
 	 */
 	val = readl_relaxed(FRAC0);
-	val &= ~(0x3f << BP_FRAC0_IO0FRAC);
-	val |= 30 << BP_FRAC0_IO0FRAC;
+	val &= ~((0x3f << BP_FRAC0_IO0FRAC) | (0x3f << BP_FRAC0_IO1FRAC));
+	val |= (30 << BP_FRAC0_IO0FRAC) | (30 << BP_FRAC0_IO1FRAC);
 	writel_relaxed(val, FRAC0);
 }
Signature · 1 line
1.7.9.5
#1 lore raw

PATCH 1/1 clk: mxs: imx28: decrease the frequency of ref_io1 for SSP2 and SSP3

Quoted 3 lines · Lauri Hintsala

SSP0 and SSP1 use ref_io0 which has decreased frequency. Expand the frequency fix for ref_io1 to get SSP2 and SSP3 to work.

The patch looks okay. Just to confirm that you are running SSP2&SSP3 into the same frequency problem that we had with SSP0&SSP1? I never got a board to verify that for SSP2&SSP3.

Regards,
Shawn

Quoted 27 lines
Signed-off-by Lauri Hintsala <[email protected]>
---
 drivers/clk/mxs/clk-imx28.c |    6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)
drivers/clk/mxs/clk-imx28.c +3 -3
index 2826a26..0097c3a 100644
@@ -112,11 +112,11 @@ static void __init clk_misc_init(void)
 
 	/*
 	 * 480 MHz seems too high to be ssp clock source directly,
-	 * so set frac0 to get a 288 MHz ref_io0.
+	 * so set frac0 to get a 288 MHz ref_io0 and ref_io1.
 	 */
 	val = readl_relaxed(FRAC0);
-	val &= ~(0x3f << BP_FRAC0_IO0FRAC);
-	val |= 30 << BP_FRAC0_IO0FRAC;
+	val &= ~((0x3f << BP_FRAC0_IO0FRAC) | (0x3f << BP_FRAC0_IO1FRAC));
+	val |= (30 << BP_FRAC0_IO0FRAC) | (30 << BP_FRAC0_IO1FRAC);
 	writel_relaxed(val, FRAC0);
 }
Signature · 1 line
1.7.9.5
author
#2 lore raw

PATCH 1/1 clk: mxs: imx28: decrease the frequency of ref_io1 for SSP2 and SSP3

Quoted 7 lines · Shawn Guo
Quoted 3 lines · Lauri Hintsala

SSP0 and SSP1 use ref_io0 which has decreased frequency. Expand the frequency fix for ref_io1 to get SSP2 and SSP3 to work.

The patch looks okay. Just to confirm that you are running SSP2&SSP3 into the same frequency problem that we had with SSP0&SSP1? I never got a board to verify that for SSP2&SSP3.

SDIO device connected to SSP2 is not detect without this change. I don't know what is the history of ref_io0 frequency change but the same change is needed for ref_io1 to get SSP2 to work on our imx28 based module.

Regards,
Lauri

#3 lore raw

PATCH 1/1 clk: mxs: imx28: decrease the frequency of ref_io1 for SSP2 and SSP3

In reply to Shawn Guo

Dear Shawn Guo,

Quoted 7 lines · Lauri Hintsala
Quoted 2 lines

SSP0 and SSP1 use ref_io0 which has decreased frequency. Expand the frequency fix for ref_io1 to get SSP2 and SSP3 to work.

The patch looks okay. Just to confirm that you are running SSP2&SSP3 into the same frequency problem that we had with SSP0&SSP1? I never got a board to verify that for SSP2&SSP3.

What problem is that? I've been running the SPI driver against two types of SPI flashes on SSP2 without trouble ...

Quoted 26 lines

Regards,
Shawn

Quoted 23 lines
Signed-off-by Lauri Hintsala <[email protected]>

---

 drivers/clk/mxs/clk-imx28.c |    6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)
drivers/clk/mxs/clk-imx28.c +1 -1
index 2826a26..0097c3a 100644
@@ -112,11 +112,11 @@ static void __init clk_misc_init(void)
 
 	/*
 
 	 * 480 MHz seems too high to be ssp clock source directly,
 
-	 * so set frac0 to get a 288 MHz ref_io0.
+	 * so set frac0 to get a 288 MHz ref_io0 and ref_io1.
 
 	 */
 
 	val = readl_relaxed(FRAC0);
Quoted 8 lines

drivers/clk/mxs/clk-imx28.c static void __init clk_misc_init(void)

Quoted 8 lines
drivers/clk/mxs/clk-imx28.c +2 -2
-	val &= ~(0x3f << BP_FRAC0_IO0FRAC);
-	val |= 30 << BP_FRAC0_IO0FRAC;
+	val &= ~((0x3f << BP_FRAC0_IO0FRAC) | (0x3f << BP_FRAC0_IO1FRAC));
+	val |= (30 << BP_FRAC0_IO0FRAC) | (30 << BP_FRAC0_IO1FRAC);
 
 	writel_relaxed(val, FRAC0);
 
 }

Best regards,
Marek Vasut

Applied
#5 lore raw

PATCH 1/1 clk: mxs: imx28: decrease the frequency of ref_io1 for SSP2 and SSP3

In reply to Lauri Hintsala
Quoted 4 lines · Lauri Hintsala

SSP0 and SSP1 use ref_io0 which has decreased frequency. Expand the frequency fix for ref_io1 to get SSP2 and SSP3 to work.

Signed-off-by Lauri Hintsala <[email protected]>

Applied, thanks.

Quoted 26 lines
---
 drivers/clk/mxs/clk-imx28.c |    6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)
drivers/clk/mxs/clk-imx28.c +3 -3
index 2826a26..0097c3a 100644
@@ -112,11 +112,11 @@ static void __init clk_misc_init(void)
 
 	/*
 	 * 480 MHz seems too high to be ssp clock source directly,
-	 * so set frac0 to get a 288 MHz ref_io0.
+	 * so set frac0 to get a 288 MHz ref_io0 and ref_io1.
 	 */
 	val = readl_relaxed(FRAC0);
-	val &= ~(0x3f << BP_FRAC0_IO0FRAC);
-	val |= 30 << BP_FRAC0_IO0FRAC;
+	val &= ~((0x3f << BP_FRAC0_IO0FRAC) | (0x3f << BP_FRAC0_IO1FRAC));
+	val |= (30 << BP_FRAC0_IO0FRAC) | (30 << BP_FRAC0_IO1FRAC);
 	writel_relaxed(val, FRAC0);
 }
Signature · 1 line
1.7.9.5