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cm4008: set gd->ram_size in dram_init

PATCH Superseded Yann Vernier 2 participants 4 messages Jul 4, 2012 – Jul 5, 2012

Subsystems (2)
Arm (32-bit) Arm/actions semi architecture

v1 of 2 Superseded Latest is v2 →

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Yann Vernier

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#0 lore raw

PATCH 1/3 cm4008: set gd->ram_size in dram_init

Leave dram_init_banksize to set up the bank info data. ram_size was previously uninitialized.

Signed-off-by Yann Vernier <[email protected]>
---
 board/cm4008/cm4008.c |    3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)
board/cm4008/cm4008.c +1 -2
index ed493a8..557cd8e 100644
@@ -97,8 +97,7 @@ int board_init (void)
 
 int dram_init (void)
 {
-	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
-	gd->bd->bi_dram[0].size  = PHYS_SDRAM_1_SIZE;
+	gd->ram_size  = PHYS_SDRAM_1_SIZE;
 
 	return (0);
 }
Signature · 1 line
1.7.10
#1 lore raw

PATCH 1/3 cm4008: set gd->ram_size in dram_init

Quoted 14 lines · Yann Vernier

Leave dram_init_banksize to set up the bank info data. ram_size was previously uninitialized.

Signed-off-by Yann Vernier <[email protected]>
---
 board/cm4008/cm4008.c |    3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)
board/cm4008/cm4008.c +0 -0
index ed493a8..557cd8e 100644

board/cm4008/cm4008.c int board_init (void) · line 103

Quoted 9 lines
board/cm4008/cm4008.c +1 -2
@@ -97,8 +97,7 @@ int board_init (void)
 
 int dram_init (void)
 {
-	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
-	gd->bd->bi_dram[0].size  = PHYS_SDRAM_1_SIZE;
+	gd->ram_size  = PHYS_SDRAM_1_SIZE;
 
 	return (0);
 }

The dram_init should look like this nowadays:

---8<---
int dram_init (void)

{
        /* dram_init must store complete ramsize in gd->ram_size */
        gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
                        CONFIG_SYS_SDRAM_SIZE);
        return 0;
}

--->8---

PHYS_SDRAM_1_SIZE is also a remnant from older days, please switch to CONFIG_SYS_SDRAM_SIZE. The get_ram_size() should check how many ram is really accesable (think of a board which may have more options for RAM, just insert the biggest possible option to CONFIG_SYS_SDRAM_SIZE).

Best regards

Andreas Bie?mann

author
#2 lore raw

PATCH v2 1/1 arm: cm4008, cm41xx: set gd->ram_size in dram_init

Leave dram_init_banksize to set up the bank info data. ram_size was previously uninitialized. Also, generalize lowlevel assembly to support more RAM options.

Signed-off-by Yann Vernier <[email protected]>

---
Changes for v2:
- Update to use CONFIG_SYS_SDRAM_ constants
- Update cm41xx also
- Map SDRAM to match configuration

---
 arch/arm/cpu/arm920t/ks8695/lowlevel_init.S |    8 +++-----
 board/cm4008/cm4008.c                       |    5 +++--
 board/cm41xx/cm41xx.c                       |    5 +++--
 include/configs/cm4008.h                    |    5 ++---
 include/configs/cm41xx.h                    |    5 ++---
 5 files changed, 13 insertions(+), 15 deletions(-)
arch/arm/cpu/arm920t/ks8695/lowlevel_init.S +3 -5
index e9f1227..df13de6 100644
@@ -131,11 +131,9 @@ highflash:
 	 * before relocating, we have to setup RAM timing
 	 */
 	ldr	r1, =(KS8695_IO_BASE+KS8695_SDRAM_CTRL0)
-#if (PHYS_SDRAM_1_SIZE == 0x02000000)
-	ldr	r2, =0x7fc0000e		/* 32MB */
-#else
-	ldr	r2, =0x3fc0000e		/* 16MB */
-#endif
+	/* 8 column address bits, 4 banks, 32 bits data width */
+	ldr	r2, =((CONFIG_SYS_SDRAM_BASE+CONFIG_SYS_SDRAM_SIZE-0x10000)<<(22-16) | \
+		      (CONFIG_SYS_SDRAM_BASE>>(16-12) | 0x00e))
 	str	r2, [r1]		/* configure sdram bank0 setup */
 	ldr	r1, =(KS8695_IO_BASE+KS8695_SDRAM_CTRL1)
 	mov	r2, #0
board/cm4008/cm4008.c +3 -2
index ed493a8..6c0da9a 100644
@@ -97,8 +97,9 @@ int board_init (void)
 
 int dram_init (void)
 {
-	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
-	gd->bd->bi_dram[0].size  = PHYS_SDRAM_1_SIZE;
+	/* dram_init must store complete ramsize in gd->ram_size */
+	gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
+			CONFIG_SYS_SDRAM_SIZE);
 
 	return (0);
 }
board/cm41xx/cm41xx.c +3 -2
index d9dff4e..6aef617 100644
@@ -97,8 +97,9 @@ int board_init (void)
 
 int dram_init (void)
 {
-	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
-	gd->bd->bi_dram[0].size  = PHYS_SDRAM_1_SIZE;
+	/* dram_init must store complete ramsize in gd->ram_size */
+	gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
+			CONFIG_SYS_SDRAM_SIZE);
 
 	return (0);
 }
include/configs/cm4008.h +2 -3
index 408e918..58b0f4b 100644
@@ -110,9 +110,8 @@
  * Physical Memory Map
  */
 #define CONFIG_NR_DRAM_BANKS	1	   /* we have 1 bank of DRAM */
-#define PHYS_SDRAM_1		0x00000000 /* SDRAM Bank #1 */
-#define PHYS_SDRAM_1_SIZE	0x01000000 /* 16 MB */
-#define CONFIG_SYS_SDRAM_BASE	PHYS_SDRAM_1
+#define CONFIG_SYS_SDRAM_BASE	0x00000000 /* SDRAM Bank #1 */
+#define CONFIG_SYS_SDRAM_SIZE	0x01000000 /* 16 MB */
 
 #define CONFIG_SYS_INIT_SP_ADDR	0x00020000 /* lowest 128k of RAM */
include/configs/cm41xx.h +2 -3
index d85a600..d29040c 100644
@@ -110,9 +110,8 @@
  * Physical Memory Map
  */
 #define CONFIG_NR_DRAM_BANKS	1	   /* we have 1 bank of DRAM */
-#define PHYS_SDRAM_1		0x00000000 /* SDRAM Bank #1 */
-#define PHYS_SDRAM_1_SIZE	0x02000000 /* 32 MB */
-#define CONFIG_SYS_SDRAM_BASE	PHYS_SDRAM_1
+#define CONFIG_SYS_SDRAM_BASE	0x00000000 /* SDRAM Bank #1 */
+#define CONFIG_SYS_SDRAM_SIZE	0x02000000 /* 32 MB */
 
 #define CONFIG_SYS_INIT_SP_ADDR	0x00020000 /* lowest 128k of RAM */
Signature · 1 line
1.7.10
#3 lore raw

PATCH v2 1/1 arm: cm4008, cm41xx: set gd->ram_size in dram_init

Quoted 24 lines · Yann Vernier

Leave dram_init_banksize to set up the bank info data. ram_size was previously uninitialized. Also, generalize lowlevel assembly to support more RAM options.

Signed-off-by Yann Vernier <[email protected]>

---
Changes for v2:
- Update to use CONFIG_SYS_SDRAM_ constants
- Update cm41xx also
- Map SDRAM to match configuration

---
 arch/arm/cpu/arm920t/ks8695/lowlevel_init.S |    8 +++-----
 board/cm4008/cm4008.c                       |    5 +++--
 board/cm41xx/cm41xx.c                       |    5 +++--
 include/configs/cm4008.h                    |    5 ++---
 include/configs/cm41xx.h                    |    5 ++---
 5 files changed, 13 insertions(+), 15 deletions(-)
arch/arm/cpu/arm920t/ks8695/lowlevel_init.S +0 -0
index e9f1227..df13de6 100644
@@ -131,11 +131,9 @@ highflash:
 	 * before relocating, we have to setup RAM timing

arch/arm/cpu/arm920t/ks8695/lowlevel_init.S highflash: · line 136

Quoted 10 lines
arch/arm/cpu/arm920t/ks8695/lowlevel_init.S +3 -5
 	 */
 	ldr	r1, =(KS8695_IO_BASE+KS8695_SDRAM_CTRL0)
-#if (PHYS_SDRAM_1_SIZE == 0x02000000)
-	ldr	r2, =0x7fc0000e		/* 32MB */
-#else
-	ldr	r2, =0x3fc0000e		/* 16MB */
-#endif
+	/* 8 column address bits, 4 banks, 32 bits data width */
+	ldr	r2, =((CONFIG_SYS_SDRAM_BASE+CONFIG_SYS_SDRAM_SIZE-0x10000)<<(22-16) | \
+		      (CONFIG_SYS_SDRAM_BASE>>(16-12) | 0x00e))

ugh ... magic. Will it work for every possible setting?
How about one setting CONFIG_SYS_SDRAM_BASE != 0x0? I the base address related to register content in any way?

Would be great to have a little documentation here why it is shifted that way, unfortunately I can not find a KS8695 spec in the net. Don't get me wrong it is ok to do so. I think it is way better than hard coding the values like before but would be great to understand why it is done that way.

Best regards

Andreas Bie?mann