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clk: clk-imx7d: fix ahb clk definition

PATCH New Dong Aisheng 3 participants 7 messages Apr 10, 2017 – Apr 19, 2017

Subsystems (3)
Arm i.MX and Layerscape Common clk NXP i.MX clock drivers
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Dong Aisheng

author
#0 lore raw

PATCH 1/2 clk: clk-imx7d: fix ahb clk definition

MX7D ahb clk actually has no LPCG gate, current LPCG offset 0x4200 used actually is for adc, not ahb. After fix, correct ocram_s_clk parent accordingly as well.

Cc Shawn Guo <[email protected]>
Cc Stefan Agner <[email protected]>
Cc Fabio Estevam <[email protected]>
Signed-off-by Dong Aisheng <[email protected]>
---
 drivers/clk/imx/clk-imx7d.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)
drivers/clk/imx/clk-imx7d.c +2 -3
index ae1d31b..ad04483 100644
@@ -725,7 +725,7 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node)
 	clks[IMX7D_DISP_AXI_ROOT_DIV] = imx_clk_divider2("disp_axi_post_div", "disp_axi_pre_div", base + 0x8880, 0, 6);
 	clks[IMX7D_ENET_AXI_ROOT_DIV] = imx_clk_divider2("enet_axi_post_div", "enet_axi_pre_div", base + 0x8900, 0, 6);
 	clks[IMX7D_NAND_USDHC_BUS_ROOT_DIV] = imx_clk_divider2("nand_usdhc_post_div", "nand_usdhc_pre_div", base + 0x8980, 0, 6);
-	clks[IMX7D_AHB_CHANNEL_ROOT_DIV] = imx_clk_divider2("ahb_post_div", "ahb_pre_div", base + 0x9000, 0, 6);
+	clks[IMX7D_AHB_CHANNEL_ROOT_DIV] = imx_clk_divider2("ahb_root_clk", "ahb_pre_div", base + 0x9000, 0, 6);
 	clks[IMX7D_DRAM_ROOT_DIV] = imx_clk_divider2("dram_post_div", "dram_cg", base + 0x9880, 0, 3);
 	clks[IMX7D_DRAM_PHYM_ALT_ROOT_DIV] = imx_clk_divider2("dram_phym_alt_post_div", "dram_phym_alt_pre_div", base + 0xa000, 0, 3);
 	clks[IMX7D_DRAM_ALT_ROOT_DIV] = imx_clk_divider2("dram_alt_post_div", "dram_alt_pre_div", base + 0xa080, 0, 3);

@@ -796,9 +796,8 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node)
 	clks[IMX7D_DISP_AXI_ROOT_CLK] = imx_clk_gate4("disp_axi_root_clk", "disp_axi_post_div", base + 0x4050, 0);
 	clks[IMX7D_ENET_AXI_ROOT_CLK] = imx_clk_gate4("enet_axi_root_clk", "enet_axi_post_div", base + 0x4060, 0);
 	clks[IMX7D_OCRAM_CLK] = imx_clk_gate4("ocram_clk", "axi_post_div", base + 0x4110, 0);
-	clks[IMX7D_OCRAM_S_CLK] = imx_clk_gate4("ocram_s_clk", "ahb_post_div", base + 0x4120, 0);
+	clks[IMX7D_OCRAM_S_CLK] = imx_clk_gate4("ocram_s_clk", "ahb_root_clk", base + 0x4120, 0);
 	clks[IMX7D_NAND_USDHC_BUS_ROOT_CLK] = imx_clk_gate4("nand_usdhc_root_clk", "nand_usdhc_post_div", base + 0x4130, 0);
-	clks[IMX7D_AHB_CHANNEL_ROOT_CLK] = imx_clk_gate4("ahb_root_clk", "ahb_post_div", base + 0x4200, 0);
 	clks[IMX7D_DRAM_ROOT_CLK] = imx_clk_gate4("dram_root_clk", "dram_post_div", base + 0x4130, 0);
 	clks[IMX7D_DRAM_PHYM_ROOT_CLK] = imx_clk_gate4("dram_phym_root_clk", "dram_phym_cg", base + 0x4130, 0);
 	clks[IMX7D_DRAM_PHYM_ALT_ROOT_CLK] = imx_clk_gate4("dram_phym_alt_root_clk", "dram_phym_alt_post_div", base + 0x4130, 0);
Signature · 1 line
2.7.4
#1 lore raw

PATCH 1/2 clk: clk-imx7d: fix ahb clk definition

Quoted 3 lines · Dong Aisheng

MX7D ahb clk actually has no LPCG gate, current LPCG offset 0x4200 used actually is for adc, not ahb. After fix, correct ocram_s_clk parent accordingly as well.

Reviewed-by Stefan Agner <[email protected]>
Tested-by Stefan Agner <[email protected]>
Quoted 60 lines
Cc Shawn Guo <[email protected]>
Cc Stefan Agner <[email protected]>
Cc Fabio Estevam <[email protected]>
Signed-off-by Dong Aisheng <[email protected]>
---
 drivers/clk/imx/clk-imx7d.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)
drivers/clk/imx/clk-imx7d.c +0 -0
index ae1d31b..ad04483 100644
@@ -725,7 +725,7 @@ static void __init imx7d_clocks_init(struct
 device_node *ccm_node)
 	clks[IMX7D_DISP_AXI_ROOT_DIV] =

imx_clk_divider2("disp_axi_post_div", "disp_axi_pre_div", base + 0x8880, 0, 6);
clks[IMX7D_ENET_AXI_ROOT_DIV] =
imx_clk_divider2("enet_axi_post_div", "enet_axi_pre_div", base + 0x8900, 0, 6);
clks[IMX7D_NAND_USDHC_BUS_ROOT_DIV] =
imx_clk_divider2("nand_usdhc_post_div", "nand_usdhc_pre_div", base + 0x8980, 0, 6);

drivers/clk/imx/clk-imx7d.c +0 -1
-	clks[IMX7D_AHB_CHANNEL_ROOT_DIV] = imx_clk_divider2("ahb_post_div",

"ahb_pre_div", base + 0x9000, 0, 6);

drivers/clk/imx/clk-imx7d.c +1 -0
+	clks[IMX7D_AHB_CHANNEL_ROOT_DIV] = imx_clk_divider2("ahb_root_clk",

"ahb_pre_div", base + 0x9000, 0, 6);
clks[IMX7D_DRAM_ROOT_DIV] = imx_clk_divider2("dram_post_div",
"dram_cg", base + 0x9880, 0, 3);
clks[IMX7D_DRAM_PHYM_ALT_ROOT_DIV] =
imx_clk_divider2("dram_phym_alt_post_div", "dram_phym_alt_pre_div", base + 0xa000, 0, 3);
clks[IMX7D_DRAM_ALT_ROOT_DIV] =
imx_clk_divider2("dram_alt_post_div", "dram_alt_pre_div", base + 0xa080, 0, 3);

drivers/clk/imx/clk-imx7d.c +1 -1
@@ -796,9 +796,8 @@ static void __init imx7d_clocks_init(struct
 device_node *ccm_node)
 	clks[IMX7D_DISP_AXI_ROOT_CLK] = imx_clk_gate4("disp_axi_root_clk",
 "disp_axi_post_div", base + 0x4050, 0);
 	clks[IMX7D_ENET_AXI_ROOT_CLK] = imx_clk_gate4("enet_axi_root_clk",
 "enet_axi_post_div", base + 0x4060, 0);
 	clks[IMX7D_OCRAM_CLK] = imx_clk_gate4("ocram_clk", "axi_post_div",
 base + 0x4110, 0);
-	clks[IMX7D_OCRAM_S_CLK] = imx_clk_gate4("ocram_s_clk",
 "ahb_post_div", base + 0x4120, 0);
+	clks[IMX7D_OCRAM_S_CLK] = imx_clk_gate4("ocram_s_clk",

"ahb_root_clk", base + 0x4120, 0);
clks[IMX7D_NAND_USDHC_BUS_ROOT_CLK] =
imx_clk_gate4("nand_usdhc_root_clk", "nand_usdhc_post_div", base + 0x4130, 0);

drivers/clk/imx/clk-imx7d.c +0 -1
-	clks[IMX7D_AHB_CHANNEL_ROOT_CLK] = imx_clk_gate4("ahb_root_clk",

"ahb_post_div", base + 0x4200, 0);
clks[IMX7D_DRAM_ROOT_CLK] = imx_clk_gate4("dram_root_clk",
"dram_post_div", base + 0x4130, 0);
clks[IMX7D_DRAM_PHYM_ROOT_CLK] = imx_clk_gate4("dram_phym_root_clk",
"dram_phym_cg", base + 0x4130, 0);
clks[IMX7D_DRAM_PHYM_ALT_ROOT_CLK] =
imx_clk_gate4("dram_phym_alt_root_clk", "dram_phym_alt_post_div", base
+ 0x4130, 0);

author
#2 lore raw

PATCH 2/2 clk: imx7d: add the missing ipg_root_clk

In reply to Dong Aisheng

Add the missing ipg_root_clk which actually is already used by many orphan clks in current tree.

Cc Shawn Guo <[email protected]>
Cc Stefan Agner <[email protected]>
Cc Fabio Estevam <[email protected]>
Signed-off-by Dong Aisheng <[email protected]>
---
 drivers/clk/imx/clk-imx7d.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)
drivers/clk/imx/clk-imx7d.c +2 -1
index ad04483..5620551 100644
@@ -386,7 +386,7 @@ static int const clks_init_on[] __initconst = {
 	IMX7D_PLL_SYS_MAIN_480M_CLK, IMX7D_NAND_USDHC_BUS_ROOT_CLK,
 	IMX7D_DRAM_PHYM_ROOT_CLK, IMX7D_DRAM_ROOT_CLK,
 	IMX7D_DRAM_PHYM_ALT_ROOT_CLK, IMX7D_DRAM_ALT_ROOT_CLK,
-	IMX7D_AHB_CHANNEL_ROOT_CLK,
+	IMX7D_AHB_CHANNEL_ROOT_CLK, IMX7D_IPG_ROOT_CLK,
 };
 
 static struct clk_onecell_data clk_data;

@@ -726,6 +726,7 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node)
 	clks[IMX7D_ENET_AXI_ROOT_DIV] = imx_clk_divider2("enet_axi_post_div", "enet_axi_pre_div", base + 0x8900, 0, 6);
 	clks[IMX7D_NAND_USDHC_BUS_ROOT_DIV] = imx_clk_divider2("nand_usdhc_post_div", "nand_usdhc_pre_div", base + 0x8980, 0, 6);
 	clks[IMX7D_AHB_CHANNEL_ROOT_DIV] = imx_clk_divider2("ahb_root_clk", "ahb_pre_div", base + 0x9000, 0, 6);
+	clks[IMX7D_IPG_ROOT_CLK] = imx_clk_divider2("ipg_root_clk", "ahb_root_clk", base + 0x9080, 0, 2);
 	clks[IMX7D_DRAM_ROOT_DIV] = imx_clk_divider2("dram_post_div", "dram_cg", base + 0x9880, 0, 3);
 	clks[IMX7D_DRAM_PHYM_ALT_ROOT_DIV] = imx_clk_divider2("dram_phym_alt_post_div", "dram_phym_alt_pre_div", base + 0xa000, 0, 3);
 	clks[IMX7D_DRAM_ALT_ROOT_DIV] = imx_clk_divider2("dram_alt_post_div", "dram_alt_pre_div", base + 0xa080, 0, 3);
Signature · 1 line
2.7.4
#3 lore raw

PATCH 2/2 clk: imx7d: add the missing ipg_root_clk

Quoted 2 lines · Dong Aisheng

Add the missing ipg_root_clk which actually is already used by many orphan clks in current tree.

Reviewed-by Stefan Agner <[email protected]>
Tested-by Stefan Agner <[email protected]>

--
Stefan

Quoted 42 lines
Cc Shawn Guo <[email protected]>
Cc Stefan Agner <[email protected]>
Cc Fabio Estevam <[email protected]>
Signed-off-by Dong Aisheng <[email protected]>
---
 drivers/clk/imx/clk-imx7d.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)
drivers/clk/imx/clk-imx7d.c +1 -1
index ad04483..5620551 100644
@@ -386,7 +386,7 @@ static int const clks_init_on[] __initconst = {
 	IMX7D_PLL_SYS_MAIN_480M_CLK, IMX7D_NAND_USDHC_BUS_ROOT_CLK,
 	IMX7D_DRAM_PHYM_ROOT_CLK, IMX7D_DRAM_ROOT_CLK,
 	IMX7D_DRAM_PHYM_ALT_ROOT_CLK, IMX7D_DRAM_ALT_ROOT_CLK,
-	IMX7D_AHB_CHANNEL_ROOT_CLK,
+	IMX7D_AHB_CHANNEL_ROOT_CLK, IMX7D_IPG_ROOT_CLK,
 };
 
 static struct clk_onecell_data clk_data;

@@ -726,6 +726,7 @@ static void __init imx7d_clocks_init(struct
 device_node *ccm_node)
 	clks[IMX7D_ENET_AXI_ROOT_DIV] =

imx_clk_divider2("enet_axi_post_div", "enet_axi_pre_div", base + 0x8900, 0, 6);
clks[IMX7D_NAND_USDHC_BUS_ROOT_DIV] =
imx_clk_divider2("nand_usdhc_post_div", "nand_usdhc_pre_div", base + 0x8980, 0, 6);
clks[IMX7D_AHB_CHANNEL_ROOT_DIV] = imx_clk_divider2("ahb_root_clk",
"ahb_pre_div", base + 0x9000, 0, 6);

drivers/clk/imx/clk-imx7d.c +1 -0
+	clks[IMX7D_IPG_ROOT_CLK] = imx_clk_divider2("ipg_root_clk",

"ahb_root_clk", base + 0x9080, 0, 2);
clks[IMX7D_DRAM_ROOT_DIV] = imx_clk_divider2("dram_post_div",
"dram_cg", base + 0x9880, 0, 3);
clks[IMX7D_DRAM_PHYM_ALT_ROOT_DIV] =
imx_clk_divider2("dram_phym_alt_post_div", "dram_phym_alt_pre_div", base + 0xa000, 0, 3);
clks[IMX7D_DRAM_ALT_ROOT_DIV] =
imx_clk_divider2("dram_alt_post_div", "dram_alt_pre_div", base + 0xa080, 0, 3);

Applied
#4 lore raw

PATCH 2/2 clk: imx7d: add the missing ipg_root_clk

In reply to Dong Aisheng
Quoted 8 lines · Dong Aisheng

Add the missing ipg_root_clk which actually is already used by many orphan clks in current tree.

Cc Shawn Guo <[email protected]>
Cc Stefan Agner <[email protected]>
Cc Fabio Estevam <[email protected]>
Signed-off-by Dong Aisheng <[email protected]>

---

Applied to clk-next

Signature · 2 lines
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
#5 lore raw

PATCH 1/2 clk: clk-imx7d: fix ahb clk definition

In reply to Dong Aisheng

Stephen, Shawn,

Will this patchset make it into 4.12? It would be good, because this device tree change:
https://patchwork.kernel.org/patch/9652841/

...depends on patch 2. Assuming the device tree change will go into 4.13, if this makes into 4.12 we do not have to deal with the dependency in the 4.13 merge window...

--
Stefan

Quoted 63 lines · Dong Aisheng

MX7D ahb clk actually has no LPCG gate, current LPCG offset 0x4200 used actually is for adc, not ahb. After fix, correct ocram_s_clk parent accordingly as well.

Cc Shawn Guo <[email protected]>
Cc Stefan Agner <[email protected]>
Cc Fabio Estevam <[email protected]>
Signed-off-by Dong Aisheng <[email protected]>
---
 drivers/clk/imx/clk-imx7d.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)
drivers/clk/imx/clk-imx7d.c +0 -0
index ae1d31b..ad04483 100644
@@ -725,7 +725,7 @@ static void __init imx7d_clocks_init(struct
 device_node *ccm_node)
 	clks[IMX7D_DISP_AXI_ROOT_DIV] =

imx_clk_divider2("disp_axi_post_div", "disp_axi_pre_div", base + 0x8880, 0, 6);
clks[IMX7D_ENET_AXI_ROOT_DIV] =
imx_clk_divider2("enet_axi_post_div", "enet_axi_pre_div", base + 0x8900, 0, 6);
clks[IMX7D_NAND_USDHC_BUS_ROOT_DIV] =
imx_clk_divider2("nand_usdhc_post_div", "nand_usdhc_pre_div", base + 0x8980, 0, 6);

drivers/clk/imx/clk-imx7d.c +0 -1
-	clks[IMX7D_AHB_CHANNEL_ROOT_DIV] = imx_clk_divider2("ahb_post_div",

"ahb_pre_div", base + 0x9000, 0, 6);

drivers/clk/imx/clk-imx7d.c +1 -0
+	clks[IMX7D_AHB_CHANNEL_ROOT_DIV] = imx_clk_divider2("ahb_root_clk",

"ahb_pre_div", base + 0x9000, 0, 6);
clks[IMX7D_DRAM_ROOT_DIV] = imx_clk_divider2("dram_post_div",
"dram_cg", base + 0x9880, 0, 3);
clks[IMX7D_DRAM_PHYM_ALT_ROOT_DIV] =
imx_clk_divider2("dram_phym_alt_post_div", "dram_phym_alt_pre_div", base + 0xa000, 0, 3);
clks[IMX7D_DRAM_ALT_ROOT_DIV] =
imx_clk_divider2("dram_alt_post_div", "dram_alt_pre_div", base + 0xa080, 0, 3);

drivers/clk/imx/clk-imx7d.c +1 -1
@@ -796,9 +796,8 @@ static void __init imx7d_clocks_init(struct
 device_node *ccm_node)
 	clks[IMX7D_DISP_AXI_ROOT_CLK] = imx_clk_gate4("disp_axi_root_clk",
 "disp_axi_post_div", base + 0x4050, 0);
 	clks[IMX7D_ENET_AXI_ROOT_CLK] = imx_clk_gate4("enet_axi_root_clk",
 "enet_axi_post_div", base + 0x4060, 0);
 	clks[IMX7D_OCRAM_CLK] = imx_clk_gate4("ocram_clk", "axi_post_div",
 base + 0x4110, 0);
-	clks[IMX7D_OCRAM_S_CLK] = imx_clk_gate4("ocram_s_clk",
 "ahb_post_div", base + 0x4120, 0);
+	clks[IMX7D_OCRAM_S_CLK] = imx_clk_gate4("ocram_s_clk",

"ahb_root_clk", base + 0x4120, 0);
clks[IMX7D_NAND_USDHC_BUS_ROOT_CLK] =
imx_clk_gate4("nand_usdhc_root_clk", "nand_usdhc_post_div", base + 0x4130, 0);

drivers/clk/imx/clk-imx7d.c +0 -1
-	clks[IMX7D_AHB_CHANNEL_ROOT_CLK] = imx_clk_gate4("ahb_root_clk",

"ahb_post_div", base + 0x4200, 0);
clks[IMX7D_DRAM_ROOT_CLK] = imx_clk_gate4("dram_root_clk",
"dram_post_div", base + 0x4130, 0);
clks[IMX7D_DRAM_PHYM_ROOT_CLK] = imx_clk_gate4("dram_phym_root_clk",
"dram_phym_cg", base + 0x4130, 0);
clks[IMX7D_DRAM_PHYM_ALT_ROOT_CLK] =
imx_clk_gate4("dram_phym_alt_root_clk", "dram_phym_alt_post_div", base
+ 0x4130, 0);

Applied
#6 lore raw

PATCH 1/2 clk: clk-imx7d: fix ahb clk definition

In reply to Dong Aisheng
Quoted 9 lines · Dong Aisheng

MX7D ahb clk actually has no LPCG gate, current LPCG offset 0x4200 used actually is for adc, not ahb. After fix, correct ocram_s_clk parent accordingly as well.

Cc Shawn Guo <[email protected]>
Cc Stefan Agner <[email protected]>
Cc Fabio Estevam <[email protected]>
Signed-off-by Dong Aisheng <[email protected]>

---

Applied to clk-next

Signature · 2 lines
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project