Add support for QCOM GDSCs

From: Stephen Boyd <[email protected]>

GDSCs (Global Distributed Switch Controllers) are responsible for safely collapsing and restoring power to peripherals in the SoC. These are best modelled as power domains using genpd and given the registers are scattered throughout the clock controller register space, its best to have the support added through the clock driver.

Signed-off-by Stephen Boyd <[email protected]>

Signed-off-by Rajendra Nayak <[email protected]>

---
 drivers/clk/qcom/Kconfig  |   5 ++
 drivers/clk/qcom/Makefile |   1 +
 drivers/clk/qcom/gdsc.c   | 130 ++++++++++++++++++++++++++++++++++++++++++++++
 drivers/clk/qcom/gdsc.h   |  43 +++++++++++++++
 4 files changed, 179 insertions(+)
 create mode 100644 drivers/clk/qcom/gdsc.c
 create mode 100644 drivers/clk/qcom/gdsc.h

drivers/clk/qcom/gdsc.c new file +1 -0

@@ -0,0 +1,130 @@
+/*

drivers/clk/qcom/gdsc.c new file +8 -0

+#define EN_FEW_WAIT_MASK	(0xF << 16)
+#define CLK_DIS_WAIT_MASK	(0xF << 12)
+#define SW_OVERRIDE_MASK	BIT(2)
+#define HW_CONTROL_MASK		BIT(1)
+#define SW_COLLAPSE_MASK	BIT(0)
+
+/* Wait 2^n CXO cycles between all states. Here, n=2 (4 cycles). */
+#define EN_REST_WAIT_VAL	(0x2 << 20)

drivers/clk/qcom/gdsc.c new file +10 -0

+	return !!(val & PWR_ON_MASK);
+}
+
+static int gdsc_toggle_logic(struct gdsc *sc, bool en)
+{
+	int ret;
+	u32 val = en ? 0 : SW_COLLAPSE_MASK;
+	u32 check = en ? PWR_ON_MASK : 0;
+	unsigned long timeout;
+

drivers/clk/qcom/gdsc.c new file +23 -0

+	return -ETIMEDOUT;
+}
+
+static int gdsc_enable(struct generic_pm_domain *domain)
+{
+	struct gdsc *sc = domain_to_gdsc(domain);
+	int ret;
+
+	ret = gdsc_toggle_logic(sc, true);
+	if (ret)
+		return ret;
+	/*
+	 * If clocks to this power domain were already on, they will take an
+	 * additional 4 clock cycles to re-enable after the power domain is
+	 * enabled. Delay to account for this. A delay is also needed to ensure
+	 * clocks are not enabled within 400ns of enabling power to the
+	 * memories.
+	 */
+	udelay(1);
+
+	return 0;
+}
+

drivers/clk/qcom/gdsc.c new file +20 -0

+}
+
+int gdsc_init(struct generic_pm_domain *domain, struct regmap *regmap)
+{
+	struct gdsc *sc = domain_to_gdsc(domain);
+	u32 mask;
+	u32 val;
+	int on;
+
+	sc->regmap = regmap;
+
+	/*
+	 * Disable HW trigger: collapse/restore occur based on registers writes.
+	 * Disable SW override: Use hardware state-machine for sequencing.
+	 * Configure wait time between states.
+	 */
+	mask = HW_CONTROL_MASK | SW_OVERRIDE_MASK |
+	       EN_REST_WAIT_MASK | EN_FEW_WAIT_MASK | CLK_DIS_WAIT_MASK;
+	val = EN_REST_WAIT_VAL | EN_FEW_WAIT_VAL | CLK_DIS_WAIT_VAL;
+	regmap_update_bits(sc->regmap, sc->gdscr, mask, val);

The common clk probe registers a clk provider and a reset controller. Update it to register a genpd provider using the gdsc data provided by each platform.

Signed-off-by Rajendra Nayak <[email protected]>

---
 drivers/clk/qcom/common.c | 27 ++++++++++++++++++++++++++-
 drivers/clk/qcom/common.h |  2 ++
 2 files changed, 28 insertions(+), 1 deletion(-)

drivers/clk/qcom/common.c +0 -0

index e20d947..d5b65fa 100644

drivers/clk/qcom/common.c +7 -1

 	struct clk *clks[];
 };
 

@@ -66,10 +68,12 @@ int qcom_cc_really_probe(struct platform_device *pdev,
 	struct device *dev = &pdev->dev;
 	struct clk *clk;
 	struct clk_onecell_data *data;
+	struct genpd_onecell_data *pd;
 	struct clk **clks;
 	struct qcom_reset_controller *reset;
 	struct qcom_cc *cc;
 	size_t num_clks = desc->num_clks;
+	size_t num_gdscs = desc->num_gdscs;
 	struct clk_regmap **rclks = desc->clks;
 
 	cc = devm_kzalloc(dev, sizeof(*cc) + sizeof(*clks) * num_clks,

@@ -79,8 +83,11 @@ int qcom_cc_really_probe(struct platform_device *pdev,
 
 	clks = cc->clks;
 	data = &cc->data;
+	pd = &cc->pd_data;
 	data->clks = clks;
 	data->clk_num = num_clks;
+	pd->domains = desc->gdscs;
+	pd->num_domains = num_gdscs;
 
 	for (i = 0; i < num_clks; i++) {
 		if (!rclks[i]) {

@@ -108,8 +115,25 @@ int qcom_cc_really_probe(struct platform_device *pdev,
 
 	ret = reset_controller_register(&reset->rcdev);
 	if (ret)
-		of_clk_del_provider(dev->of_node);
+		goto err_reset;
 
+	if (num_gdscs) {

drivers/clk/qcom/common.c +7 -0

+
+	return 0;
+err_pd:
+	reset_controller_unregister(&reset->rcdev);
+err_reset:
+	of_clk_del_provider(dev->of_node);
 	return ret;
 }
 EXPORT_SYMBOL_GPL(qcom_cc_really_probe);

@@ -128,6 +152,7 @@ EXPORT_SYMBOL_GPL(qcom_cc_probe);
 
 void qcom_cc_remove(struct platform_device *pdev)
 {
+	of_genpd_del_provider(pdev->dev.of_node);
 	of_clk_del_provider(pdev->dev.of_node);
 	reset_controller_unregister(platform_get_drvdata(pdev));
 }

drivers/clk/qcom/common.h +0 -0

index f519322..55e69c5 100644

drivers/clk/qcom/common.h +1 -0

+	size_t num_gdscs;
 };

GDSCs (Global Distributed Switch Controllers) control switches that supply power to an on-chip power domain and hence can be programmed in SW to safely power collapse and restore power to the respective PDs. They are part of a considerable number of recent QCOM SoCs (This series adds support for msm8974, msm8916 and apq8084 devices) and are part of the Clock control block.

The series implements support for GDSC using the genpd framework modelling these as SW controllable power domains.

8916 support has a dependency on the Global Clock controller support [1] posted by Georgi Djakov.

[1]
https://lkml.org/lkml/2015/2/25/416

Rajendra Nayak (3):
clk: qcom: gdsc: Prepare common clk probe to register gdscs
clk: qcom: gdsc: Add GDSCs in msm8916 GCC
clk: qcom: gdsc: Add GDSCs in apq8084 GCC

Stephen Boyd (3):
clk: qcom: Add support for GDSCs
clk: qcom: gdsc: Add GDSCs in msm8974 GCC
clk: qcom: gdsc: Add GDSCs in msm8974 MMCC

 drivers/clk/qcom/Kconfig                      |   8 ++
 drivers/clk/qcom/Makefile                     |   1 +
 drivers/clk/qcom/common.c                     |  27 +++++-
 drivers/clk/qcom/common.h                     |   2 +
 drivers/clk/qcom/gcc-apq8084.c                |  38 ++++++++
 drivers/clk/qcom/gcc-msm8916.c                |  46 +++++++++
 drivers/clk/qcom/gcc-msm8974.c                |  14 +++
 drivers/clk/qcom/gdsc.c                       | 130 ++++++++++++++++++++++++++
 drivers/clk/qcom/gdsc.h                       |  43 +++++++++

 drivers/clk/qcom/mmcc-msm8974.c               |  54 +++++++++++
 include/dt-bindings/clock/qcom,gcc-apq8084.h  |   6 ++
 include/dt-bindings/clock/qcom,gcc-msm8916.h  |   8 ++
 include/dt-bindings/clock/qcom,gcc-msm8974.h  |   3 +
 include/dt-bindings/clock/qcom,mmcc-msm8974.h |   8 ++
 14 files changed, 387 insertions(+), 1 deletion(-)
 create mode 100644 drivers/clk/qcom/gdsc.c
 create mode 100644 drivers/clk/qcom/gdsc.h

Quoted 36 lines

GDSCs (Global Distributed Switch Controllers) control switches that supply power to an on-chip power domain and hence can be programmed in SW to safely power collapse and restore power to the respective PDs. They are part of a considerable number of recent QCOM SoCs (This series adds support for msm8974, msm8916 and apq8084 devices) and are part of the Clock control block.

The series implements support for GDSC using the genpd framework modelling these as SW controllable power domains.

8916 support has a dependency on the Global Clock controller support [1] posted by Georgi Djakov.

[1]
https://lkml.org/lkml/2015/2/25/416

Rajendra Nayak (3):
clk: qcom: gdsc: Prepare common clk probe to register gdscs
clk: qcom: gdsc: Add GDSCs in msm8916 GCC
clk: qcom: gdsc: Add GDSCs in apq8084 GCC

Stephen Boyd (3):
clk: qcom: Add support for GDSCs
clk: qcom: gdsc: Add GDSCs in msm8974 GCC
clk: qcom: gdsc: Add GDSCs in msm8974 MMCC

 drivers/clk/qcom/Kconfig                      |   8 ++
 drivers/clk/qcom/Makefile                     |   1 +
 drivers/clk/qcom/common.c                     |  27 +++++-
 drivers/clk/qcom/common.h                     |   2 +
 drivers/clk/qcom/gcc-apq8084.c                |  38 ++++++++
 drivers/clk/qcom/gcc-msm8916.c                |  46 +++++++++
 drivers/clk/qcom/gcc-msm8974.c                |  14 +++
 drivers/clk/qcom/gdsc.c                       | 130
++++++++++++++++++++++++++
 drivers/clk/qcom/gdsc.h                       |  43 +++++++++

Quoted 9 lines

 drivers/clk/qcom/mmcc-msm8974.c               |  54 +++++++++++
 include/dt-bindings/clock/qcom,gcc-apq8084.h  |   6 ++
 include/dt-bindings/clock/qcom,gcc-msm8916.h  |   8 ++
 include/dt-bindings/clock/qcom,gcc-msm8974.h  |   3 +
 include/dt-bindings/clock/qcom,mmcc-msm8974.h |   8 ++
 14 files changed, 387 insertions(+), 1 deletion(-)
 create mode 100644 drivers/clk/qcom/gdsc.c
 create mode 100644 drivers/clk/qcom/gdsc.h

You missed a patch who adds appropriate changes in qcom,gcc.txt (qcom,mmcc.txt), at least #power-domain-cells property should be described.