i.MX: fsl_esdhc: allow use with cache enabled.

PATCH Superseded Eric Nelson 6 participants 16 messages Apr 26, 2012 – Jul 20, 2012 1 message not in the archive

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Eric Nelson

author

2012-04-26 00:28 UTC #1 lore raw

PATCH v2 1/1 i.MX: fsl_esdhc: allow use with cache enabled.

Signed-off-by Eric Nelson <[email protected]>

---
V2 fixes checkpatch errors and typecasts as pointed out on the ML.

 drivers/mmc/fsl_esdhc.c |   17 ++++++++++++++++-
 1 files changed, 16 insertions(+), 1 deletions(-)

drivers/mmc/fsl_esdhc.c +16 -1

index a2f35e3..539d848 100644
@@ -190,6 +190,10 @@ static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data)
 		esdhc_clrsetbits32(&regs->wml, WML_RD_WML_MASK, wml_value);
 		esdhc_write32(&regs->dsaddr, (u32)data->dest);
 	} else {
+		flush_dcache_range((ulong)data->src,
+				   (ulong)data->src+data->blocks
+					 *data->blocksize);
+
 		if (wml_value > WML_WR_WML_MAX)
 			wml_value = WML_WR_WML_MAX_VAL;
 		if ((esdhc_read32(&regs->prsstat) & PRSSTAT_WPSPL) == 0) {

@@ -249,7 +253,15 @@ static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data)
 	return 0;
 }
 
-
+static void check_and_invalidate_dcache_range
+	(struct mmc_cmd *cmd,
+	 struct mmc_data *data) {
+	unsigned start = (unsigned)data->dest ;
+	unsigned size = roundup(ARCH_DMA_MINALIGN,
+				data->blocks*data->blocksize);
+	unsigned end = start+size ;
+	invalidate_dcache_range(start, end);
+}
 /*
  * Sends a command out on the bus.  Takes the mmc pointer,
  * a command pointer, and an optional data pointer.

@@ -311,6 +323,9 @@ esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
 	while (!(esdhc_read32(&regs->irqstat) & IRQSTAT_CC))
 		;
 
+	if (data && (data->flags & MMC_DATA_READ))
+		check_and_invalidate_dcache_range(cmd, data);
+
 	irqstat = esdhc_read32(&regs->irqstat);
 	esdhc_write32(&regs->irqstat, irqstat);

Signature · 1 line

1.7.9

Andy Fleming

2012-05-08 22:59 UTC #2 lore raw

PATCH v2 1/1 i.MX: fsl_esdhc: allow use with cache enabled.

drivers/mmc/fsl_esdhc.c static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data) · line 196

Quoted 10 lines

drivers/mmc/fsl_esdhc.c +4 -0

@@ -190,6 +190,10 @@ static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data)
 ? ? ? ? ? ? ? ?esdhc_clrsetbits32(&regs->wml, WML_RD_WML_MASK, wml_value);
 ? ? ? ? ? ? ? ?esdhc_write32(&regs->dsaddr, (u32)data->dest);
 ? ? ? ?} else {
+ ? ? ? ? ? ? ? flush_dcache_range((ulong)data->src,
+ ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?(ulong)data->src+data->blocks
+ ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?*data->blocksize);
+

This still won't work. I don't believe this is implemented at all on the FSL PowerPC parts that use this controller.

At the very least, it needs to be protected by an ifdef.

drivers/mmc/fsl_esdhc.c static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data) · line 258

Quoted 11 lines

drivers/mmc/fsl_esdhc.c +3 -1

 ? ? ? ? ? ? ? ?if (wml_value > WML_WR_WML_MAX)
 ? ? ? ? ? ? ? ? ? ? ? ?wml_value = WML_WR_WML_MAX_VAL;
 ? ? ? ? ? ? ? ?if ((esdhc_read32(&regs->prsstat) & PRSSTAT_WPSPL) == 0) {

@@ -249,7 +253,15 @@ static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data)
 ? ? ? ?return 0;
 ?}
 
-
+static void check_and_invalidate_dcache_range
+ ? ? ? (struct mmc_cmd *cmd,
+ ? ? ? ?struct mmc_data *data) {

This is non-standard formatting in U-Boot.

Andy

Eric Nelson

author

2012-05-08 23:31 UTC #3 lore raw

PATCH v2 1/1 i.MX: fsl_esdhc: allow use with cache enabled.

Thanks Andy,

Quoted 15 lines · Andy Fleming

drivers/mmc/fsl_esdhc.c static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data) · line 196
Quoted 10 lines
drivers/mmc/fsl_esdhc.c +4 -0
@@ -190,6 +190,10 @@ static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data)
                esdhc_clrsetbits32(&regs->wml, WML_RD_WML_MASK, wml_value);
                esdhc_write32(&regs->dsaddr, (u32)data->dest);
        } else {
+               flush_dcache_range((ulong)data->src,
+                                  (ulong)data->src+data->blocks
+                                        *data->blocksize);
+
This still won't work. I don't believe this is implemented at all on the FSL PowerPC parts that use this controller.

Quoted 2 lines

At the very least, it needs to be protected by an ifdef.

It seems more generally useful to implement a PowerPC cache layer than to instrument each driver that supports cache.

Do you know how many other peripherals are shared between ARM and PPC that might be broken by cache operations?

Quoted 7 lines

drivers/mmc/fsl_esdhc.c +0 -0

                if (wml_value>  WML_WR_WML_MAX)
                        wml_value = WML_WR_WML_MAX_VAL;
                if ((esdhc_read32(&regs->prsstat)&  PRSSTAT_WPSPL) == 0) {

@@ -249,7 +253,15 @@ static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data)
        return 0;
  }

Quoted 8 lines

drivers/mmc/fsl_esdhc.c static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data) · line 258
Quoted 4 lines
drivers/mmc/fsl_esdhc.c +3 -1
-
+static void check_and_invalidate_dcache_range
+       (struct mmc_cmd *cmd,
+        struct mmc_data *data) {
This is non-standard formatting in U-Boot.

Ok. I can address that in a V3 once I know the direction.

Regards,

Eric

Stefano Babic

2012-05-09 05:45 UTC #4 lore raw

PATCH v2 1/1 i.MX: fsl_esdhc: allow use with cache enabled.

Quoted 20 lines · Eric Nelson

Thanks Andy,
Quoted 17 lines · Andy Fleming
drivers/mmc/fsl_esdhc.c static int esdhc_setup_data(struct mmc *mmc, · line 198
Quoted 12 lines
drivers/mmc/fsl_esdhc.c +4 -0
@@ -190,6 +190,10 @@ static int esdhc_setup_data(struct mmc *mmc,
 struct mmc_data *data)
                esdhc_clrsetbits32(&regs->wml, WML_RD_WML_MASK,
 wml_value);
                esdhc_write32(&regs->dsaddr, (u32)data->dest);
        } else {
+               flush_dcache_range((ulong)data->src,
+                                  (ulong)data->src+data->blocks
+                                        *data->blocksize);
+
This still won't work. I don't believe this is implemented at all on the FSL PowerPC parts that use this controller.

Quoted 5 lines

Quoted 2 lines
At the very least, it needs to be protected by an ifdef.
It seems more generally useful to implement a PowerPC cache layer than to instrument each driver that supports cache.

Some PowerPC (MPC86xx, arch/powerpc/cpu/mpc86xx/cache.S) have this layer, some other not. This driver is used by MPC85xx and flush_dcache_range is not implemented. The reason is that this SOC uses its internal snooping mechanism and does not need to explicitely flush the buffers in the drivers.

The problem with an #ifdef is that it is not very generic - we should add some #if (defined(CONFIG_MX51) || defined(CONFIG_MX53) || ... and update the driver for each new SOCs. I think also that maybe the best way is to add an empty flush_dcache_range() to the MPC85xx, maybe as weak function.

Best regards,
Stefano

Signature · 5 lines

=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

Dirk Behme

2012-05-15 12:58 UTC #5 lore raw

PATCH v2 1/1 i.MX: fsl_esdhc: allow use with cache enabled.

Quoted 31 lines · Stefano Babic

Quoted 19 lines · Eric Nelson
Thanks Andy,
Quoted 16 lines · Andy Fleming
drivers/mmc/fsl_esdhc.c static int esdhc_setup_data(struct mmc *mmc, · line 198
Quoted 12 lines
drivers/mmc/fsl_esdhc.c +4 -0
@@ -190,6 +190,10 @@ static int esdhc_setup_data(struct mmc *mmc,
 struct mmc_data *data)
                esdhc_clrsetbits32(&regs->wml, WML_RD_WML_MASK,
 wml_value);
                esdhc_write32(&regs->dsaddr, (u32)data->dest);
        } else {
+               flush_dcache_range((ulong)data->src,
+                                  (ulong)data->src+data->blocks
+                                        *data->blocksize);
+
This still won't work. I don't believe this is implemented at all on the FSL PowerPC parts that use this controller.
Quoted 4 lines
Quoted 2 lines
At the very least, it needs to be protected by an ifdef.
It seems more generally useful to implement a PowerPC cache layer than to instrument each driver that supports cache.
Some PowerPC (MPC86xx, arch/powerpc/cpu/mpc86xx/cache.S) have this layer, some other not. This driver is used by MPC85xx and flush_dcache_range is not implemented. The reason is that this SOC uses its internal snooping mechanism and does not need to explicitely flush the buffers in the drivers.

Quoted 5 lines

The problem with an #ifdef is that it is not very generic - we should add some #if (defined(CONFIG_MX51) || defined(CONFIG_MX53) || ... and update the driver for each new SOCs. I think also that maybe the best way is to add an empty flush_dcache_range() to the MPC85xx, maybe as weak function.

You might have noticed that I'm looking through my list of open patches.
So: Any news regarding V3 of this patch? ;)

Many thanks

Dirk

Anatolij Gustschin

2012-05-15 13:09 UTC #6 lore raw

PATCH v2 1/1 i.MX: fsl_esdhc: allow use with cache enabled.

Hi Dirk,

Quoted 1 line · On Tue, 15 May 2012 14:58:54 +0200 Dirk Behme <[email protected]> wrote:

On 09.05.2012 07:45, Stefano Babic wrote:

...

Quoted 8 lines

Quoted 5 lines
The problem with an #ifdef is that it is not very generic - we should add some #if (defined(CONFIG_MX51) || defined(CONFIG_MX53) || ... and update the driver for each new SOCs. I think also that maybe the best way is to add an empty flush_dcache_range() to the MPC85xx, maybe as weak function.
You might have noticed that I'm looking through my list of open patches.
So: Any news regarding V3 of this patch? ;)

Stefano is on vacation; please don't expect any quick reply from him.

Thanks,
Anatolij

Eric Nelson

author

2012-05-15 23:01 UTC #7 lore raw

PATCH v2 1/1 i.MX: fsl_esdhc: allow use with cache enabled.

Quoted 13 lines · Anatolij Gustschin

Hi Dirk,
Quoted 1 line · On Tue, 15 May 2012 14:58:54 +0200 Dirk Behme<[email protected]> wrote:
On 09.05.2012 07:45, Stefano Babic wrote:
...
Quoted 6 lines
Quoted 5 lines
The problem with an #ifdef is that it is not very generic - we should add some #if (defined(CONFIG_MX51) || defined(CONFIG_MX53) || ... and update the driver for each new SOCs. I think also that maybe the best way is to add an empty flush_dcache_range() to the MPC85xx, maybe as weak function.

Quoted 5 lines

Quoted 2 lines
You might have noticed that I'm looking through my list of open patches.
So: Any news regarding V3 of this patch? ;)
Stefano is on vacation; please don't expect any quick reply from him.

Vacation? Is that one of those European words I should really know? ;)

I don't have the same excuse. I'm just struggling to find a few hours to take a stab at this.

I'm without a PPC device and compiler, so I'll need some assistance in validating things.

Regards,

Eric

Marek Vasut

2012-05-15 23:35 UTC #8 lore raw

PATCH v2 1/1 i.MX: fsl_esdhc: allow use with cache enabled.

Dear Eric Nelson,

Quoted 20 lines · Anatolij Gustschin

Quoted 14 lines
Hi Dirk,
On Tue, 15 May 2012 14:58:54 +0200
Quoted 1 line · Dirk Behme
On 09.05.2012 07:45, Stefano Babic wrote:
...
Quoted 6 lines
Quoted 5 lines
The problem with an #ifdef is that it is not very generic - we should add some #if (defined(CONFIG_MX51) || defined(CONFIG_MX53) || ... and update the driver for each new SOCs. I think also that maybe the best way is to add an empty flush_dcache_range() to the MPC85xx, maybe as weak function.
Quoted 4 lines
Quoted 2 lines
You might have noticed that I'm looking through my list of open patches.
So: Any news regarding V3 of this patch? ;)
Stefano is on vacation; please don't expect any quick reply from him.

Quoted 7 lines

Vacation? Is that one of those European words I should really know? ;)
I don't have the same excuse. I'm just struggling to find a few hours to take a stab at this.
I'm without a PPC device and compiler, so I'll need some assistance in validating things.

Well if you put up the tree somewhere, I can run it for you ;-)

Quoted 5 lines

Regards,
Eric

Best regards,
Marek Vasut

Stefano Babic

2012-06-12 17:07 UTC #9 lore raw

PATCH v2 1/1 i.MX: fsl_esdhc: allow use with cache enabled.

In reply to Dirk Behme

Quoted 32 lines · Dirk Behme

Quoted 31 lines · Stefano Babic
Quoted 19 lines · Eric Nelson
Thanks Andy,
Quoted 16 lines · Andy Fleming
drivers/mmc/fsl_esdhc.c static int esdhc_setup_data(struct mmc *mmc, · line 198
Quoted 12 lines
drivers/mmc/fsl_esdhc.c +4 -0
@@ -190,6 +190,10 @@ static int esdhc_setup_data(struct mmc *mmc,
 struct mmc_data *data)
                esdhc_clrsetbits32(&regs->wml, WML_RD_WML_MASK,
 wml_value);
                esdhc_write32(&regs->dsaddr, (u32)data->dest);
        } else {
+               flush_dcache_range((ulong)data->src,
+                                  (ulong)data->src+data->blocks
+                                        *data->blocksize);
+
This still won't work. I don't believe this is implemented at all on the FSL PowerPC parts that use this controller.
Quoted 4 lines
Quoted 2 lines
At the very least, it needs to be protected by an ifdef.
It seems more generally useful to implement a PowerPC cache layer than to instrument each driver that supports cache.
Some PowerPC (MPC86xx, arch/powerpc/cpu/mpc86xx/cache.S) have this layer, some other not. This driver is used by MPC85xx and flush_dcache_range is not implemented. The reason is that this SOC uses its internal snooping mechanism and does not need to explicitely flush the buffers in the drivers.

Quoted 8 lines

Quoted 5 lines
The problem with an #ifdef is that it is not very generic - we should add some #if (defined(CONFIG_MX51) || defined(CONFIG_MX53) || ... and update the driver for each new SOCs. I think also that maybe the best way is to add an empty flush_dcache_range() to the MPC85xx, maybe as weak function.
You might have noticed that I'm looking through my list of open patches.
So: Any news regarding V3 of this patch? ;)

This is my turn to look back if there are some news. Has anyone taken a look at it ?

Best regards,
Stefano Babic

Signature · 5 lines

=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

Eric Nelson

author

2012-06-12 17:14 UTC #10 lore raw

PATCH v2 1/1 i.MX: fsl_esdhc: allow use with cache enabled.

Quoted 39 lines · Stefano Babic

Quoted 38 lines · Dirk Behme
Quoted 36 lines · Stefano Babic
Quoted 19 lines · Eric Nelson
Thanks Andy,
Quoted 16 lines · Andy Fleming
drivers/mmc/fsl_esdhc.c static int esdhc_setup_data(struct mmc *mmc, · line 198
Quoted 12 lines
drivers/mmc/fsl_esdhc.c +4 -0
@@ -190,6 +190,10 @@ static int esdhc_setup_data(struct mmc *mmc,
 struct mmc_data *data)
                 esdhc_clrsetbits32(&regs->wml, WML_RD_WML_MASK,
 wml_value);
                 esdhc_write32(&regs->dsaddr, (u32)data->dest);
         } else {
+               flush_dcache_range((ulong)data->src,
+                                  (ulong)data->src+data->blocks
+                                        *data->blocksize);
+
This still won't work. I don't believe this is implemented at all on the FSL PowerPC parts that use this controller.
Quoted 4 lines
Quoted 2 lines
At the very least, it needs to be protected by an ifdef.
It seems more generally useful to implement a PowerPC cache layer than to instrument each driver that supports cache.
Some PowerPC (MPC86xx, arch/powerpc/cpu/mpc86xx/cache.S) have this layer, some other not. This driver is used by MPC85xx and flush_dcache_range is not implemented. The reason is that this SOC uses its internal snooping mechanism and does not need to explicitely flush the buffers in the drivers.
The problem with an #ifdef is that it is not very generic - we should add some #if (defined(CONFIG_MX51) || defined(CONFIG_MX53) || ... and update the driver for each new SOCs. I think also that maybe the best way is to add an empty flush_dcache_range() to the MPC85xx, maybe as weak function.

Quoted 9 lines

Quoted 2 lines
You might have noticed that I'm looking through my list of open patches.
So: Any news regarding V3 of this patch? ;)
This is my turn to look back if there are some news. Has anyone taken a look at it ?
Best regards,
Stefano Babic

Sorry Stefano,

I've been meaning to generate an update but seem to be starving for time.

Some other messages on the list regarding PPC seem to indicate that the real solution here is a set of cache stubs for PPC, not an SDHC patch though.

I'm not likely to have any time until after FTF next week.

Any chance that a PPC maintainer can chime in here?

Please advise,

Eric

Marek Vasut

2012-06-12 17:23 UTC #11 lore raw

PATCH v2 1/1 i.MX: fsl_esdhc: allow use with cache enabled.

Dear Eric Nelson,

Quoted 58 lines · Stefano Babic

Quoted 44 lines · Dirk Behme
Quoted 43 lines · Stefano Babic
Quoted 41 lines · Eric Nelson
Quoted 24 lines
Thanks Andy,
Quoted 21 lines · Andy Fleming
Quoted 7 lines
drivers/mmc/fsl_esdhc.c +0 -0
@@ -190,6 +190,10 @@ static int esdhc_setup_data(struct mmc *mmc,
 struct mmc_data *data)
 
                 esdhc_clrsetbits32(&regs->wml, WML_RD_WML_MASK,
 
drivers/mmc/fsl_esdhc.c static int esdhc_setup_data(struct mmc *mmc,
Quoted 10 lines
drivers/mmc/fsl_esdhc.c +4 -0
 wml_value);
 
                 esdhc_write32(&regs->dsaddr, (u32)data->dest);
 
         } else {
 
+               flush_dcache_range((ulong)data->src,
+                                  (ulong)data->src+data->blocks
+                                        *data->blocksize);
+
This still won't work. I don't believe this is implemented at all on the FSL PowerPC parts that use this controller.
Quoted 4 lines
Quoted 1 line
At the very least, it needs to be protected by an ifdef.
It seems more generally useful to implement a PowerPC cache layer than to instrument each driver that supports cache.
Some PowerPC (MPC86xx, arch/powerpc/cpu/mpc86xx/cache.S) have this layer, some other not. This driver is used by MPC85xx and flush_dcache_range is not implemented. The reason is that this SOC uses its internal snooping mechanism and does not need to explicitely flush the buffers in the drivers.
The problem with an #ifdef is that it is not very generic - we should add some #if (defined(CONFIG_MX51) || defined(CONFIG_MX53) || ... and update the driver for each new SOCs. I think also that maybe the best way is to add an empty flush_dcache_range() to the MPC85xx, maybe as weak function.
Quoted 8 lines
Quoted 2 lines
You might have noticed that I'm looking through my list of open patches.
So: Any news regarding V3 of this patch? ;)
This is my turn to look back if there are some news. Has anyone taken a look at it ?
Best regards,
Stefano Babic
Sorry Stefano,
I've been meaning to generate an update but seem to be starving for time.

Quoted 7 lines

Some other messages on the list regarding PPC seem to indicate that the real solution here is a set of cache stubs for PPC, not an SDHC patch though.
I'm not likely to have any time until after FTF next week.
Any chance that a PPC maintainer can chime in here?

I think WD applied the cache stub patch already. Can you try now please?

Quoted 5 lines

Please advise,
Eric

Best regards,
Marek Vasut

Dirk Behme

2012-07-11 06:29 UTC #12 lore raw

PATCH v2 1/1 i.MX: fsl_esdhc: allow use with cache enabled.

Quoted 58 lines · Marek Vasut

Dear Eric Nelson,
Quoted 56 lines · Stefano Babic
Quoted 40 lines · Dirk Behme
Quoted 39 lines · Stefano Babic
Quoted 38 lines · Eric Nelson
Quoted 23 lines
Thanks Andy,
Quoted 20 lines · Andy Fleming
Quoted 7 lines
drivers/mmc/fsl_esdhc.c +0 -0
@@ -190,6 +190,10 @@ static int esdhc_setup_data(struct mmc *mmc,
 struct mmc_data *data)
 
                 esdhc_clrsetbits32(&regs->wml, WML_RD_WML_MASK,
 
drivers/mmc/fsl_esdhc.c static int esdhc_setup_data(struct mmc *mmc,
Quoted 10 lines
drivers/mmc/fsl_esdhc.c +4 -0
 wml_value);
 
                 esdhc_write32(&regs->dsaddr, (u32)data->dest);
 
         } else {
 
+               flush_dcache_range((ulong)data->src,
+                                  (ulong)data->src+data->blocks
+                                        *data->blocksize);
+
This still won't work. I don't believe this is implemented at all on the FSL PowerPC parts that use this controller.
Quoted 3 lines
Quoted 1 line
At the very least, it needs to be protected by an ifdef.
It seems more generally useful to implement a PowerPC cache layer than to instrument each driver that supports cache.
Some PowerPC (MPC86xx, arch/powerpc/cpu/mpc86xx/cache.S) have this layer, some other not. This driver is used by MPC85xx and flush_dcache_range is not implemented. The reason is that this SOC uses its internal snooping mechanism and does not need to explicitely flush the buffers in the drivers.
The problem with an #ifdef is that it is not very generic - we should add some #if (defined(CONFIG_MX51) || defined(CONFIG_MX53) || ... and update the driver for each new SOCs. I think also that maybe the best way is to add an empty flush_dcache_range() to the MPC85xx, maybe as weak function.
Quoted 7 lines
Quoted 2 lines
You might have noticed that I'm looking through my list of open patches.
So: Any news regarding V3 of this patch? ;)
This is my turn to look back if there are some news. Has anyone taken a look at it ?
Best regards,
Stefano Babic
Sorry Stefano,
I've been meaning to generate an update but seem to be starving for time.
Some other messages on the list regarding PPC seem to indicate that the real solution here is a set of cache stubs for PPC, not an SDHC patch though.

Quoted 5 lines

Quoted 3 lines
I'm not likely to have any time until after FTF next week.
Any chance that a PPC maintainer can chime in here?
I think WD applied the cache stub patch already. Can you try now please?

Ping ;)

Thanks

Dirk

Marek Vasut

2012-07-13 10:37 UTC #13 lore raw

PATCH v2 1/1 i.MX: fsl_esdhc: allow use with cache enabled.

Dear Dirk Behme,

[...]

Quoted 9 lines

Quoted 5 lines
Quoted 3 lines
I'm not likely to have any time until after FTF next week.
Any chance that a PPC maintainer can chime in here?
I think WD applied the cache stub patch already. Can you try now please?
Ping ;)
Thanks

Adding our human interactions expert into CC :)

Best regards,
Marek Vasut

Marek Vasut

2012-07-20 02:32 UTC #14 lore raw

PATCH v2 1/1 i.MX: fsl_esdhc: allow use with cache enabled.

In reply to Dirk Behme

Dear Dirk Behme,

[...]

Quoted 11 lines

Quoted 5 lines
Quoted 3 lines
I'm not likely to have any time until after FTF next week.
Any chance that a PPC maintainer can chime in here?
I think WD applied the cache stub patch already. Can you try now please?
Ping ;)
Thanks
Dirk

I just noticed this with latest mainline:
Configuring for MPC8569MDS_ATM - Board: MPC8569MDS, Options: ATM
make: *** [u-boot] Error 1
powerpc-linux-size: './u-boot': No such file
drivers/mmc/libmmc.o: In function `esdhc_setup_data':
/home/marex/testing/u-boot.git/drivers/mmc/fsl_esdhc.c:193: undefined reference to `flush_dcache_range'
drivers/mmc/libmmc.o: In function `check_and_invalidate_dcache_range':
/home/marex/testing/u-boot.git/drivers/mmc/fsl_esdhc.c:263: undefined reference to `invalidate_dcache_range'
make: *** [u-boot] Error 1
Configuring for MPC8569MDS_NAND - Board: MPC8569MDS, Options: NAND
make: *** [u-boot] Error 1
powerpc-linux-size: './u-boot': No such file
drivers/mmc/libmmc.o: In function `esdhc_setup_data':
/home/marex/testing/u-boot.git/drivers/mmc/fsl_esdhc.c:193: undefined reference to `flush_dcache_range'
drivers/mmc/libmmc.o: In function `check_and_invalidate_dcache_range':
/home/marex/testing/u-boot.git/drivers/mmc/fsl_esdhc.c:263: undefined reference to `invalidate_dcache_range'
make: *** [u-boot] Error 1

Can this be caused by this patch?

Best regards,
Marek Vasut

Dirk Behme

2012-07-20 05:35 UTC #15 lore raw

PATCH v2 1/1 i.MX: fsl_esdhc: allow use with cache enabled.

Quoted 36 lines · Marek Vasut

Dear Dirk Behme,
[...]
Quoted 9 lines
Quoted 4 lines
Quoted 3 lines
I'm not likely to have any time until after FTF next week.
Any chance that a PPC maintainer can chime in here?
I think WD applied the cache stub patch already. Can you try now please?
Ping ;)
Thanks
Dirk
I just noticed this with latest mainline:
Configuring for MPC8569MDS_ATM - Board: MPC8569MDS, Options: ATM
make: *** [u-boot] Error 1
powerpc-linux-size: './u-boot': No such file
drivers/mmc/libmmc.o: In function `esdhc_setup_data':
/home/marex/testing/u-boot.git/drivers/mmc/fsl_esdhc.c:193: undefined reference to `flush_dcache_range'
drivers/mmc/libmmc.o: In function `check_and_invalidate_dcache_range':
/home/marex/testing/u-boot.git/drivers/mmc/fsl_esdhc.c:263: undefined reference to `invalidate_dcache_range'
make: *** [u-boot] Error 1
Configuring for MPC8569MDS_NAND - Board: MPC8569MDS, Options: NAND
make: *** [u-boot] Error 1
powerpc-linux-size: './u-boot': No such file
drivers/mmc/libmmc.o: In function `esdhc_setup_data':
/home/marex/testing/u-boot.git/drivers/mmc/fsl_esdhc.c:193: undefined reference to `flush_dcache_range'
drivers/mmc/libmmc.o: In function `check_and_invalidate_dcache_range':
/home/marex/testing/u-boot.git/drivers/mmc/fsl_esdhc.c:263: undefined reference to `invalidate_dcache_range'
make: *** [u-boot] Error 1

Quoted 1 line

Can this be caused by this patch?

Yes, I think so.

Reading the logs, to my understanding the conclusion in

http://lists.denx.de/pipermail/u-boot/2012-May/124036.html

was to "add an empty flush_dcache_range() to the MPC85xx, maybe as weak function".

Then

http://lists.denx.de/pipermail/u-boot/2012-June/126097.html

mentions "WD applied the cache stub patch already".

So do we have this "cache stub patch" somewhere which fixes the issue mentioned above? I'm not sure I've seen it ...

Best regards

Dirk

Stefano Babic

2012-07-20 08:53 UTC #16 lore raw

PATCH v2 1/1 i.MX: fsl_esdhc: allow use with cache enabled.

Quoted 8 lines · Dirk Behme

Then
http://lists.denx.de/pipermail/u-boot/2012-June/126097.html
mentions "WD applied the cache stub patch already".
So do we have this "cache stub patch" somewhere which fixes the issue mentioned above? I'm not sure I've seen it ...

It is done, but I see it is compiled only if USB is activated. We need a fix like:

(quoted diff) +0 -0

b/arch/powerpc/cpu/mpc85xx/Makefile
index 7d65aa7..34f6c54 100644

arch/powerpc/cpu/mpc85xx/Makefile +1 -1

@@ -131,7 +131,7 @@ COBJS       += tlb.o
 COBJS  += traps.o
 
 # Stub implementations of cache management functions for USB
-COBJS-$(CONFIG_USB_EHCI) += cache.o
+COBJS += cache.o
 
 SRCS   := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS   := $(addprefix $(obj),$(SOBJS) $(COBJS))

I send a proper patch.

Stefano

Signature · 5 lines

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