ARM: tegra: fix U16 divider range check
Subsystems (3)
PATCH 1/1 ARM: tegra: fix U16 divider range check
From: Stephen Warren <[email protected]>
A U16 divider can divide a clock by 1..64K. However, the range-check in clk_div16_get_divider() limited the range to 1..256. Fix this. NVIDIA's downstream kernels already have the fixed range-check.
In practice this is a problem on Whistler's I2C bus, which uses a bus clock rate of 100KHz (rather than the more common 400KHz on Tegra boards), which requires a HW module clock of 8*100KHz. The parent clock is 216MHz, leading to a desired divider of 270. Prior to conversion to the common clock framework, this range error was somehow ignored/irrelevant and caused no problems. However, the common clock framework evidently has more rigorous error-checking, so this failure causes the I2C bus to fail to operate correctly.
--- arch/arm/mach-tegra/tegra2_clocks.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-)
arch/arm/mach-tegra/tegra2_clocks.c +1 -1
@@ -223,7 +223,7 @@ static int clk_div16_get_divider(unsigned long parent_rate, unsigned long rate)if (divider_u16 -1 <0 )return 0 ; -if (divider_u16 -1 >255 ) +if (divider_u16 -1 >0xFFFF )return -EINVAL ;return divider_u16 -1 ;
Signature · 1 line
1.7.0.4
PATCH 1/1 ARM: tegra: fix U16 divider range check
Quoted 15 lines · Stephen Warren
From: Stephen Warren<[email protected]>
A U16 divider can divide a clock by 1..64K. However, the range-check in
clk_div16_get_divider()limited the range to 1..256. Fix this. NVIDIA's downstream kernels already have the fixed range-check.In practice this is a problem on Whistler's I2C bus, which uses a bus clock rate of 100KHz (rather than the more common 400KHz on Tegra boards), which requires a HW module clock of 8*100KHz. The parent clock is 216MHz, leading to a desired divider of 270. Prior to conversion to the common clock framework, this range error was somehow ignored/irrelevant and caused no problems. However, the common clock framework evidently has more rigorous error-checking, so this failure causes the I2C bus to fail to operate correctly.
Quoted 1 line
Signed-off-by Stephen Warren<[email protected]>
Thanks Stephen!!
Verified on Cardhu and Ventana with common clock framework patches.
Quoted 17 lines
--- arch/arm/mach-tegra/tegra2_clocks.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-)arch/arm/mach-tegra/tegra2_clocks.c +1
-1@@ -223,7 +223,7 @@ static int clk_div16_get_divider(unsigned long parent_rate, unsigned long rate)if (divider_u16 -1 <0 )return 0 ; -if (divider_u16 -1 >255 ) +if (divider_u16 -1 >0xFFFF )return -EINVAL ;return divider_u16 -1 ;
Stephen Warren
AppliedPATCH 1/1 ARM: tegra: fix U16 divider range check
In reply to Stephen WarrenQuoted 6 lines · Stephen Warren
From: Stephen Warren <[email protected]>
A U16 divider can divide a clock by 1..64K. However, the range-check in
clk_div16_get_divider()limited the range to 1..256. Fix this. NVIDIA's downstream kernels already have the fixed range-check.
Quoted 8 lines
In practice this is a problem on Whistler's I2C bus, which uses a bus clock rate of 100KHz (rather than the more common 400KHz on Tegra boards), which requires a HW module clock of 8*100KHz. The parent clock is 216MHz, leading to a desired divider of 270. Prior to conversion to the common clock framework, this range error was somehow ignored/irrelevant and caused no problems. However, the common clock framework evidently has more rigorous error-checking, so this failure causes the I2C bus to fail to operate correctly.
Applied to for-3.7/common-clk.