Rework for mxs SoC family support

similarity index 100%
rename from arch/arm/cpu/arm926ejs/mx28/clock.c
rename to arch/arm/cpu/arm926ejs/mxs/clock.c

similarity index 100%
rename from arch/arm/cpu/arm926ejs/mx28/iomux.c
rename to arch/arm/cpu/arm926ejs/mxs/iomux.c

similarity index 100%
rename from arch/arm/cpu/arm926ejs/mx28/mx28.c
rename to arch/arm/cpu/arm926ejs/mxs/mx28.c

similarity index 100%
rename from arch/arm/cpu/arm926ejs/mx28/mx28_init.h
rename to arch/arm/cpu/arm926ejs/mxs/mx28_init.h

similarity index 100%
rename from arch/arm/cpu/arm926ejs/mx28/spl_boot.c
rename to arch/arm/cpu/arm926ejs/mxs/spl_boot.c

similarity index 100%
rename from arch/arm/cpu/arm926ejs/mx28/spl_lradc_init.c
rename to arch/arm/cpu/arm926ejs/mxs/spl_lradc_init.c

similarity index 100%
rename from arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c
rename to arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c

similarity index 100%
rename from arch/arm/cpu/arm926ejs/mx28/spl_power_init.c
rename to arch/arm/cpu/arm926ejs/mxs/spl_power_init.c

similarity index 100%
rename from arch/arm/cpu/arm926ejs/mx28/timer.c
rename to arch/arm/cpu/arm926ejs/mxs/timer.c

similarity index 100%
rename from arch/arm/include/asm/arch-mx28/clock.h
rename to arch/arm/include/asm/arch-mxs/clock.h

similarity index 100%
rename from arch/arm/include/asm/arch-mx28/dma.h
rename to arch/arm/include/asm/arch-mxs/dma.h

similarity index 100%
rename from arch/arm/include/asm/arch-mx28/gpio.h
rename to arch/arm/include/asm/arch-mxs/gpio.h

similarity index 100%
rename from arch/arm/include/asm/arch-mx28/imx-regs.h
rename to arch/arm/include/asm/arch-mxs/imx-regs.h

similarity index 100%
rename from arch/arm/include/asm/arch-mx28/iomux-mx28.h
rename to arch/arm/include/asm/arch-mxs/iomux-mx28.h

similarity index 100%
rename from arch/arm/include/asm/arch-mx28/iomux.h
rename to arch/arm/include/asm/arch-mxs/iomux.h

similarity index 100%
rename from arch/arm/include/asm/arch-mx28/regs-apbh.h
rename to arch/arm/include/asm/arch-mxs/regs-apbh.h

similarity index 100%
rename from arch/arm/include/asm/arch-mx28/regs-base.h
rename to arch/arm/include/asm/arch-mxs/regs-base.h

similarity index 100%
rename from arch/arm/include/asm/arch-mx28/regs-bch.h
rename to arch/arm/include/asm/arch-mxs/regs-bch.h

similarity index 100%
rename from arch/arm/include/asm/arch-mx28/regs-clkctrl.h
rename to arch/arm/include/asm/arch-mxs/regs-clkctrl.h

similarity index 100%
rename from arch/arm/include/asm/arch-mx28/regs-common.h
rename to arch/arm/include/asm/arch-mxs/regs-common.h

similarity index 100%
rename from arch/arm/include/asm/arch-mx28/regs-digctl.h
rename to arch/arm/include/asm/arch-mxs/regs-digctl.h

similarity index 100%
rename from arch/arm/include/asm/arch-mx28/regs-gpmi.h
rename to arch/arm/include/asm/arch-mxs/regs-gpmi.h

similarity index 100%
rename from arch/arm/include/asm/arch-mx28/regs-i2c.h
rename to arch/arm/include/asm/arch-mxs/regs-i2c.h

similarity index 100%
rename from arch/arm/include/asm/arch-mx28/regs-lcdif.h
rename to arch/arm/include/asm/arch-mxs/regs-lcdif.h

similarity index 100%
rename from arch/arm/include/asm/arch-mx28/regs-lradc.h
rename to arch/arm/include/asm/arch-mxs/regs-lradc.h

similarity index 100%
rename from arch/arm/include/asm/arch-mx28/regs-ocotp.h
rename to arch/arm/include/asm/arch-mxs/regs-ocotp.h

similarity index 100%
rename from arch/arm/include/asm/arch-mx28/regs-pinctrl.h
rename to arch/arm/include/asm/arch-mxs/regs-pinctrl.h

similarity index 100%
rename from arch/arm/include/asm/arch-mx28/regs-power.h
rename to arch/arm/include/asm/arch-mxs/regs-power.h

similarity index 100%
rename from arch/arm/include/asm/arch-mx28/regs-rtc.h
rename to arch/arm/include/asm/arch-mxs/regs-rtc.h

similarity index 100%
rename from arch/arm/include/asm/arch-mx28/regs-ssp.h
rename to arch/arm/include/asm/arch-mxs/regs-ssp.h

similarity index 100%
rename from arch/arm/include/asm/arch-mx28/regs-timrot.h
rename to arch/arm/include/asm/arch-mxs/regs-timrot.h

similarity index 100%
rename from arch/arm/include/asm/arch-mx28/regs-usb.h
rename to arch/arm/include/asm/arch-mxs/regs-usb.h

similarity index 100%
rename from arch/arm/include/asm/arch-mx28/regs-usbphy.h
rename to arch/arm/include/asm/arch-mxs/regs-usbphy.h

similarity index 100%
rename from arch/arm/include/asm/arch-mx28/sys_proto.h
rename to arch/arm/include/asm/arch-mxs/sys_proto.h

index f12d927..641c502 100644
@@ -47,8 +47,8 @@
  */
 #define	CONFIG_SPL
 #define	CONFIG_SPL_NO_CPU_SUPPORT_CODE
-#define	CONFIG_SPL_START_S_PATH		"arch/arm/cpu/arm926ejs/mx28"
-#define	CONFIG_SPL_LDSCRIPT	"arch/arm/cpu/arm926ejs/mx28/u-boot-spl.lds"
+#define	CONFIG_SPL_START_S_PATH		"arch/arm/cpu/arm926ejs/mxs"
+#define	CONFIG_SPL_LDSCRIPT	"arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds"
 #define	CONFIG_SPL_LIBCOMMON_SUPPORT
 #define	CONFIG_SPL_LIBGENERIC_SUPPORT
 #define	CONFIG_SPL_GPIO_SUPPORT

index 54d21e6..d05c07e 100644
@@ -41,8 +41,8 @@
  */
 #define CONFIG_SPL
 #define CONFIG_SPL_NO_CPU_SUPPORT_CODE
-#define CONFIG_SPL_START_S_PATH	"arch/arm/cpu/arm926ejs/mx28"
-#define CONFIG_SPL_LDSCRIPT	"arch/arm/cpu/arm926ejs/mx28/u-boot-spl.lds"
+#define CONFIG_SPL_START_S_PATH	"arch/arm/cpu/arm926ejs/mxs"
+#define CONFIG_SPL_LDSCRIPT	"arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds"
 #define CONFIG_SPL_LIBCOMMON_SUPPORT
 #define CONFIG_SPL_LIBGENERIC_SUPPORT
 #define CONFIG_SPL_GPIO_SUPPORT

index 0439f9c..3e29c56 100644
@@ -207,7 +207,7 @@ void mx28_set_sspclk(enum mxs_sspclock ssp, uint32_t freq, int xtal)
 		return;
 
 	clkreg = (uint32_t)(&clkctrl_regs->hw_clkctrl_ssp0) +
-			(ssp * sizeof(struct mx28_register_32));
+			(ssp * sizeof(struct mxs_register_32));
 
 	clrbits_le32(clkreg, CLKCTRL_SSP_CLKGATE);
 	while (readl(clkreg) & CLKCTRL_SSP_CLKGATE)

@@ -256,7 +256,7 @@ static uint32_t mx28_get_sspclk(enum mxs_sspclock ssp)
 		return XTAL_FREQ_KHZ;
 
 	clkreg = (uint32_t)(&clkctrl_regs->hw_clkctrl_ssp0) +
-			(ssp * sizeof(struct mx28_register_32));
+			(ssp * sizeof(struct mxs_register_32));
 
 	tmp = readl(clkreg) & CLKCTRL_SSP_DIV_MASK;
 

index 12916b6..73f1446 100644
@@ -43,7 +43,7 @@ int mxs_iomux_setup_pad(iomux_cfg_t pad)
 {
 	u32 reg, ofs, bp, bm;
 	void *iomux_base = (void *)MXS_PINCTRL_BASE;
-	struct mx28_register_32 *mxs_reg;
+	struct mxs_register_32 *mxs_reg;
 
 	/* muxsel */
 	ofs = 0x100;

@@ -70,7 +70,7 @@ int mxs_iomux_setup_pad(iomux_cfg_t pad)
 	/* vol */
 	if (PAD_VOL_VALID(pad)) {
 		bp = PAD_PIN(pad) % 8 * 4 + 2;
-		mxs_reg = (struct mx28_register_32 *)(iomux_base + ofs);
+		mxs_reg = (struct mxs_register_32 *)(iomux_base + ofs);
 		if (PAD_VOL(pad))
 			writel(1 << bp, &mxs_reg->reg_set);
 		else

@@ -82,7 +82,7 @@ int mxs_iomux_setup_pad(iomux_cfg_t pad)
 		ofs = PULL_OFFSET;
 		ofs += PAD_BANK(pad) * 0x10;
 		bp = PAD_PIN(pad);
-		mxs_reg = (struct mx28_register_32 *)(iomux_base + ofs);
+		mxs_reg = (struct mxs_register_32 *)(iomux_base + ofs);
 		if (PAD_PULL(pad))
 			writel(1 << bp, &mxs_reg->reg_set);
 		else

index cf7a50f..65fcd75 100644
@@ -81,7 +81,7 @@ void enable_caches(void)
 #endif
 }
 
-int mx28_wait_mask_set(struct mx28_register_32 *reg, uint32_t mask, int timeout)
+int mx28_wait_mask_set(struct mxs_register_32 *reg, uint32_t mask, int timeout)
 {
 	while (--timeout) {
 		if ((readl(&reg->reg) & mask) == mask)

@@ -92,7 +92,7 @@ int mx28_wait_mask_set(struct mx28_register_32 *reg, uint32_t mask, int timeout)
 	return !timeout;
 }
 
-int mx28_wait_mask_clr(struct mx28_register_32 *reg, uint32_t mask, int timeout)
+int mx28_wait_mask_clr(struct mxs_register_32 *reg, uint32_t mask, int timeout)
 {
 	while (--timeout) {
 		if ((readl(&reg->reg) & mask) == 0)

@@ -103,7 +103,7 @@ int mx28_wait_mask_clr(struct mx28_register_32 *reg, uint32_t mask, int timeout)
 	return !timeout;
 }
 
-int mx28_reset_block(struct mx28_register_32 *reg)
+int mx28_reset_block(struct mxs_register_32 *reg)
 {
 	/* Clear SFTRST */
 	writel(MX28_BLOCK_SFTRST, &reg->reg_clr);

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index d2e1953..bcea419 100644
@@ -1,5 +1,5 @@
 /*
- * Freescale i.MX28 Register Accessors
+ * Freescale i.MXS Register Accessors
  *
  * Copyright (C) 2011 Marek Vasut <[email protected]>
  * on behalf of DENX Software Engineering GmbH

@@ -20,11 +20,11 @@
  *
  */
 
-#ifndef __MX28_REGS_COMMON_H__
-#define __MX28_REGS_COMMON_H__
+#ifndef __MXS_REGS_COMMON_H__
+#define __MXS_REGS_COMMON_H__
 
 /*
- * The i.MX28 has interesting feature when it comes to register access. There
+ * The i.MXS has interesting feature when it comes to register access. There
  * are four kinds of access to one particular register. Those are:
  *
  * 1) Common read/write access. To use this mode, just write to the address of

@@ -47,36 +47,36 @@
  *
  */
 
-#define	__mx28_reg_8(name)		\
+#define	__mxs_reg_8(name)		\
 	uint8_t	name[4];		\
 	uint8_t	name##_set[4];		\
 	uint8_t	name##_clr[4];		\
 	uint8_t	name##_tog[4];		\
 
-#define	__mx28_reg_32(name)		\
+#define	__mxs_reg_32(name)		\
 	uint32_t name;			\
 	uint32_t name##_set;		\
 	uint32_t name##_clr;		\
 	uint32_t name##_tog;
 
-struct mx28_register_8 {
-	__mx28_reg_8(reg)
+struct mxs_register_8 {
+	__mxs_reg_8(reg)
 };
 
-struct mx28_register_32 {
-	__mx28_reg_32(reg)
+struct mxs_register_32 {
+	__mxs_reg_32(reg)
 };
 
-#define	mx28_reg_8(name)				\
+#define	mxs_reg_8(name)				\
 	union {						\
-		struct { __mx28_reg_8(name) };		\
-		struct mx28_register_8 name##_reg;	\
+		struct { __mxs_reg_8(name) };		\
+		struct mxs_register_8 name##_reg;	\
 	};
 
-#define	mx28_reg_32(name)				\
+#define	mxs_reg_32(name)				\
 	union {						\
-		struct { __mx28_reg_32(name) };		\
-		struct mx28_register_32 name##_reg;	\
+		struct { __mxs_reg_32(name) };		\
+		struct mxs_register_32 name##_reg;	\
 	};
 
-#endif	/* __MX28_REGS_COMMON_H__ */
+#endif	/* __MXS_REGS_COMMON_H__ */

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index 1b487f4..190a570 100644
@@ -30,22 +30,22 @@
 
 #ifndef	__ASSEMBLY__
 struct mx28_gpmi_regs {
-	mx28_reg_32(hw_gpmi_ctrl0)
-	mx28_reg_32(hw_gpmi_compare)
-	mx28_reg_32(hw_gpmi_eccctrl)
-	mx28_reg_32(hw_gpmi_ecccount)
-	mx28_reg_32(hw_gpmi_payload)
-	mx28_reg_32(hw_gpmi_auxiliary)
-	mx28_reg_32(hw_gpmi_ctrl1)
-	mx28_reg_32(hw_gpmi_timing0)
-	mx28_reg_32(hw_gpmi_timing1)
+	mxs_reg_32(hw_gpmi_ctrl0)
+	mxs_reg_32(hw_gpmi_compare)
+	mxs_reg_32(hw_gpmi_eccctrl)
+	mxs_reg_32(hw_gpmi_ecccount)
+	mxs_reg_32(hw_gpmi_payload)
+	mxs_reg_32(hw_gpmi_auxiliary)
+	mxs_reg_32(hw_gpmi_ctrl1)
+	mxs_reg_32(hw_gpmi_timing0)
+	mxs_reg_32(hw_gpmi_timing1)
 
 	uint32_t	reserved[4];
 
-	mx28_reg_32(hw_gpmi_data)
-	mx28_reg_32(hw_gpmi_stat)
-	mx28_reg_32(hw_gpmi_debug)
-	mx28_reg_32(hw_gpmi_version)
+	mxs_reg_32(hw_gpmi_data)
+	mxs_reg_32(hw_gpmi_stat)
+	mxs_reg_32(hw_gpmi_debug)
+	mxs_reg_32(hw_gpmi_version)
 };
 #endif
 

index 2e2e814..418a3c0 100644
@@ -27,20 +27,20 @@
 
 #ifndef	__ASSEMBLY__
 struct mx28_i2c_regs {
-	mx28_reg_32(hw_i2c_ctrl0)
-	mx28_reg_32(hw_i2c_timing0)
-	mx28_reg_32(hw_i2c_timing1)
-	mx28_reg_32(hw_i2c_timing2)
-	mx28_reg_32(hw_i2c_ctrl1)
-	mx28_reg_32(hw_i2c_stat)
-	mx28_reg_32(hw_i2c_queuectrl)
-	mx28_reg_32(hw_i2c_queuestat)
-	mx28_reg_32(hw_i2c_queuecmd)
-	mx28_reg_32(hw_i2c_queuedata)
-	mx28_reg_32(hw_i2c_data)
-	mx28_reg_32(hw_i2c_debug0)
-	mx28_reg_32(hw_i2c_debug1)
-	mx28_reg_32(hw_i2c_version)
+	mxs_reg_32(hw_i2c_ctrl0)
+	mxs_reg_32(hw_i2c_timing0)
+	mxs_reg_32(hw_i2c_timing1)
+	mxs_reg_32(hw_i2c_timing2)
+	mxs_reg_32(hw_i2c_ctrl1)
+	mxs_reg_32(hw_i2c_stat)
+	mxs_reg_32(hw_i2c_queuectrl)
+	mxs_reg_32(hw_i2c_queuestat)
+	mxs_reg_32(hw_i2c_queuecmd)
+	mxs_reg_32(hw_i2c_queuedata)
+	mxs_reg_32(hw_i2c_data)
+	mxs_reg_32(hw_i2c_debug0)
+	mxs_reg_32(hw_i2c_debug1)
+	mxs_reg_32(hw_i2c_version)
 };
 #endif
 

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index 8eadc6d..3c9e3b0 100644
@@ -26,10 +26,10 @@
 
 #ifndef	__ASSEMBLY__
 struct mx28_power_regs {
-	mx28_reg_32(hw_power_ctrl)
-	mx28_reg_32(hw_power_5vctrl)
-	mx28_reg_32(hw_power_minpwr)
-	mx28_reg_32(hw_power_charge)
+	mxs_reg_32(hw_power_ctrl)
+	mxs_reg_32(hw_power_5vctrl)
+	mxs_reg_32(hw_power_minpwr)
+	mxs_reg_32(hw_power_charge)
 	uint32_t	hw_power_vdddctrl;
 	uint32_t	reserved_vddd[3];
 	uint32_t	hw_power_vddactrl;

@@ -44,23 +44,23 @@ struct mx28_power_regs {
 	uint32_t	reserved_misc[3];
 	uint32_t	hw_power_dclimits;
 	uint32_t	reserved_dclimits[3];
-	mx28_reg_32(hw_power_loopctrl)
+	mxs_reg_32(hw_power_loopctrl)
 	uint32_t	hw_power_sts;
 	uint32_t	reserved_sts[3];
-	mx28_reg_32(hw_power_speed)
+	mxs_reg_32(hw_power_speed)
 	uint32_t	hw_power_battmonitor;
 	uint32_t	reserved_battmonitor[3];
 
 	uint32_t	reserved[4];
 
-	mx28_reg_32(hw_power_reset)
-	mx28_reg_32(hw_power_debug)
-	mx28_reg_32(hw_power_thermal)
-	mx28_reg_32(hw_power_usb1ctrl)
-	mx28_reg_32(hw_power_special)
-	mx28_reg_32(hw_power_version)
-	mx28_reg_32(hw_power_anaclkctrl)
-	mx28_reg_32(hw_power_refctrl)
+	mxs_reg_32(hw_power_reset)
+	mxs_reg_32(hw_power_debug)
+	mxs_reg_32(hw_power_thermal)
+	mxs_reg_32(hw_power_usb1ctrl)
+	mxs_reg_32(hw_power_special)
+	mxs_reg_32(hw_power_version)
+	mxs_reg_32(hw_power_anaclkctrl)
+	mxs_reg_32(hw_power_refctrl)
 };
 #endif
 

index e605a03..0b660ae 100644
@@ -27,20 +27,20 @@
 
 #ifndef	__ASSEMBLY__
 struct mx28_rtc_regs {
-	mx28_reg_32(hw_rtc_ctrl)
-	mx28_reg_32(hw_rtc_stat)
-	mx28_reg_32(hw_rtc_milliseconds)
-	mx28_reg_32(hw_rtc_seconds)
-	mx28_reg_32(hw_rtc_rtc_alarm)
-	mx28_reg_32(hw_rtc_watchdog)
-	mx28_reg_32(hw_rtc_persistent0)
-	mx28_reg_32(hw_rtc_persistent1)
-	mx28_reg_32(hw_rtc_persistent2)
-	mx28_reg_32(hw_rtc_persistent3)
-	mx28_reg_32(hw_rtc_persistent4)
-	mx28_reg_32(hw_rtc_persistent5)
-	mx28_reg_32(hw_rtc_debug)
-	mx28_reg_32(hw_rtc_version)
+	mxs_reg_32(hw_rtc_ctrl)
+	mxs_reg_32(hw_rtc_stat)
+	mxs_reg_32(hw_rtc_milliseconds)
+	mxs_reg_32(hw_rtc_seconds)
+	mxs_reg_32(hw_rtc_rtc_alarm)
+	mxs_reg_32(hw_rtc_watchdog)
+	mxs_reg_32(hw_rtc_persistent0)
+	mxs_reg_32(hw_rtc_persistent1)
+	mxs_reg_32(hw_rtc_persistent2)
+	mxs_reg_32(hw_rtc_persistent3)
+	mxs_reg_32(hw_rtc_persistent4)
+	mxs_reg_32(hw_rtc_persistent5)
+	mxs_reg_32(hw_rtc_debug)
+	mxs_reg_32(hw_rtc_version)
 };
 #endif
 

index be71d48..85b9894 100644
@@ -29,26 +29,26 @@
 
 #ifndef	__ASSEMBLY__
 struct mx28_ssp_regs {
-	mx28_reg_32(hw_ssp_ctrl0)
-	mx28_reg_32(hw_ssp_cmd0)
-	mx28_reg_32(hw_ssp_cmd1)
-	mx28_reg_32(hw_ssp_xfer_size)
-	mx28_reg_32(hw_ssp_block_size)
-	mx28_reg_32(hw_ssp_compref)
-	mx28_reg_32(hw_ssp_compmask)
-	mx28_reg_32(hw_ssp_timing)
-	mx28_reg_32(hw_ssp_ctrl1)
-	mx28_reg_32(hw_ssp_data)
-	mx28_reg_32(hw_ssp_sdresp0)
-	mx28_reg_32(hw_ssp_sdresp1)
-	mx28_reg_32(hw_ssp_sdresp2)
-	mx28_reg_32(hw_ssp_sdresp3)
-	mx28_reg_32(hw_ssp_ddr_ctrl)
-	mx28_reg_32(hw_ssp_dll_ctrl)
-	mx28_reg_32(hw_ssp_status)
-	mx28_reg_32(hw_ssp_dll_sts)
-	mx28_reg_32(hw_ssp_debug)
-	mx28_reg_32(hw_ssp_version)
+	mxs_reg_32(hw_ssp_ctrl0)
+	mxs_reg_32(hw_ssp_cmd0)
+	mxs_reg_32(hw_ssp_cmd1)
+	mxs_reg_32(hw_ssp_xfer_size)
+	mxs_reg_32(hw_ssp_block_size)
+	mxs_reg_32(hw_ssp_compref)
+	mxs_reg_32(hw_ssp_compmask)
+	mxs_reg_32(hw_ssp_timing)
+	mxs_reg_32(hw_ssp_ctrl1)
+	mxs_reg_32(hw_ssp_data)
+	mxs_reg_32(hw_ssp_sdresp0)
+	mxs_reg_32(hw_ssp_sdresp1)
+	mxs_reg_32(hw_ssp_sdresp2)
+	mxs_reg_32(hw_ssp_sdresp3)
+	mxs_reg_32(hw_ssp_ddr_ctrl)
+	mxs_reg_32(hw_ssp_dll_ctrl)
+	mxs_reg_32(hw_ssp_status)
+	mxs_reg_32(hw_ssp_dll_sts)
+	mxs_reg_32(hw_ssp_debug)
+	mxs_reg_32(hw_ssp_version)
 };
 #endif
 

index 3e8dfe7..332654f 100644
@@ -29,25 +29,25 @@
 
 #ifndef	__ASSEMBLY__
 struct mx28_timrot_regs {
-	mx28_reg_32(hw_timrot_rotctrl)
-	mx28_reg_32(hw_timrot_rotcount)
-	mx28_reg_32(hw_timrot_timctrl0)
-	mx28_reg_32(hw_timrot_running_count0)
-	mx28_reg_32(hw_timrot_fixed_count0)
-	mx28_reg_32(hw_timrot_match_count0)
-	mx28_reg_32(hw_timrot_timctrl1)
-	mx28_reg_32(hw_timrot_running_count1)
-	mx28_reg_32(hw_timrot_fixed_count1)
-	mx28_reg_32(hw_timrot_match_count1)
-	mx28_reg_32(hw_timrot_timctrl2)
-	mx28_reg_32(hw_timrot_running_count2)
-	mx28_reg_32(hw_timrot_fixed_count2)
-	mx28_reg_32(hw_timrot_match_count2)
-	mx28_reg_32(hw_timrot_timctrl3)
-	mx28_reg_32(hw_timrot_running_count3)
-	mx28_reg_32(hw_timrot_fixed_count3)
-	mx28_reg_32(hw_timrot_match_count3)
-	mx28_reg_32(hw_timrot_version)
+	mxs_reg_32(hw_timrot_rotctrl)
+	mxs_reg_32(hw_timrot_rotcount)
+	mxs_reg_32(hw_timrot_timctrl0)
+	mxs_reg_32(hw_timrot_running_count0)
+	mxs_reg_32(hw_timrot_fixed_count0)
+	mxs_reg_32(hw_timrot_match_count0)
+	mxs_reg_32(hw_timrot_timctrl1)
+	mxs_reg_32(hw_timrot_running_count1)
+	mxs_reg_32(hw_timrot_fixed_count1)
+	mxs_reg_32(hw_timrot_match_count1)
+	mxs_reg_32(hw_timrot_timctrl2)
+	mxs_reg_32(hw_timrot_running_count2)
+	mxs_reg_32(hw_timrot_fixed_count2)
+	mxs_reg_32(hw_timrot_match_count2)
+	mxs_reg_32(hw_timrot_timctrl3)
+	mxs_reg_32(hw_timrot_running_count3)
+	mxs_reg_32(hw_timrot_fixed_count3)
+	mxs_reg_32(hw_timrot_match_count3)
+	mxs_reg_32(hw_timrot_version)
 };
 #endif
 

index 0291d81..5dd5125 100644
@@ -24,16 +24,16 @@
 #define __REGS_USBPHY_H__
 
 struct mx28_usbphy_regs {
-	mx28_reg_32(hw_usbphy_pwd)
-	mx28_reg_32(hw_usbphy_tx)
-	mx28_reg_32(hw_usbphy_rx)
-	mx28_reg_32(hw_usbphy_ctrl)
-	mx28_reg_32(hw_usbphy_status)
-	mx28_reg_32(hw_usbphy_debug)
-	mx28_reg_32(hw_usbphy_debug0_status)
-	mx28_reg_32(hw_usbphy_debug1)
-	mx28_reg_32(hw_usbphy_version)
-	mx28_reg_32(hw_usbphy_ip)
+	mxs_reg_32(hw_usbphy_pwd)
+	mxs_reg_32(hw_usbphy_tx)
+	mxs_reg_32(hw_usbphy_rx)
+	mxs_reg_32(hw_usbphy_ctrl)
+	mxs_reg_32(hw_usbphy_status)
+	mxs_reg_32(hw_usbphy_debug)
+	mxs_reg_32(hw_usbphy_debug0_status)
+	mxs_reg_32(hw_usbphy_debug1)
+	mxs_reg_32(hw_usbphy_version)
+	mxs_reg_32(hw_usbphy_ip)
 };
 
 #define	USBPHY_PWD_RXPWDRX				(1 << 20)

index e701c64..7337458 100644
@@ -23,11 +23,11 @@
 #ifndef __MX28_H__
 #define __MX28_H__
 
-int mx28_reset_block(struct mx28_register_32 *reg);
-int mx28_wait_mask_set(struct mx28_register_32 *reg,
+int mx28_reset_block(struct mxs_register_32 *reg);
+int mx28_wait_mask_set(struct mxs_register_32 *reg,
 		       uint32_t mask,
 		       int timeout);
-int mx28_wait_mask_clr(struct mx28_register_32 *reg,
+int mx28_wait_mask_clr(struct mxs_register_32 *reg,
 		       uint32_t mask,
 		       int timeout);
 

index 38dbc81..29f19ba 100644
@@ -73,8 +73,8 @@ int gpio_get_value(unsigned gpio)
 {
 	uint32_t bank = PAD_BANK(gpio);
 	uint32_t offset = PINCTRL_DIN(bank);
-	struct mx28_register_32 *reg =
-		(struct mx28_register_32 *)(MXS_PINCTRL_BASE + offset);
+	struct mxs_register_32 *reg =
+		(struct mxs_register_32 *)(MXS_PINCTRL_BASE + offset);
 
 	return (readl(&reg->reg) >> PAD_PIN(gpio)) & 1;
 }

@@ -83,8 +83,8 @@ void gpio_set_value(unsigned gpio, int value)
 {
 	uint32_t bank = PAD_BANK(gpio);
 	uint32_t offset = PINCTRL_DOUT(bank);
-	struct mx28_register_32 *reg =
-		(struct mx28_register_32 *)(MXS_PINCTRL_BASE + offset);
+	struct mxs_register_32 *reg =
+		(struct mxs_register_32 *)(MXS_PINCTRL_BASE + offset);
 
 	if (value)
 		writel(1 << PAD_PIN(gpio), &reg->reg_set);

@@ -96,8 +96,8 @@ int gpio_direction_input(unsigned gpio)
 {
 	uint32_t bank = PAD_BANK(gpio);
 	uint32_t offset = PINCTRL_DOE(bank);
-	struct mx28_register_32 *reg =
-		(struct mx28_register_32 *)(MXS_PINCTRL_BASE + offset);
+	struct mxs_register_32 *reg =
+		(struct mxs_register_32 *)(MXS_PINCTRL_BASE + offset);
 
 	writel(1 << PAD_PIN(gpio), &reg->reg_clr);
 

@@ -108,8 +108,8 @@ int gpio_direction_output(unsigned gpio, int value)
 {
 	uint32_t bank = PAD_BANK(gpio);
 	uint32_t offset = PINCTRL_DOE(bank);
-	struct mx28_register_32 *reg =
-		(struct mx28_register_32 *)(MXS_PINCTRL_BASE + offset);
+	struct mxs_register_32 *reg =
+		(struct mxs_register_32 *)(MXS_PINCTRL_BASE + offset);
 
 	writel(1 << PAD_PIN(gpio), &reg->reg_set);
 

index e1bd37e..f32df51 100644
@@ -75,8 +75,8 @@ int ehci_hcd_init(void)
 
 	int ret;
 	uint32_t usb_base, cap_base;
-	struct mx28_register_32 *digctl_ctrl =
-		(struct mx28_register_32 *)HW_DIGCTL_CTRL;
+	struct mxs_register_32 *digctl_ctrl =
+		(struct mxs_register_32 *)HW_DIGCTL_CTRL;
 	struct mx28_clkctrl_regs *clkctrl_regs =
 		(struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
 

@@ -119,8 +119,8 @@ int ehci_hcd_stop(void)
 {
 	int ret;
 	uint32_t tmp;
-	struct mx28_register_32 *digctl_ctrl =
-		(struct mx28_register_32 *)HW_DIGCTL_CTRL;
+	struct mxs_register_32 *digctl_ctrl =
+		(struct mxs_register_32 *)HW_DIGCTL_CTRL;
 	struct mx28_clkctrl_regs *clkctrl_regs =
 		(struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
 

index 3e29c56..bfea6ab 100644
@@ -43,8 +43,8 @@
 
 static uint32_t mx28_get_pclk(void)
 {
-	struct mx28_clkctrl_regs *clkctrl_regs =
-		(struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
+	struct mxs_clkctrl_regs *clkctrl_regs =
+		(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
 
 	uint32_t clkctrl, clkseq, div;
 	uint8_t clkfrac, frac;

@@ -75,8 +75,8 @@ static uint32_t mx28_get_pclk(void)
 
 static uint32_t mx28_get_hclk(void)
 {
-	struct mx28_clkctrl_regs *clkctrl_regs =
-		(struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
+	struct mxs_clkctrl_regs *clkctrl_regs =
+		(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
 
 	uint32_t div;
 	uint32_t clkctrl;

@@ -93,8 +93,8 @@ static uint32_t mx28_get_hclk(void)
 
 static uint32_t mx28_get_emiclk(void)
 {
-	struct mx28_clkctrl_regs *clkctrl_regs =
-		(struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
+	struct mxs_clkctrl_regs *clkctrl_regs =
+		(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
 
 	uint32_t clkctrl, clkseq, div;
 	uint8_t clkfrac, frac;

@@ -118,8 +118,8 @@ static uint32_t mx28_get_emiclk(void)
 
 static uint32_t mx28_get_gpmiclk(void)
 {
-	struct mx28_clkctrl_regs *clkctrl_regs =
-		(struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
+	struct mxs_clkctrl_regs *clkctrl_regs =
+		(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
 
 	uint32_t clkctrl, clkseq, div;
 	uint8_t clkfrac, frac;

@@ -145,8 +145,8 @@ static uint32_t mx28_get_gpmiclk(void)
  */
 void mx28_set_ioclk(enum mxs_ioclock io, uint32_t freq)
 {
-	struct mx28_clkctrl_regs *clkctrl_regs =
-		(struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
+	struct mxs_clkctrl_regs *clkctrl_regs =
+		(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
 	uint32_t div;
 	int io_reg;
 

@@ -178,8 +178,8 @@ void mx28_set_ioclk(enum mxs_ioclock io, uint32_t freq)
  */
 static uint32_t mx28_get_ioclk(enum mxs_ioclock io)
 {
-	struct mx28_clkctrl_regs *clkctrl_regs =
-		(struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
+	struct mxs_clkctrl_regs *clkctrl_regs =
+		(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
 	uint8_t ret;
 	int io_reg;
 

@@ -199,8 +199,8 @@ static uint32_t mx28_get_ioclk(enum mxs_ioclock io)
  */
 void mx28_set_sspclk(enum mxs_sspclock ssp, uint32_t freq, int xtal)
 {
-	struct mx28_clkctrl_regs *clkctrl_regs =
-		(struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
+	struct mxs_clkctrl_regs *clkctrl_regs =
+		(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
 	uint32_t clk, clkreg;
 
 	if (ssp > MXC_SSPCLK3)

@@ -243,8 +243,8 @@ void mx28_set_sspclk(enum mxs_sspclock ssp, uint32_t freq, int xtal)
  */
 static uint32_t mx28_get_sspclk(enum mxs_sspclock ssp)
 {
-	struct mx28_clkctrl_regs *clkctrl_regs =
-		(struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
+	struct mxs_clkctrl_regs *clkctrl_regs =
+		(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
 	uint32_t clkreg;
 	uint32_t clk, tmp;
 

@@ -273,12 +273,12 @@ static uint32_t mx28_get_sspclk(enum mxs_sspclock ssp)
  */
 void mx28_set_ssp_busclock(unsigned int bus, uint32_t freq)
 {
-	struct mx28_ssp_regs *ssp_regs;
+	struct mxs_ssp_regs *ssp_regs;
 	const uint32_t sspclk = mx28_get_sspclk(bus);
 	uint32_t reg;
 	uint32_t divide, rate, tgtclk;
 
-	ssp_regs = (struct mx28_ssp_regs *)(MXS_SSP0_BASE + (bus * 0x2000));
+	ssp_regs = (struct mxs_ssp_regs *)(MXS_SSP0_BASE + (bus * 0x2000));
 
 	/*
 	 * SSP bit rate = SSPCLK / (CLOCK_DIVIDE * (1 + CLOCK_RATE)),

index 65fcd75..dc271cf 100644
@@ -51,10 +51,10 @@ void reset_cpu(ulong ignored) __attribute__((noreturn));
 
 void reset_cpu(ulong ignored)
 {
-	struct mx28_rtc_regs *rtc_regs =
-		(struct mx28_rtc_regs *)MXS_RTC_BASE;
-	struct mx28_lcdif_regs *lcdif_regs =
-		(struct mx28_lcdif_regs *)MXS_LCDIF_BASE;
+	struct mxs_rtc_regs *rtc_regs =
+		(struct mxs_rtc_regs *)MXS_RTC_BASE;
+	struct mxs_lcdif_regs *lcdif_regs =
+		(struct mxs_lcdif_regs *)MXS_LCDIF_BASE;
 
 	/*
 	 * Shut down the LCD controller as it interferes with BootROM boot mode

@@ -155,8 +155,8 @@ int arch_misc_init(void)
 
 int arch_cpu_init(void)
 {
-	struct mx28_clkctrl_regs *clkctrl_regs =
-		(struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
+	struct mxs_clkctrl_regs *clkctrl_regs =
+		(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
 	extern uint32_t _start;
 
 	mx28_fixup_vt((uint32_t)&_start);

@@ -190,8 +190,8 @@ int arch_cpu_init(void)
 #if defined(CONFIG_DISPLAY_CPUINFO)
 static const char *get_cpu_type(void)
 {
-	struct mx28_digctl_regs *digctl_regs =
-		(struct mx28_digctl_regs *)MXS_DIGCTL_BASE;
+	struct mxs_digctl_regs *digctl_regs =
+		(struct mxs_digctl_regs *)MXS_DIGCTL_BASE;
 
 	switch (readl(&digctl_regs->hw_digctl_chipid) & HW_DIGCTL_CHIPID_MASK) {
 	case HW_DIGCTL_CHIPID_MX28:

@@ -203,8 +203,8 @@ static const char *get_cpu_type(void)
 
 static const char *get_cpu_rev(void)
 {
-	struct mx28_digctl_regs *digctl_regs =
-		(struct mx28_digctl_regs *)MXS_DIGCTL_BASE;
+	struct mxs_digctl_regs *digctl_regs =
+		(struct mxs_digctl_regs *)MXS_DIGCTL_BASE;
 	uint8_t rev = readl(&digctl_regs->hw_digctl_chipid) & 0x000000FF;
 
 	switch (readl(&digctl_regs->hw_digctl_chipid) & HW_DIGCTL_CHIPID_MASK) {

@@ -249,8 +249,8 @@ int do_mx28_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
 #ifdef	CONFIG_CMD_NET
 int cpu_eth_init(bd_t *bis)
 {
-	struct mx28_clkctrl_regs *clkctrl_regs =
-		(struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
+	struct mxs_clkctrl_regs *clkctrl_regs =
+		(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
 
 	/* Turn on ENET clocks */
 	clrbits_le32(&clkctrl_regs->hw_clkctrl_enet,

@@ -291,8 +291,8 @@ void mx28_adjust_mac(int dev_id, unsigned char *mac)
 #define	MXS_OCOTP_MAX_TIMEOUT	1000000
 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
 {
-	struct mx28_ocotp_regs *ocotp_regs =
-		(struct mx28_ocotp_regs *)MXS_OCOTP_BASE;
+	struct mxs_ocotp_regs *ocotp_regs =
+		(struct mxs_ocotp_regs *)MXS_OCOTP_BASE;
 	uint32_t data;
 
 	memset(mac, 0, 6);

index 88a603c..c1df81d 100644
@@ -32,7 +32,7 @@
 
 void mx28_lradc_init(void)
 {
-	struct mx28_lradc_regs *regs = (struct mx28_lradc_regs *)MXS_LRADC_BASE;
+	struct mxs_lradc_regs *regs = (struct mxs_lradc_regs *)MXS_LRADC_BASE;
 
 	writel(LRADC_CTRL0_SFTRST, &regs->hw_lradc_ctrl0_clr);
 	writel(LRADC_CTRL0_CLKGATE, &regs->hw_lradc_ctrl0_clr);

@@ -51,7 +51,7 @@ void mx28_lradc_init(void)
 
 void mx28_lradc_enable_batt_measurement(void)
 {
-	struct mx28_lradc_regs *regs = (struct mx28_lradc_regs *)MXS_LRADC_BASE;
+	struct mxs_lradc_regs *regs = (struct mxs_lradc_regs *)MXS_LRADC_BASE;
 
 	/* Check if the channel is present at all. */
 	if (!(readl(&regs->hw_lradc_status) & LRADC_STATUS_CHANNEL7_PRESENT))

index cca1316..e7ed5e0 100644
@@ -100,8 +100,8 @@ void init_mx28_200mhz_ddr2(void)
 
 void mx28_mem_init_clock(void)
 {
-	struct mx28_clkctrl_regs *clkctrl_regs =
-		(struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
+	struct mxs_clkctrl_regs *clkctrl_regs =
+		(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
 
 	/* Gate EMI clock */
 	writeb(CLKCTRL_FRAC_CLKGATE,

@@ -131,8 +131,8 @@ void mx28_mem_init_clock(void)
 
 void mx28_mem_setup_cpu_and_hbus(void)
 {
-	struct mx28_clkctrl_regs *clkctrl_regs =
-		(struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
+	struct mxs_clkctrl_regs *clkctrl_regs =
+		(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
 
 	/* Set fractional divider for ref_cpu to 480 * 18 / 19 = 454MHz
 	 * and ungate CPU clock */

@@ -163,8 +163,8 @@ void mx28_mem_setup_cpu_and_hbus(void)
 
 void mx28_mem_setup_vdda(void)
 {
-	struct mx28_power_regs *power_regs =
-		(struct mx28_power_regs *)MXS_POWER_BASE;
+	struct mxs_power_regs *power_regs =
+		(struct mxs_power_regs *)MXS_POWER_BASE;
 
 	writel((0xc << POWER_VDDACTRL_TRG_OFFSET) |
 		(0x7 << POWER_VDDACTRL_BO_OFFSET_OFFSET) |

@@ -174,8 +174,8 @@ void mx28_mem_setup_vdda(void)
 
 void mx28_mem_setup_vddd(void)
 {
-	struct mx28_power_regs *power_regs =
-		(struct mx28_power_regs *)MXS_POWER_BASE;
+	struct mxs_power_regs *power_regs =
+		(struct mxs_power_regs *)MXS_POWER_BASE;
 
 	writel((0x1c << POWER_VDDDCTRL_TRG_OFFSET) |
 		(0x7 << POWER_VDDDCTRL_BO_OFFSET_OFFSET) |

@@ -204,10 +204,10 @@ uint32_t mx28_mem_get_size(void)
 
 void mx28_mem_init(void)
 {
-	struct mx28_clkctrl_regs *clkctrl_regs =
-		(struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
-	struct mx28_pinctrl_regs *pinctrl_regs =
-		(struct mx28_pinctrl_regs *)MXS_PINCTRL_BASE;
+	struct mxs_clkctrl_regs *clkctrl_regs =
+		(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
+	struct mxs_pinctrl_regs *pinctrl_regs =
+		(struct mxs_pinctrl_regs *)MXS_PINCTRL_BASE;
 
 	/* Set DDR2 mode */
 	writel(PINCTRL_EMI_DS_CTRL_DDR_MODE_DDR2,

294 lines not on this page · raw message

index 5b73f4a..c4b0f5e 100644
@@ -62,8 +62,8 @@ static inline unsigned long us_to_tick(unsigned long us)
 
 int timer_init(void)
 {
-	struct mx28_timrot_regs *timrot_regs =
-		(struct mx28_timrot_regs *)MXS_TIMROT_BASE;
+	struct mxs_timrot_regs *timrot_regs =
+		(struct mxs_timrot_regs *)MXS_TIMROT_BASE;
 
 	/* Reset Timers and Rotary Encoder module */
 	mx28_reset_block(&timrot_regs->hw_timrot_rotctrl_reg);

@@ -84,8 +84,8 @@ int timer_init(void)
 
 unsigned long long get_ticks(void)
 {
-	struct mx28_timrot_regs *timrot_regs =
-		(struct mx28_timrot_regs *)MXS_TIMROT_BASE;
+	struct mxs_timrot_regs *timrot_regs =
+		(struct mxs_timrot_regs *)MXS_TIMROT_BASE;
 
 	/* Current tick value */
 	uint32_t now = readl(&timrot_regs->hw_timrot_running_count0);

index 7c6bd04..e18e677 100644
@@ -29,7 +29,7 @@
 #include <asm/arch/regs-common.h>
 
 #ifndef	__ASSEMBLY__
-struct mx28_apbh_regs {
+struct mxs_apbh_regs {
 	mxs_reg_32(hw_apbh_ctrl0)
 	mxs_reg_32(hw_apbh_ctrl1)
 	mxs_reg_32(hw_apbh_ctrl2)

index 58517c4..40baa4d 100644
@@ -29,7 +29,7 @@
 #include <asm/arch/regs-common.h>
 
 #ifndef	__ASSEMBLY__
-struct mx28_bch_regs {
+struct mxs_bch_regs {
 	mxs_reg_32(hw_bch_ctrl)
 	mxs_reg_32(hw_bch_status0)
 	mxs_reg_32(hw_bch_mode)

index 127370b..b662fbe 100644
@@ -29,7 +29,7 @@
 #include <asm/arch/regs-common.h>
 
 #ifndef	__ASSEMBLY__
-struct mx28_clkctrl_regs {
+struct mxs_clkctrl_regs {
 	mxs_reg_32(hw_clkctrl_pll0ctrl0)	/* 0x00 */
 	mxs_reg_32(hw_clkctrl_pll0ctrl1)	/* 0x10 */
 	mxs_reg_32(hw_clkctrl_pll1ctrl0)	/* 0x20 */

index 5e4f564..e7cc4b4 100644
@@ -25,7 +25,7 @@
 #include <asm/arch/regs-common.h>
 
 #ifndef	__ASSEMBLY__
-struct mx28_digctl_regs {
+struct mxs_digctl_regs {
 	mxs_reg_32(hw_digctl_ctrl)				/* 0x000 */
 	mxs_reg_32(hw_digctl_status)				/* 0x010 */
 	mxs_reg_32(hw_digctl_hclkcount)			/* 0x020 */

index 190a570..624d618 100644
@@ -29,7 +29,7 @@
 #include <asm/arch/regs-common.h>
 
 #ifndef	__ASSEMBLY__
-struct mx28_gpmi_regs {
+struct mxs_gpmi_regs {
 	mxs_reg_32(hw_gpmi_ctrl0)
 	mxs_reg_32(hw_gpmi_compare)
 	mxs_reg_32(hw_gpmi_eccctrl)

index 418a3c0..067cfd3 100644
@@ -26,7 +26,7 @@
 #include <asm/arch/regs-common.h>
 
 #ifndef	__ASSEMBLY__
-struct mx28_i2c_regs {
+struct mxs_i2c_regs {
 	mxs_reg_32(hw_i2c_ctrl0)
 	mxs_reg_32(hw_i2c_timing0)
 	mxs_reg_32(hw_i2c_timing1)

index 87bfa0d..b90b2d4 100644
@@ -29,7 +29,7 @@
 #include <asm/arch/regs-common.h>
 
 #ifndef	__ASSEMBLY__
-struct mx28_lcdif_regs {
+struct mxs_lcdif_regs {
 	mxs_reg_32(hw_lcdif_ctrl)		/* 0x00 */
 	mxs_reg_32(hw_lcdif_ctrl1)		/* 0x10 */
 	mxs_reg_32(hw_lcdif_ctrl2)		/* 0x20 */

index 0054c23..28d8382 100644
@@ -29,7 +29,7 @@
 #include <asm/arch/regs-common.h>
 
 #ifndef	__ASSEMBLY__
-struct mx28_lradc_regs {
+struct mxs_lradc_regs {
 	mxs_reg_32(hw_lradc_ctrl0);
 	mxs_reg_32(hw_lradc_ctrl1);
 	mxs_reg_32(hw_lradc_ctrl2);

index a2ac6a2..3269892 100644
@@ -29,7 +29,7 @@
 #include <asm/arch/regs-common.h>
 
 #ifndef	__ASSEMBLY__
-struct mx28_ocotp_regs {
+struct mxs_ocotp_regs {
 	mxs_reg_32(hw_ocotp_ctrl)	/* 0x0 */
 	mxs_reg_32(hw_ocotp_data)	/* 0x10 */
 	mxs_reg_32(hw_ocotp_cust0)	/* 0x20 */

index ca1d791..d584170 100644
@@ -29,7 +29,7 @@
 #include <asm/arch/regs-common.h>
 
 #ifndef	__ASSEMBLY__
-struct mx28_pinctrl_regs {
+struct mxs_pinctrl_regs {
 	mxs_reg_32(hw_pinctrl_ctrl)		/* 0x0 */
 
 	uint32_t	reserved1[60];

index 3c9e3b0..a46a372 100644
@@ -25,7 +25,7 @@
 #include <asm/arch/regs-common.h>
 
 #ifndef	__ASSEMBLY__
-struct mx28_power_regs {
+struct mxs_power_regs {
 	mxs_reg_32(hw_power_ctrl)
 	mxs_reg_32(hw_power_5vctrl)
 	mxs_reg_32(hw_power_minpwr)

index 0b660ae..6b2dd33 100644
@@ -26,7 +26,7 @@
 #include <asm/arch/regs-common.h>
 
 #ifndef	__ASSEMBLY__
-struct mx28_rtc_regs {
+struct mxs_rtc_regs {
 	mxs_reg_32(hw_rtc_ctrl)
 	mxs_reg_32(hw_rtc_stat)
 	mxs_reg_32(hw_rtc_milliseconds)

index 85b9894..cf52a28 100644
@@ -28,7 +28,7 @@
 #include <asm/arch/regs-common.h>
 
 #ifndef	__ASSEMBLY__
-struct mx28_ssp_regs {
+struct mxs_ssp_regs {
 	mxs_reg_32(hw_ssp_ctrl0)
 	mxs_reg_32(hw_ssp_cmd0)
 	mxs_reg_32(hw_ssp_cmd1)

index 332654f..529a3bc 100644
@@ -28,7 +28,7 @@
 #include <asm/arch/regs-common.h>
 
 #ifndef	__ASSEMBLY__
-struct mx28_timrot_regs {
+struct mxs_timrot_regs {
 	mxs_reg_32(hw_timrot_rotctrl)
 	mxs_reg_32(hw_timrot_rotcount)
 	mxs_reg_32(hw_timrot_timctrl0)

index ea61de8..d8bcd77 100644
@@ -23,7 +23,7 @@
 #ifndef __REGS_USB_H__
 #define __REGS_USB_H__
 
-struct mx28_usb_regs {
+struct mxs_usb_regs {
 	uint32_t		hw_usbctrl_id;			/* 0x000 */
 	uint32_t		hw_usbctrl_hwgeneral;		/* 0x004 */
 	uint32_t		hw_usbctrl_hwhost;		/* 0x008 */

index 5dd5125..288e8fa 100644
@@ -23,7 +23,7 @@
 #ifndef __REGS_USBPHY_H__
 #define __REGS_USBPHY_H__
 
-struct mx28_usbphy_regs {
+struct mxs_usbphy_regs {
 	mxs_reg_32(hw_usbphy_pwd)
 	mxs_reg_32(hw_usbphy_tx)
 	mxs_reg_32(hw_usbphy_rx)

index 3d28ea8..74da3ea 100644
@@ -122,8 +122,8 @@ int fecmxc_mii_postcall(int phy)
 
 int board_eth_init(bd_t *bis)
 {
-	struct mx28_clkctrl_regs *clkctrl_regs =
-		(struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
+	struct mxs_clkctrl_regs *clkctrl_regs =
+		(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
 	struct eth_device *dev;
 	int ret;
 

index 1bc83e9..1320277 100644
@@ -115,8 +115,8 @@ int fecmxc_mii_postcall(int phy)
 
 int board_eth_init(bd_t *bis)
 {
-	struct mx28_clkctrl_regs *clkctrl_regs =
-		(struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
+	struct mxs_clkctrl_regs *clkctrl_regs =
+		(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
 	struct eth_device *dev;
 	int ret;
 

index cb2193e..38eff4f 100644
@@ -76,8 +76,8 @@ static unsigned int mxs_dma_cmd_address(struct mxs_dma_desc *desc)
  */
 static int mxs_dma_read_semaphore(int channel)
 {
-	struct mx28_apbh_regs *apbh_regs =
-		(struct mx28_apbh_regs *)MXS_APBH_BASE;
+	struct mxs_apbh_regs *apbh_regs =
+		(struct mxs_apbh_regs *)MXS_APBH_BASE;
 	uint32_t tmp;
 	int ret;
 

@@ -119,8 +119,8 @@ inline void mxs_dma_flush_desc(struct mxs_dma_desc *desc) {}
  */
 static int mxs_dma_enable(int channel)
 {
-	struct mx28_apbh_regs *apbh_regs =
-		(struct mx28_apbh_regs *)MXS_APBH_BASE;
+	struct mxs_apbh_regs *apbh_regs =
+		(struct mxs_apbh_regs *)MXS_APBH_BASE;
 	unsigned int sem;
 	struct mxs_dma_chan *pchan;
 	struct mxs_dma_desc *pdesc;

@@ -191,8 +191,8 @@ static int mxs_dma_enable(int channel)
 static int mxs_dma_disable(int channel)
 {
 	struct mxs_dma_chan *pchan;
-	struct mx28_apbh_regs *apbh_regs =
-		(struct mx28_apbh_regs *)MXS_APBH_BASE;
+	struct mxs_apbh_regs *apbh_regs =
+		(struct mxs_apbh_regs *)MXS_APBH_BASE;
 	int ret;
 
 	ret = mxs_dma_validate_chan(channel);

@@ -220,8 +220,8 @@ static int mxs_dma_disable(int channel)
  */
 static int mxs_dma_reset(int channel)
 {
-	struct mx28_apbh_regs *apbh_regs =
-		(struct mx28_apbh_regs *)MXS_APBH_BASE;
+	struct mxs_apbh_regs *apbh_regs =
+		(struct mxs_apbh_regs *)MXS_APBH_BASE;
 	int ret;
 
 	ret = mxs_dma_validate_chan(channel);

@@ -241,8 +241,8 @@ static int mxs_dma_reset(int channel)
  */
 static int mxs_dma_enable_irq(int channel, int enable)
 {
-	struct mx28_apbh_regs *apbh_regs =
-		(struct mx28_apbh_regs *)MXS_APBH_BASE;
+	struct mxs_apbh_regs *apbh_regs =
+		(struct mxs_apbh_regs *)MXS_APBH_BASE;
 	int ret;
 
 	ret = mxs_dma_validate_chan(channel);

@@ -267,8 +267,8 @@ static int mxs_dma_enable_irq(int channel, int enable)
  */
 static int mxs_dma_ack_irq(int channel)
 {
-	struct mx28_apbh_regs *apbh_regs =
-		(struct mx28_apbh_regs *)MXS_APBH_BASE;
+	struct mxs_apbh_regs *apbh_regs =
+		(struct mxs_apbh_regs *)MXS_APBH_BASE;
 	int ret;
 
 	ret = mxs_dma_validate_chan(channel);

@@ -504,8 +504,8 @@ static int mxs_dma_finish(int channel, struct list_head *head)
  */
 static int mxs_dma_wait_complete(uint32_t timeout, unsigned int chan)
 {
-	struct mx28_apbh_regs *apbh_regs =
-		(struct mx28_apbh_regs *)MXS_APBH_BASE;
+	struct mxs_apbh_regs *apbh_regs =
+		(struct mxs_apbh_regs *)MXS_APBH_BASE;
 	int ret;
 
 	ret = mxs_dma_validate_chan(chan);

@@ -554,8 +554,8 @@ int mxs_dma_go(int chan)
  */
 void mxs_dma_init(void)
 {
-	struct mx28_apbh_regs *apbh_regs =
-		(struct mx28_apbh_regs *)MXS_APBH_BASE;
+	struct mxs_apbh_regs *apbh_regs =
+		(struct mxs_apbh_regs *)MXS_APBH_BASE;
 
 	mx28_reset_block(&apbh_regs->hw_apbh_ctrl0_reg);
 

index 48aaaa6..5d61d7a 100644
@@ -38,7 +38,7 @@
 
 void mxs_i2c_reset(void)
 {
-	struct mx28_i2c_regs *i2c_regs = (struct mx28_i2c_regs *)MXS_I2C0_BASE;
+	struct mxs_i2c_regs *i2c_regs = (struct mxs_i2c_regs *)MXS_I2C0_BASE;
 	int ret;
 
 	ret = mx28_reset_block(&i2c_regs->hw_i2c_ctrl0_reg);

@@ -57,7 +57,7 @@ void mxs_i2c_reset(void)
 
 void mxs_i2c_setup_read(uint8_t chip, int len)
 {
-	struct mx28_i2c_regs *i2c_regs = (struct mx28_i2c_regs *)MXS_I2C0_BASE;
+	struct mxs_i2c_regs *i2c_regs = (struct mxs_i2c_regs *)MXS_I2C0_BASE;
 
 	writel(I2C_QUEUECMD_RETAIN_CLOCK | I2C_QUEUECMD_PRE_SEND_START |
 		I2C_QUEUECMD_MASTER_MODE | I2C_QUEUECMD_DIRECTION |

@@ -76,7 +76,7 @@ void mxs_i2c_setup_read(uint8_t chip, int len)
 void mxs_i2c_write(uchar chip, uint addr, int alen,
 			uchar *buf, int blen, int stop)
 {
-	struct mx28_i2c_regs *i2c_regs = (struct mx28_i2c_regs *)MXS_I2C0_BASE;
+	struct mxs_i2c_regs *i2c_regs = (struct mxs_i2c_regs *)MXS_I2C0_BASE;
 	uint32_t data;
 	int i, remain, off;
 

@@ -119,7 +119,7 @@ void mxs_i2c_write(uchar chip, uint addr, int alen,
 
 int mxs_i2c_wait_for_ack(void)
 {
-	struct mx28_i2c_regs *i2c_regs = (struct mx28_i2c_regs *)MXS_I2C0_BASE;
+	struct mxs_i2c_regs *i2c_regs = (struct mxs_i2c_regs *)MXS_I2C0_BASE;
 	uint32_t tmp;
 	int timeout = MXS_I2C_MAX_TIMEOUT;
 

@@ -157,7 +157,7 @@ err:
 
 int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
 {
-	struct mx28_i2c_regs *i2c_regs = (struct mx28_i2c_regs *)MXS_I2C0_BASE;
+	struct mxs_i2c_regs *i2c_regs = (struct mxs_i2c_regs *)MXS_I2C0_BASE;
 	uint32_t tmp = 0;
 	int ret;
 	int i;

@@ -212,7 +212,7 @@ int i2c_probe(uchar chip)
 
 void i2c_init(int speed, int slaveadd)
 {
-	struct mx28_i2c_regs *i2c_regs = (struct mx28_i2c_regs *)MXS_I2C0_BASE;
+	struct mxs_i2c_regs *i2c_regs = (struct mxs_i2c_regs *)MXS_I2C0_BASE;
 
 	mxs_i2c_reset();
 

index 4187a94..b7ad9ca 100644
@@ -52,7 +52,7 @@
 
 struct mxsmmc_priv {
 	int			id;
-	struct mx28_ssp_regs	*regs;
+	struct mxs_ssp_regs	*regs;
 	uint32_t		clkseq_bypass;
 	uint32_t		*clkctrl_ssp;
 	uint32_t		buswidth;

@@ -70,7 +70,7 @@ static int
 mxsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
 {
 	struct mxsmmc_priv *priv = (struct mxsmmc_priv *)mmc->priv;
-	struct mx28_ssp_regs *ssp_regs = priv->regs;
+	struct mxs_ssp_regs *ssp_regs = priv->regs;
 	uint32_t reg;
 	int timeout;
 	uint32_t data_count;

@@ -282,7 +282,7 @@ mxsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
 static void mxsmmc_set_ios(struct mmc *mmc)
 {
 	struct mxsmmc_priv *priv = (struct mxsmmc_priv *)mmc->priv;
-	struct mx28_ssp_regs *ssp_regs = priv->regs;
+	struct mxs_ssp_regs *ssp_regs = priv->regs;
 
 	/* Set the clock speed */
 	if (mmc->clock)

@@ -311,7 +311,7 @@ static void mxsmmc_set_ios(struct mmc *mmc)
 static int mxsmmc_init(struct mmc *mmc)
 {
 	struct mxsmmc_priv *priv = (struct mxsmmc_priv *)mmc->priv;
-	struct mx28_ssp_regs *ssp_regs = priv->regs;
+	struct mxs_ssp_regs *ssp_regs = priv->regs;
 
 	/* Reset SSP */
 	mx28_reset_block(&ssp_regs->hw_ssp_ctrl0_reg);

@@ -335,8 +335,8 @@ static int mxsmmc_init(struct mmc *mmc)
 
 int mxsmmc_initialize(bd_t *bis, int id, int (*wp)(int))
 {
-	struct mx28_clkctrl_regs *clkctrl_regs =
-		(struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
+	struct mxs_clkctrl_regs *clkctrl_regs =
+		(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
 	struct mmc *mmc = NULL;
 	struct mxsmmc_priv *priv = NULL;
 	int ret;

@@ -366,22 +366,22 @@ int mxsmmc_initialize(bd_t *bis, int id, int (*wp)(int))
 	priv->id = id;
 	switch (id) {
 	case 0:
-		priv->regs = (struct mx28_ssp_regs *)MXS_SSP0_BASE;
+		priv->regs = (struct mxs_ssp_regs *)MXS_SSP0_BASE;
 		priv->clkseq_bypass = CLKCTRL_CLKSEQ_BYPASS_SSP0;
 		priv->clkctrl_ssp = &clkctrl_regs->hw_clkctrl_ssp0;
 		break;
 	case 1:
-		priv->regs = (struct mx28_ssp_regs *)MXS_SSP1_BASE;
+		priv->regs = (struct mxs_ssp_regs *)MXS_SSP1_BASE;
 		priv->clkseq_bypass = CLKCTRL_CLKSEQ_BYPASS_SSP1;
 		priv->clkctrl_ssp = &clkctrl_regs->hw_clkctrl_ssp1;
 		break;
 	case 2:
-		priv->regs = (struct mx28_ssp_regs *)MXS_SSP2_BASE;
+		priv->regs = (struct mxs_ssp_regs *)MXS_SSP2_BASE;
 		priv->clkseq_bypass = CLKCTRL_CLKSEQ_BYPASS_SSP2;
 		priv->clkctrl_ssp = &clkctrl_regs->hw_clkctrl_ssp2;
 		break;
 	case 3:
-		priv->regs = (struct mx28_ssp_regs *)MXS_SSP3_BASE;
+		priv->regs = (struct mxs_ssp_regs *)MXS_SSP3_BASE;
 		priv->clkseq_bypass = CLKCTRL_CLKSEQ_BYPASS_SSP3;
 		priv->clkctrl_ssp = &clkctrl_regs->hw_clkctrl_ssp3;
 		break;

index 9c95811..807c9fd 100644
@@ -233,7 +233,7 @@ static uint32_t mxs_nand_mark_bit_offset(struct mtd_info *mtd)
  */
 static int mxs_nand_wait_for_bch_complete(void)
 {
-	struct mx28_bch_regs *bch_regs = (struct mx28_bch_regs *)MXS_BCH_BASE;
+	struct mxs_bch_regs *bch_regs = (struct mxs_bch_regs *)MXS_BCH_BASE;
 	int timeout = MXS_NAND_BCH_TIMEOUT;
 	int ret;
 

@@ -338,8 +338,8 @@ static int mxs_nand_device_ready(struct mtd_info *mtd)
 {
 	struct nand_chip *chip = mtd->priv;
 	struct mxs_nand_info *nand_info = chip->priv;
-	struct mx28_gpmi_regs *gpmi_regs =
-		(struct mx28_gpmi_regs *)MXS_GPMI_BASE;
+	struct mxs_gpmi_regs *gpmi_regs =
+		(struct mxs_gpmi_regs *)MXS_GPMI_BASE;
 	uint32_t tmp;
 
 	tmp = readl(&gpmi_regs->hw_gpmi_stat);

@@ -968,7 +968,7 @@ static int mxs_nand_scan_bbt(struct mtd_info *mtd)
 {
 	struct nand_chip *nand = mtd->priv;
 	struct mxs_nand_info *nand_info = nand->priv;
-	struct mx28_bch_regs *bch_regs = (struct mx28_bch_regs *)MXS_BCH_BASE;
+	struct mxs_bch_regs *bch_regs = (struct mxs_bch_regs *)MXS_BCH_BASE;
 	uint32_t tmp;
 
 	/* Configure BCH and set NFC geometry */

@@ -1056,8 +1056,8 @@ int mxs_nand_alloc_buffers(struct mxs_nand_info *nand_info)
  */
 int mxs_nand_init(struct mxs_nand_info *info)
 {
-	struct mx28_gpmi_regs *gpmi_regs =
-		(struct mx28_gpmi_regs *)MXS_GPMI_BASE;
+	struct mxs_gpmi_regs *gpmi_regs =
+		(struct mxs_gpmi_regs *)MXS_GPMI_BASE;
 	int i = 0, j;
 
 	info->desc = malloc(sizeof(struct mxs_dma_desc *) *

index 5beb1a0..72f7400 100644
@@ -31,7 +31,7 @@
 /* Set time in seconds since 1970-01-01 */
 int mxs_rtc_set_time(uint32_t secs)
 {
-	struct mx28_rtc_regs *rtc_regs = (struct mx28_rtc_regs *)MXS_RTC_BASE;
+	struct mxs_rtc_regs *rtc_regs = (struct mxs_rtc_regs *)MXS_RTC_BASE;
 	int ret;
 
 	writel(secs, &rtc_regs->hw_rtc_seconds);

@@ -52,7 +52,7 @@ int mxs_rtc_set_time(uint32_t secs)
 
 int rtc_get(struct rtc_time *time)
 {
-	struct mx28_rtc_regs *rtc_regs = (struct mx28_rtc_regs *)MXS_RTC_BASE;
+	struct mxs_rtc_regs *rtc_regs = (struct mxs_rtc_regs *)MXS_RTC_BASE;
 	uint32_t secs;
 
 	secs = readl(&rtc_regs->hw_rtc_seconds);

@@ -73,7 +73,7 @@ int rtc_set(struct rtc_time *time)
 
 void rtc_reset(void)
 {
-	struct mx28_rtc_regs *rtc_regs = (struct mx28_rtc_regs *)MXS_RTC_BASE;
+	struct mxs_rtc_regs *rtc_regs = (struct mxs_rtc_regs *)MXS_RTC_BASE;
 	int ret;
 
 	/* Set time to 1970-01-01 */

index 4ff8474..bd834fb 100644
@@ -55,7 +55,7 @@ struct mxs_spi_slave {
 	struct spi_slave	slave;
 	uint32_t		max_khz;
 	uint32_t		mode;
-	struct mx28_ssp_regs	*regs;
+	struct mxs_ssp_regs	*regs;
 	struct mxs_dma_desc	*desc;
 };
 

@@ -82,7 +82,7 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
 {
 	struct mxs_spi_slave *mxs_slave;
 	uint32_t addr;
-	struct mx28_ssp_regs *ssp_regs;
+	struct mxs_ssp_regs *ssp_regs;
 	int reg;
 	struct mxs_dma_desc *desc;
 

@@ -108,7 +108,7 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
 	mxs_slave->slave.cs = cs;
 	mxs_slave->max_khz = max_hz / 1000;
 	mxs_slave->mode = mode;
-	mxs_slave->regs = (struct mx28_ssp_regs *)addr;
+	mxs_slave->regs = (struct mxs_ssp_regs *)addr;
 	mxs_slave->desc = desc;
 	ssp_regs = mxs_slave->regs;
 

@@ -136,7 +136,7 @@ void spi_free_slave(struct spi_slave *slave)
 int spi_claim_bus(struct spi_slave *slave)
 {
 	struct mxs_spi_slave *mxs_slave = to_mxs_slave(slave);
-	struct mx28_ssp_regs *ssp_regs = mxs_slave->regs;
+	struct mxs_ssp_regs *ssp_regs = mxs_slave->regs;
 	uint32_t reg = 0;
 
 	mx28_reset_block(&ssp_regs->hw_ssp_ctrl0_reg);

@@ -159,13 +159,13 @@ void spi_release_bus(struct spi_slave *slave)
 {
 }
 
-static void mxs_spi_start_xfer(struct mx28_ssp_regs *ssp_regs)
+static void mxs_spi_start_xfer(struct mxs_ssp_regs *ssp_regs)
 {
 	writel(SSP_CTRL0_LOCK_CS, &ssp_regs->hw_ssp_ctrl0_set);
 	writel(SSP_CTRL0_IGNORE_CRC, &ssp_regs->hw_ssp_ctrl0_clr);
 }
 
-static void mxs_spi_end_xfer(struct mx28_ssp_regs *ssp_regs)
+static void mxs_spi_end_xfer(struct mxs_ssp_regs *ssp_regs)
 {
 	writel(SSP_CTRL0_LOCK_CS, &ssp_regs->hw_ssp_ctrl0_clr);
 	writel(SSP_CTRL0_IGNORE_CRC, &ssp_regs->hw_ssp_ctrl0_set);

@@ -174,7 +174,7 @@ static void mxs_spi_end_xfer(struct mx28_ssp_regs *ssp_regs)
 static int mxs_spi_xfer_pio(struct mxs_spi_slave *slave,
 			char *data, int length, int write, unsigned long flags)
 {
-	struct mx28_ssp_regs *ssp_regs = slave->regs;
+	struct mxs_ssp_regs *ssp_regs = slave->regs;
 
 	if (flags & SPI_XFER_BEGIN)
 		mxs_spi_start_xfer(ssp_regs);

@@ -223,14 +223,13 @@ static int mxs_spi_xfer_pio(struct mxs_spi_slave *slave,
 	}
 
 	return 0;
-
 }
 
 static int mxs_spi_xfer_dma(struct mxs_spi_slave *slave,
 			char *data, int length, int write, unsigned long flags)
 {
 	struct mxs_dma_desc *desc = slave->desc;
-	struct mx28_ssp_regs *ssp_regs = slave->regs;
+	struct mxs_ssp_regs *ssp_regs = slave->regs;
 	uint32_t ctrl0 = SSP_CTRL0_DATA_XFER;
 	uint32_t cache_data_count;
 	int dmach;

@@ -289,7 +288,7 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
 		const void *dout, void *din, unsigned long flags)
 {
 	struct mxs_spi_slave *mxs_slave = to_mxs_slave(slave);
-	struct mx28_ssp_regs *ssp_regs = mxs_slave->regs;
+	struct mxs_ssp_regs *ssp_regs = mxs_slave->regs;
 	int len = bitlen / 8;
 	char dummy;
 	int write = 0;

index f32df51..e263747 100644
@@ -39,8 +39,8 @@
 #endif
 
 static struct ehci_mxs {
-	struct mx28_usb_regs	*usb_regs;
-	struct mx28_usbphy_regs	*phy_regs;
+	struct mxs_usb_regs	*usb_regs;
+	struct mxs_usbphy_regs	*phy_regs;
 } ehci_mxs;
 
 int mxs_ehci_get_port(struct ehci_mxs *mxs_usb, int port)

@@ -60,8 +60,8 @@ int mxs_ehci_get_port(struct ehci_mxs *mxs_usb, int port)
 		return -1;
 	}
 
-	mxs_usb->usb_regs = (struct mx28_usb_regs *)usb_base;
-	mxs_usb->phy_regs = (struct mx28_usbphy_regs *)phy_base;
+	mxs_usb->usb_regs = (struct mxs_usb_regs *)usb_base;
+	mxs_usb->phy_regs = (struct mxs_usbphy_regs *)phy_base;
 	return 0;
 }
 

@@ -77,8 +77,8 @@ int ehci_hcd_init(void)
 	uint32_t usb_base, cap_base;
 	struct mxs_register_32 *digctl_ctrl =
 		(struct mxs_register_32 *)HW_DIGCTL_CTRL;
-	struct mx28_clkctrl_regs *clkctrl_regs =
-		(struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
+	struct mxs_clkctrl_regs *clkctrl_regs =
+		(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
 
 	ret = mxs_ehci_get_port(&ehci_mxs, CONFIG_EHCI_MXS_PORT);
 	if (ret)

@@ -121,8 +121,8 @@ int ehci_hcd_stop(void)
 	uint32_t tmp;
 	struct mxs_register_32 *digctl_ctrl =
 		(struct mxs_register_32 *)HW_DIGCTL_CTRL;
-	struct mx28_clkctrl_regs *clkctrl_regs =
-		(struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
+	struct mxs_clkctrl_regs *clkctrl_regs =
+		(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
 
 	ret = mxs_ehci_get_port(&ehci_mxs, CONFIG_EHCI_MXS_PORT);
 	if (ret)

index dc271cf..a61f75b 100644
@@ -222,8 +222,8 @@ static const char *get_cpu_rev(void)
 
 int print_cpuinfo(void)
 {
-	struct mx28_spl_data *data = (struct mx28_spl_data *)
-		((CONFIG_SYS_TEXT_BASE - sizeof(struct mx28_spl_data)) & ~0xf);
+	struct mxs_spl_data *data = (struct mxs_spl_data *)
+		((CONFIG_SYS_TEXT_BASE - sizeof(struct mxs_spl_data)) & ~0xf);
 
 	printf("CPU:   Freescale i.MX%s rev%s at %d MHz\n",
 		get_cpu_type(),

@@ -322,8 +322,8 @@ void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
 
 int mx28_dram_init(void)
 {
-	struct mx28_spl_data *data = (struct mx28_spl_data *)
-		((CONFIG_SYS_TEXT_BASE - sizeof(struct mx28_spl_data)) & ~0xf);
+	struct mxs_spl_data *data = (struct mxs_spl_data *)
+		((CONFIG_SYS_TEXT_BASE - sizeof(struct mxs_spl_data)) & ~0xf);
 
 	if (data->mem_dram_size == 0) {
 		printf("MX28:\n"

similarity index 81%
rename from arch/arm/cpu/arm926ejs/mxs/mx28_init.h
rename to arch/arm/cpu/arm926ejs/mxs/mxs_init.h
index e3a4493..2ddc5bc 100644
@@ -28,18 +28,18 @@
 
 void early_delay(int delay);
 
-void mx28_power_init(void);
+void mxs_power_init(void);
 
 #ifdef	CONFIG_SPL_MX28_PSWITCH_WAIT
-void mx28_power_wait_pswitch(void);
+void mxs_power_wait_pswitch(void);
 #else
-static inline void mx28_power_wait_pswitch(void) { }
+static inline void mxs_power_wait_pswitch(void) { }
 #endif
 
-void mx28_mem_init(void);
-uint32_t mx28_mem_get_size(void);
+void mxs_mem_init(void);
+uint32_t mxs_mem_get_size(void);
 
-void mx28_lradc_init(void);
-void mx28_lradc_enable_batt_measurement(void);
+void mxs_lradc_init(void);
+void mxs_lradc_enable_batt_measurement(void);
 
 #endif	/* __M28_INIT_H__ */

index a6dfca3..46f6770 100644
@@ -31,7 +31,7 @@
 #include <asm/arch/sys_proto.h>
 #include <asm/gpio.h>
 
-#include "mx28_init.h"
+#include "mxs_init.h"
 
 /*
  * This delay function is intended to be used only in early stage of boot, where

@@ -58,7 +58,7 @@ const iomux_cfg_t iomux_boot[] = {
 	MX28_PAD_LCD_D05__GPIO_1_5 | MUX_CONFIG_BOOTMODE_PAD,
 };
 
-uint8_t mx28_get_bootmode_index(void)
+uint8_t mxs_get_bootmode_index(void)
 {
 	uint8_t bootmode = 0;
 	int i;

@@ -92,22 +92,22 @@ uint8_t mx28_get_bootmode_index(void)
 	return i;
 }
 
-void mx28_common_spl_init(const iomux_cfg_t *iomux_setup,
+void mxs_common_spl_init(const iomux_cfg_t *iomux_setup,
 			const unsigned int iomux_size)
 {
-	struct mx28_spl_data *data = (struct mx28_spl_data *)
-		((CONFIG_SYS_TEXT_BASE - sizeof(struct mx28_spl_data)) & ~0xf);
-	uint8_t bootmode = mx28_get_bootmode_index();
+	struct mxs_spl_data *data = (struct mxs_spl_data *)
+		((CONFIG_SYS_TEXT_BASE - sizeof(struct mxs_spl_data)) & ~0xf);
+	uint8_t bootmode = mxs_get_bootmode_index();
 
 	mxs_iomux_setup_multiple_pads(iomux_setup, iomux_size);
-	mx28_power_init();
+	mxs_power_init();
 
-	mx28_mem_init();
-	data->mem_dram_size = mx28_mem_get_size();
+	mxs_mem_init();
+	data->mem_dram_size = mxs_mem_get_size();
 
 	data->boot_mode_idx = bootmode;
 
-	mx28_power_wait_pswitch();
+	mxs_power_wait_pswitch();
 }
 
 /* Support aparatus */

index c1df81d..d90f0a1 100644
@@ -28,9 +28,9 @@
 #include <asm/io.h>
 #include <asm/arch/imx-regs.h>
 
-#include "mx28_init.h"
+#include "mxs_init.h"
 
-void mx28_lradc_init(void)
+void mxs_lradc_init(void)
 {
 	struct mxs_lradc_regs *regs = (struct mxs_lradc_regs *)MXS_LRADC_BASE;
 

@@ -49,7 +49,7 @@ void mx28_lradc_init(void)
 			LRADC_CTRL4_LRADC6SELECT_CHANNEL10);
 }
 
-void mx28_lradc_enable_batt_measurement(void)
+void mxs_lradc_enable_batt_measurement(void)
 {
 	struct mxs_lradc_regs *regs = (struct mxs_lradc_regs *)MXS_LRADC_BASE;
 

index e7ed5e0..88d1abe 100644
@@ -29,7 +29,7 @@
 #include <asm/arch/iomux-mx28.h>
 #include <asm/arch/imx-regs.h>
 
-#include "mx28_init.h"
+#include "mxs_init.h"
 
 static uint32_t mx28_dram_vals[] = {
 	0x00000000, 0x00000000, 0x00000000, 0x00000000,

@@ -82,23 +82,23 @@ static uint32_t mx28_dram_vals[] = {
 	0x00000000, 0x00010001
 };
 
-void __mx28_adjust_memory_params(uint32_t *dram_vals)
+void __mxs_adjust_memory_params(uint32_t *dram_vals)
 {
 }
-void mx28_adjust_memory_params(uint32_t *dram_vals)
-	__attribute__((weak, alias("__mx28_adjust_memory_params")));
+void mxs_adjust_memory_params(uint32_t *dram_vals)
+	__attribute__((weak, alias("__mxs_adjust_memory_params")));
 
 void init_mx28_200mhz_ddr2(void)
 {
 	int i;
 
-	mx28_adjust_memory_params(mx28_dram_vals);
+	mxs_adjust_memory_params(mx28_dram_vals);
 
 	for (i = 0; i < ARRAY_SIZE(mx28_dram_vals); i++)
 		writel(mx28_dram_vals[i], MXS_DRAM_BASE + (4 * i));
 }
 
-void mx28_mem_init_clock(void)
+void mxs_mem_init_clock(void)
 {
 	struct mxs_clkctrl_regs *clkctrl_regs =
 		(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;

@@ -129,7 +129,7 @@ void mx28_mem_init_clock(void)
 	early_delay(10000);
 }
 
-void mx28_mem_setup_cpu_and_hbus(void)
+void mxs_mem_setup_cpu_and_hbus(void)
 {
 	struct mxs_clkctrl_regs *clkctrl_regs =
 		(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;

@@ -161,7 +161,7 @@ void mx28_mem_setup_cpu_and_hbus(void)
 	early_delay(15000);
 }
 
-void mx28_mem_setup_vdda(void)
+void mxs_mem_setup_vdda(void)
 {
 	struct mxs_power_regs *power_regs =
 		(struct mxs_power_regs *)MXS_POWER_BASE;

@@ -172,7 +172,7 @@ void mx28_mem_setup_vdda(void)
 		&power_regs->hw_power_vddactrl);
 }
 
-void mx28_mem_setup_vddd(void)
+void mxs_mem_setup_vddd(void)
 {
 	struct mxs_power_regs *power_regs =
 		(struct mxs_power_regs *)MXS_POWER_BASE;

@@ -183,7 +183,7 @@ void mx28_mem_setup_vddd(void)
 		&power_regs->hw_power_vdddctrl);
 }
 
-uint32_t mx28_mem_get_size(void)
+uint32_t mxs_mem_get_size(void)
 {
 	uint32_t sz, da;
 	uint32_t *vt = (uint32_t *)0x20;

@@ -202,7 +202,7 @@ uint32_t mx28_mem_get_size(void)
 	return sz;
 }
 
-void mx28_mem_init(void)
+void mxs_mem_init(void)
 {
 	struct mxs_clkctrl_regs *clkctrl_regs =
 		(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;

@@ -219,9 +219,9 @@ void mx28_mem_init(void)
 
 	early_delay(11000);
 
-	mx28_mem_init_clock();
+	mxs_mem_init_clock();
 
-	mx28_mem_setup_vdda();
+	mxs_mem_setup_vdda();
 
 	/*
 	 * Configure the DRAM registers

@@ -242,9 +242,9 @@ void mx28_mem_init(void)
 	while (!(readl(MXS_DRAM_BASE + 0xe8) & (1 << 20)))
 		;
 
-	mx28_mem_setup_vddd();
+	mxs_mem_setup_vddd();
 
 	early_delay(10000);
 
-	mx28_mem_setup_cpu_and_hbus();
+	mxs_mem_setup_cpu_and_hbus();
 }

439 lines not on this page · raw message

index 7337458..91645eb 100644
@@ -35,7 +35,7 @@ int mxsmmc_initialize(bd_t *bis, int id, int (*wp)(int));
 
 #ifdef CONFIG_SPL_BUILD
 #include <asm/arch/iomux-mx28.h>
-void mx28_common_spl_init(const iomux_cfg_t *iomux_setup,
+void mxs_common_spl_init(const iomux_cfg_t *iomux_setup,
 			const unsigned int iomux_size);
 #endif
 

@@ -64,7 +64,7 @@ static const struct mx28_pair mx28_boot_modes[] = {
 	{ 0x00, 0x00, "Reserved/Unknown/Wrong" },
 };
 
-struct mx28_spl_data {
+struct mxs_spl_data {
 	uint8_t		boot_mode_idx;
 	uint32_t	mem_dram_size;
 };

index 7a12592..49e8a75 100644
@@ -218,5 +218,5 @@ const iomux_cfg_t iomux_setup[] = {
 
 void board_init_ll(void)
 {
-	mx28_common_spl_init(iomux_setup, ARRAY_SIZE(iomux_setup));
+	mxs_common_spl_init(iomux_setup, ARRAY_SIZE(iomux_setup));
 }

index 40d8cf6..16a6d8a 100644
@@ -180,5 +180,5 @@ void mx28_adjust_memory_params(uint32_t *dram_vals)
 
 void board_init_ll(void)
 {
-	mx28_common_spl_init(iomux_setup, ARRAY_SIZE(iomux_setup));
+	mxs_common_spl_init(iomux_setup, ARRAY_SIZE(iomux_setup));
 }

similarity index 100%
rename from arch/arm/cpu/arm926ejs/mxs/mx28.c
rename to arch/arm/cpu/arm926ejs/mxs/mxs.c