SMVP Support on MIPS34KC (linux-2.6.35)
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Hello Joe.
The 2.6.35.9 is obsolete with regards to SMVP support. You should grab the latest 3.4.2 kernel that has complete and working SMVP. To access it, do the following:
git clone git://git.linux-mips.org/pub/scm/linux-mti
git checkout -b linux-mti-3.4.2 origin/linux-mti-3.4.2
Use the 'arch/mips/configs/maltasmvp_defconfig' as your base configuration file. If you have any issues, please let me know.
- -Steve
P.S. You can also reach me at <sjhill AT mips DOT com> -----BEGIN PGP SIGNATURE-----
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Hi Steve,
Thanks for the suggestion. We moved to 3.4.2 kernel and observed the same
issue, ie System hangs while booting. In 3.4.2 port, we are using mips timers (count & compare - csrc-r4k.c & cevt-r4k.c) as clocksource. The last few prints on the console are :
Synchronize counters across 2 CPUs: done.
NET: Registered protocol family 16
bio: create slab <bio-0> at 0
Switching to clocksource MIPS
As mentioned in my previous post, even with 3.4.2 kernel, the control loops in stop_machine_cpu_stop function. Do you suspect anything here? btw, if we set "clocksource=jiffies" in the bootargs, the system boot goes fine. The issue is observed only during switching from default clocksource to MIPS clocksource. Also, the boot works fine with 'nosmp=1' option & MIPS clocksource.
Please suggest on the possible debug approach for this issue.
Thanks for your support.
Regards,
Joe
Quoted 31 lines · sjhill-3 wrote:
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Hash: SHA1Hello Joe.
The 2.6.35.9 is obsolete with regards to SMVP support. You should grab the latest 3.4.2 kernel that has complete and working SMVP. To access it, do the
following:git clone
git://git.linux-mips.org/pub/scm/linux-mti
git checkout -b linux-mti-3.4.2 origin/linux-mti-3.4.2Use the '
arch/mips/configs/maltasmvp_defconfig' as your base configuration file. If you have any issues, please let me know.- -Steve
P.S. You can also reach me at <sjhill AT mips DOT com> -----BEGIN PGP SIGNATURE-----
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Quoted 5 lines · JoeJ
Synchronize counters across 2 CPUs: done. NET: Registered protocol family 16 bio: create slab <bio-0> at 0 Switching to clocksource MIPS
Quoted 7 lines
As mentioned in my previous post, even with 3.4.2 kernel, the control loops in
stop_machine_cpu_stopfunction. Do you suspect anything here? btw, if we set "clocksource=jiffies" in the bootargs, the system boot goes fine. The issue is observed only during switching from default clocksource to MIPS clocksource. Also, the boot works fine with 'nosmp=1' option & MIPS clocksource.
Make user that you select both CONFIG_CSRC_R4K ad CONFIG_CSRC_GIC for your clock sources. The GIC counter will be used from synchronization across the CPUs. Secondly, the hang is not actually a hard hang. Wait 50 seconds and I bet you will see the boot complete.
- -Steve
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Hi Steve,
CONFIG_CSRC_R4K is defined . However, I have not
enabled CONFIG_CSRC_GIC and gic_present is initialized to 'zero' . I am a bit confused about CONFIG_SRC_GIC macros. I am not sure if GIC is an external timer outside the mips 34Kc core (specific to malta reference board)? In that case, we might have to replace to GIC source code with our own General purpose timer code. Can you please confirm if i am missing something here? It will be verfy helpful if you can explain a bit about the significance of CSRC_R4K & CSRC_GIC macros definitions in SMVP model.
We have been stuck with this issue for quiet sometime and looking for ways
to resolve this at the best possible way. Your suggestions are really helpful in this regard.
Regards,
Jeffin
Quoted 33 lines · Steven J. Hill
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Hash: SHA1Quoted 7 lines · JoeJ
Synchronize counters across 2 CPUs: done. NET: Registered protocol family 16 bio: create slab <bio-0> at 0 Switching to clocksource MIPS
As mentioned in my previous post, even with 3.4.2 kernel, the control loops in
stop_machine_cpu_stopfunction. Do you suspect anything here?btw,
Quoted 1 line
if we set "clocksource=jiffies" in the bootargs, the system boot goes
fine.
Quoted 4 lines
The issue is observed only during switching from default clocksource to MIPS clocksource. Also, the boot works fine with 'nosmp=1' option & MIPS clocksource.
Make user that you select both
CONFIG_CSRC_R4KadCONFIG_CSRC_GICfor your clock sources. The GIC counter will be used from synchronization across the CPUs. Secondly, the hang is not actually a hard hang. Wait 50 seconds and I bet you will see the boot complete.- -Steve
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Jeffin,
You will need to file an official support request with MIPS to proceed further. Additional time spent on this will need to be tracked. Thanks.
- -Steve
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Steve,
I have posted in the mips portal, addressing to you. Hope you must have got
the mail.
Regards,
Jeffin
Quoted 21 lines · sjhill-3 wrote:
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Hash: SHA1Jeffin,
You will need to file an official support request with MIPS to proceed further. Additional time spent on this will need to be tracked. Thanks.
- -Steve
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View this message in context: http://old.nabble.com/SMVP-Support-on-MIPS34KC-%28linux-2.6.35%29-tp34219711p34245663.html Sent from the linux-mips main mailing list archive at Nabble.com.