tegra: Add NAND flash support

The NAND layer needs to use cache-aligned buffers by default. Towards this goal. align the default buffers and their members according to the minimum DMA alignment defined for the architecture.

Signed-off-by Simon Glass <[email protected]>

---
Changes in v2:
- Add new patch to align default buffers in nand_base

 drivers/mtd/nand/nand_base.c |    3 ++-
 include/linux/mtd/nand.h     |    7 ++++---
 2 files changed, 6 insertions(+), 4 deletions(-)

-----Original Message-----
From: Simon Glass [mailto:sjg at chromium.org]
Sent: Sunday, July 29, 2012 11:53 PM
To: U-Boot Mailing List
Cc: Tom Warren; Stephen Warren; Scott Wood; Simon Glass
Subject: [PATCH v4 1/6] nand: Try to align the default buffers

The NAND layer needs to use cache-aligned buffers by default. Towards this goal. align the default buffers and their members according to the minimum DMA alignment defined for the architecture.

Signed-off-by Simon Glass <[email protected]>

---
Changes in v2:
- Add new patch to align default buffers in nand_base

 drivers/mtd/nand/nand_base.c |    3 ++-
 include/linux/mtd/nand.h     |    7 ++++---
 2 files changed, 6 insertions(+), 4 deletions(-)

drivers/mtd/nand/nand_base.c +2 -1

index bfd668f..891af1f 100644
@@ -2936,7 +2936,8 @@ int nand_scan_tail(struct mtd_info *mtd)
 	struct nand_chip *chip = mtd->priv;
 
 	if (!(chip->options & NAND_OWN_BUFFERS))
-		chip->buffers = kmalloc(sizeof(*chip->buffers), GFP_KERNEL);
+		chip->buffers = memalign(ARCH_DMA_MINALIGN,
+					 sizeof(*chip->buffers));
 	if (!chip->buffers)
 		return -ENOMEM;
 

include/linux/mtd/nand.h index renamed from include/linux/mtd/nand.h +0 -0

82704de..dc839e7 100644

include/linux/mtd/nand.h +0 -0

@@ -391,9 +391,10 @@ struct nand_ecc_ctrl {
  * consecutive order.

include/linux/mtd/nand.h +0 -1

 /**
--

1.7.7.3

Simon,

Quoted 57 lines

-----Original Message-----
From: Simon Glass [mailto:sjg at chromium.org]
Sent: Sunday, July 29, 2012 11:53 PM
To: U-Boot Mailing List
Cc: Tom Warren; Stephen Warren; Scott Wood; Simon Glass
Subject: [PATCH v4 1/6] nand: Try to align the default buffers

The NAND layer needs to use cache-aligned buffers by default. Towards this goal. align the default buffers and their members according to the minimum DMA alignment defined for the architecture.

Signed-off-by Simon Glass <[email protected]>

---
Changes in v2:
- Add new patch to align default buffers in nand_base

 drivers/mtd/nand/nand_base.c |    3 ++-
 include/linux/mtd/nand.h     |    7 ++++---
 2 files changed, 6 insertions(+), 4 deletions(-)

drivers/mtd/nand/nand_base.c +2 -1

index bfd668f..891af1f 100644
@@ -2936,7 +2936,8 @@ int nand_scan_tail(struct mtd_info *mtd)
 
 	struct nand_chip *chip = mtd->priv;
 
 	if (!(chip->options & NAND_OWN_BUFFERS))
 
-		chip->buffers = kmalloc(sizeof(*chip->buffers), GFP_KERNEL);
+		chip->buffers = memalign(ARCH_DMA_MINALIGN,
+					 sizeof(*chip->buffers));
 

drivers/mtd/nand/nand_base.c +0 -0

 	if (!chip->buffers)
 
 		return -ENOMEM;

include/linux/mtd/nand.h index renamed from include/linux/mtd/nand.h +0 -0

82704de..dc839e7 100644

include/linux/mtd/nand.h +4 -3

@@ -391,9 +391,10 @@ struct nand_ecc_ctrl {
 
  * consecutive order.
  */
 
 struct nand_buffers {
 
-	uint8_t	ecccalc[NAND_MAX_OOBSIZE];
-	uint8_t	ecccode[NAND_MAX_OOBSIZE];
-	uint8_t databuf[NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE];
+	uint8_t	ecccalc[ALIGN(NAND_MAX_OOBSIZE, ARCH_DMA_MINALIGN)];
+	uint8_t	ecccode[ALIGN(NAND_MAX_OOBSIZE, ARCH_DMA_MINALIGN)];
+	uint8_t databuf[ALIGN(NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE,
+			      ARCH_DMA_MINALIGN)];

Quoted 1 line

};

This causes build failures in the M28EVK build (./MAKEALL -a arm, with current u-boot-tegra/next & gcc 4.4.1):

In file included from mxs_nand.c:29:
/home/tom/denx/uboot-tegra/include/linux/mtd/nand.h:394: warning: implicit declaration of function 'ALIGN' /home/tom/denx/uboot-tegra/include/linux/mtd/nand.h:394: error:
'ARCH_DMA_MINALIGN' undeclared here (not in a function) /home/tom/denx/uboot-tegra/include/linux/mtd/nand.h:394: error: variably modified 'ecccalc' at file scope /home/tom/denx/uboot-tegra/include/linux/mtd/nand.h:395: error: variably modified 'ecccode' at file scope /home/tom/denx/uboot-tegra/include/linux/mtd/nand.h:397: error: variably modified 'databuf' at file scope make[1]: *** [mxs_nand.o] Error 1 make[1]: *** Waiting for unfinished jobs....
make: *** [drivers/mtd/nand/libnand.o] Error 2
make: *** Waiting for unfinished jobs....

PTAL. Thanks,

Tom

Quoted 4 lines

/**

--
1.7.7.3

-----Original Message-----
From: Marek Vasut [mailto:marex at denx.de]
Sent: Friday, September 07, 2012 11:43 AM
To: u-boot at lists.denx.de
Cc: Tom Warren; Simon Glass; Scott Wood
Subject: Re: [U-Boot] [PATCH v4 1/6] nand: Try to align the default buffers

Dear Tom Warren,

Quoted 60 lines

Simon,

Quoted 58 lines

-----Original Message-----
From: Simon Glass [mailto:sjg at chromium.org]
Sent: Sunday, July 29, 2012 11:53 PM
To: U-Boot Mailing List
Cc: Tom Warren; Stephen Warren; Scott Wood; Simon Glass
Subject: [PATCH v4 1/6] nand: Try to align the default buffers

The NAND layer needs to use cache-aligned buffers by default. Towards this goal. align the default buffers and their members according to the minimum DMA alignment defined for the architecture.

Signed-off-by Simon Glass <[email protected]>

---
Changes in v2:
- Add new patch to align default buffers in nand_base

 drivers/mtd/nand/nand_base.c |    3 ++-
 include/linux/mtd/nand.h     |    7 ++++---
 2 files changed, 6 insertions(+), 4 deletions(-)

(quoted diff) +0 -0

b/drivers/mtd/nand/nand_base.c index bfd668f..891af1f 100644

drivers/mtd/nand/nand_base.c +2 -1

@@ -2936,7 +2936,8 @@ int nand_scan_tail(struct mtd_info *mtd)
 
 	struct nand_chip *chip = mtd->priv;
 
 	if (!(chip->options & NAND_OWN_BUFFERS))
 
-		chip->buffers = kmalloc(sizeof(*chip->buffers), GFP_KERNEL);
+		chip->buffers = memalign(ARCH_DMA_MINALIGN,
+					 sizeof(*chip->buffers));
 

drivers/mtd/nand/nand_base.c +0 -0

 	if (!chip->buffers)
 
 		return -ENOMEM;

include/linux/mtd/nand.h +0 -0

index
82704de..dc839e7 100644

include/linux/mtd/nand.h +4 -3

@@ -391,9 +391,10 @@ struct nand_ecc_ctrl {
 
  * consecutive order.
  */
 
 struct nand_buffers {
 
-	uint8_t	ecccalc[NAND_MAX_OOBSIZE];
-	uint8_t	ecccode[NAND_MAX_OOBSIZE];
-	uint8_t databuf[NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE];
+	uint8_t	ecccalc[ALIGN(NAND_MAX_OOBSIZE, ARCH_DMA_MINALIGN)];
+	uint8_t	ecccode[ALIGN(NAND_MAX_OOBSIZE, ARCH_DMA_MINALIGN)];
+	uint8_t databuf[ALIGN(NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE,
+			      ARCH_DMA_MINALIGN)];

Quoted 1 line

Quoted 1 line

};

include asm/cache.h or something ?

Quoted 20 lines

This causes build failures in the M28EVK build (./MAKEALL -a arm, with current u-boot-tegra/next & gcc 4.4.1):

In file included from mxs_nand.c:29:
/home/tom/denx/uboot-tegra/include/linux/mtd/nand.h:394: warning:
implicit declaration of function 'ALIGN' /home/tom/denx/uboot-tegra/include/linux/mtd/nand.h:394: error:
'ARCH_DMA_MINALIGN' undeclared here (not in a function) /home/tom/denx/uboot-tegra/include/linux/mtd/nand.h:394: error:
variably modified 'ecccalc' at file scope /home/tom/denx/uboot-tegra/include/linux/mtd/nand.h:395: error:
variably modified 'ecccode' at file scope /home/tom/denx/uboot-tegra/include/linux/mtd/nand.h:397: error:
variably modified 'databuf' at file scope make[1]: *** [mxs_nand.o] Error 1
make[1]: *** Waiting for unfinished jobs....
make: *** [drivers/mtd/nand/libnand.o] Error 2
make: *** Waiting for unfinished jobs....

Quoted 8 lines

PTAL. Thanks,

Tom

Quoted 4 lines

/**

--
1.7.7.3

Best regards,
Marek Vasut

Marek,

Quoted 38 lines

-----Original Message-----
From: Marek Vasut [mailto:marex at denx.de]
Sent: Friday, September 07, 2012 11:43 AM
To: u-boot at lists.denx.de
Cc: Tom Warren; Simon Glass; Scott Wood
Subject: Re: [U-Boot] [PATCH v4 1/6] nand: Try to align the default buffers

Dear Tom Warren,

Quoted 28 lines

Simon,

Quoted 26 lines

-----Original Message-----
From: Simon Glass [mailto:sjg at chromium.org]
Sent: Sunday, July 29, 2012 11:53 PM
To: U-Boot Mailing List
Cc: Tom Warren; Stephen Warren; Scott Wood; Simon Glass
Subject: [PATCH v4 1/6] nand: Try to align the default buffers

The NAND layer needs to use cache-aligned buffers by default. Towards this goal. align the default buffers and their members according to the minimum DMA alignment defined for the architecture.

Signed-off-by Simon Glass <[email protected]>

---
Changes in v2:
- Add new patch to align default buffers in nand_base

 drivers/mtd/nand/nand_base.c |    3 ++-
 include/linux/mtd/nand.h     |    7 ++++---
 2 files changed, 6 insertions(+), 4 deletions(-)

(quoted diff) +0 -0

b/drivers/mtd/nand/nand_base.c index bfd668f..891af1f 100644

drivers/mtd/nand/nand_base.c +0 -0

@@ -2936,7 +2936,8 @@ int nand_scan_tail(struct mtd_info *mtd)
 

Quoted 5 lines

Quoted 5 lines

drivers/mtd/nand/nand_base.c int nand_scan_tail(struct mtd_info *mtd)

Quoted 5 lines

drivers/mtd/nand/nand_base.c +0 -1

 	struct nand_chip *chip = mtd->priv;
 
 	if (!(chip->options & NAND_OWN_BUFFERS))
 
-		chip->buffers = kmalloc(sizeof(*chip->buffers), 

Quoted 27 lines

Quoted 27 lines

Quoted 27 lines

drivers/mtd/nand/nand_base.c +2 -0

+		chip->buffers = memalign(ARCH_DMA_MINALIGN,
+					 sizeof(*chip->buffers));
 

drivers/mtd/nand/nand_base.c +0 -0

 	if (!chip->buffers)
 
 		return -ENOMEM;

include/linux/mtd/nand.h +0 -0

index
82704de..dc839e7 100644

include/linux/mtd/nand.h +4 -3

@@ -391,9 +391,10 @@ struct nand_ecc_ctrl {
 
  * consecutive order.
  */
 
 struct nand_buffers {
 
-	uint8_t	ecccalc[NAND_MAX_OOBSIZE];
-	uint8_t	ecccode[NAND_MAX_OOBSIZE];
-	uint8_t databuf[NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE];
+	uint8_t	ecccalc[ALIGN(NAND_MAX_OOBSIZE, ARCH_DMA_MINALIGN)];
+	uint8_t	ecccode[ALIGN(NAND_MAX_OOBSIZE, ARCH_DMA_MINALIGN)];
+	uint8_t databuf[ALIGN(NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE,
+			      ARCH_DMA_MINALIGN)];

Quoted 3 lines

Quoted 1 line

Quoted 1 line

};

include asm/cache.h or something ?

Thanks, Marek. Mxs_nand.c appears to be 99% yours (and you're listed as the maintainer of m28evk) - would you be willing to submit a patch? That'll also fix apx4devkit, which fails w/the same errors.

Tom

arch/arm/dts/tegra20.dtsi +7 -0

index f95be58..d936b1e 100644
@@ -204,4 +204,11 @@
 		compatible = "nvidia,tegra20-kbc";
 		reg = <0x7000e200 0x0078>;
 	};
+
+	nand: nand-controller@70008000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "nvidia,tegra20-nand";
+		reg = <0x70008000 0x100>;
+	};
 };

doc/device-tree-bindings/nand/nvidia,tegra20-nand.txt new file +0 -0

new file mode 100644
index 0000000..86ae408

doc/device-tree-bindings/nand/nvidia,tegra20-nand.txt new file +5 -0

+Example
+-------
+
+nand-controller@0x70008000 {
+	compatible = "nvidia,tegra20-nand";

Quoted 22 lines · Simon Glass

arch/arm/dts/tegra20.dtsi +7 -0

index f95be58..d936b1e 100644
@@ -204,4 +204,11 @@
              compatible = "nvidia,tegra20-kbc";
              reg = <0x7000e200 0x0078>;
      };
+
+     nand: nand-controller@70008000 {
+             #address-cells = <1>;
+             #size-cells = <0>;
+             compatible = "nvidia,tegra20-nand";
+             reg = <0x70008000 0x100>;
+     };
 };

doc/device-tree-bindings/nand/nvidia,tegra20-nand.txt new file +0 -0

new file mode 100644
index 0000000..86ae408

doc/device-tree-bindings/nand/nvidia,tegra20-nand.txt line 7

Quoted 7 lines

doc/device-tree-bindings/nand/nvidia,tegra20-nand.txt new file +7 -0

@@ -0,0 +1,53 @@
+NAND Flash
+----------
+
+(there isn't yet a generic binding in Linux, so this describes what is in
+U-Boot. There should not be Linux-specific or U-Boot specific binding, just
+a binding that describes this hardware. But agreeing a binding in Linux in
+the absence of a driver may be beyond my powers.)

Please at least attempt to get a binding accepted in Linux, or perhaps in a neutral repository such as devicetree.org (but point out on devicetree-discuss that you've posted it there). The device tree is supposed to describe the hardware, not what Linux currently uses.

Quoted 5 lines

doc/device-tree-bindings/nand/nvidia,tegra20-nand.txt new file +5 -0

+Example
+-------
+
+nand-controller@0x70008000 {
+     compatible = "nvidia,tegra20-nand";

doc/device-tree-bindings/nand/nvidia,tegra20-nand.txt line 53

Quoted 10 lines

doc/device-tree-bindings/nand/nvidia,tegra20-nand.txt new file +10 -0

+     #address-cells = <1>;
+     #size-cells = <0>;
+     nvidia,wp-gpios = <&gpio 59 0>;         /* PH3 */
+     nvidia,nand-width = <8>;
+     nvidia,timing = <26 100 20 80 20 10 12 10 70>;
+     nand@0 {
+             reg = <0>;
+             compatible = "hynix,hy27uf4g2b", "nand-flash";
+     };
+};

Where is "reg" in the parent node? You're not supposed to have a unit
address without reg. Also, most bus bindings don't put 0x in the unit
address).

I see that it's OK in the actual .dtsi -- it's just the example that needs fixing.

-Scott

Add a flash node to handle the NAND, including memory timings and page / block size information.

Signed-off-by Simon Glass <[email protected]>

---
Changes in v2:
- Update NAND binding to add "nvidia," prefix

Changes in v3:
- Add reg property for unit address (should be used for chip select)
- Update fdt binding to make everything Nvidia-specific

Changes in v4:
- Remove fdt bindings related to page structure

 board/nvidia/dts/tegra20-seaboard.dts |   10 ++++++++++
 1 files changed, 10 insertions(+), 0 deletions(-)

board/nvidia/dts/tegra20-seaboard.dts +0 -0

index 3352539..25a63a0 100644
@@ -153,4 +153,14 @@
 			0x1f04008a>;
 		linux,fn-keymap = <0x05040002>;
 	};

Quoted 31 lines · Simon Glass

Add a flash node to handle the NAND, including memory timings and page / block size information.

Signed-off-by Simon Glass <[email protected]>

---
Changes in v2:
- Update NAND binding to add "nvidia," prefix

Changes in v3:
- Add reg property for unit address (should be used for chip select)
- Update fdt binding to make everything Nvidia-specific

Changes in v4:
- Remove fdt bindings related to page structure

 board/nvidia/dts/tegra20-seaboard.dts |   10 ++++++++++
 1 files changed, 10 insertions(+), 0 deletions(-)

board/nvidia/dts/tegra20-seaboard.dts +5 -0

index 3352539..25a63a0 100644
@@ -153,4 +153,14 @@
                      0x1f04008a>;
              linux,fn-keymap = <0x05040002>;
      };
+
+     nand-controller@70008000 {
+             nvidia,wp-gpios = <&gpio 59 0>;         /* PH3 */
+             nvidia,width = <8>;
+             nvidia,timing = <26 100 20 80 20 10 12 10 70>;

board/nvidia/dts/tegra20-seaboard.dts line 165

Quoted 5 lines

board/nvidia/dts/tegra20-seaboard.dts +5 -0

+             nand@0 {
+                     reg = <0>;
+                     compatible = "hynix,hy27uf4g2b", "nand-flash";
+             };
+     };

Are #address-cells, #size-cells, and reg on the controller node provided by an /include/?

-Scott

From: Jim Lin <[email protected]>

A device tree is used to configure the NAND, including memory timings and block/pages sizes.

If this node is not present or is disabled, then NAND will not be initialized.

Signed-off-by Jim Lin <[email protected]>

Signed-off-by Simon Glass <[email protected]>

This enables NAND support for the Seaboard.

include/configs/seaboard.h +0 -0

 
 #include "tegra20-common-post.h"

Quoted 6 lines

This enables NAND support for the Seaboard.

include/configs/seaboard.h +0 -0

 
 #include "tegra20-common-post.h"

include/configs/seaboard.h line 116

Quoted 9 lines

include/configs/seaboard.h +9 -0

+/* NAND support */
+#define CONFIG_CMD_NAND
+#define CONFIG_TEGRA_NAND
+
+/* Max number of NAND devices */
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+
+/* Somewhat oddly, the NAND base address must be a config option */
+#define CONFIG_SYS_NAND_BASE	TEGRA20_NAND_BASE

Simon, I just noticed that all these config options are added after the include of tegra20-common-post.h. That file should be included at the very end in case it needs to do something different based on the board-specific configuration. I don't suppose you could move those lines before the include?

Am Donnerstag, den 01.11.2012, 15:57 -0600 schrieb Stephen Warren:

Quoted 7 lines · Simon Glass

Quoted 6 lines

This enables NAND support for the Seaboard.

include/configs/seaboard.h +0 -0

 
 #include "tegra20-common-post.h"

Quoted 15 lines

include/configs/seaboard.h line 116

Quoted 9 lines

include/configs/seaboard.h +9 -0

+/* NAND support */
+#define CONFIG_CMD_NAND
+#define CONFIG_TEGRA_NAND
+
+/* Max number of NAND devices */
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+
+/* Somewhat oddly, the NAND base address must be a config option */
+#define CONFIG_SYS_NAND_BASE       TEGRA20_NAND_BASE

Simon, I just noticed that all these config options are added after the include of tegra20-common-post.h. That file should be included at the very end in case it needs to do something different based on the board-specific configuration. I don't suppose you could move those lines before the include?

Also CONFIG_SYS_NAND_BASE is not really used in the current Tegra nand controller codebase, in fact you can get away with not defining it. We should probably use this define in our driver code, but then we should add this define to some common Tegra place and not to individual board files.

Regards,
Lucas

-----Original Message-----
From: Simon Glass [mailto:sjg at chromium.org]
Sent: Sunday, July 29, 2012 11:53 PM
To: U-Boot Mailing List
Cc: Tom Warren; Stephen Warren; Scott Wood; Simon Glass
Subject: [PATCH v4 0/6] tegra: Add NAND flash support

This series adds NAND flash support to Tegra and enables it on Seaboard.

Included here is a proposed device tree binding with most of the properties private to "nvidia,". The binding includes information about the NAND controller as well as the connected NAND device. The Seaboard has a Hynix HY27UF4G2B.

The driver supports ECC-based access and uses DMA and NAND acceleration features of the Tegra SOC to provide access at reasonable speed.

Changes in v2:
- Add new patch to align default buffers in nand_base
- Added comment about the behaviour of the 'resp' register
- Call set_bus_width_page_size() at init to report errors earlier
- Change set_bus_width_page_size() to return an error when needed
- Change timing structure member to u32 to match device tree
- Check for supported bus width in board_nand_init()
- Fix tegra nand header file to remove BIT defines
- Implement a dummy nand_select_chip() instead of nand_hwcontro()
- Make nand_command() display an error on an unknown command
- Minor code tidy-ups in driver for style
- Move cache logic into a separate dma_prepare() function
- Remove CMD_TRANS_SIZE_BYTESx enum
- Remove space after casts
- Remove use of 'register' variables
- Rename struct nand_info to struct nand_drv to avoid nand_info_t confusion
- Support 4096 byte page devices, drop 1024 and 2048
- Tidy up nand_waitfor_cmd_completion() logic
- Update NAND binding to add "nvidia," prefix
- Use s32 for device tree integer values

Changes in v3:
- Add reg property for unit address (should be used for chip select)
- Change note in fdt binding about the need for a hardware-specific binding
- Fix up typos in fdt binding, and rename the file
- Update fdt binding to make everything Nvidia-specific

Changes in v4:
- Align buffer length to cache line size in dma_prepare()
- Fix "Write Page 0x0 timeout with ECC" error on 4.4.1
- Fix the issue that read_byte can read at most 4 times
- Get some information from Read ID data instead of from device tree
- In nand_command, set NAND_CMD_RNDOUT as unsupported command
- Modify eccoob layout
- Move to using CONFIG_SYS_NAND_SELF_INIT
- Remove "DEFAULT" from comment because that function is not default
- Remove fdt bindings related to page structure
- Remove local read_buf and write_buf functions
- Remove some fields in fdt_nand structure
- Rename CONFIG_TEGRA2_NAND to CONFIG_TEGRA_NAND
- Rename variables my_* as our_*
- Use virt_to_phys() when filling address register

Jim Lin (1):
tegra: nand: Add Tegra NAND driver

Simon Glass (5):
nand: Try to align the default buffers
tegra: Add NAND support to funcmux
tegra: fdt: Add NAND controller binding and definitions
tegra: fdt: Add NAND definitions to fdt
tegra: Enable NAND on Seaboard

 arch/arm/cpu/tegra20-common/funcmux.c              |    7 +
 arch/arm/dts/tegra20.dtsi                          |    7 +
 arch/arm/include/asm/arch-tegra20/funcmux.h        |    3 +
 arch/arm/include/asm/arch-tegra20/tegra20.h        |    1 +
 board/nvidia/dts/tegra20-seaboard.dts              |   10 +
 .../nand/nvidia,tegra20-nand.txt                   |   53 +
 drivers/mtd/nand/Makefile                          |    1 +
 drivers/mtd/nand/nand_base.c                       |    3 +-
 drivers/mtd/nand/tegra_nand.c                      | 1026
++++++++++++++++++++
 drivers/mtd/nand/tegra_nand.h                      |  257 +++++
 include/configs/seaboard.h                         |    9 +
 include/configs/tegra20-common.h                   |    2 +
 include/fdtdec.h                                   |    1 +
 include/linux/mtd/nand.h                           |    7 +-
 lib/fdtdec.c                                       |    1 +
 15 files changed, 1384 insertions(+), 4 deletions(-)  create mode 100644
doc/device-tree-bindings/nand/nvidia,tegra20-nand.txt
 create mode 100644 drivers/mtd/nand/tegra_nand.c  create mode 100644

drivers/mtd/nand/tegra_nand.h

--
1.7.7.3

This series adds NAND flash support to Tegra and enables it on Seaboard.

Included here is a proposed device tree binding with most of the properties private to "nvidia,". The binding includes information about the NAND controller as well as the connected NAND device. The Seaboard has a Hynix HY27UF4G2B.

The driver supports ECC-based access and uses DMA and NAND acceleration features of the Tegra SOC to provide access at reasonable speed.

-----Original Message-----
From: Stephen Warren [mailto:swarren at wwwdotorg.org]
Sent: Monday, July 30, 2012 10:34 AM
To: Simon Glass
Cc: U-Boot Mailing List; Tom Warren; Scott Wood
Subject: Re: [PATCH v4 0/6] tegra: Add NAND flash support

Quoted 7 lines · Simon Glass

This series adds NAND flash support to Tegra and enables it on Seaboard.

Included here is a proposed device tree binding with most of the properties private to "nvidia,". The binding includes information about the NAND controller as well as the connected NAND device. The Seaboard has a Hynix HY27UF4G2B.

Quoted 2 lines

The driver supports ECC-based access and uses DMA and NAND acceleration features of the Tegra SOC to provide access at reasonable

speed.

Along with a couple of patches that I'll post momentarily, this works for me on Harmony, so:

Tested-by Stephen Warren <[email protected]>

This series adds NAND flash support to Tegra and enables it on Seaboard.

Included here is a proposed device tree binding with most of the properties private to "nvidia,". The binding includes information about the NAND controller as well as the connected NAND device. The Seaboard has a Hynix HY27UF4G2B.

The driver supports ECC-based access and uses DMA and NAND acceleration features of the Tegra SOC to provide access at reasonable speed.

-----Original Message-----
From: Simon Glass [mailto:sjg at chromium.org]
Sent: Sunday, July 29, 2012 11:53 PM
To: U-Boot Mailing List
Cc: Tom Warren; Stephen Warren; Scott Wood; Simon Glass
Subject: [PATCH v4 0/6] tegra: Add NAND flash support

This series adds NAND flash support to Tegra and enables it on Seaboard.

Included here is a proposed device tree binding with most of the properties private to "nvidia,". The binding includes information about the NAND controller as well as the connected NAND device. The Seaboard has a Hynix HY27UF4G2B.

The driver supports ECC-based access and uses DMA and NAND acceleration features of the Tegra SOC to provide access at reasonable speed.

Changes in v2:
- Add new patch to align default buffers in nand_base
- Added comment about the behaviour of the 'resp' register
- Call set_bus_width_page_size() at init to report errors earlier
- Change set_bus_width_page_size() to return an error when needed
- Change timing structure member to u32 to match device tree
- Check for supported bus width in board_nand_init()
- Fix tegra nand header file to remove BIT defines
- Implement a dummy nand_select_chip() instead of nand_hwcontro()
- Make nand_command() display an error on an unknown command
- Minor code tidy-ups in driver for style
- Move cache logic into a separate dma_prepare() function
- Remove CMD_TRANS_SIZE_BYTESx enum
- Remove space after casts
- Remove use of 'register' variables
- Rename struct nand_info to struct nand_drv to avoid nand_info_t confusion
- Support 4096 byte page devices, drop 1024 and 2048
- Tidy up nand_waitfor_cmd_completion() logic
- Update NAND binding to add "nvidia," prefix
- Use s32 for device tree integer values

Changes in v3:
- Add reg property for unit address (should be used for chip select)
- Change note in fdt binding about the need for a hardware-specific binding
- Fix up typos in fdt binding, and rename the file
- Update fdt binding to make everything Nvidia-specific

Changes in v4:
- Align buffer length to cache line size in dma_prepare()
- Fix "Write Page 0x0 timeout with ECC" error on 4.4.1
- Fix the issue that read_byte can read at most 4 times
- Get some information from Read ID data instead of from device tree
- In nand_command, set NAND_CMD_RNDOUT as unsupported command
- Modify eccoob layout
- Move to using CONFIG_SYS_NAND_SELF_INIT
- Remove "DEFAULT" from comment because that function is not default
- Remove fdt bindings related to page structure
- Remove local read_buf and write_buf functions
- Remove some fields in fdt_nand structure
- Rename CONFIG_TEGRA2_NAND to CONFIG_TEGRA_NAND
- Rename variables my_* as our_*
- Use virt_to_phys() when filling address register

Jim Lin (1):
tegra: nand: Add Tegra NAND driver

Simon Glass (5):
nand: Try to align the default buffers
tegra: Add NAND support to funcmux
tegra: fdt: Add NAND controller binding and definitions
tegra: fdt: Add NAND definitions to fdt
tegra: Enable NAND on Seaboard

 arch/arm/cpu/tegra20-common/funcmux.c              |    7 +
 arch/arm/dts/tegra20.dtsi                          |    7 +
 arch/arm/include/asm/arch-tegra20/funcmux.h        |    3 +
 arch/arm/include/asm/arch-tegra20/tegra20.h        |    1 +
 board/nvidia/dts/tegra20-seaboard.dts              |   10 +
 .../nand/nvidia,tegra20-nand.txt                   |   53 +
 drivers/mtd/nand/Makefile                          |    1 +
 drivers/mtd/nand/nand_base.c                       |    3 +-
 drivers/mtd/nand/tegra_nand.c                      | 1026
++++++++++++++++++++
 drivers/mtd/nand/tegra_nand.h                      |  257 +++++
 include/configs/seaboard.h                         |    9 +
 include/configs/tegra20-common.h                   |    2 +
 include/fdtdec.h                                   |    1 +
 include/linux/mtd/nand.h                           |    7 +-
 lib/fdtdec.c                                       |    1 +
 15 files changed, 1384 insertions(+), 4 deletions(-)  create mode 100644
doc/device-tree-bindings/nand/nvidia,tegra20-nand.txt
 create mode 100644 drivers/mtd/nand/tegra_nand.c  create mode 100644

drivers/mtd/nand/tegra_nand.h

--
1.7.7.3

Simon,

Quoted 7 lines

-----Original Message-----
From: Simon Glass [mailto:sjg at chromium.org]
Sent: Sunday, July 29, 2012 11:53 PM
To: U-Boot Mailing List
Cc: Tom Warren; Stephen Warren; Scott Wood; Simon Glass
Subject: [PATCH v4 0/6] tegra: Add NAND flash support

Quoted 1 line

This series adds NAND flash support to Tegra and enables it on Seaboard.

Applied to u-boot-tegra/next, thanks. The fix for the m28evk and apx4devkit builds (moving common.h to the top in mxs_nand.c) can come from you or Marek, and I'll add it to /next later. But for now, all tegra20 boards build fine.

Tom

Quoted 81 lines

Included here is a proposed device tree binding with most of the properties private to "nvidia,". The binding includes information about the NAND controller as well as the connected NAND device. The Seaboard has a Hynix HY27UF4G2B.

The driver supports ECC-based access and uses DMA and NAND acceleration features of the Tegra SOC to provide access at reasonable speed.

Changes in v2:
- Add new patch to align default buffers in nand_base
- Added comment about the behaviour of the 'resp' register
- Call set_bus_width_page_size() at init to report errors earlier
- Change set_bus_width_page_size() to return an error when needed
- Change timing structure member to u32 to match device tree
- Check for supported bus width in board_nand_init()
- Fix tegra nand header file to remove BIT defines
- Implement a dummy nand_select_chip() instead of nand_hwcontro()
- Make nand_command() display an error on an unknown command
- Minor code tidy-ups in driver for style
- Move cache logic into a separate dma_prepare() function
- Remove CMD_TRANS_SIZE_BYTESx enum
- Remove space after casts
- Remove use of 'register' variables
- Rename struct nand_info to struct nand_drv to avoid nand_info_t confusion
- Support 4096 byte page devices, drop 1024 and 2048
- Tidy up nand_waitfor_cmd_completion() logic
- Update NAND binding to add "nvidia," prefix
- Use s32 for device tree integer values

Changes in v3:
- Add reg property for unit address (should be used for chip select)
- Change note in fdt binding about the need for a hardware-specific binding
- Fix up typos in fdt binding, and rename the file
- Update fdt binding to make everything Nvidia-specific

Changes in v4:
- Align buffer length to cache line size in dma_prepare()
- Fix "Write Page 0x0 timeout with ECC" error on 4.4.1
- Fix the issue that read_byte can read at most 4 times
- Get some information from Read ID data instead of from device tree
- In nand_command, set NAND_CMD_RNDOUT as unsupported command
- Modify eccoob layout
- Move to using CONFIG_SYS_NAND_SELF_INIT
- Remove "DEFAULT" from comment because that function is not default
- Remove fdt bindings related to page structure
- Remove local read_buf and write_buf functions
- Remove some fields in fdt_nand structure
- Rename CONFIG_TEGRA2_NAND to CONFIG_TEGRA_NAND
- Rename variables my_* as our_*
- Use virt_to_phys() when filling address register

Jim Lin (1):
tegra: nand: Add Tegra NAND driver

Simon Glass (5):
nand: Try to align the default buffers
tegra: Add NAND support to funcmux
tegra: fdt: Add NAND controller binding and definitions
tegra: fdt: Add NAND definitions to fdt
tegra: Enable NAND on Seaboard

 arch/arm/cpu/tegra20-common/funcmux.c              |    7 +
 arch/arm/dts/tegra20.dtsi                          |    7 +
 arch/arm/include/asm/arch-tegra20/funcmux.h        |    3 +
 arch/arm/include/asm/arch-tegra20/tegra20.h        |    1 +
 board/nvidia/dts/tegra20-seaboard.dts              |   10 +
 .../nand/nvidia,tegra20-nand.txt                   |   53 +
 drivers/mtd/nand/Makefile                          |    1 +
 drivers/mtd/nand/nand_base.c                       |    3 +-
 drivers/mtd/nand/tegra_nand.c                      | 1026
++++++++++++++++++++
 drivers/mtd/nand/tegra_nand.h                      |  257 +++++
 include/configs/seaboard.h                         |    9 +
 include/configs/tegra20-common.h                   |    2 +
 include/fdtdec.h                                   |    1 +
 include/linux/mtd/nand.h                           |    7 +-
 lib/fdtdec.c                                       |    1 +
 15 files changed, 1384 insertions(+), 4 deletions(-)  create mode 100644
doc/device-tree-bindings/nand/nvidia,tegra20-nand.txt
 create mode 100644 drivers/mtd/nand/tegra_nand.c  create mode 100644

Quoted 4 lines

drivers/mtd/nand/tegra_nand.h

--
1.7.7.3

--
nvpublic

-----Original Message-----
From: sjg at google.com [mailto:sjg at google.com] On Behalf Of Simon Glass
Sent: Friday, September 07, 2012 2:33 PM
To: Tom Warren
Cc: U-Boot Mailing List; Stephen Warren; Scott Wood; Marek Vasut
Subject: Re: [PATCH v4 0/6] tegra: Add NAND flash support

Hi Tom,

Quoted 9 lines · Tom Warren

Simon,

Quoted 7 lines

-----Original Message-----
From: Simon Glass [mailto:sjg at chromium.org]
Sent: Sunday, July 29, 2012 11:53 PM
To: U-Boot Mailing List
Cc: Tom Warren; Stephen Warren; Scott Wood; Simon Glass
Subject: [PATCH v4 0/6] tegra: Add NAND flash support

Quoted 3 lines

Quoted 1 line

This series adds NAND flash support to Tegra and enables it on Seaboard.

Applied to u-boot-tegra/next, thanks. The fix for the m28evk and

apx4devkit builds (moving common.h to the top in mxs_nand.c) can come from you or Marek, and I'll add it to /next later. But for now, all tegra20 boards build fine.

OK thanks.

With LCD I had a few comments, but the main question is with the bindings. Can we get a resolution there?

Regards,
Simon

Simon,

Quoted 26 lines

-----Original Message-----
From: sjg at google.com [mailto:sjg at google.com] On Behalf Of Simon Glass
Sent: Friday, September 07, 2012 2:33 PM
To: Tom Warren
Cc: U-Boot Mailing List; Stephen Warren; Scott Wood; Marek Vasut
Subject: Re: [PATCH v4 0/6] tegra: Add NAND flash support

Hi Tom,

Quoted 9 lines · Tom Warren

Simon,

Quoted 7 lines

-----Original Message-----
From: Simon Glass [mailto:sjg at chromium.org]
Sent: Sunday, July 29, 2012 11:53 PM
To: U-Boot Mailing List
Cc: Tom Warren; Stephen Warren; Scott Wood; Simon Glass
Subject: [PATCH v4 0/6] tegra: Add NAND flash support

Quoted 3 lines

Quoted 1 line

This series adds NAND flash support to Tegra and enables it on Seaboard.

Applied to u-boot-tegra/next, thanks. The fix for the m28evk and

apx4devkit builds (moving common.h to the top in mxs_nand.c) can come from you or Marek, and I'll add it to /next later. But for now, all tegra20 boards build fine.

Quoted 4 lines

OK thanks.

With LCD I had a few comments, but the main question is with the bindings. Can we get a resolution there?

Sorry, missed this question in the flurry of Tegra30 patches I've been working on.

What exactly do you need? Can we start a discussion offline w/Stephen & whomever else you need to get this resolved and moving forward again? It's the only thing left hanging for Tegra20.

Quoted 28 lines · Tom Warren

Simon,

Quoted 26 lines

-----Original Message-----
From: sjg at google.com [mailto:sjg at google.com] On Behalf Of Simon Glass
Sent: Friday, September 07, 2012 2:33 PM
To: Tom Warren
Cc: U-Boot Mailing List; Stephen Warren; Scott Wood; Marek Vasut
Subject: Re: [PATCH v4 0/6] tegra: Add NAND flash support

Hi Tom,

Quoted 9 lines · Tom Warren

Simon,

Quoted 7 lines

-----Original Message-----
From: Simon Glass [mailto:sjg at chromium.org]
Sent: Sunday, July 29, 2012 11:53 PM
To: U-Boot Mailing List
Cc: Tom Warren; Stephen Warren; Scott Wood; Simon Glass
Subject: [PATCH v4 0/6] tegra: Add NAND flash support

Quoted 3 lines

Quoted 1 line

This series adds NAND flash support to Tegra and enables it on Seaboard.

Applied to u-boot-tegra/next, thanks. The fix for the m28evk and

apx4devkit builds (moving common.h to the top in mxs_nand.c) can come from you or Marek, and I'll add it to /next later. But for now, all tegra20 boards build fine.

Quoted 8 lines

Quoted 4 lines

OK thanks.

With LCD I had a few comments, but the main question is with the bindings. Can we get a resolution there?

Sorry, missed this question in the flurry of Tegra30 patches I've been working on.

What exactly do you need? Can we start a discussion offline w/Stephen & whomever else you need to get this resolved and moving forward again? It's the only thing left hanging for Tegra20.

The issue is making sure that the kernel and U-Boot use the exact same DT binding.

The main people to work with here are:

Thierry Reding (Avionic Design) and Mark Zhang (NVIDIA) who're working on the tegradrm driver for the Linux kernel.

I believe Thierry is close to publishing an updated version of tegradrm which would presumably be a good base.

You probably also want to look at:

http://lists.freedesktop.org/archives/dri-devel/2012-July/024875.html

... although I think that's implicitly included in the tegradrm stuff.

Simon,

Quoted 7 lines

-----Original Message-----
From: Simon Glass [mailto:sjg at chromium.org]
Sent: Sunday, July 29, 2012 11:53 PM
To: U-Boot Mailing List
Cc: Tom Warren; Stephen Warren; Scott Wood; Simon Glass
Subject: [PATCH v4 0/6] tegra: Add NAND flash support

Quoted 1 line

This series adds NAND flash support to Tegra and enables it on Seaboard.

Applied to u-boot-tegra/next, thanks. The fix for the m28evk and apx4devkit builds (moving common.h to the top in mxs_nand.c) can come from you or Marek, and I'll add it to /next later. But for now, all tegra20 boards build fine.

Tom

Quoted 89 lines

Included here is a proposed device tree binding with most of the properties private to "nvidia,". The binding includes information about the NAND controller as well as the connected NAND device. The Seaboard has a Hynix HY27UF4G2B.

The driver supports ECC-based access and uses DMA and NAND acceleration features of the Tegra SOC to provide access at reasonable speed.

Changes in v2:
- Add new patch to align default buffers in nand_base
- Added comment about the behaviour of the 'resp' register
- Call set_bus_width_page_size() at init to report errors earlier
- Change set_bus_width_page_size() to return an error when needed
- Change timing structure member to u32 to match device tree
- Check for supported bus width in board_nand_init()
- Fix tegra nand header file to remove BIT defines
- Implement a dummy nand_select_chip() instead of nand_hwcontro()
- Make nand_command() display an error on an unknown command
- Minor code tidy-ups in driver for style
- Move cache logic into a separate dma_prepare() function
- Remove CMD_TRANS_SIZE_BYTESx enum
- Remove space after casts
- Remove use of 'register' variables
- Rename struct nand_info to struct nand_drv to avoid nand_info_t confusion - Support 4096 byte page devices, drop 1024 and 2048
- Tidy up nand_waitfor_cmd_completion() logic
- Update NAND binding to add "nvidia," prefix
- Use s32 for device tree integer values

Changes in v3:
- Add reg property for unit address (should be used for chip select)
- Change note in fdt binding about the need for a hardware-specific binding - Fix up typos in fdt binding, and rename the file
- Update fdt binding to make everything Nvidia-specific

Changes in v4:
- Align buffer length to cache line size in dma_prepare()
- Fix "Write Page 0x0 timeout with ECC" error on 4.4.1
- Fix the issue that read_byte can read at most 4 times
- Get some information from Read ID data instead of from device tree
- In nand_command, set NAND_CMD_RNDOUT as unsupported command
- Modify eccoob layout
- Move to using CONFIG_SYS_NAND_SELF_INIT
- Remove "DEFAULT" from comment because that function is not default
- Remove fdt bindings related to page structure
- Remove local read_buf and write_buf functions
- Remove some fields in fdt_nand structure
- Rename CONFIG_TEGRA2_NAND to CONFIG_TEGRA_NAND
- Rename variables my_* as our_*
- Use virt_to_phys() when filling address register

Jim Lin (1):
tegra: nand: Add Tegra NAND driver

Simon Glass (5):
nand: Try to align the default buffers
tegra: Add NAND support to funcmux
tegra: fdt: Add NAND controller binding and definitions
tegra: fdt: Add NAND definitions to fdt
tegra: Enable NAND on Seaboard

 arch/arm/cpu/tegra20-common/funcmux.c              |    7 +
 arch/arm/dts/tegra20.dtsi                          |    7 +
 arch/arm/include/asm/arch-tegra20/funcmux.h        |    3 +
 arch/arm/include/asm/arch-tegra20/tegra20.h        |    1 +
 board/nvidia/dts/tegra20-seaboard.dts              |   10 +
 .../nand/nvidia,tegra20-nand.txt                   |   53 +
 drivers/mtd/nand/Makefile                          |    1 +
 drivers/mtd/nand/nand_base.c                       |    3 +-
 drivers/mtd/nand/tegra_nand.c                      | 1026

++++++++++++++++++++

 drivers/mtd/nand/tegra_nand.h                      |  257 +++++
 include/configs/seaboard.h                         |    9 +
 include/configs/tegra20-common.h                   |    2 +
 include/fdtdec.h                                   |    1 +
 include/linux/mtd/nand.h                           |    7 +-
 lib/fdtdec.c                                       |    1 +
 15 files changed, 1384 insertions(+), 4 deletions(-)  create mode 100644

doc/device-tree-bindings/nand/nvidia,tegra20-nand.txt

 create mode 100644 drivers/mtd/nand/tegra_nand.c  create mode 100644

drivers/mtd/nand/tegra_nand.h

--
1.7.7.3