cmd_nand: dump: Align data and OOB buffers

PATCH New Thierry Reding 5 participants 8 messages Jul 31, 2012 – Sep 7, 2012 Tegra architecture support

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Thierry Reding

author

2012-07-31 06:21 UTC #0 lore raw

PATCH 1/2 cmd_nand: dump: Align data and OOB buffers

In order for cache invalidation and flushing to work properly, the data and OOB buffers must be aligned to full cache lines.

Signed-off-by Thierry Reding <[email protected]>

---
 common/cmd_nand.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

common/cmd_nand.c +2 -2

index a91ccf4..4367f5a 100644
@@ -48,8 +48,8 @@ static int nand_dump(nand_info_t *nand, ulong off, int only_oob, int repeat)
 
 	last = off;
 
-	datbuf = malloc(nand->writesize);
-	oobbuf = malloc(nand->oobsize);
+	datbuf = memalign(ARCH_DMA_MINALIGN, nand->writesize);
+	oobbuf = memalign(ARCH_DMA_MINALIGN, nand->oobsize);
 	if (!datbuf || !oobbuf) {
 		puts("No memory for page buffer\n");
 		return 1;

Signature · 1 line

1.7.11.3

Thierry Reding

author

2012-07-31 06:21 UTC #1 lore raw

PATCH 2/2 tegra: Enable NAND on TEC

This commit enables NAND support on the Tamonten Evaluation Carrier and adds the corresponding device tree nodes. Furthermore, the U-Boot environment can now be stored in NAND.

Signed-off-by Thierry Reding <[email protected]>

---
 board/avionic-design/dts/tegra20-tec.dts | 11 +++++++++++
 include/configs/tec.h                    | 12 ++++++++++--
 2 files changed, 21 insertions(+), 2 deletions(-)

board/avionic-design/dts/tegra20-tec.dts +11 -0

index 9faebd8..bb3851b 100644
@@ -55,4 +55,15 @@
 	usb at c5004000 {
 		status = "disabled";
 	};
+
+	nand-controller at 70008000 {
+		nvidia,wp-gpios = <&gpio 23 0>; /* PC7 */
+		nvidia,width = <8>;
+		nvidia,timing = <26 100 20 80 20 10 12 10 70>;
+
+		nand at 0 {
+			reg = <0>;
+			compatible = "hynix,hy27uf4g2b", "nand-flash";
+		};
+	};
 };

include/configs/tec.h +10 -2

index 9b3f88d..54fcd41 100644
@@ -45,14 +45,22 @@
 
 #define CONFIG_BOARD_EARLY_INIT_F
 
-#define CONFIG_ENV_IS_NOWHERE
-
 /* SD/MMC */
 #define CONFIG_MMC
 #define CONFIG_GENERIC_MMC
 #define CONFIG_TEGRA_MMC
 #define CONFIG_CMD_MMC
 
+/* NAND support */
+#define CONFIG_CMD_NAND
+#define CONFIG_TEGRA_NAND
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_BASE		TEGRA20_NAND_BASE
+
+/* Environment not stored */
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET		(SZ_512M - SZ_128K) /* 128K sector size */
+
 /* USB host support */
 #define CONFIG_USB_EHCI
 #define CONFIG_USB_EHCI_TEGRA

Signature · 1 line

1.7.11.3

Stephen Warren

2012-07-31 15:40 UTC #2 lore raw

PATCH 2/2 tegra: Enable NAND on TEC

include/configs/tec.h line 62

Quoted 9 lines · Thierry Reding

This commit enables NAND support on the Tamonten Evaluation Carrier and adds the corresponding device tree nodes. Furthermore, the U-Boot environment can now be stored in NAND.
include/configs/tec.h +3 -0
 
+/* Environment not stored */
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET		(SZ_512M - SZ_128K) /* 128K sector size */

I guess you also need to update the comment;-)

Thierry Reding

author

2012-07-31 17:58 UTC #3 lore raw

PATCH 2/2 tegra: Enable NAND on TEC

Quoted 5 lines · Stephen Warren

Quoted 3 lines · Thierry Reding
This commit enables NAND support on the Tamonten Evaluation Carrier and adds the corresponding device tree nodes. Furthermore, the U-Boot environment can now be stored in NAND.

Quoted 7 lines

include/configs/tec.h line 62
Quoted 5 lines
include/configs/tec.h +3 -0
 
+/* Environment not stored */
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET		(SZ_512M - SZ_128K) /* 128K sector size */
I guess you also need to update the comment;-)

Hehe. Will do. =)

Thierry
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Simon Glass

2012-07-31 07:00 UTC #4 lore raw

PATCH 1/2 cmd_nand: dump: Align data and OOB buffers

In reply to Thierry Reding

+Scott

Quoted 4 lines · Thierry Reding

In order for cache invalidation and flushing to work properly, the data and OOB buffers must be aligned to full cache lines.
Signed-off-by Thierry Reding <[email protected]>

Acked-by Simon Glass <[email protected]>

Quoted 22 lines

---
 common/cmd_nand.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

common/cmd_nand.c +2 -3

index a91ccf4..4367f5a 100644
@@ -48,8 +48,8 @@ static int nand_dump(nand_info_t *nand, ulong off, int only_oob, int repeat)
 
        last = off;
 
-       datbuf = malloc(nand->writesize);
-       oobbuf = malloc(nand->oobsize);
+       datbuf = memalign(ARCH_DMA_MINALIGN, nand->writesize);
+       oobbuf = memalign(ARCH_DMA_MINALIGN, nand->oobsize);
        if (!datbuf || !oobbuf) {
                puts("No memory for page buffer\n");
                return 1;
--

1.7.11.3

Stephen Warren

2012-07-31 15:40 UTC #5 lore raw

PATCH 1/2 cmd_nand: dump: Align data and OOB buffers

In reply to Thierry Reding

Quoted 4 lines · Thierry Reding

In order for cache invalidation and flushing to work properly, the data and OOB buffers must be aligned to full cache lines.
Signed-off-by Thierry Reding <[email protected]>

You probably want to CC the NAND maintainer, Scott Wood (I have here) so he can ack this or apply it.

Quoted 19 lines

---
 common/cmd_nand.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

common/cmd_nand.c +2 -2

index a91ccf4..4367f5a 100644
@@ -48,8 +48,8 @@ static int nand_dump(nand_info_t *nand, ulong off, int only_oob, int repeat)
 
 	last = off;
 
-	datbuf = malloc(nand->writesize);
-	oobbuf = malloc(nand->oobsize);
+	datbuf = memalign(ARCH_DMA_MINALIGN, nand->writesize);
+	oobbuf = memalign(ARCH_DMA_MINALIGN, nand->oobsize);
 	if (!datbuf || !oobbuf) {
 		puts("No memory for page buffer\n");
 		return 1;

Scott Wood

2012-07-31 16:14 UTC #6 lore raw

PATCH 1/2 cmd_nand: dump: Align data and OOB buffers

Quoted 21 lines · Stephen Warren

Quoted 4 lines · Thierry Reding
In order for cache invalidation and flushing to work properly, the data and OOB buffers must be aligned to full cache lines.
Signed-off-by Thierry Reding <[email protected]>
You probably want to CC the NAND maintainer, Scott Wood (I have here) so he can ack this or apply it.
Quoted 12 lines
---
 common/cmd_nand.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)
common/cmd_nand.c +0 -0
index a91ccf4..4367f5a 100644
@@ -48,8 +48,8 @@ static int nand_dump(nand_info_t *nand, ulong off, int only_oob, int repeat)
 
 	last = off;
 

Quoted 8 lines

common/cmd_nand.c static int nand_dump(nand_info_t *nand, ulong off, int only_oob, int repeat) · line 55
Quoted 7 lines
common/cmd_nand.c +2 -2
-	datbuf = malloc(nand->writesize);
-	oobbuf = malloc(nand->oobsize);
+	datbuf = memalign(ARCH_DMA_MINALIGN, nand->writesize);
+	oobbuf = memalign(ARCH_DMA_MINALIGN, nand->oobsize);
 	if (!datbuf || !oobbuf) {
 		puts("No memory for page buffer\n");
 		return 1;

Acked-by Scott Wood <[email protected]>

...though I'm still not fond of the idea that every user of an API has to know whether DMA might be used on the buffer.

-Scott

Tom Warren

2012-09-07 21:42 UTC #7 lore raw

PATCH 1/2 cmd_nand: dump: Align data and OOB buffers

In reply to Thierry Reding

Thierry,

Quoted 4 lines · Thierry Reding

In order for cache invalidation and flushing to work properly, the data and OOB buffers must be aligned to full cache lines.
Signed-off-by Thierry Reding <[email protected]>

This patch, along with the Tegra: 'Enable NAND on TEC' patch, applied to u-boot-tegra/next. Thanks!

Tom

Quoted 22 lines

---
 common/cmd_nand.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

common/cmd_nand.c +2 -3

index a91ccf4..4367f5a 100644
@@ -48,8 +48,8 @@ static int nand_dump(nand_info_t *nand, ulong off, int only_oob, int repeat)
 
        last = off;
 
-       datbuf = malloc(nand->writesize);
-       oobbuf = malloc(nand->oobsize);
+       datbuf = memalign(ARCH_DMA_MINALIGN, nand->writesize);
+       oobbuf = memalign(ARCH_DMA_MINALIGN, nand->oobsize);
        if (!datbuf || !oobbuf) {
                puts("No memory for page buffer\n");
                return 1;
--

1.7.11.3