EXYNOS5: USB: Add USB 2.0 and USB 3.0 support for exynos5

index b81cc56..1a4ea07 100644
@@ -26,10 +26,29 @@ static int exynos4_usb_host_phy_is_on(void)
 	return (readl(EXYNOS4_PHYPWR) & PHY1_STD_ANALOG_POWERDOWN) ? 0 : 1;
 }
 
-static void exynos4210_usb_phy_clkset(struct platform_device *pdev)
+static struct clk *exynos_usb_clock_enable(struct platform_device *pdev)
+{
+	struct clk *usb_clk = NULL;
+	int err = 0;
+
+	usb_clk = clk_get(&pdev->dev, "otg");
+	if (IS_ERR(usb_clk)) {
+		dev_err(&pdev->dev, "Failed to get otg clock\n");
+		return NULL;
+	}
+
+	err = clk_enable(usb_clk);
+	if (err) {
+		clk_put(usb_clk);
+		return NULL;
+	}
+	return usb_clk;
+}
+
+static int exynos4210_usb_phy_clkset(struct platform_device *pdev)
 {
 	struct clk *xusbxti_clk;
-	u32 phyclk;
+	u32 phyclk = 0;
 
 	xusbxti_clk = clk_get(&pdev->dev, "xusbxti");
 	if (xusbxti_clk && !IS_ERR(xusbxti_clk)) {

@@ -80,6 +99,7 @@ static void exynos4210_usb_phy_clkset(struct platform_device *pdev)
 		}
 		clk_put(xusbxti_clk);
 	}
+	return phyclk;
 }
 
 static int exynos4210_usb_phy0_init(struct platform_device *pdev)

@@ -120,21 +140,12 @@ static int exynos4210_usb_phy1_init(struct platform_device *pdev)
 {
 	struct clk *otg_clk;
 	u32 rstcon;
-	int err;
 
 	atomic_inc(&host_usage);
 
-	otg_clk = clk_get(&pdev->dev, "otg");
-	if (IS_ERR(otg_clk)) {
-		dev_err(&pdev->dev, "Failed to get otg clock\n");
-		return PTR_ERR(otg_clk);
-	}
-
-	err = clk_enable(otg_clk);
-	if (err) {
-		clk_put(otg_clk);
-		return err;
-	}
+	otg_clk = exynos_usb_clock_enable(pdev);
+	if (otg_clk == NULL)
+		dev_err(&pdev->dev, "Failed to enable otg clock\n");
 
 	if (exynos4_usb_host_phy_is_on())
 		return 0;

@@ -173,22 +184,13 @@ static int exynos4210_usb_phy1_init(struct platform_device *pdev)
 static int exynos4210_usb_phy1_exit(struct platform_device *pdev)
 {
 	struct clk *otg_clk;
-	int err;
 
 	if (atomic_dec_return(&host_usage) > 0)
 		return 0;
 
-	otg_clk = clk_get(&pdev->dev, "otg");
-	if (IS_ERR(otg_clk)) {
-		dev_err(&pdev->dev, "Failed to get otg clock\n");
-		return PTR_ERR(otg_clk);
-	}
-
-	err = clk_enable(otg_clk);
-	if (err) {
-		clk_put(otg_clk);
-		return err;
-	}
+	otg_clk = exynos_usb_clock_enable(pdev);
+	if (otg_clk == NULL)
+		dev_err(&pdev->dev, "Failed to enable otg clock\n");
 
 	writel((readl(EXYNOS4_PHYPWR) | PHY1_STD_ANALOG_POWERDOWN),
 			EXYNOS4_PHYPWR);

index 4eb39cd..92d5e61 100644
@@ -275,6 +275,11 @@ static struct map_desc exynos5_iodesc[] __initdata = {
 		.pfn		= __phys_to_pfn(EXYNOS5_PA_GIC_DIST),
 		.length		= SZ_4K,
 		.type		= MT_DEVICE,
+	}, {
+		.virtual	= (unsigned long)S3C_VA_USB_HSPHY,
+		.pfn		= __phys_to_pfn(EXYNOS5_PA_USB_PHY),
+		.length		= SZ_4K,
+		.type		= MT_DEVICE,
 	},
 };
 

index c72b675..331ae57 100644
@@ -192,6 +192,8 @@
 #define EXYNOS4_PA_UART			0x13800000
 #define EXYNOS5_PA_UART			0x12C00000
 
+#define EXYNOS5_PA_USB_PHY		0x12130000
+
 #define EXYNOS4_PA_VP			0x12C00000
 #define EXYNOS4_PA_MIXER		0x12C10000
 #define EXYNOS4_PA_SDO			0x12C20000

index ef770bc..39a4b34 100644
@@ -15,12 +15,19 @@
 #include <asm/mach/arch.h>
 #include <asm/hardware/gic.h>
 #include <mach/map.h>
+#include <mach/ohci.h>
 
 #include <plat/cpu.h>
 #include <plat/regs-serial.h>
+#include <plat/usb-phy.h>
 
 #include "common.h"
 
+static struct exynos4_ohci_platdata smdk5250_ohci_pdata = {
+	.phy_init = s5p_usb_phy_init,
+	.phy_exit = s5p_usb_phy_exit,
+};
+
 /*
  * The following lookup table is used to override device names when devices
  * are registered from device tree. This is temporarily added to enable

@@ -56,6 +63,8 @@ static const struct of_dev_auxdata exynos5250_auxdata_lookup[] __initconst = {
 	OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA0, "dma-pl330.0", NULL),
 	OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA1, "dma-pl330.1", NULL),
 	OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_MDMA1, "dma-pl330.2", NULL),
+	OF_DEV_AUXDATA("samsung,exynos-ohci", 0x12120000,
+				"exynos-ohci", &smdk5250_ohci_pdata),
 	{},
 };
 

index 39a4b34..0cc626e 100644
@@ -20,6 +20,7 @@
 #include <plat/cpu.h>
 #include <plat/regs-serial.h>
 #include <plat/usb-phy.h>
+#include <plat/ehci.h>
 
 #include "common.h"
 

@@ -28,6 +29,11 @@ static struct exynos4_ohci_platdata smdk5250_ohci_pdata = {
 	.phy_exit = s5p_usb_phy_exit,
 };
 
+static struct s5p_ehci_platdata smdk5250_ehci_pdata = {
+	.phy_init = s5p_usb_phy_init,
+	.phy_exit = s5p_usb_phy_exit,
+};
+
 /*
  * The following lookup table is used to override device names when devices
  * are registered from device tree. This is temporarily added to enable

@@ -65,6 +71,8 @@ static const struct of_dev_auxdata exynos5250_auxdata_lookup[] __initconst = {
 	OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_MDMA1, "dma-pl330.2", NULL),
 	OF_DEV_AUXDATA("samsung,exynos-ohci", 0x12120000,
 				"exynos-ohci", &smdk5250_ohci_pdata),
+	OF_DEV_AUXDATA("samsung,exynos-ehci", 0x12110000,
+				"s5p-ehci", &smdk5250_ehci_pdata),
 	{},
 };
 

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281 lines not on this page · raw message

index 774533c..af1b917 100644
@@ -668,6 +668,11 @@ static struct clk exynos5_init_clocks_off[] = {
 		.enable		= exynos5_clk_ip_fsys_ctrl ,
 		.ctrlbit	= (1 << 18),
 	}, {
+		.name		= "usbdrd30",
+		.parent		= &exynos5_clk_aclk_200.clk,
+		.enable		= exynos5_clk_ip_fsys_ctrl,
+		.ctrlbit	= (1 << 19),
+	}, {
 		.name		= "usbotg",
 		.enable		= exynos5_clk_ip_fsys_ctrl,
 		.ctrlbit	= (1 << 7),

@@ -909,6 +914,16 @@ struct clksrc_sources exynos5_clkset_group = {
 	.nr_sources	= ARRAY_SIZE(exynos5_clkset_group_list),
 };
 
+struct clk *exynos5_clkset_usbdrd30_list[] = {
+	[0] = &exynos5_clk_mout_mpll.clk,
+	[1] = &exynos5_clk_mout_cpll.clk,
+};
+
+struct clksrc_sources exynos5_clkset_usbdrd30 = {
+	.sources        = exynos5_clkset_usbdrd30_list,
+	.nr_sources     = ARRAY_SIZE(exynos5_clkset_usbdrd30_list),
+};
+
 /* Possible clock sources for aclk_266_gscl_sub Mux */
 static struct clk *clk_src_gscl_266_list[] = {
 	[0] = &clk_ext_xtal_mux,

@@ -1199,6 +1214,15 @@ static struct clksrc_clk exynos5_clksrcs[] = {
 			.parent		= &exynos5_clk_mout_cpll.clk,
 		},
 		.reg_div = { .reg = EXYNOS5_CLKDIV_GEN, .shift = 4, .size = 3 },
+	}, {
+		.clk    = {
+			.name           = "sclk_usbdrd30",
+			.enable         = exynos5_clksrc_mask_fsys_ctrl,
+			.ctrlbit        = (1 << 28),
+		},
+		.sources = &exynos5_clkset_usbdrd30,
+		.reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 28, .size = 1 },
+		.reg_div = { .reg = EXYNOS5_CLKDIV_FSYS0, .shift = 24, .size = 4 },
 	},
 };
 

index 92d5e61..c17f1df 100644
@@ -280,6 +280,11 @@ static struct map_desc exynos5_iodesc[] __initdata = {
 		.pfn		= __phys_to_pfn(EXYNOS5_PA_USB_PHY),
 		.length		= SZ_4K,
 		.type		= MT_DEVICE,
+	}, {
+		.virtual        = (unsigned long)S5P_VA_DRD_PHY,
+		.pfn            = __phys_to_pfn(EXYNOS5_PA_DRD_PHY),
+		.length         = SZ_4K,
+		.type           = MT_DEVICE,
 	},
 };
 

index 331ae57..b95b245 100644
@@ -193,6 +193,7 @@
 #define EXYNOS5_PA_UART			0x12C00000
 
 #define EXYNOS5_PA_USB_PHY		0x12130000
+#define EXYNOS5_PA_DRD_PHY		0x12100000
 
 #define EXYNOS4_PA_VP			0x12C00000
 #define EXYNOS4_PA_MIXER		0x12C10000

index d4e392b..67132b4 100644
@@ -39,6 +39,10 @@
 #define S5P_HDMI_PHY_CONTROL			S5P_PMUREG(0x0700)
 #define S5P_HDMI_PHY_ENABLE			(1 << 0)
 
+/* only for EXYNOS5250*/
+#define S5P_USBDRD_PHY_CONTROL			S5P_PMUREG(0x0704)
+#define S5P_USBDRD_PHY_ENABLE			(1 << 0)
+
 #define S5P_DAC_PHY_CONTROL			S5P_PMUREG(0x070C)
 #define S5P_DAC_PHY_ENABLE			(1 << 0)
 

index c2d7bda..836863a 100644
@@ -40,6 +40,8 @@
 #define S5P_VA_GIC_CPU		S3C_ADDR(0x02810000)
 #define S5P_VA_GIC_DIST		S3C_ADDR(0x02820000)
 
+#define S5P_VA_DRD_PHY		S3C_ADDR(0x03000000)
+
 #define VA_VIC(x)		(S3C_VA_IRQ + ((x) * 0x10000))
 #define VA_VIC0			VA_VIC(0)
 #define VA_VIC1			VA_VIC(1)

index 0cc626e..fc1ed3f 100644
@@ -10,6 +10,7 @@
 */
 
 #include <linux/of_platform.h>
+#include <linux/platform_data/dwc3-exynos.h>
 #include <linux/serial_core.h>
 
 #include <asm/mach/arch.h>

@@ -34,6 +35,12 @@ static struct s5p_ehci_platdata smdk5250_ehci_pdata = {
 	.phy_exit = s5p_usb_phy_exit,
 };
 
+static struct dwc3_exynos_data smdk5250_xhci_pdata = {
+	.phy_type = S5P_USB_PHY_DRD,
+	.phy_init = s5p_usb_phy_init,
+	.phy_exit = s5p_usb_phy_exit,
+};
+
 /*
  * The following lookup table is used to override device names when devices
  * are registered from device tree. This is temporarily added to enable

@@ -73,6 +80,8 @@ static const struct of_dev_auxdata exynos5250_auxdata_lookup[] __initconst = {
 				"exynos-ohci", &smdk5250_ohci_pdata),
 	OF_DEV_AUXDATA("samsung,exynos-ehci", 0x12110000,
 				"s5p-ehci", &smdk5250_ehci_pdata),
+	OF_DEV_AUXDATA("samsung,exynos-xhci", 0x12000000,
+				"exynos-dwc3", &smdk5250_xhci_pdata),
 	{},
 };
 

index e6f2f84..b90871d 100644
@@ -18,12 +18,14 @@
 #include <mach/regs-usb-phy.h>
 #include <plat/cpu.h>
 #include <plat/usb-phy.h>
+#include <plat/regs-usb3-exynos-drd-phy.h>
 
 #define PHY_ENABLE	1
 #define PHY_DISABLE	0
 
 enum usb_phy_type {
 	USB_PHY		= (0x1 << 0),
+	USB_PHY_DRD	= (0x1 << 1),
 };
 
 static atomic_t host_usage;

@@ -161,11 +163,44 @@ static int exynos4210_usb_phy_clkset(struct platform_device *pdev)
 	return phyclk;
 }
 
+static u32 exynos_usb_phy30_set_clock(struct platform_device *pdev)
+{
+	u32 reg, refclk;
+
+	refclk = exynos4210_usb_phy_clkset(pdev);
+	reg = EXYNOS_USB3_PHYCLKRST_REFCLKSEL(3) |
+	      EXYNOS_USB3_PHYCLKRST_FSEL(refclk);
+
+	switch (refclk) {
+	case EXYNOS5_CLKSEL_50M:
+		reg |= (EXYNOS_USB3_PHYCLKRST_MPLL_MULTIPLIER(0x02) |
+			EXYNOS_USB3_PHYCLKRST_SSC_REF_CLK_SEL(0x00));
+		break;
+	case EXYNOS5_CLKSEL_20M:
+		reg |= (EXYNOS_USB3_PHYCLKRST_MPLL_MULTIPLIER(0x7d) |
+			EXYNOS_USB3_PHYCLKRST_SSC_REF_CLK_SEL(0x00));
+		break;
+	case EXYNOS5_CLKSEL_19200K:
+		reg |= (EXYNOS_USB3_PHYCLKRST_MPLL_MULTIPLIER(0x02) |
+			EXYNOS_USB3_PHYCLKRST_SSC_REF_CLK_SEL(0x88));
+		break;
+	case EXYNOS5_CLKSEL_24M:
+	default:
+		reg |= (EXYNOS_USB3_PHYCLKRST_MPLL_MULTIPLIER(0x68) |
+			EXYNOS_USB3_PHYCLKRST_SSC_REF_CLK_SEL(0x88));
+		break;
+	}
+
+	return reg;
+}
+
 static void exynos_usb_phy_control(enum usb_phy_type phy_type , int on)
 {
 	if (soc_is_exynos5250()) {
 		if (phy_type & USB_PHY)
 			writel(on, S5P_USBHOST_PHY_CONTROL);
+		if (phy_type & USB_PHY_DRD)
+			writel(on, S5P_USBDRD_PHY_CONTROL);
 	}
 }
 

@@ -413,6 +448,88 @@ static int exynos5_usb_phy20_exit(struct platform_device *pdev)
 	return 0;
 }
 
+static int exynos5_usb_phy30_init(struct platform_device *pdev)
+{
+	struct clk *host_clk;
+	u32 reg;
+
+	host_clk = exynos_usb_clock_enable(pdev);
+	if (host_clk == NULL) {
+		dev_err(&pdev->dev, "Failed to enable USB3.0 host clock this time\n");
+		return -1;
+	}
+
+	exynos_usb_phy_control(USB_PHY_DRD, PHY_ENABLE);
+
+	/* Reset USB 3.0 PHY */
+	writel(0x00000000, EXYNOS_USB3_PHYREG0);
+	writel(0x24d4e6e4, EXYNOS_USB3_PHYPARAM0);
+	writel(0x03fff81c, EXYNOS_USB3_PHYPARAM1);
+	writel(0x00000000, EXYNOS_USB3_PHYRESUME);
+
+	writel(0x08000040, EXYNOS_USB3_LINKSYSTEM);
+	writel(0x00000004, EXYNOS_USB3_PHYBATCHG);
+
+	/* PHYTEST POWERDOWN Control */
+	reg = readl(EXYNOS_USB3_PHYTEST);
+	reg &= ~(EXYNOS_USB3_PHYTEST_POWERDOWN_SSP |
+		 EXYNOS_USB3_PHYTEST_POWERDOWN_HSP);
+	writel(reg, EXYNOS_USB3_PHYTEST);
+
+	/* UTMI Power Control */
+	writel(EXYNOS_USB3_PHYUTMI_OTGDISABLE, EXYNOS_USB3_PHYUTMI);
+
+	reg = exynos_usb_phy30_set_clock(pdev);
+
+	reg |= (EXYNOS_USB3_PHYCLKRST_PORTRESET |
+		/* Digital power supply in normal operating mode */
+		EXYNOS_USB3_PHYCLKRST_RETENABLEN |
+		/* Enable ref clock for SS function */
+		EXYNOS_USB3_PHYCLKRST_REF_SSP_EN |
+		/* Enable spread spectrum */
+		EXYNOS_USB3_PHYCLKRST_SSC_EN) |
+		EXYNOS_USB3_PHYCLKRST_COMMONONN;
+	writel(reg, EXYNOS_USB3_PHYCLKRST);
+
+	udelay(10);
+
+	reg &= ~(EXYNOS_USB3_PHYCLKRST_PORTRESET);
+	writel(reg, EXYNOS_USB3_PHYCLKRST);
+
+	clk_disable(host_clk);
+	clk_put(host_clk);
+	return 0;
+}
+
+static int exynos5_usb_phy30_exit(struct platform_device *pdev)
+{
+	struct clk *host_clk;
+	u32 reg;
+
+	host_clk = exynos_usb_clock_enable(pdev);
+	if (host_clk == NULL) {
+		dev_err(&pdev->dev, "Failed to enable USB3.0 host clock this time\n");
+		return -1;
+	}
+
+	reg = EXYNOS_USB3_PHYUTMI_OTGDISABLE |
+		EXYNOS_USB3_PHYUTMI_FORCESUSPEND |
+		EXYNOS_USB3_PHYUTMI_FORCESLEEP;
+	writel(reg, EXYNOS_USB3_PHYUTMI);
+
+	/* Control PHYTEST to remove leakage current */
+	reg = readl(EXYNOS_USB3_PHYTEST);
+	reg |= (EXYNOS_USB3_PHYTEST_POWERDOWN_SSP |
+		 EXYNOS_USB3_PHYTEST_POWERDOWN_HSP);
+	writel(reg, EXYNOS_USB3_PHYTEST);
+
+	exynos_usb_phy_control(USB_PHY_DRD, PHY_DISABLE);
+
+	clk_disable(host_clk);
+	clk_put(host_clk);
+	return 0;
+}
+
 int s5p_usb_phy_init(struct platform_device *pdev, int type)
 {
 	if (type == S5P_USB_PHY_DEVICE)

@@ -422,6 +539,11 @@ int s5p_usb_phy_init(struct platform_device *pdev, int type)
 			return exynos5_usb_phy20_init(pdev);
 		else
 			return exynos4210_usb_phy1_init(pdev);
+	} else if (type == S5P_USB_PHY_DRD) {
+		if (soc_is_exynos5250())
+			return exynos5_usb_phy30_init(pdev);
+		else
+			dev_err(&pdev->dev, "USB 3.0 DRD not present\n");
 	}
 
 	return -EINVAL;

@@ -436,6 +558,11 @@ int s5p_usb_phy_exit(struct platform_device *pdev, int type)
 			return exynos5_usb_phy20_exit(pdev);
 		else
 			return exynos4210_usb_phy1_exit(pdev);
+	} else if (type == S5P_USB_PHY_DRD) {
+		if (soc_is_exynos5250())
+			return exynos5_usb_phy30_exit(pdev);
+		else
+			dev_err(&pdev->dev, "USB 3.0 DRD not present\n");
 	}
 	return -EINVAL;
 }

75 lines not on this page · raw message

index 959bcdb..f784101 100644
@@ -14,6 +14,7 @@
 enum s5p_usb_phy_type {
 	S5P_USB_PHY_DEVICE,
 	S5P_USB_PHY_HOST,
+	S5P_USB_PHY_DRD,
 };
 
 extern int s5p_usb_phy_init(struct platform_device *pdev, int type);