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snowball: Adding architecture dependent initialisation

PATCH New mathieu.poirier at linaro.org 2 participants 2 messages Aug 14, 2012 Arm (32-bit)

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PATCH 1/1 snowball: Adding architecture dependent initialisation

From: "Mathieu J. Poirier" <[email protected]>

Enabling timers and clocks in PRCMU and cleaning up mailbox.

Signed-off-by Mathieu Poirier <[email protected]>
Signed-off-by John Rigby <[email protected]>

---
Changes for v2:
- Removed duplicate definition of PRCMU_BASE.

---
 arch/arm/cpu/armv7/u8500/Makefile       |    2 +-
 arch/arm/cpu/armv7/u8500/cpu.c          |   41 +++++++++++++++++++++++++++++++
 arch/arm/cpu/armv7/u8500/prcmu.c        |   30 ++++++++++++++++++++++
 arch/arm/include/asm/arch-u8500/prcmu.h |   24 ++++++++++++++----
 board/st-ericsson/u8500/u8500_href.c    |    3 +-
 include/configs/snowball.h              |    1 +
 6 files changed, 93 insertions(+), 8 deletions(-)
 create mode 100644 arch/arm/cpu/armv7/u8500/cpu.c
arch/arm/cpu/armv7/u8500/Makefile +1 -1
index 77accde..ce8af96 100644
@@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(SOC).o
 
-COBJS	= timer.o clock.o prcmu.o
+COBJS	= timer.o clock.o prcmu.o cpu.o
 SOBJS	= lowlevel.o
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
arch/arm/cpu/armv7/u8500/cpu.c new file +41 -0

41 lines not on this page · raw message

arch/arm/cpu/armv7/u8500/prcmu.c +30 -0
index b256d27..4918bbc 100644
@@ -40,6 +40,8 @@
 #define PRCM_MBOX_CPU_SET (U8500_PRCMU_BASE + 0x100)
 #define PRCM_MBOX_CPU_CLR (U8500_PRCMU_BASE + 0x104)
 
+#define I2C_MBOX_BIT    (1 << 5)
+
 static int prcmu_is_ready(void)
 {
 	int ready = readb(PRCM_XP70_CUR_PWR_STATE) == AP_EXECUTE;

@@ -162,3 +164,31 @@ int prcmu_i2c_write(u8 reg, u16 slave, u8 reg_data)
 		return -1;
 	}
 }
+
+void u8500_prcmu_enable(u32 *reg)
+{
+	writel(readl(reg) | (1 << 8), reg);
+}
+
+void db8500_prcmu_init(void)
+{
+	/* Enable timers */
+	writel(1 << 17, PRCM_TCR);
+
+	u8500_prcmu_enable((u32 *)PRCM_PER1CLK_MGT_REG);
+	u8500_prcmu_enable((u32 *)PRCM_PER2CLK_MGT_REG);
+	u8500_prcmu_enable((u32 *)PRCM_PER3CLK_MGT_REG);
+	/* PER4CLK does not exist */
+	u8500_prcmu_enable((u32 *)PRCM_PER5CLK_MGT_REG);
+	u8500_prcmu_enable((u32 *)PRCM_PER6CLK_MGT_REG);
+	/* Only exists in ED but is always ok to write to */
+	u8500_prcmu_enable((u32 *)PRCM_PER7CLK_MGT_REG);
+
+	u8500_prcmu_enable((u32 *)PRCM_UARTCLK_MGT_REG);
+	u8500_prcmu_enable((u32 *)PRCM_I2CCLK_MGT_REG);
+
+	u8500_prcmu_enable((u32 *)PRCM_SDMMCCLK_MGT_REG);
+
+	/* Clean up the mailbox interrupts after pre-u-boot code. */
+	writel(I2C_MBOX_BIT, PRCM_ARM_IT1_CLEAR);
+}
arch/arm/include/asm/arch-u8500/prcmu.h +19 -5
index 0836983..1fd4d2a 100644
@@ -27,12 +27,23 @@
 #define I2C_RD_OK	2
 #define I2CWRITE	0
 
-#define _PRCMU_TCDM_BASE    U8500_PRCMU_TCDM_BASE
-#define PRCM_XP70_CUR_PWR_STATE (_PRCMU_TCDM_BASE + 0xFFC)      /* 4 BYTES */
-
-#define PRCM_REQ_MB5        (_PRCMU_TCDM_BASE + 0xE44)    /* 4 bytes  */
-#define PRCM_ACK_MB5        (_PRCMU_TCDM_BASE + 0xDF4)    /* 4 bytes */
+#define PRCMU_BASE			U8500_PRCMU_BASE
+#define PRCM_UARTCLK_MGT_REG		(PRCMU_BASE + 0x018)
+#define PRCM_MSPCLK_MGT_REG		(PRCMU_BASE + 0x01C)
+#define PRCM_I2CCLK_MGT_REG		(PRCMU_BASE + 0x020)
+#define PRCM_SDMMCCLK_MGT_REG		(PRCMU_BASE + 0x024)
+#define PRCM_PER1CLK_MGT_REG		(PRCMU_BASE + 0x02C)
+#define PRCM_PER2CLK_MGT_REG		(PRCMU_BASE + 0x030)
+#define PRCM_PER3CLK_MGT_REG		(PRCMU_BASE + 0x034)
+#define PRCM_PER5CLK_MGT_REG		(PRCMU_BASE + 0x038)
+#define PRCM_PER6CLK_MGT_REG		(PRCMU_BASE + 0x03C)
+#define PRCM_PER7CLK_MGT_REG		(PRCMU_BASE + 0x040)
 
+#define PRCM_ARM_IT1_CLEAR		(PRCMU_BASE + 0x48C)
+#define PRCM_TCR			(PRCMU_BASE + 0x1C8)
+#define PRCM_REQ_MB5			(PRCMU_BASE + 0xE44)
+#define PRCM_ACK_MB5			(PRCMU_BASE + 0xDF4)
+#define PRCM_XP70_CUR_PWR_STATE		(PRCMU_BASE + 0xFFC)
 /* Mailbox 5 Requests */
 #define PRCM_REQ_MB5_I2COPTYPE_REG	(PRCM_REQ_MB5 + 0x0)
 #define PRCM_REQ_MB5_BIT_FIELDS		(PRCM_REQ_MB5 + 0x1)

@@ -52,4 +63,7 @@
 extern int prcmu_i2c_read(u8 reg, u16 slave);
 extern int prcmu_i2c_write(u8 reg, u16 slave, u8 reg_data);
 
+void u8500_prcmu_enable(u32 *reg);
+void db8500_prcmu_init(void);
+
 #endif /* __MACH_PRCMU_FW_V1_H */
board/st-ericsson/u8500/u8500_href.c +1 -2
index 6e3fc87..b4b8751 100644
@@ -26,8 +26,8 @@
 #include <asm/arch/gpio.h>
 #include <asm/arch/hardware.h>
 #include <asm/arch/sys_proto.h>
-#ifdef CONFIG_MMC
 #include <asm/arch/prcmu.h>
+#ifdef CONFIG_MMC
 #include "../../../drivers/mmc/arm_pl180_mmci.h"
 #endif
 

@@ -42,7 +42,6 @@
  * SGA: Smart Graphic accelerator
  * B2R2: Graphic blitter
  */
-#define PRCMU_BASE	CFG_PRCMU_BASE	/* 0x80157000 for U8500 */
 #define PRCM_ARMCLKFIX_MGT_REG		(PRCMU_BASE + 0x000)
 #define PRCM_ACLK_MGT_REG		(PRCMU_BASE + 0x004)
 #define PRCM_SVAMMDSPCLK_MGT_REG	(PRCMU_BASE + 0x008)
include/configs/snowball.h +1 -0
index 9877513..d3ca55d 100644
@@ -31,6 +31,7 @@
 #define CONFIG_SNOWBALL
 #define CONFIG_SYS_ICACHE_OFF
 #define CONFIG_SYS_DCACHE_OFF
+#define CONFIG_ARCH_CPU_INIT
 
 /*
  * High Level Configuration Options
Signature · 1 line
1.7.5.4
#1 lore raw

PATCH 1/1 snowball: Adding architecture dependent initialisation

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Hash: SHA1

Quoted 7 lines · mathieu.poirier at linaro.org

From: "Mathieu J. Poirier" <[email protected]>

Enabling timers and clocks in PRCMU and cleaning up mailbox.

Signed-off-by Mathieu Poirier <[email protected]>
Signed-off-by John Rigby <[email protected]> --- Changes for

v2: - Removed duplicate definition of PRCMU_BASE.

Acked-by Tom Rini <[email protected]>

Albert, do you want me to re-do or can you just drop this patch in-place? Thanks!

- --
Tom
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