mx53_smd: add spi nor support

PATCH New Terry Lv 2 participants 6 messages Aug 15, 2012 – Aug 17, 2012

Subsystems (3)

Arm (32-bit) Arm i.MX and Layerscape SPI

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Terry Lv

author

2012-08-15 06:38 UTC #0 lore raw

PATCH 1/3 mx53_smd: add spi nor support

Add spi nor support to mx53 smd, including iomux, configs, etc. To test spi nor on mx53 smd:
MX53SMD U-Boot > sf probe 0:21249
JEDEC ID: 0x202016
m25p32 (4096 Kbytes)
SF: Detected m25p32 with page size 0 Bytes, total 4 MiB

Here, 21249 is integer of hex 0x5301. 0x01 is cs and 0x53 is active gpio number.

Signed-off-by Terry Lv <[email protected]>

---
 board/freescale/mx53smd/mx53smd.c |   63 +++++++++++++++++++++++++++++++++++++
 include/configs/mx53smd.h         |   17 ++++++++++
 2 files changed, 80 insertions(+), 0 deletions(-)

board/freescale/mx53smd/mx53smd.c +63 -0

index 87fa7fa..abb1e9b 100644
@@ -127,6 +127,65 @@ static void setup_iomux_fec(void)
 			PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
 }
 
+#ifdef CONFIG_MXC_SPI
+static void setup_iomux_spi(u8 bus, u8 ss)
+{
+	switch (bus) {
+	case 0:
+		/* SCLK */
+		mxc_request_iomux(MX53_PIN_EIM_D16, IOMUX_CONFIG_ALT4);
+		mxc_iomux_set_pad(MX53_PIN_EIM_D16,
+				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH);
+		mxc_iomux_set_input(MX53_ECSPI1_IPP_CSPI_CLK_IN_SELECT_INPUT,
+				0x3);
+
+		/* MISO */
+		mxc_request_iomux(MX53_PIN_EIM_D17, IOMUX_CONFIG_ALT4);
+		mxc_iomux_set_pad(MX53_PIN_EIM_D17,
+				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH);
+		mxc_iomux_set_input(MX53_ECSPI1_IPP_IND_MISO_SELECT_INPUT,
+				0x3);
+
+		/* MOSI */
+		mxc_request_iomux(MX53_PIN_EIM_D18, IOMUX_CONFIG_ALT4);
+		mxc_iomux_set_pad(MX53_PIN_EIM_D18,
+				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH);
+		mxc_iomux_set_input(MX53_ECSPI1_IPP_IND_MOSI_SELECT_INPUT,
+				0x3);
+
+		if (0 == ss) {
+			mxc_request_iomux(MX53_PIN_EIM_EB2,
+						IOMUX_CONFIG_ALT4);
+			mxc_iomux_set_pad(MX53_PIN_EIM_EB2,
+				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH);
+			mxc_iomux_set_input(
+				MX53_ECSPI1_IPP_IND_SS_B_1_SELECT_INPUT,
+				0x3);
+
+			mxc_request_iomux(MX53_PIN_EIM_EB2, IOMUX_CONFIG_ALT1);
+			mxc_iomux_set_pad(MX53_PIN_EIM_EB2,
+					PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH);
+		} else if (1 == ss){
+			mxc_request_iomux(MX53_PIN_EIM_D19, IOMUX_CONFIG_ALT4);
+			mxc_iomux_set_pad(MX53_PIN_EIM_D19,
+				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH);
+			mxc_iomux_set_input(
+					MX53_ECSPI1_IPP_IND_SS_B_2_SELECT_INPUT,
+					0x2);
+
+			mxc_request_iomux(MX53_PIN_EIM_D19, IOMUX_CONFIG_ALT1);
+			mxc_iomux_set_pad(MX53_PIN_EIM_D19,
+					PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH);
+		}
+		break;
+	case 1:
+	case 2:
+	default:
+		break;
+	}
+}
+#endif
+
 #ifdef CONFIG_FSL_ESDHC
 struct fsl_esdhc_cfg esdhc_cfg[1] = {
 	{MMC_SDHC1_BASE_ADDR, 1},

@@ -203,6 +262,10 @@ int board_early_init_f(void)
 {
 	setup_iomux_uart();
 	setup_iomux_fec();
+#if defined(CONFIG_MXC_SPI) && defined(CONFIG_SPI_FLASH) \
+	&& defined(CONFIG_SPI_FLASH_BUS) && defined(CONFIG_SPI_FLASH_CS)
+	setup_iomux_spi(CONFIG_SPI_FLASH_BUS, CONFIG_SPI_FLASH_CS);
+#endif
 
 	return 0;
 }

include/configs/mx53smd.h +17 -0

index 48b32dd..e830c1b 100644
@@ -65,6 +65,23 @@
 #define CONFIG_CMD_FAT
 #define CONFIG_DOS_PARTITION
 
+/* SPI Configs*/
+#define CONFIG_CMD_SPI
+#define CONFIG_MXC_SPI
+#define CONFIG_SPI_VER_2_3	1
+#define CONFIG_CSPI1_BASE_ADDR	CSPI1_BASE_ADDR
+#define CONFIG_CSPI2_BASE_ADDR	CSPI2_BASE_ADDR
+#define CONFIG_CSPI3_BASE_ADDR	CSPI3_BASE_ADDR
+
+/* SPI Flash Configs */
+#define CONFIG_CMD_SF
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_STMICRO	1
+#define CONFIG_SF_DEFAULT_SPEED 25000000
+#define CONFIG_SF_DEFAULT_MODE  (SPI_MODE_0)
+#define CONFIG_SPI_FLASH_BUS	0
+#define CONFIG_SPI_FLASH_CS	1
+
 /* Eth Configs */
 #define CONFIG_HAS_ETH1
 #define CONFIG_MII

Signature · 1 line

1.7.0.4

Terry Lv

author

2012-08-15 06:38 UTC #1 lore raw

PATCH 2/3 mxc_spi: change to use version config instead of soc config in mxc_spi

In mxc_spi, we used to use soc config, e.g. CONFIG_MX35, CONFIG_MX51. In this way, we can't exlain the difference of spi in each soc and we need to modify the driver for each new soc.
Thus, now it use spi version config which can be found in reference manual to diff. And new soc just need to add spi version config in config files to enable it. it would be eaiser than before.

Signed-off-by Terry Lv <[email protected]>

---
 README                |    4 ++-
 drivers/spi/mxc_spi.c |   59 ++++++++++++++++++++++++-------------------------
 2 files changed, 32 insertions(+), 31 deletions(-)
 mode change 100644 => 100755 drivers/spi/mxc_spi.c

README +3 -1

index 07f1d11..19268d9 100644
@@ -1910,7 +1910,9 @@ The following options need to be configured:
 		CONFIG_MXC_SPI
 
 		Enables the driver for the SPI controllers on i.MX and MXC
-		SoCs. Currently i.MX31/35/51 are supported.
+		SoCs. The board must also define the version of SPI controller
+		and SPI base addresses that will be used.
+		Currently i.MX31/35/51/53 are supported.
 
 - FPGA Support: CONFIG_FPGA

drivers/spi/mxc_spi.c +29 ~~-30~~

119 lines not on this page · raw message

Signature · 1 line

1.7.0.4

Stefano Babic

2012-08-17 10:44 UTC #2 lore raw

PATCH 2/3 mxc_spi: change to use version config instead of soc config in mxc_spi

Quoted 9 lines · Terry Lv

In mxc_spi, we used to use soc config, e.g. CONFIG_MX35, CONFIG_MX51. In this way, we can't exlain the difference of spi in each soc and we need to modify the driver for each new soc.
Thus, now it use spi version config which can be found in reference manual to diff. And new soc just need to add spi version config in config files to enable it. it would be eaiser than before.
Signed-off-by Terry Lv <[email protected]>
---

Hi Terry,

Quoted 10 lines

 README                |    4 ++-
 drivers/spi/mxc_spi.c |   59 ++++++++++++++++++++++++-------------------------
 2 files changed, 32 insertions(+), 31 deletions(-)
 mode change 100644 => 100755 drivers/spi/mxc_spi.c

README +0 -0

index 07f1d11..19268d9 100644

README The following options need to be configured: · line 1915

Quoted 7 lines

README +3 -1

@@ -1910,7 +1910,9 @@ The following options need to be configured:
 		CONFIG_MXC_SPI
 
 		Enables the driver for the SPI controllers on i.MX and MXC
-		SoCs. Currently i.MX31/35/51 are supported.
+		SoCs. The board must also define the version of SPI controller
+		and SPI base addresses that will be used.
+		Currently i.MX31/35/51/53 are supported.

I agree with this series, that drops also all nasty adresses using the defines from ix-regs.h. However, I disagree that you move the decision which controller should be used into the board configuration file. This is a SOC propriety, not a board configuration option. A MX31 board cannot set CONFIG_SPI_VER_2_3 - it must use always the right one that belong to the SOC.

I thing that the version number should be moved into the corresponding imx-regs.hm selecting another name, CONFIG_ can then be misleading with the board configuration (only SPI_VER_*, maybe ?).

Best regards,
Stefano Babic

Signature · 5 lines

=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

Terry Lv

author

2012-08-15 06:38 UTC #3 lore raw

PATCH 3/3 mxc_spi: apply new mxc_spi version configs to other soc configs

In reply to Terry Lv

Apply new mxc_spi version configs to other soc configs.

Signed-off-by Terry Lv <[email protected]>

---
 arch/arm/include/asm/arch-mx31/imx-regs.h |    4 ++++
 include/configs/efikamx.h                 |    4 ++++
 include/configs/flea3.h                   |    3 +++
 include/configs/imx31_litekit.h           |    5 +++++
 include/configs/imx31_phycore.h           |    4 ++++
 include/configs/mx31ads.h                 |    4 ++++
 include/configs/mx31pdk.h                 |    4 ++++
 include/configs/mx35pdk.h                 |    8 +++++++-
 include/configs/mx51evk.h                 |    4 ++++
 include/configs/qong.h                    |    4 ++++
 include/configs/tt01.h                    |    5 +++++
 11 files changed, 48 insertions(+), 1 deletions(-)

arch/arm/include/asm/arch-mx31/imx-regs.h +4 -0

index 0147920..4f9c78c 100644
@@ -24,6 +24,10 @@
 #ifndef __ASM_ARCH_MX31_IMX_REGS_H
 #define __ASM_ARCH_MX31_IMX_REGS_H
 
+#define CSPI1_BASE_ADDR	0x43fa4000
+#define CSPI2_BASE_ADDR	0x50010000
+#define CSPI3_BASE_ADDR	0x53f84000
+
 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
 #include <asm/types.h>

include/configs/efikamx.h +4 -0

index a07c8b5..1fe558d 100644
@@ -99,6 +99,10 @@
 
 #define CONFIG_HARD_SPI
 #define CONFIG_MXC_SPI
+#define CONFIG_SPI_VER_2_3	1
+#define CONFIG_CSPI1_BASE_ADDR	CSPI1_BASE_ADDR
+#define CONFIG_CSPI2_BASE_ADDR	CSPI2_BASE_ADDR
+#define CONFIG_CSPI3_BASE_ADDR	CSPI3_BASE_ADDR
 #define CONFIG_DEFAULT_SPI_BUS		1
 #define CONFIG_DEFAULT_SPI_MODE		(SPI_MODE_0 | SPI_CS_HIGH)

include/configs/flea3.h +3 -0

index d88c578..0d85ed5 100644
@@ -71,6 +71,9 @@
 #define CONFIG_SYS_I2C_SPEED		100000
 #define CONFIG_SYS_I2C_SLAVE		0xfe
 #define CONFIG_MXC_SPI
+#define CONFIG_SPI_VER_0_7	1
+#define CONFIG_CSPI1_BASE_ADDR	CSPI1_BASE_ADDR
+#define CONFIG_CSPI2_BASE_ADDR	CSPI2_BASE_ADDR
 #define CONFIG_MXC_GPIO
 
 /*

include/configs/imx31_litekit.h +5 -0

index 1455ea2..d213ed0 100644
@@ -69,6 +69,11 @@
 
 #define CONFIG_HARD_SPI		1
 #define CONFIG_MXC_SPI		1
+#define CONFIG_SPI_VER_0_5	1
+#define CONFIG_CSPI1_BASE_ADDR	CSPI1_BASE_ADDR
+#define CONFIG_CSPI2_BASE_ADDR	CSPI2_BASE_ADDR
+#define CONFIG_CSPI3_BASE_ADDR	CSPI3_BASE_ADDR
+
 #define CONFIG_DEFAULT_SPI_BUS	1
 #define CONFIG_DEFAULT_SPI_MODE	(SPI_MODE_0 | SPI_CS_HIGH)

include/configs/imx31_phycore.h +4 -0

index 1b75197..f7c2e2d 100644
@@ -213,6 +213,10 @@
 
 #define CONFIG_HARD_SPI
 #define CONFIG_MXC_SPI
+#define CONFIG_SPI_VER_0_5	1
+#define CONFIG_CSPI1_BASE_ADDR	CSPI1_BASE_ADDR
+#define CONFIG_CSPI2_BASE_ADDR	CSPI2_BASE_ADDR
+#define CONFIG_CSPI3_BASE_ADDR	CSPI3_BASE_ADDR
 #define CONFIG_CMD_SPI
 
 #define CONFIG_S6E63D6

include/configs/mx31ads.h +4 -0

index 7e011ae..eff70de 100644
@@ -65,6 +65,10 @@
 
 #define CONFIG_HARD_SPI		1
 #define CONFIG_MXC_SPI		1
+#define CONFIG_SPI_VER_0_5	1
+#define CONFIG_CSPI1_BASE_ADDR	CSPI1_BASE_ADDR
+#define CONFIG_CSPI2_BASE_ADDR	CSPI2_BASE_ADDR
+#define CONFIG_CSPI3_BASE_ADDR	CSPI3_BASE_ADDR
 #define CONFIG_DEFAULT_SPI_BUS	1
 #define CONFIG_DEFAULT_SPI_MODE	(SPI_MODE_0 | SPI_CS_HIGH)
 #define CONFIG_MXC_GPIO

include/configs/mx31pdk.h +4 -0

index 4253c3e..8210f97 100644
@@ -67,6 +67,10 @@
 
 #define CONFIG_HARD_SPI
 #define CONFIG_MXC_SPI
+#define CONFIG_SPI_VER_0_5	1
+#define CONFIG_CSPI1_BASE_ADDR	CSPI1_BASE_ADDR
+#define CONFIG_CSPI2_BASE_ADDR	CSPI2_BASE_ADDR
+#define CONFIG_CSPI3_BASE_ADDR	CSPI3_BASE_ADDR
 #define CONFIG_DEFAULT_SPI_BUS	1
 #define CONFIG_DEFAULT_SPI_MODE	(SPI_MODE_0 | SPI_CS_HIGH)

include/configs/mx35pdk.h +7 -1

index 32ed609..26eb1d5 100644
@@ -62,9 +62,15 @@
 #define CONFIG_SYS_I2C_MX35_PORT1
 #define CONFIG_SYS_I2C_SPEED		100000
 #define CONFIG_SYS_I2C_SLAVE		0xfe
-#define CONFIG_MXC_SPI
 #define CONFIG_MXC_GPIO
 
+/*
+ * SPI Configs
+ */
+#define CONFIG_MXC_SPI
+#define CONFIG_SPI_VER_0_7	1
+#define CONFIG_CSPI1_BASE_ADDR	CSPI1_BASE_ADDR
+#define CONFIG_CSPI2_BASE_ADDR	CSPI2_BASE_ADDR
 
 /*
  * PMIC Configs

include/configs/mx51evk.h +4 -0

index 7c7544f..0c23d04 100644
@@ -68,6 +68,10 @@
 #define CONFIG_CMD_SPI
 
 #define CONFIG_MXC_SPI
+#define CONFIG_SPI_VER_2_3	1
+#define CONFIG_CSPI1_BASE_ADDR	CSPI1_BASE_ADDR
+#define CONFIG_CSPI2_BASE_ADDR	CSPI2_BASE_ADDR
+#define CONFIG_CSPI3_BASE_ADDR	CSPI3_BASE_ADDR
 
 /* PMIC Controller */
 #define CONFIG_PMIC

include/configs/qong.h +4 -0

index 3346802..d2bc39d 100644
@@ -56,6 +56,10 @@
 #define CONFIG_HW_WATCHDOG
 
 #define CONFIG_MXC_SPI
+#define CONFIG_SPI_VER_0_5	1
+#define CONFIG_CSPI1_BASE_ADDR	CSPI1_BASE_ADDR
+#define CONFIG_CSPI2_BASE_ADDR	CSPI2_BASE_ADDR
+#define CONFIG_CSPI3_BASE_ADDR	CSPI3_BASE_ADDR
 #define CONFIG_DEFAULT_SPI_BUS	1
 #define CONFIG_DEFAULT_SPI_MODE	(SPI_MODE_0 | SPI_CS_HIGH)
 #define CONFIG_RTC_MC13XXX

include/configs/tt01.h +5 -0

index 6ef25cd..1de0f10 100644
@@ -151,6 +151,11 @@
 #define CONFIG_SYS_MX31_UART2
 
 #define CONFIG_MXC_SPI
+#define CONFIG_SPI_VER_0_5	1
+#define CONFIG_CSPI1_BASE_ADDR	CSPI1_BASE_ADDR
+#define CONFIG_CSPI2_BASE_ADDR	CSPI2_BASE_ADDR
+#define CONFIG_CSPI3_BASE_ADDR	CSPI3_BASE_ADDR
+
 #define CONFIG_MXC_GPIO
 
 /* MC13783 connected to CSPI3 and SS0 */

Signature · 1 line

1.7.0.4

Stefano Babic

2012-08-17 10:46 UTC #4 lore raw

PATCH 3/3 mxc_spi: apply new mxc_spi version configs to other soc configs

Quoted 37 lines · Terry Lv

Apply new mxc_spi version configs to other soc configs.

Signed-off-by Terry Lv <[email protected]>

---
 arch/arm/include/asm/arch-mx31/imx-regs.h |    4 ++++
 include/configs/efikamx.h                 |    4 ++++
 include/configs/flea3.h                   |    3 +++
 include/configs/imx31_litekit.h           |    5 +++++
 include/configs/imx31_phycore.h           |    4 ++++
 include/configs/mx31ads.h                 |    4 ++++
 include/configs/mx31pdk.h                 |    4 ++++
 include/configs/mx35pdk.h                 |    8 +++++++-
 include/configs/mx51evk.h                 |    4 ++++
 include/configs/qong.h                    |    4 ++++
 include/configs/tt01.h                    |    5 +++++
 11 files changed, 48 insertions(+), 1 deletions(-)

arch/arm/include/asm/arch-mx31/imx-regs.h +4 -0

index 0147920..4f9c78c 100644
@@ -24,6 +24,10 @@
 #ifndef __ASM_ARCH_MX31_IMX_REGS_H
 #define __ASM_ARCH_MX31_IMX_REGS_H
 
+#define CSPI1_BASE_ADDR	0x43fa4000
+#define CSPI2_BASE_ADDR	0x50010000
+#define CSPI3_BASE_ADDR	0x53f84000
+
 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
 #include <asm/types.h>

include/configs/efikamx.h +0 -0

index a07c8b5..1fe558d 100644

include/configs/efikamx.h line 105

Quoted 7 lines

include/configs/efikamx.h +4 -0

@@ -99,6 +99,10 @@
 
 #define CONFIG_HARD_SPI
 #define CONFIG_MXC_SPI
+#define CONFIG_SPI_VER_2_3	1
+#define CONFIG_CSPI1_BASE_ADDR	CSPI1_BASE_ADDR
+#define CONFIG_CSPI2_BASE_ADDR	CSPI2_BASE_ADDR
+#define CONFIG_CSPI3_BASE_ADDR	CSPI3_BASE_ADDR

These are not configurable. If a board is a MX5, they are fixed from imx-regs.h. See also my previous answer to Patch 2/3.

Best regards,
Stefano Babic

Signature · 5 lines

=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

Stefano Babic

2012-08-17 10:36 UTC #5 lore raw

PATCH 1/3 mx53_smd: add spi nor support

In reply to Terry Lv

Quoted 2 lines · Terry Lv

Add spi nor support to mx53 smd, including iomux, configs, etc. To test spi nor on mx53 smd:

Hi Terry,

Quoted 7 lines

MX53SMD U-Boot > sf probe 0:21249
JEDEC ID: 0x202016
m25p32 (4096 Kbytes)
SF: Detected m25p32 with page size 0 Bytes, total 4 MiB
Here, 21249 is integer of hex 0x5301. 0x01 is cs and 0x53 is active gpio number.

I think sf probe accepts also parameter in hex, such as sf probe 0x5301.

Quoted 55 lines

Signed-off-by Terry Lv <[email protected]>

---
 board/freescale/mx53smd/mx53smd.c |   63 +++++++++++++++++++++++++++++++++++++
 include/configs/mx53smd.h         |   17 ++++++++++
 2 files changed, 80 insertions(+), 0 deletions(-)

board/freescale/mx53smd/mx53smd.c +40 -0

index 87fa7fa..abb1e9b 100644
@@ -127,6 +127,65 @@ static void setup_iomux_fec(void)
 			PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
 }
 
+#ifdef CONFIG_MXC_SPI
+static void setup_iomux_spi(u8 bus, u8 ss)
+{
+	switch (bus) {
+	case 0:
+		/* SCLK */
+		mxc_request_iomux(MX53_PIN_EIM_D16, IOMUX_CONFIG_ALT4);
+		mxc_iomux_set_pad(MX53_PIN_EIM_D16,
+				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH);
+		mxc_iomux_set_input(MX53_ECSPI1_IPP_CSPI_CLK_IN_SELECT_INPUT,
+				0x3);
+
+		/* MISO */
+		mxc_request_iomux(MX53_PIN_EIM_D17, IOMUX_CONFIG_ALT4);
+		mxc_iomux_set_pad(MX53_PIN_EIM_D17,
+				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH);
+		mxc_iomux_set_input(MX53_ECSPI1_IPP_IND_MISO_SELECT_INPUT,
+				0x3);
+
+		/* MOSI */
+		mxc_request_iomux(MX53_PIN_EIM_D18, IOMUX_CONFIG_ALT4);
+		mxc_iomux_set_pad(MX53_PIN_EIM_D18,
+				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH);
+		mxc_iomux_set_input(MX53_ECSPI1_IPP_IND_MOSI_SELECT_INPUT,
+				0x3);
+
+		if (0 == ss) {
+			mxc_request_iomux(MX53_PIN_EIM_EB2,
+						IOMUX_CONFIG_ALT4);
+			mxc_iomux_set_pad(MX53_PIN_EIM_EB2,
+				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH);
+			mxc_iomux_set_input(
+				MX53_ECSPI1_IPP_IND_SS_B_1_SELECT_INPUT,
+				0x3);
+
+			mxc_request_iomux(MX53_PIN_EIM_EB2, IOMUX_CONFIG_ALT1);
+			mxc_iomux_set_pad(MX53_PIN_EIM_EB2,
+					PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH);
+		} else if (1 == ss){
+			mxc_request_iomux(MX53_PIN_EIM_D19, IOMUX_CONFIG_ALT4);

board/freescale/mx53smd/mx53smd.c static void setup_iomux_fec(void) · line 179

Quoted 10 lines

board/freescale/mx53smd/mx53smd.c +10 -0

+			mxc_iomux_set_pad(MX53_PIN_EIM_D19,
+				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH);
+			mxc_iomux_set_input(
+					MX53_ECSPI1_IPP_IND_SS_B_2_SELECT_INPUT,
+					0x2);
+
+			mxc_request_iomux(MX53_PIN_EIM_D19, IOMUX_CONFIG_ALT1);
+			mxc_iomux_set_pad(MX53_PIN_EIM_D19,
+					PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH);
+		}

Instead of this if-else, it can be more readable if you introduce a switch-case, printing in the default case an error message if the cs is not expected.

board/freescale/mx53smd/mx53smd.c static void setup_iomux_fec(void) · line 184

Quoted 5 lines

board/freescale/mx53smd/mx53smd.c +5 -0
+		break;
+	case 1:
+	case 2:
+	default:
+		break;

bus different as 1 is an error currently on this board. Insert a default case, with some message as "unsupported" or such like that.

include/configs/mx53smd.h line 71

Quoted 12 lines

include/configs/mx53smd.h +4 -0

index 48b32dd..e830c1b 100644
@@ -65,6 +65,23 @@
 #define CONFIG_CMD_FAT
 #define CONFIG_DOS_PARTITION
 
+/* SPI Configs*/
+#define CONFIG_CMD_SPI
+#define CONFIG_MXC_SPI
+#define CONFIG_SPI_VER_2_3	1

Ok, this depends on your previous patchset. It must be merged firstly before applying this series. Can you mention it in the next changelog ?

include/configs/mx53smd.h line 83

Quoted 12 lines

include/configs/mx53smd.h +12 -0

+#define CONFIG_CSPI1_BASE_ADDR	CSPI1_BASE_ADDR
+#define CONFIG_CSPI2_BASE_ADDR	CSPI2_BASE_ADDR
+#define CONFIG_CSPI3_BASE_ADDR	CSPI3_BASE_ADDR
+
+/* SPI Flash Configs */
+#define CONFIG_CMD_SF
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_STMICRO	1
+#define CONFIG_SF_DEFAULT_SPEED 25000000
+#define CONFIG_SF_DEFAULT_MODE  (SPI_MODE_0)
+#define CONFIG_SPI_FLASH_BUS	0
+#define CONFIG_SPI_FLASH_CS	1

There is also a CONFIG_SF_DEFAULT_CS, if you like to use it. You can set it to 0x5301 (better write as in your comment, (GPIO << 8) + CS) and sf probe will take it automatically.

Best regards,
Stefano Babic

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