mx35: Move clock enums to clock.h

Signed-off-by Beno?t Th?baudeau <[email protected]>

Cc Stefano Babic <[email protected]>

---

 .../arch/arm/include/asm/arch-mx35/clock.h         |    2 --
 1 file changed, 2 deletions(-)

arch/arm/include/asm/arch-mx35/clock.h +0 -0

index 5dc53ba..e94f124 100644

The MFN bit-field of the PLL registers represents a signed value. See the reference manual.

Signed-off-by Beno?t Th?baudeau <[email protected]>

Cc Stefano Babic <[email protected]>

---

 .../arch/arm/cpu/arm1136/mx35/generic.c            |    9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

arch/arm/cpu/arm1136/mx35/generic.c +1 -0

index dba4903..e369c86 100644
@@ -24,6 +24,7 @@
  */
 
 #include <common.h>
+#include <div64.h>
 #include <asm/io.h>
 #include <asm/errno.h>
 #include <asm/arch/imx-regs.h>

Quoted 6 lines

The MFN bit-field of the PLL registers represents a signed value. See the reference manual.

Signed-off-by Beno?t Th?baudeau <[email protected]>

Cc Stefano Babic <[email protected]>

---

Hi Beno?t,

Quoted 19 lines

 .../arch/arm/cpu/arm1136/mx35/generic.c            |    9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

arch/arm/cpu/arm1136/mx35/generic.c +1 -0

index dba4903..e369c86 100644
@@ -24,6 +24,7 @@
  */
 
 #include <common.h>
+#include <div64.h>
 #include <asm/io.h>
 #include <asm/errno.h>
 #include <asm/arch/imx-regs.h>

@@ -126,15 +127,17 @@ static int get_ahb_div(u32 pdr0)
 static u32 decode_pll(u32 reg, u32 infreq)
 {
 	u32 mfi = (reg >> 10) & 0xf;

arch/arm/cpu/arm1136/mx35/generic.c static int get_ahb_div(u32 pdr0) · line 131

Quoted 4 lines

arch/arm/cpu/arm1136/mx35/generic.c +2 -2

-	u32 mfn = reg & 0x3f;
-	u32 mfd = (reg >> 16) & 0x3f;
+	s32 mfn = reg & 0x3ff;
+	u32 mfd = (reg >> 16) & 0x3ff;

The MFN is a signed value. But you are masking now 11 bits. According to the manual, bit 9-0 are MFN. You are taking in the mask the first bit of MFI, and this is wrong, isn't it ?

The MFN bit-field of the PLL registers represents a signed value. See the reference manual.

Signed-off-by Beno?t Th?baudeau <[email protected]>

Cc Stefano Babic <[email protected]>

---

Signed-off-by Beno?t Th?baudeau <[email protected]>

Cc Stefano Babic <[email protected]>

---

The clock dividers that were used do not match at all the reference manual. They were either completely broken, or came from an early silicon revision incompatible with the current one.

Signed-off-by Beno?t Th?baudeau <[email protected]>

Cc Stefano Babic <[email protected]>

---
 .../arch/arm/cpu/arm1136/mx35/generic.c            |   48 ++++++++------------
 .../arch/arm/include/asm/arch-mx35/crm_regs.h      |   42 ++++++-----------
 2 files changed, 31 insertions(+), 59 deletions(-)

arch/arm/cpu/arm1136/mx35/generic.c +0 -0

index e369c86..4af052c 100644

arch/arm/cpu/arm1136/mx35/generic.c +0 -0

 	}
 	return freq / div;
 }

@@ -199,19 +196,16 @@ u32 imx_get_uartclk(void)
 		freq = decode_pll(readl(&ccm->ppctl),

arch/arm/cpu/arm1136/mx35/generic.c +1 -1

 	return freq;
 }
 
 unsigned int mxc_get_main_clock(enum mxc_main_clock clk)
 {
 	u32 nfc_pdf, hsp_podf;
-	u32 pll, ret_val = 0, usb_prdf, usb_podf;
+	u32 pll, ret_val = 0, usb_podf;
 	struct ccm_regs *ccm =
 		(struct ccm_regs *)IMX_CCM_BASE;
 

Quoted 26 lines · Beno?t Th?baudeau

The clock dividers that were used do not match at all the reference manual. They
were either completely broken, or came from an early silicon revision
incompatible with the current one.

Signed-off-by Beno?t Th?baudeau <[email protected]>

Cc Stefano Babic <[email protected]>

---
 .../arch/arm/cpu/arm1136/mx35/generic.c            |   48
 ++++++++------------
 .../arch/arm/include/asm/arch-mx35/crm_regs.h      |   42
 ++++++-----------
 2 files changed, 31 insertions(+), 59 deletions(-)

(quoted diff) +0 -0

u-boot-4d3c95f/arch/arm/cpu/arm1136/mx35/generic.c index e369c86..4af052c 100644

arch/arm/cpu/arm1136/mx35/generic.c +0 -2

@@ -171,17 +171,14 @@ static u32 get_ipg_per_clk(void)
 	u32 pdr4 = readl(&ccm->pdr4);
 	u32 div;
 	if (pdr0 & MXC_CCM_PDR0_PER_SEL) {
-		div = (CCM_GET_DIVIDER(pdr4,
-			MXC_CCM_PDR4_PER0_PRDF_MASK,

arch/arm/cpu/arm1136/mx35/generic.c static u32 get_ipg_per_clk(void) · line 177

Quoted 2 lines

arch/arm/cpu/arm1136/mx35/generic.c +0 -2

-			MXC_CCM_PDR4_PER0_PODF_OFFSET) + 1) *
-			(CCM_GET_DIVIDER(pdr4,

It seems also to me that the current code is wrong if MXC_CCM_PDR0_PER_SEL is set. Maybe it was never set. As I see in figure
5-4, the ipg_per_clk depends only on pdr[21:16]. No idea where the second multiplier comes.

arch/arm/cpu/arm1136/mx35/generic.c static u32 get_ipg_per_clk(void) · line 176

Quoted 4 lines

arch/arm/cpu/arm1136/mx35/generic.c +2 -1

+		div = CCM_GET_DIVIDER(pdr4,
 			MXC_CCM_PDR4_PER0_PODF_MASK,
-			MXC_CCM_PDR4_PER0_PODF_OFFSET) + 1);
+			MXC_CCM_PDR4_PER0_PODF_OFFSET) + 1;

The name remains quite confusing. In the manual is PER0_DIV, which is the meaning of PODF here ?

Anyway, the masks you set are correct, I agree.

arch/arm/cpu/arm1136/mx35/generic.c static u32 get_ipg_per_clk(void) · line 181

Quoted 6 lines

arch/arm/cpu/arm1136/mx35/generic.c +1 -1

 	} else {
 		div = CCM_GET_DIVIDER(pdr0,
 			MXC_CCM_PDR0_PER_PODF_MASK,
 			MXC_CCM_PDR0_PER_PODF_OFFSET) + 1;
-		freq /= get_ahb_div(pdr0);
+		div *= get_ahb_div(pdr0);

This does not change the behavior.

Quoted 10 lines

arch/arm/cpu/arm1136/mx35/generic.c +0 -3

 	}
 	return freq / div;
 }

@@ -199,19 +196,16 @@ u32 imx_get_uartclk(void)
 		freq = decode_pll(readl(&ccm->ppctl),
 			CONFIG_MX35_HCLK_FREQ);
 	}
-	freq /= ((CCM_GET_DIVIDER(pdr4,
-			MXC_CCM_PDR4_UART_PRDF_MASK,
-			MXC_CCM_PDR4_UART_PRDF_OFFSET) + 1) *

arch/arm/cpu/arm1136/mx35/generic.c u32 imx_get_uartclk(void) · line 201

Quoted 5 lines

arch/arm/cpu/arm1136/mx35/generic.c +2 -2

-		(CCM_GET_DIVIDER(pdr4,
+	freq /= CCM_GET_DIVIDER(pdr4,
 			MXC_CCM_PDR4_UART_PODF_MASK,
-			MXC_CCM_PDR4_UART_PODF_OFFSET) + 1));
+			MXC_CCM_PDR4_UART_PODF_OFFSET) + 1;

This is also right. I am only asking myself why it works correctly now.

Quoted 11 lines

arch/arm/cpu/arm1136/mx35/generic.c +1 -1

 	return freq;
 }
 
 unsigned int mxc_get_main_clock(enum mxc_main_clock clk)
 {
 	u32 nfc_pdf, hsp_podf;
-	u32 pll, ret_val = 0, usb_prdf, usb_podf;
+	u32 pll, ret_val = 0, usb_podf;
 	struct ccm_regs *ccm =
 		(struct ccm_regs *)IMX_CCM_BASE;
 

arch/arm/cpu/arm1136/mx35/generic.c unsigned int mxc_get_main_clock(enum · line 253

Quoted 8 lines

arch/arm/cpu/arm1136/mx35/generic.c +1 -2

@@ -255,8 +249,7 @@ unsigned int mxc_get_main_clock(enum
 mxc_main_clock clk)
 		ret_val = pll / (nfc_pdf + 1);
 		break;
 	case USB_CLK:
-		usb_prdf = (reg4 >> 25) & 0x7;
-		usb_podf = (reg4 >> 22) & 0x7;
+		usb_podf = (reg4 >> 22) & 0x3F;

Agree again. The code seems generated from another manual. Maybe the USB_DIV field was split into two fields. With this in mind, there is no
apparent error in current code, but it cannot be derived from the manual.

arch/arm/cpu/arm1136/mx35/generic.c unsigned int mxc_get_peri_clock(enum · line 284

Quoted 11 lines

arch/arm/cpu/arm1136/mx35/generic.c +0 -0

 		break;
 	default:

arch/arm/cpu/arm1136/mx35/generic.c +1 -2

 		printf("Unknown clock: %d\n", clk);

@@ -287,11 +280,10 @@ unsigned int mxc_get_peri_clock(enum
 mxc_peri_clock clk)
 	case UART2_BAUD:
 	case UART3_BAUD:
 		clk_sel = mpdr3 & (1 << 14);
-		pre_pdf = (mpdr4 >> 13) & 0x7;
-		pdf = (mpdr4 >> 10) & 0x7;
+		pdf = (mpdr4 >> 10) & 0x3F;

Right !

The main issue about this patch is that it does not fix one problem, but
a lot of. Really it should be split into several patches.

Anyway, I
will
make some tests on the mx35 boards I have - if I will not get problems,
I will push it, hoping that someone else can make some further tests.

Hi Stefano,

Quoted 5 lines

It seems also to me that the current code is wrong if MXC_CCM_PDR0_PER_SEL is set. Maybe it was never set. As I see in figure
5-4, the ipg_per_clk depends only on pdr[21:16]. No idea where the second multiplier comes.

It looks like the current code is based on a pre(PRDF)-/post(PODF)-divider scheme.

Perhaps the first silicon revision was different and incompatible, or it was just a bug in the older revisions of the reference manual. The history of the reference manual says that this figure and some CCM register descriptions have been updated at some point. Anyway, Linux does like my patch.

Quoted 7 lines

arch/arm/cpu/arm1136/mx35/generic.c static u32 get_ipg_per_clk(void) · line 176

Quoted 4 lines

arch/arm/cpu/arm1136/mx35/generic.c +2 -1

+		div = CCM_GET_DIVIDER(pdr4,
 			MXC_CCM_PDR4_PER0_PODF_MASK,
-			MXC_CCM_PDR4_PER0_PODF_OFFSET) + 1);
+			MXC_CCM_PDR4_PER0_PODF_OFFSET) + 1;

The name remains quite confusing. In the manual is PER0_DIV, which is the meaning of PODF here ?

It the abbreviation FSL uses for post-dividers. If the pre-divider is merged with the post-divider to form a single divider, the naming from the RM makes more sense. Do you want a new version changing this naming?

Yes, make this small change - then from my point of view I am ready to merge it.

The clock dividers that were used do not match at all the reference manual. They were either completely broken, or came from an early silicon revision incompatible with the current one.

Signed-off-by Beno?t Th?baudeau <[email protected]>

Cc Stefano Babic <[email protected]>

---

Each eSDHC instance has a dedicated clock.

Signed-off-by Beno?t Th?baudeau <[email protected]>

Cc Stefano Babic <[email protected]>

---

 .../arch/arm/cpu/arm1136/mx35/generic.c            |   14 ++++++++++++--
 .../arch/arm/include/asm/arch-mx35/clock.h         |    4 +++-
 2 files changed, 15 insertions(+), 3 deletions(-)

arch/arm/cpu/arm1136/mx35/generic.c +0 -0

index 4af052c..15a0098 100644
@@ -368,8 +368,12 @@ unsigned int mxc_get_clock(enum mxc_clock clk)
 		return get_ipg_per_clk();
 	case MXC_UART_CLK:
 		return imx_get_uartclk();

Quoted 5 lines

Each eSDHC instance has a dedicated clock.

Signed-off-by Beno?t Th?baudeau <[email protected]>

Cc Stefano Babic <[email protected]>

---

Hi Beno?t,

Quoted 20 lines

 .../arch/arm/cpu/arm1136/mx35/generic.c            |   14
 ++++++++++++--
 .../arch/arm/include/asm/arch-mx35/clock.h         |    4 +++-
 2 files changed, 15 insertions(+), 3 deletions(-)

(quoted diff) +0 -0

u-boot-4d3c95f/arch/arm/cpu/arm1136/mx35/generic.c index 4af052c..15a0098 100644

arch/arm/cpu/arm1136/mx35/generic.c +4 -1

@@ -368,8 +368,12 @@ unsigned int mxc_get_clock(enum mxc_clock clk)
 		return get_ipg_per_clk();
 	case MXC_UART_CLK:
 		return imx_get_uartclk();
-	case MXC_ESDHC_CLK:
+	case MXC_ESDHC1_CLK:
 		return mxc_get_peri_clock(ESDHC1_CLK);
+	case MXC_ESDHC2_CLK:
+		return mxc_get_peri_clock(ESDHC2_CLK);
+	case MXC_ESDHC3_CLK:

arch/arm/cpu/arm1136/mx35/generic.c unsigned int mxc_get_clock(enum mxc_clock clk) · line 379

Quoted 4 lines

arch/arm/cpu/arm1136/mx35/generic.c +1 -0

+		return mxc_get_peri_clock(ESDHC3_CLK);
 	case MXC_USB_CLK:
 		return mxc_get_main_clock(USB_CLK);
 	case MXC_FEC_CLK:

Your change let understand that we can have different clocks among the
ESDHC controllers.

One thing is not clear to me is that the MX35 have
two ESDHC controllers, and you define here a thitd one. Where is it ?

Even if the two controllers can have different clocks, this is not supported by the driver. In fact, in drivers/mmc/fsl_esdhc.c:

int sdhc_clk = gd->sdhc_clk;

The driver uses always the same clock, stored in the global structure.
Before extending the code as in this patch, the driver should be modified to handle separate clocks. Currently the driver supports multiple controller, but they share the same clock or at least the same
frequency.

Quoted 5 lines

Even if the two controllers can have different clocks, this is not supported by the driver. In fact, in drivers/mmc/fsl_esdhc.c:

int sdhc_clk = gd->sdhc_clk;

Quoted 7 lines

The driver uses always the same clock, stored in the global structure.
Before extending the code as in this patch, the driver should be modified to handle separate clocks. Currently the driver supports multiple controller, but they share the same clock or at least the same
frequency.

Indeed, I had seen that. I didn't know what to decide as to the driver clocks,
so I made this change to select the correct clock if a single clock or frequency
is used.

If several clock frequencies are to be supported at once, what kind of API would
you like? gd->sdhc_clk could be changed to an array, then the corresponding
index could be passed to the init function through the fsl_esdhc_cfg struct.

Hi Stefano,

Quoted 19 lines

Quoted 5 lines

Even if the two controllers can have different clocks, this is not supported by the driver. In fact, in drivers/mmc/fsl_esdhc.c:

int sdhc_clk = gd->sdhc_clk;

Quoted 7 lines

The driver uses always the same clock, stored in the global structure.
Before extending the code as in this patch, the driver should be modified to handle separate clocks. Currently the driver supports multiple controller, but they share the same clock or at least the same
frequency.

Indeed, I had seen that. I didn't know what to decide as to the driver clocks,
so I made this change to select the correct clock if a single clock or frequency
is used.

Quoted 6 lines

If several clock frequencies are to be supported at once, what kind of API would
you like? gd->sdhc_clk could be changed to an array, then the corresponding
index could be passed to the init function through the fsl_esdhc_cfg struct.

But there is also the issue of fsl_esdhc_mmc_init() that would need a new config just to pass this index. I don't like that. Any suggestion?

Quoted 31 lines

Quoted 22 lines

Quoted 6 lines

Even if the two controllers can have different clocks, this is not
supported by the driver. In fact, in drivers/mmc/fsl_esdhc.c:

int sdhc_clk = gd->sdhc_clk;

Quoted 8 lines

The driver uses always the same clock, stored in the global structure.
Before extending the code as in this patch, the driver should be modified to handle separate clocks. Currently the driver supports multiple controller, but they share the same clock or at least the
same
frequency.

Indeed, I had seen that. I didn't know what to decide as to the driver clocks,
so I made this change to select the correct clock if a single clock
or frequency
is used.

Quoted 8 lines

If several clock frequencies are to be supported at once, what kind
of API would
you like? gd->sdhc_clk could be changed to an array, then the corresponding
index could be passed to the init function through the fsl_esdhc_cfg
struct.

Quoted 3 lines

But there is also the issue of fsl_esdhc_mmc_init() that would need a new config
just to pass this index. I don't like that. Any suggestion?

There is another issue. The driver is used by both ARM (i.MX) and PowerPCs (PowerQuickIII, ...).

fsl_esdhc_mmc_init() is already the interface when one parameter is enough. If we need more than one controller, we should already call fsl_esdhc_initialize() with the cfg structure.

Then adding a field to the struct fsl_esdhc_cfg is maybe not too bad. Instead of an index, we can add directly the frequency - reading the driver this is all that the driver needs.

OK, then this patch does the job for the single eSDHC instance use case, which will still use gd->sdhc_clk.

I will make another patch before or after this one for the multi-instance use case.

I will do the same in the v2 of my mx5 clock
series (for gd->sdhc_clk). I think I also have the same stuff for mx25.

Quoted 4 lines

OK, then this patch does the job for the single eSDHC instance use case, which
will still use gd->sdhc_clk.

Yes, but then we do not need ESDHC1, ESDHC2 and ESDHC3, because the driver does not support different clocks.

Quoted 2 lines

I will make another patch before or after this one for the multi-instance use case.

Fine.

Quoted 3 lines

I will do the same in the v2 of my mx5 clock
series (for gd->sdhc_clk). I think I also have the same stuff for mx25.

Ok - I read the series for MX5, but I need to check it with the manuals
to understand the changes. I need some more time...

Each eSDHC instance has a dedicated clock.

gd->sdhc_clk must also be set accordingly. This is good for the case only a single SDHC instance is used (initialization made with fsl_esdhc_mmc_init()). A future patch will fix the multi-instance use case (initialization made directly with fsl_esdhc_initialize()).

Signed-off-by Beno?t Th?baudeau <[email protected]>

Cc Stefano Babic <[email protected]>

Cc Eric B?nard <[email protected]>

Cc Otavio Salvador <[email protected]>

---

Add cpu_mmc_init() function to make it easy to init a single eSDHC instance.

Signed-off-by Beno?t Th?baudeau <[email protected]>

Cc Stefano Babic <[email protected]>

---
Changes for v2:
- Do not define cpu_mmc_init() if CONFIG_FSL_ESDHC is not defined.

 .../arch/arm/cpu/arm1136/mx35/generic.c            |   15 ++++++++++++++-
 1 file changed, 14 insertions(+), 1 deletion(-)

arch/arm/cpu/arm1136/mx35/generic.c +7 -1

index 15a0098..8f61069 100644
@@ -31,6 +31,9 @@
 #include <asm/arch/crm_regs.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/sys_proto.h>
+#ifdef CONFIG_FSL_ESDHC
+#include <fsl_esdhc.h>
+#endif
 #include <netdev.h>
 
 #define CLK_CODE(arm, ahb, sel) (((arm) << 16) + ((ahb) << 8) + (sel))

@@ -458,7 +461,6 @@ int print_cpuinfo(void)
  * Initializes on-chip ethernet controllers.
  * to override, implement board_eth_init()
  */
-
 int cpu_eth_init(bd_t *bis)
 {
 	int rc = -ENODEV;

@@ -470,6 +472,17 @@ int cpu_eth_init(bd_t *bis)
 	return rc;
 }
 
+#ifdef CONFIG_FSL_ESDHC
+/*
+ * Initializes on-chip MMC controllers.
+ * to override, implement board_mmc_init()

Add cpu_mmc_init() function to make it easy to init a single eSDHC instance.

Signed-off-by Beno?t Th?baudeau <[email protected]>

Cc Stefano Babic <[email protected]>

---
Changes for v2:
- Do not define cpu_mmc_init() if CONFIG_FSL_ESDHC is not defined.

 .../arch/arm/cpu/arm1136/mx35/generic.c            |   15 ++++++++++++++-
 1 file changed, 14 insertions(+), 1 deletion(-)

arch/arm/cpu/arm1136/mx35/generic.c +7 -1

index 15a0098..8f61069 100644
@@ -31,6 +31,9 @@
 #include <asm/arch/crm_regs.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/sys_proto.h>
+#ifdef CONFIG_FSL_ESDHC
+#include <fsl_esdhc.h>
+#endif
 #include <netdev.h>
 
 #define CLK_CODE(arm, ahb, sel) (((arm) << 16) + ((ahb) << 8) + (sel))

@@ -458,7 +461,6 @@ int print_cpuinfo(void)
  * Initializes on-chip ethernet controllers.
  * to override, implement board_eth_init()
  */
-
 int cpu_eth_init(bd_t *bis)
 {
 	int rc = -ENODEV;

@@ -470,6 +472,17 @@ int cpu_eth_init(bd_t *bis)
 	return rc;
 }
 
+#ifdef CONFIG_FSL_ESDHC
+/*
+ * Initializes on-chip MMC controllers.
+ * to override, implement board_mmc_init()

Signed-off-by Beno?t Th?baudeau <[email protected]>

Cc Stefano Babic <[email protected]>

---
 .../arch/arm/cpu/arm1136/mx35/generic.c            |    4 +--
 .../arch/arm/include/asm/arch-mx35/clock.h         |   28 +++++++++++++++++++-
 .../arch/arm/include/asm/arch-mx35/imx-regs.h      |   26 ------------------
 3 files changed, 29 insertions(+), 29 deletions(-)

arch/arm/cpu/arm1136/mx35/generic.c +2 -2

index 986b1f9..dba4903 100644
@@ -205,7 +205,7 @@ u32 imx_get_uartclk(void)
 	return freq;
 }
 
-unsigned int mxc_get_main_clock(enum mxc_main_clocks clk)
+unsigned int mxc_get_main_clock(enum mxc_main_clock clk)
 {
 	u32 nfc_pdf, hsp_podf;
 	u32 pll, ret_val = 0, usb_prdf, usb_podf;

@@ -270,7 +270,7 @@ unsigned int mxc_get_main_clock(enum mxc_main_clocks clk)
 
 	return ret_val;
 }
-unsigned int mxc_get_peri_clock(enum mxc_peri_clocks clk)
+unsigned int mxc_get_peri_clock(enum mxc_peri_clock clk)
 {
 	u32 ret_val = 0, pdf, pre_pdf, clk_sel;
 	struct ccm_regs *ccm =

arch/arm/include/asm/arch-mx35/clock.h +27 -1

index 4c0ddfd..5dc53ba 100644
@@ -25,7 +25,7 @@
 #define __ASM_ARCH_CLOCK_H
 
 enum mxc_clock {
-	MXC_ARM_CLK = 0,
+	MXC_ARM_CLK,
 	MXC_AHB_CLK,
 	MXC_IPG_CLK,
 	MXC_IPG_PERCLK,

@@ -36,6 +36,32 @@ enum mxc_clock {
 	MXC_FEC_CLK,
 };
 
+enum mxc_main_clock {
+	CPU_CLK,
+	AHB_CLK,
+	IPG_CLK,
+	IPG_PER_CLK,
+	NFC_CLK,
+	USB_CLK,
+	HSP_CLK,
+};
+
+enum mxc_peri_clock {
+	UART1_BAUD,
+	UART2_BAUD,
+	UART3_BAUD,
+	SSI1_BAUD,
+	SSI2_BAUD,
+	CSI_BAUD,
+	MSHC_CLK,
+	ESDHC1_CLK,
+	ESDHC2_CLK,
+	ESDHC3_CLK,
+	SPDIF_CLK,
+	SPI1_CLK,
+	SPI2_CLK,
+};
+
 unsigned int imx_decode_pll(unsigned int pll, unsigned int f_ref);
 
 u32 imx_get_uartclk(void);

arch/arm/include/asm/arch-mx35/imx-regs.h +0 -19

index 3146006..fba29b2 100644
@@ -216,32 +216,6 @@
 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
 #include <asm/types.h>
 
-enum mxc_main_clocks {
-	CPU_CLK,
-	AHB_CLK,
-	IPG_CLK,
-	IPG_PER_CLK,
-	NFC_CLK,
-	USB_CLK,
-	HSP_CLK,
-};
-
-enum mxc_peri_clocks {
-	UART1_BAUD,
-	UART2_BAUD,
-	UART3_BAUD,
-	SSI1_BAUD,
-	SSI2_BAUD,
-	CSI_BAUD,
-	MSHC_CLK,
-	ESDHC1_CLK,

Signed-off-by Beno?t Th?baudeau <[email protected]>

Cc Stefano Babic <[email protected]>

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