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powerpc/mpc85xx: Enable L2 at the beginning of U-boot for E6500

PATCH New York Sun 3 participants 19 messages Aug 17, 2012 – Aug 24, 2012 PowerPC

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York Sun

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#0 lore raw

PATCH 1/11 powerpc/mpc85xx: Enable L2 at the beginning of U-boot for E6500

Using E6500 L1 cache as initram requires L2 cache enabled. Add l2-cache cluster enabling.

Signed-off-by York Sun <[email protected]>
Signed-off-by Kumar Gala <[email protected]>
---
 arch/powerpc/cpu/mpc85xx/cpu_init.c   |   39 ++++++++++++++++++++++-
 arch/powerpc/cpu/mpc85xx/start.S      |   57 +++++++++++++++++++++++++++++++++
 arch/powerpc/include/asm/immap_85xx.h |   43 +++++++++++++++++++++++++
 3 files changed, 138 insertions(+), 1 deletions(-)
arch/powerpc/cpu/mpc85xx/cpu_init.c +38 -1
index 2c78905..1a2858a 100644
@@ -309,6 +309,34 @@ static void __fsl_serdes__init(void)
 }
 __attribute__((weak, alias("__fsl_serdes__init"))) void fsl_serdes_init(void);
 
+#ifdef CONFIG_E6500
+int enable_cluster_l2(void)
+{
+	int i = 0;
+	u32 cluster;
+	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	struct ccsr_cluster_l2 *l2cache;
+
+	cluster = in_be32(&gur->tp_cluster[i++].lower);
+	if (cluster & TP_CLUSTER_EOC)
+		return 0;
+
+	do {
+		l2cache = (void *)(CONFIG_SYS_FSL_CLUSTER_1_L2 + i * 0x40000);
+		cluster = in_be32(&gur->tp_cluster[i++].lower);
+
+		printf("enable l2 for cluster %d %p\n", i, l2cache);
+
+		out_be32(&l2cache->l2csr0, L2CSR0_L2FI|L2CSR0_L2LFC);
+		while ((in_be32(&l2cache->l2csr0) & (L2CSR0_L2FI|L2CSR0_L2LFC)) != 0)
+			;
+		out_be32(&l2cache->l2csr0, L2CSR0_L2E);
+	} while ((cluster & TP_CLUSTER_EOC) != TP_CLUSTER_EOC);
+
+	return 0;
+}
+#endif
+
 /*
  * Initialize L2 as cache.
  *

@@ -322,6 +350,11 @@ int cpu_init_r(void)
 #ifdef CONFIG_SYS_LBC_LCRR
 	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
 #endif
+#ifdef CONFIG_L2_CACHE
+	volatile ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR;
+#elif defined(CONFIG_E6500)
+	struct ccsr_cluster_l2 * l2cache = (void *)CONFIG_SYS_FSL_CLUSTER_1_L2;
+#endif
 
 #if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \
 	defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011)

@@ -363,7 +396,6 @@ int cpu_init_r(void)
 	puts ("L2:    ");
 
 #if defined(CONFIG_L2_CACHE)
-	volatile ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR;
 	volatile uint cache_ctl;
 	uint ver;
 	u32 l2siz_field;

@@ -474,6 +506,11 @@ int cpu_init_r(void)
 	}
 
 skip_l2:
+#elif defined(CONFIG_E6500)
+	if (l2cache->l2csr0 & L2CSR0_L2E)
+		printf("%d KB enabled\n", (l2cache->l2cfg0 & 0x3fff) * 64);
+
+	enable_cluster_l2();
 #else
 	puts("disabled\n");
 #endif
arch/powerpc/cpu/mpc85xx/start.S +57 -0

63 lines not on this page · raw message

arch/powerpc/include/asm/immap_85xx.h +43 -0

53 lines not on this page · raw message

Signature · 1 line
1.7.0.4
author
#1 lore raw

PATCH 2/11 powerpc/mpc85xx: setup stash id for L1 and L2 cache

Setup stash id for L1 cache as (coreID) * 2 + 32 + 0 Setup stash id for L2 cache as (cluster) * 2 + 32 + 1 Stash id for L2 is only set for Chassis 2.

Signed-off-by York Sun <[email protected]>
Signed-off-by Andy Fleming <[email protected]>

Rework L2 initialization to get all clusters

The code was double-incrementing the index, and therefore writing the wrong stash ID to the cluster. Added some comments to clarify what was happening, too.

Signed-off-by Andy Fleming <[email protected]>
---
 arch/powerpc/cpu/mpc85xx/cpu_init.c   |   20 ++++++++++++++------
 arch/powerpc/cpu/mpc85xx/fdt.c        |   13 ++++++++++++-
 arch/powerpc/cpu/mpc85xx/release.S    |   14 +++++++-------
 arch/powerpc/cpu/mpc85xx/start.S      |    8 +++++---
 arch/powerpc/include/asm/immap_85xx.h |   24 ++++++++++++++++++++----
 5 files changed, 58 insertions(+), 21 deletions(-)
arch/powerpc/cpu/mpc85xx/cpu_init.c +14 -6
index 1a2858a..e60129a 100644
@@ -309,7 +309,7 @@ static void __fsl_serdes__init(void)
 }
 __attribute__((weak, alias("__fsl_serdes__init"))) void fsl_serdes_init(void);
 
-#ifdef CONFIG_E6500
+#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
 int enable_cluster_l2(void)
 {
 	int i = 0;

@@ -317,13 +317,20 @@ int enable_cluster_l2(void)
 	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 	struct ccsr_cluster_l2 *l2cache;
 
-	cluster = in_be32(&gur->tp_cluster[i++].lower);
+	cluster = in_be32(&gur->tp_cluster[i].lower);
 	if (cluster & TP_CLUSTER_EOC)
 		return 0;
 
+	/* The first cache has already been set up, so skip it */
+	i++;
+
+	/* Look through the remaining clusters, and set up their caches */
 	do {
 		l2cache = (void *)(CONFIG_SYS_FSL_CLUSTER_1_L2 + i * 0x40000);
-		cluster = in_be32(&gur->tp_cluster[i++].lower);
+		cluster = in_be32(&gur->tp_cluster[i].lower);
+
+		/* set stash ID to (cluster) * 2 + 32 + 1 */
+		clrsetbits_be32(&l2cache->l2csr1, 0xff, 32 + i * 2 + 1);
 
 		printf("enable l2 for cluster %d %p\n", i, l2cache);
 

@@ -331,7 +338,8 @@ int enable_cluster_l2(void)
 		while ((in_be32(&l2cache->l2csr0) & (L2CSR0_L2FI|L2CSR0_L2LFC)) != 0)
 			;
 		out_be32(&l2cache->l2csr0, L2CSR0_L2E);
-	} while ((cluster & TP_CLUSTER_EOC) != TP_CLUSTER_EOC);
+		i++;
+	} while (!(cluster & TP_CLUSTER_EOC));
 
 	return 0;
 }

@@ -352,7 +360,7 @@ int cpu_init_r(void)
 #endif
 #ifdef CONFIG_L2_CACHE
 	volatile ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR;
-#elif defined(CONFIG_E6500)
+#elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2)
 	struct ccsr_cluster_l2 * l2cache = (void *)CONFIG_SYS_FSL_CLUSTER_1_L2;
 #endif
 

@@ -506,7 +514,7 @@ int cpu_init_r(void)
 	}
 
 skip_l2:
-#elif defined(CONFIG_E6500)
+#elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2)
 	if (l2cache->l2csr0 & L2CSR0_L2E)
 		printf("%d KB enabled\n", (l2cache->l2cfg0 & 0x3fff) * 64);
arch/powerpc/cpu/mpc85xx/fdt.c +12 -1
index 40df01c..a15e164 100644
@@ -220,12 +220,18 @@ static inline void ft_fixup_l2cache(void *blob)
 
 	/* we dont bother w/L3 since no platform of this type has one */
 }
-#elif defined(CONFIG_BACKSIDE_L2_CACHE)
+#elif defined(CONFIG_BACKSIDE_L2_CACHE) || defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2)
 static inline void ft_fixup_l2cache(void *blob)
 {
 	int off, l2_off, l3_off = -1;
 	u32 *ph;
+#ifdef	CONFIG_BACKSIDE_L2_CACHE
 	u32 l2cfg0 = mfspr(SPRN_L2CFG0);
+#else
+	struct ccsr_cluster_l2 *l2cache =
+		(struct ccsr_cluster_l2 *)(CONFIG_SYS_FSL_CLUSTER_1_L2);
+	u32 l2cfg0 = in_be32(&l2cache->l2cfg0);
+#endif
 	u32 size, line_size, num_ways, num_sets;
 	int has_l2 = 1;
 

@@ -257,7 +263,12 @@ static inline void ft_fixup_l2cache(void *blob)
 		if (has_l2) {
 #ifdef CONFIG_SYS_CACHE_STASHING
 			u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0);
+#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
+			/* Only initialize every eighth thread */
+			if (reg && !((*reg) % 8))
+#else
 			if (reg)
+#endif
 				fdt_setprop_cell(blob, l2_off, "cache-stash-id",
 					 (*reg * 2) + 32 + 1);
 #endif
arch/powerpc/cpu/mpc85xx/release.S +7 -7
index 22e73e0..d9061c3 100644
@@ -183,13 +183,6 @@ __secondary_start_page:
 	slwi	r8,r4,5
 	add	r10,r3,r8
 
-#if defined(CONFIG_E500MC) && defined(CONFIG_SYS_CACHE_STASHING)
-	/* set stash id to (coreID) * 2 + 32 + L1 CT (0) */
-	slwi	r8,r4,1
-	addi	r8,r8,32
-	mtspr	L1CSR2,r8
-#endif
-
 #ifdef CONFIG_E6500
 	mfspr	r0,SPRN_PIR
 	/*

@@ -209,6 +202,13 @@ __secondary_start_page:
 
 	mtspr	SPRN_PIR,r4	/* write to PIR register */
 
+#ifdef CONFIG_SYS_CACHE_STASHING
+	/* set stash id to (coreID) * 2 + 32 + L1 CT (0) */
+	slwi	r8,r4,1
+	addi	r8,r8,32
+	mtspr	L1CSR2,r8
+#endif
+
 #if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \
 	defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011)
 	/*
arch/powerpc/cpu/mpc85xx/start.S +5 -3
index 739127f..6087f62 100644
@@ -169,7 +169,7 @@ l2_disabled:
 	 *
 	 */
 
-#if defined(CONFIG_E500MC) && defined(CONFIG_SYS_CACHE_STASHING)
+#ifdef CONFIG_SYS_CACHE_STASHING
 	/* set stash id to (coreID) * 2 + 32 + L1 CT (0) */
 	li	r2,(32 + 0)
 	mtspr	L1CSR2,r2

@@ -762,7 +762,7 @@ delete_temp_tlbs:
 	tlbwe
 #endif /* #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS) */
 
-#ifdef CONFIG_E6500
+#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
 create_ccsr_l2_tlb:
 	/*
 	 * Create a TLB for the MMR location of CCSR

@@ -786,10 +786,12 @@ create_ccsr_l2_tlb:
 	isync
 	msync
 	tlbwe
-enable_l2_e6500:
+enable_l2_cluster_l2:
 	/* enable L2 cache */
 	lis	r3, (CONFIG_SYS_CCSRBAR + 0xC20000)@h
 	ori	r3, r3, (CONFIG_SYS_CCSRBAR + 0xC20000)@l
+	li	r4, 33	/* stash id */
+	stw	r4, 4(r3)
 	lis	r4, (L2CSR0_L2FI|L2CSR0_L2LFC)@h
 	ori	r4, r4, (L2CSR0_L2FI|L2CSR0_L2LFC)@l
 	sync
arch/powerpc/include/asm/immap_85xx.h +20 -4
index 62d8d0b..2a27be9 100644
@@ -2947,7 +2947,7 @@ typedef struct ccsr_snvs_regs {
 #define TSEC_BASE_ADDR		(CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
 #define MDIO_BASE_ADDR		(CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET)
 
-#ifdef CONFIG_E6500
+#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
 struct ccsr_cluster_l2 {
 	u32 l2csr0;	/* 0x000 L2 cache control and status register 0 */
 	u32 l2csr1;	/* 0x004 L2 cache control and status register 1 */

@@ -2966,10 +2966,26 @@ struct ccsr_cluster_l2 {
 	u32 l2par2;	/* 0x228 L2 cache partitioning allocation register 2 */
 	u32 l2pwr2;	/* 0x22c L2 cache partitioning way register 2 */
 	u32 l2pir3;	/* 0x230 L2 cache partitioning ID register 3 */
-	u8  res_234[5];
+	u8  res_234[4];
 	u32 l2par3;	/* 0x238 L2 cache partitining allocation register 3 */
 	u32 l2pwr3;	/* 0x23c L2 cache partitining way register 3 */
-	u8  res_240[3008]; /* 0x240 - 0xdff */
+	u32 l2pir4;	/* 0x240 L2 cache partitioning ID register 3 */
+	u8  res244[4];
+	u32 l2par4;	/* 0x248 L2 cache partitioning allocation register 3 */
+	u32 l2pwr4;	/* 0x24c L2 cache partitioning way register 3 */
+	u32 l2pir5;	/* 0x250 L2 cache partitioning ID register 3 */
+	u8  res_254[4];
+	u32 l2par5;	/* 0x258 L2 cache partitioning allocation register 3 */
+	u32 l2pwr5;	/* 0x25c L2 cache partitioning way register 3 */
+	u32 l2pir6;	/* 0x260 L2 cache partitioning ID register 3 */
+	u8  res_264[4];
+	u32 l2par6;	/* 0x268 L2 cache partitioning allocation register 3 */
+	u32 l2pwr6;	/* 0x26c L2 cache partitioning way register 3 */
+	u32 l2pir7;	/* 0x270 L2 cache partitioning ID register 3 */
+	u8  res274[4];
+	u32 l2par7;	/* 0x278 L2 cache partitioning allocation register 3 */
+	u32 l2pwr7;	/* 0x27c L2 cache partitioning way register 3 */
+	u8  res_280[0xb80]; /* 0x280 - 0xdff */
 	u32 l2errinjhi;	/* 0xe00 L2 cache error injection mask high */
 	u32 l2errinjlo;	/* 0xe04 L2 cache error injection mask low */
 	u32 l2errinjctl;/* 0xe08 L2 cache error injection control */

@@ -2988,5 +3004,5 @@ struct ccsr_cluster_l2 {
 };
 #define CONFIG_SYS_FSL_CLUSTER_1_L2 \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CLUSTER_1_L2_OFFSET)
-#endif /* CONFIG_E6500 */
+#endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
 #endif /*__IMMAP_85xx__*/
Signature · 1 line
1.7.0.4
author
#2 lore raw

PATCH 3/11 powerpc/mpc85xx: change RCW MEM_PLL_PLAT for Chassis generation 2

In reply to York Sun

Chassis generation 2 has different mask and shift. Use macro instead of magic numbers.

Signed-off-by York Sun <[email protected]>
---
 arch/powerpc/cpu/mpc85xx/speed.c      |    5 +++--
 arch/powerpc/include/asm/immap_85xx.h |    7 +++++++
 2 files changed, 10 insertions(+), 2 deletions(-)
arch/powerpc/cpu/mpc85xx/speed.c +3 -2
index 203f53d..6bf49ee 100644
@@ -1,5 +1,5 @@
 /*
- * Copyright 2004, 2007-2011 Freescale Semiconductor, Inc.
+ * Copyright 2004, 2007-2012 Freescale Semiconductor, Inc.
  *
  * (C) Copyright 2003 Motorola Inc.
  * Xianghua Xiao, (X.Xiao at motorola.com)

@@ -85,7 +85,8 @@ void get_sys_info (sys_info_t * sysInfo)
 	sysInfo->freqDDRBus = sysclk;
 
 	sysInfo->freqSystemBus *= (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
-	mem_pll_rat = (in_be32(&gur->rcwsr[0]) >> 17) & 0x1f;
+	mem_pll_rat = (in_be32(&gur->rcwsr[0]) >> FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT)
+			 & FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK;
 	if (mem_pll_rat > 2)
 		sysInfo->freqDDRBus *= mem_pll_rat;
 	else
arch/powerpc/include/asm/immap_85xx.h +7 -0
index 2a27be9..ed42918 100644
@@ -1755,6 +1755,13 @@ typedef struct ccsr_gur {
 	u32	brrl;		/* Boot release */
 	u8	res17[24];
 	u32	rcwsr[16];	/* Reset control word status */
+#ifndef CONFIG_SYS_FSL_QORIQ_CHASSIS2
+#define FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT	17
+#define FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK	0x1f
+#else
+#define FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT	16
+#define FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK	0x3f
+#endif
 #define FSL_CORENET_RCWSR4_SRDS_PRTCL		0xfc000000
 #define FSL_CORENET_RCWSR5_DDR_SYNC		0x00000080
 #define FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT		 7
Signature · 1 line
1.7.0.4
author
#3 lore raw

PATCH 4/11 powerpc/mpc85xx: check number of cores

In reply to York Sun

Panic if the number of cores is more than CONFIG_MAX_CPUS because it will surely overflow gd structure.

Signed-off-by York Sun <[email protected]>
---
 arch/powerpc/cpu/mpc85xx/cpu.c |    5 +++++
 1 files changed, 5 insertions(+), 0 deletions(-)
arch/powerpc/cpu/mpc85xx/cpu.c +5 -0
index 515dd41..11b83d2 100644
@@ -127,6 +127,11 @@ int checkcpu (void)
 
 	printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr);
 
+	if (nr_cores > CONFIG_MAX_CPUS) {
+		panic("\nUnexpected number of cores: %d, max is %d\n",
+			nr_cores, CONFIG_MAX_CPUS);
+	}
+
 	get_sys_info(&sysinfo);
 
 	puts("Clock Configuration:");
Signature · 1 line
1.7.0.4
author
#4 lore raw

PATCH 5/11 powerpc/mpc85xx: use boot page translation for spin table address

In reply to York Sun

E6500 doesn't allow cache inhibit TLB alias. Use the boot page translation instead. The boot page is always cache inhibit.

Signed-off-by York Sun <[email protected]>
---
 arch/powerpc/cpu/mpc85xx/mp.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)
arch/powerpc/cpu/mpc85xx/mp.c +1 -1
index ffc2a9a..594f8e8 100644
@@ -205,7 +205,7 @@ ulong get_spin_phys_addr(void)
 	extern ulong __secondary_start_page;
 	extern ulong __spin_table;
 
-	return (determine_mp_bootpg() +
+	return (0xfffff000 +
 		(ulong)&__spin_table - (ulong)&__secondary_start_page);
 }
Signature · 1 line
1.7.0.4
#5 lore raw

PATCH 5/11 powerpc/mpc85xx: use boot page translation for spin table address

Quoted 2 lines · York Sun

E6500 doesn't allow cache inhibit TLB alias. Use the boot page translation instead. The boot page is always cache inhibit.

We're not supposed to create such aliases on any PPC core.

Please move to a cacheable spintable as described in ePAPR 1.1. This probably means not using the boot page window to access it.

-Scott

author
#6 lore raw

PATCH 5/11 powerpc/mpc85xx: use boot page translation for spin table address

Quoted 5 lines · Scott Wood
Quoted 2 lines · York Sun

E6500 doesn't allow cache inhibit TLB alias. Use the boot page translation instead. The boot page is always cache inhibit.

We're not supposed to create such aliases on any PPC core.

We seem to have been using it for quite a while, until it is broken here.

Quoted 4 lines

Please move to a cacheable spintable as described in ePAPR 1.1. This probably means not using the boot page window to access it.

No objection here.

York

#7 lore raw

PATCH 5/11 powerpc/mpc85xx: use boot page translation for spin table address

Quoted 9 lines · York Sun
Quoted 6 lines · Scott Wood
Quoted 3 lines · York Sun

E6500 doesn't allow cache inhibit TLB alias. Use the boot page translation
instead. The boot page is always cache inhibit.

We're not supposed to create such aliases on any PPC core.

We seem to have been using it for quite a while, until it is broken here.

Just because there wasn't a cop behind the billboard doesn't mean we weren't speeding. :-)

I've gotten machine checks on p4080 from such aliases under specific circumstances (just not in the specific case of what U-Boot does).

Quoted 4 lines
Quoted 3 lines

Please move to a cacheable spintable as described in ePAPR 1.1. This probably means not using the boot page window to access it.

No objection here.

While we're touching the spin table stuff, we really should fix the bug that we don't load the upper half of r3 on 64-bit so at least on non-e5500 we won't have old U-Boots floating around that don't do it.

-Scott

author
#8 lore raw

PATCH 6/11 powerpc/mpc85xx: Fix core cluster PLL calculation for Chassis generation 2

In reply to York Sun

Corenet based SoCs have different core clocks starting from Chassis generation 2. Cores are organized into clusters. Each cluster has up to 4 cores sharing same clock, which can be chosen from one of three PLLs in the cluster group with one of the devisors /1, /2 or /4. Two clusters are put together as a cluster group. These two clusters share the PLLs but may have different divisor. For example, core 0~3 are in cluster 1. Core 4~7 are in cluster 2. Core 8~11 are in cluster 3 and so on. Cluster 1 and 2 are cluster group A. Cluster 3 and 4 are in cluster group B. Cluster group A has PLL1, PLL2, PLL3. Cluster group B has PLL4, PLL5. Core 0~3 may have PLL1/2, core 4~7 may have PLL2/2. Core 8~11 may have PLL4/1.

PME and FMan blocks can take different PLLs, configured by RCW.

Signed-off-by York Sun <[email protected]>
---
 arch/powerpc/cpu/mpc85xx/speed.c      |  138 ++++++++++++++++++++++++++++++---
 arch/powerpc/include/asm/immap_85xx.h |   36 +++++----
 2 files changed, 148 insertions(+), 26 deletions(-)
arch/powerpc/cpu/mpc85xx/speed.c +128 -10
index 6bf49ee..7bf1133 100644
@@ -76,8 +76,8 @@ void get_sys_info (sys_info_t * sysInfo)
 		[13] = 2,	/* CC4 PPL / 2 */
 		[14] = 4,	/* CC4 PPL / 4 */
 	};
-	uint lcrr_div, i, freqCC_PLL[4], rcw_tmp;
-	uint ratio[4];
+	uint i, freqCC_PLL[6], rcw_tmp;
+	uint ratio[6];
 	unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
 	uint mem_pll_rat;
 

@@ -96,21 +96,139 @@ void get_sys_info (sys_info_t * sysInfo)
 	ratio[1] = (in_be32(&clk->pllc2gsr) >> 1) & 0x3f;
 	ratio[2] = (in_be32(&clk->pllc3gsr) >> 1) & 0x3f;
 	ratio[3] = (in_be32(&clk->pllc4gsr) >> 1) & 0x3f;
-	for (i = 0; i < 4; i++) {
+	ratio[4] = (in_be32(&clk->pllc5gsr) >> 1) & 0x3f;
+	ratio[5] = (in_be32(&clk->pllc6gsr) >> 1) & 0x3f;
+	for (i = 0; i < 6; i++) {
 		if (ratio[i] > 4)
 			freqCC_PLL[i] = sysclk * ratio[i];
 		else
 			freqCC_PLL[i] = sysInfo->freqSystemBus * ratio[i];
 	}
-	rcw_tmp = in_be32(&gur->rcwsr[3]);
+#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
+	/*
+	 * Each cluster has up to 4 cores, sharing the same PLL selection.
+	 * The cluster assignment is fixed per SoC. There is no way identify the
+	 * assignment so far, presuming the "first configuration" which is to
+	 * fill the lower cluster group first before moving up to next group.
+	 * PLL1, PLL2, PLL3 are cluster group A, feeding core 0~3 on cluster 1
+	 * and core 4~7 on cluster 2
+	 * PLL4, PLL5, PLL6 are cluster group B, feeding core 8~11 on cluster 3
+	 * and core 12~15 on cluster 4 if existing
+	 */
 	for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) {
-		u32 c_pll_sel = (in_be32(&clk->clkc0csr + cpu*8) >> 27) & 0xf;
+		u32 c_pll_sel = (in_be32(&clk->clkc0csr + (cpu / 4) * 8) >> 27)
+				& 0xf;
 		u32 cplx_pll = core_cplx_PLL[c_pll_sel];
+		if (cplx_pll > 3)
+			printf("Unsupported architecture configuration"
+				" in function %s\n", __func__);
+		cplx_pll += (cpu / 8) * 3;
 
 		sysInfo->freqProcessor[cpu] =
 			 freqCC_PLL[cplx_pll] / core_cplx_PLL_div[c_pll_sel];
 	}
+#define PME_CLK_SEL	0xe0000000
+#define PME_CLK_SHIFT	29
+#define FM1_CLK_SEL	0x1c000000
+#define FM1_CLK_SHIFT	26
+	rcw_tmp = in_be32(&gur->rcwsr[7]);
+
+#ifdef CONFIG_SYS_DPAA_PME
+	switch ((rcw_tmp & PME_CLK_SEL) >> PME_CLK_SHIFT) {
+	case 1:
+		sysInfo->freqPME = freqCC_PLL[0];
+		break;
+	case 2:
+		sysInfo->freqPME = freqCC_PLL[0] / 2;
+		break;
+	case 3:
+		sysInfo->freqPME = freqCC_PLL[0] / 3;
+		break;
+	case 4:
+		sysInfo->freqPME = freqCC_PLL[0] / 4;
+		break;
+	case 6:
+		sysInfo->freqPME = freqCC_PLL[1] / 2;
+		break;
+	case 7:
+		sysInfo->freqPME = freqCC_PLL[1] / 3;
+		break;
+	default:
+		printf("Error: Unknown PME clock select!\n");
+	case 0:
+		sysInfo->freqPME = sysInfo->freqSystemBus / 2;
+		break;
+
+	}
+#endif
 
+#ifdef CONFIG_SYS_DPAA_FMAN
+	switch ((rcw_tmp & FM1_CLK_SEL) >> FM1_CLK_SHIFT) {
+	case 1:
+		sysInfo->freqFMan[0] = freqCC_PLL[3];
+		break;
+	case 2:
+		sysInfo->freqFMan[0] = freqCC_PLL[3] / 2;
+		break;
+	case 3:
+		sysInfo->freqFMan[0] = freqCC_PLL[3] / 3;
+		break;
+	case 4:
+		sysInfo->freqFMan[0] = freqCC_PLL[3] / 4;
+		break;
+	case 6:
+		sysInfo->freqFMan[0] = freqCC_PLL[4] / 2;
+		break;
+	case 7:
+		sysInfo->freqFMan[0] = freqCC_PLL[4] / 3;
+		break;
+	default:
+		printf("Error: Unknown FMan1 clock select!\n");
+	case 0:
+		sysInfo->freqFMan[0] = sysInfo->freqSystemBus / 2;
+		break;
+	}
+#if (CONFIG_SYS_NUM_FMAN) == 2
+#define FM2_CLK_SEL	0x00000038
+#define FM2_CLK_SHIFT	3
+	rcw_tmp = in_be32(&gur->rcwsr[15]);
+	switch ((rcw_tmp & FM2_CLK_SEL) >> FM2_CLK_SHIFT) {
+	case 1:
+		sysInfo->freqFMan[1] = freqCC_PLL[4];
+		break;
+	case 2:
+		sysInfo->freqFMan[1] = freqCC_PLL[4] / 2;
+		break;
+	case 3:
+		sysInfo->freqFMan[1] = freqCC_PLL[4] / 3;
+		break;
+	case 4:
+		sysInfo->freqFMan[1] = freqCC_PLL[4] / 4;
+		break;
+	case 6:
+		sysInfo->freqFMan[1] = freqCC_PLL[3] / 2;
+		break;
+	case 7:
+		sysInfo->freqFMan[1] = freqCC_PLL[3] / 3;
+		break;
+	default:
+		printf("Error: Unknown FMan2 clock select!\n");
+	case 0:
+		sysInfo->freqFMan[1] = sysInfo->freqSystemBus / 2;
+		break;
+	}
+#endif	/* CONFIG_SYS_NUM_FMAN == 2 */
+#endif	/* CONFIG_SYS_DPAA_FMAN */
+
+#else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
+
+	for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) {
+		u32 c_pll_sel = (in_be32(&clk->clkc0csr + cpu*8) >> 27) & 0xf;
+		u32 cplx_pll = core_cplx_PLL[c_pll_sel];
+
+		sysInfo->freqProcessor[cpu] =
+			 freqCC_PLL[cplx_pll] / core_cplx_PLL_div[c_pll_sel];
+	}
 #define PME_CLK_SEL	0x80000000
 #define FM1_CLK_SEL	0x40000000
 #define FM2_CLK_SEL	0x20000000

@@ -158,11 +276,10 @@ void get_sys_info (sys_info_t * sysInfo)
 #endif
 #endif
 
-#else
-	uint plat_ratio,e500_ratio,half_freqSystemBus;
-#if defined(CONFIG_FSL_LBC)
-	uint lcrr_div;
-#endif
+#endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
+
+#else /* CONFIG_FSL_CORENET */
+	uint plat_ratio, e500_ratio, half_freqSystemBus;
 	int i;
 #ifdef CONFIG_QE
 	__maybe_unused u32 qe_ratio;

@@ -209,6 +326,7 @@ void get_sys_info (sys_info_t * sysInfo)
 #endif /* CONFIG_FSL_CORENET */
 
 #if defined(CONFIG_FSL_LBC)
+	uint lcrr_div;
 #if defined(CONFIG_SYS_LBC_LCRR)
 	/* We will program LCRR to this value later */
 	lcrr_div = CONFIG_SYS_LBC_LCRR & LCRR_CLKDIV;
arch/powerpc/include/asm/immap_85xx.h +20 -16
index ed42918..e5509b4 100644
@@ -1897,34 +1897,38 @@ typedef struct ccsr_gur {
 #define rmuliodnr rio1maintliodnr
 
 typedef struct ccsr_clk {
-	u32	clkc0csr;	/* Core 0 Clock control/status */
+	u32	clkc0csr;	/* 0x000 Core 0 Clock control/status */
 	u8	res1[0x1c];
-	u32	clkc1csr;	/* Core 1 Clock control/status */
+	u32	clkc1csr;	/* 0x020 Core 1 Clock control/status */
 	u8	res2[0x1c];
-	u32	clkc2csr;	/* Core 2 Clock control/status */
+	u32	clkc2csr;	/* 0x040 Core 2 Clock control/status */
 	u8	res3[0x1c];
-	u32	clkc3csr;	/* Core 3 Clock control/status */
+	u32	clkc3csr;	/* 0x060 Core 3 Clock control/status */
 	u8	res4[0x1c];
-	u32	clkc4csr;	/* Core 4 Clock control/status */
+	u32	clkc4csr;	/* 0x080 Core 4 Clock control/status */
 	u8	res5[0x1c];
-	u32	clkc5csr;	/* Core 5 Clock control/status */
+	u32	clkc5csr;	/* 0x0a0 Core 5 Clock control/status */
 	u8	res6[0x1c];
-	u32	clkc6csr;	/* Core 6 Clock control/status */
+	u32	clkc6csr;	/* 0x0c0 Core 6 Clock control/status */
 	u8	res7[0x1c];
-	u32	clkc7csr;	/* Core 7 Clock control/status */
+	u32	clkc7csr;	/* 0x0e0 Core 7 Clock control/status */
 	u8	res8[0x71c];
-	u32	pllc1gsr;	/* Cluster PLL 1 General Status */
+	u32	pllc1gsr;	/* 0x800 Cluster PLL 1 General Status */
 	u8	res10[0x1c];
-	u32	pllc2gsr;	/* Cluster PLL 2 General Status */
+	u32	pllc2gsr;	/* 0x820 Cluster PLL 2 General Status */
 	u8	res11[0x1c];
-	u32	pllc3gsr;	/* Cluster PLL 3 General Status */
+	u32	pllc3gsr;	/* 0x840 Cluster PLL 3 General Status */
 	u8	res12[0x1c];
-	u32	pllc4gsr;	/* Cluster PLL 4 General Status */
-	u8	res13[0x39c];
-	u32	pllpgsr;	/* Platform PLL General Status */
+	u32	pllc4gsr;	/* 0x860 Cluster PLL 4 General Status */
+	u8	res13[0x1c];
+	u32	pllc5gsr;	/* 0x880 Cluster PLL 5 General Status */
 	u8	res14[0x1c];
-	u32	plldgsr;	/* DDR PLL General Status */
-	u8	res15[0x3dc];
+	u32	pllc6gsr;	/* 0x8a0 Cluster PLL 6 General Status */
+	u8	res15[0x35c];
+	u32	pllpgsr;	/* 0xc00 Platform PLL General Status */
+	u8	res16[0x1c];
+	u32	plldgsr;	/* 0xc20 DDR PLL General Status */
+	u8	res17[0x3dc];
 } ccsr_clk_t;
 
 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
Signature · 1 line
1.7.0.4
author
#9 lore raw

PATCH 7/11 powerpc/mpc85xx: expand SERDES reference clock select bit

In reply to York Sun

Expand the reference clock select to three bits
000: 100 MHz
001: 125 MHz
010: 156.25MHz
011: 150 MHz
100: 161.1328125 MHz
All others reserved

Signed-off-by York Sun <[email protected]>
---
 arch/powerpc/include/asm/immap_85xx.h |    3 ++-
 1 files changed, 2 insertions(+), 1 deletions(-)
arch/powerpc/include/asm/immap_85xx.h +2 -1
index e5509b4..15d2db4 100644
@@ -2413,12 +2413,13 @@ typedef struct serdes_corenet {
 #define SRDS_RSTCTL_RSTERR	0x20000000
 #define SRDS_RSTCTL_SDPD	0x00000020
 		u32	pllcr0; /* PLL Control Register 0 */
-#define SRDS_PLLCR0_RFCK_SEL_MASK	0x30000000
+#define SRDS_PLLCR0_RFCK_SEL_MASK	0x70000000
 #define SRDS_PLLCR0_PVCOCNT_EN		0x02000000
 #define SRDS_PLLCR0_RFCK_SEL_100	0x00000000
 #define SRDS_PLLCR0_RFCK_SEL_125	0x10000000
 #define SRDS_PLLCR0_RFCK_SEL_156_25	0x20000000
 #define SRDS_PLLCR0_RFCK_SEL_150	0x30000000
+#define SRDS_PLLCR0_RFCK_SEL_161_13	0x40000000
 #define SRDS_PLLCR0_FRATE_SEL_MASK	0x00030000
 #define SRDS_PLLCR0_FRATE_SEL_5		0x00000000
 #define SRDS_PLLCR0_FRATE_SEL_6_25	0x00010000
Signature · 1 line
1.7.0.4
author
#10 lore raw

PATCH 8/11 powerpc/e6500: Move QCSP registers for QMan v3

In reply to York Sun

The QCSP registers are at offset 0x1000 for SoCs with QMan v3.

Signed-off-by York Sun <[email protected]>
---
 arch/powerpc/include/asm/immap_85xx.h |   19 ++++++++++++++++++-
 1 files changed, 18 insertions(+), 1 deletions(-)
arch/powerpc/include/asm/immap_85xx.h +18 -1
index 15d2db4..20e6915 100644
@@ -2573,13 +2573,18 @@ typedef struct ccsr_sec {
 #endif
 
 typedef struct ccsr_qman {
+#ifdef CONFIG_SYS_FSL_QMAN_V3
+	/* T4240, PSC9164 */
+	u8	res0[0x200];
+#else
+	/* P4080, SC4080, P3041, P5020, P1023, SC1023 */
 	struct {
 		u32	qcsp_lio_cfg;	/* 0x0 - SW Portal n LIO cfg */
 		u32	qcsp_io_cfg;	/* 0x4 - SW Portal n IO cfg */
 		u32	res;
 		u32	qcsp_dd_cfg;	/* 0xc - SW Portal n Dynamic Debug cfg */
 	} qcsp[32];
-
+#endif
 	/* Not actually reserved, but irrelevant to u-boot */
 	u8	res[0xbf8 - 0x200];
 	u32	ip_rev_1;

@@ -2604,6 +2609,18 @@ typedef struct ccsr_qman {
 	u32	ci_rlm_cfg;	/* Initiator Read Latency Monitor Cfg */
 	u32	ci_rlm_avg;	/* Initiator Read Latency Monitor Avg */
 	u8	res7[0x2e8];
+#ifdef CONFIG_SYS_FSL_QMAN_V3
+	/*
+	 * T4240 50 software portals
+	 * PSC9164 25 software portals
+	 */
+	struct {
+		u32	qcsp_lio_cfg;	/* 0x0 - SW Portal n LIO cfg */
+		u32	qcsp_io_cfg;	/* 0x4 - SW Portal n IO cfg */
+		u32	res;
+		u32	qcsp_dd_cfg;	/* 0xc - SW Portal n Dynamic Debug cfg */
+	} qcsp[50];
+#endif
 } ccsr_qman_t;
 
 typedef struct ccsr_bman {
Signature · 1 line
1.7.0.4
#11 lore raw

PATCH 8/11 powerpc/e6500: Move QCSP registers for QMan v3

Quoted 12 lines · York Sun

The QCSP registers are at offset 0x1000 for SoCs with QMan v3.

Signed-off-by York Sun <[email protected]>
---
 arch/powerpc/include/asm/immap_85xx.h |   19 ++++++++++++++++++-
 1 files changed, 18 insertions(+), 1 deletions(-)
arch/powerpc/include/asm/immap_85xx.h +0 -0
index 15d2db4..20e6915 100644

arch/powerpc/include/asm/immap_85xx.h typedef struct ccsr_sec { · line 2577

Quoted 5 lines
arch/powerpc/include/asm/immap_85xx.h +2 -0
@@ -2573,13 +2573,18 @@ typedef struct ccsr_sec {
 #endif
 
 typedef struct ccsr_qman {
+#ifdef CONFIG_SYS_FSL_QMAN_V3
+       /* T4240, PSC9164 */

B4860 is the name, not PSC9164

arch/powerpc/include/asm/immap_85xx.h typedef struct ccsr_sec { · line 2580

Quoted 3 lines
arch/powerpc/include/asm/immap_85xx.h +3 -0
+       u8      res0[0x200];
+#else
+       /* P4080, SC4080, P3041, P5020, P1023, SC1023 */

This comment is somewhat specific. There are others that aren't listed here. And I'm not sure the SC1023 exists (anymore). Probably we should just mention the version of the QMan that this code is for.

Quoted 12 lines
arch/powerpc/include/asm/immap_85xx.h +1 -1
        struct {
                u32     qcsp_lio_cfg;   /* 0x0 - SW Portal n LIO cfg */
                u32     qcsp_io_cfg;    /* 0x4 - SW Portal n IO cfg */
                u32     res;
                u32     qcsp_dd_cfg;    /* 0xc - SW Portal n Dynamic Debug cfg */
        } qcsp[32];
-
+#endif
        /* Not actually reserved, but irrelevant to u-boot */
        u8      res[0xbf8 - 0x200];
        u32     ip_rev_1;

arch/powerpc/include/asm/immap_85xx.h typedef struct ccsr_qman { · line 2616

Quoted 8 lines
arch/powerpc/include/asm/immap_85xx.h +5 -0
@@ -2604,6 +2609,18 @@ typedef struct ccsr_qman {
        u32     ci_rlm_cfg;     /* Initiator Read Latency Monitor Cfg */
        u32     ci_rlm_avg;     /* Initiator Read Latency Monitor Avg */
        u8      res7[0x2e8];
+#ifdef CONFIG_SYS_FSL_QMAN_V3
+       /*
+        * T4240 50 software portals
+        * PSC9164 25 software portals
+        */

B4860

Quoted 14 lines
arch/powerpc/include/asm/immap_85xx.h +7 -1
+       struct {
+               u32     qcsp_lio_cfg;   /* 0x0 - SW Portal n LIO cfg */
+               u32     qcsp_io_cfg;    /* 0x4 - SW Portal n IO cfg */
+               u32     res;
+               u32     qcsp_dd_cfg;    /* 0xc - SW Portal n Dynamic Debug cfg */
+       } qcsp[50];
+#endif
 } ccsr_qman_t;
 
 typedef struct ccsr_bman {
--

1.7.0.4

author
#12 lore raw

PATCH 8/11 powerpc/e6500: Move QCSP registers for QMan v3

Quoted 15 lines · Andy Fleming
Quoted 14 lines · York Sun

The QCSP registers are at offset 0x1000 for SoCs with QMan v3.

Signed-off-by York Sun <[email protected]>
---
 arch/powerpc/include/asm/immap_85xx.h |   19 ++++++++++++++++++-
 1 files changed, 18 insertions(+), 1 deletions(-)
arch/powerpc/include/asm/immap_85xx.h +0 -0
index 15d2db4..20e6915 100644
@@ -2573,13 +2573,18 @@ typedef struct ccsr_sec {
 #endif
Quoted 6 lines

arch/powerpc/include/asm/immap_85xx.h typedef struct ccsr_sec { · line 2577

Quoted 3 lines
arch/powerpc/include/asm/immap_85xx.h +2 -0
 typedef struct ccsr_qman {
+#ifdef CONFIG_SYS_FSL_QMAN_V3
+       /* T4240, PSC9164 */

B4860 is the name, not PSC9164

Thanks for pointing out. This patch was written when the name was PSC9164. I will fix it in next version, along with other feedback.

York

author
#13 lore raw

PATCH 9/11 powerpc/mpc85xx: Add RCW bits and registers for SerDes for corenet2

In reply to York Sun

Corenet 2nd generation Chassis has different RCW and registers for SerDes.

Signed-off-by York Sun <[email protected]>
Signed-off-by Prabhakar Kushwaha <[email protected]>
---
 arch/powerpc/include/asm/immap_85xx.h |   99 +++++++++++++++++++++++++++++++--
 1 files changed, 94 insertions(+), 5 deletions(-)
arch/powerpc/include/asm/immap_85xx.h +94 -5
index 20e6915..783bc28 100644
@@ -1755,13 +1755,30 @@ typedef struct ccsr_gur {
 	u32	brrl;		/* Boot release */
 	u8	res17[24];
 	u32	rcwsr[16];	/* Reset control word status */
-#ifndef CONFIG_SYS_FSL_QORIQ_CHASSIS2
-#define FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT	17
-#define FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK	0x1f
-#else
+
+#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
 #define FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT	16
 #define FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK	0x3f
-#endif
+#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL		0xfc000000
+#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT	26
+#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL		0x00fe0000
+#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT	17
+#define FSL_CORENET2_RCWSR4_SRDS3_PRTCL		0x0000f800
+#define FSL_CORENET2_RCWSR4_SRDS3_PRTCL_SHIFT	11
+#define FSL_CORENET2_RCWSR4_SRDS4_PRTCL		0x000000f8
+#define FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT	3
+#define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S1_PLL1	0x00800000
+#define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S1_PLL2	0x00400000
+#define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S2_PLL1	0x00200000
+#define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S2_PLL2	0x00100000
+#define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S3_PLL1	0x00080000
+#define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S3_PLL2	0x00040000
+#define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S4_PLL1	0x00020000
+#define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S4_PLL2	0x00010000
+
+#else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
+#define FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT	17
+#define FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK	0x1f
 #define FSL_CORENET_RCWSR4_SRDS_PRTCL		0xfc000000
 #define FSL_CORENET_RCWSR5_DDR_SYNC		0x00000080
 #define FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT		 7

@@ -1770,6 +1787,8 @@ typedef struct ccsr_gur {
 #define FSL_CORENET_RCWSR6_SB_EN		0x00200000
 #define FSL_CORENET_RCWSRn_SRDS_LPD_B2		0x3c000000 /* bits 162..165 */
 #define FSL_CORENET_RCWSRn_SRDS_LPD_B3		0x003c0000 /* bits 170..173 */
+#endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
+
 #define FSL_CORENET_RCWSR7_MCK_TO_PLAT_RAT	0x00400000
 #define FSL_CORENET_RCWSR8_HOST_AGT_B1		0x00e00000
 #define FSL_CORENET_RCWSR8_HOST_AGT_B2		0x00100000

@@ -2405,6 +2424,75 @@ typedef struct ccsr_gur {
 
 #define SDHCDCR_CD_INV		0x80000000 /* invert SDHC card detect */
 
+#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
+#define MAX_SERDES 4
+typedef struct serdes_corenet {
+	struct {
+		u32	rstctl;	/* Reset Control Register */
+#define SRDS_RSTCTL_RST		0x80000000
+#define SRDS_RSTCTL_RSTDONE	0x40000000
+#define SRDS_RSTCTL_RSTERR	0x20000000
+#define SRDS_RSTCTL_SWRST	0x10000000
+#define SRDS_RSTCTL_SDPD	0x00000020
+		u32	pllcr0; /* PLL Control Register 0 */
+#define SRDS_PLLCR0_POFF		0x80000000
+#define SRDS_PLLCR0_RFCK_SEL_MASK	0x70000000
+#define SRDS_PLLCR0_RFCK_SEL_100	0x00000000
+#define SRDS_PLLCR0_RFCK_SEL_125	0x10000000
+#define SRDS_PLLCR0_RFCK_SEL_156_25	0x20000000
+#define SRDS_PLLCR0_RFCK_SEL_150	0x30000000
+#define SRDS_PLLCR0_RFCK_SEL_161_13	0x40000000
+#define SRDS_PLLCR0_RFCK_SEL_122_88	0x50000000
+#define SRDS_PLLCR0_FRATE_SEL_MASK	0x000f0000
+#define SRDS_PLLCR0_FRATE_SEL_5		0x00000000
+#define SRDS_PLLCR0_FRATE_SEL_3_75	0x00050000
+#define SRDS_PLLCR0_FRATE_SEL_5_15	0x00060000
+#define SRDS_PLLCR0_FRATE_SEL_4		0x00070000
+#define SRDS_PLLCR0_FRATE_SEL_3_12	0x00090000
+#define SRDS_PLLCR0_FRATE_SEL_3		0x000a0000
+		u32	pllcr1; /* PLL Control Register 1 */
+#define SRDS_PLLCR1_PLL_BWSEL	0x08000000
+		u32	res_0c;	/* 0x00c */
+		u32	pllcr3;
+		u32	pllcr4;
+		u8	res_18[0x20-0x18];
+	} bank[2];
+	u8	res_40[0x90-0x40];
+	u32	srdstcalcr;	/* 0x90 TX Calibration Control */
+	u8	res_94[0xa0-0x94];
+	u32	srdsrcalcr;	/* 0xa0 RX Calibration Control */
+	u8	res_a4[0xb0-0xa4];
+	u32	srdsgr0;	/* 0xb0 General Register 0 */
+	u8	res_b4[0xe0-0xb4];
+	u32	srdspccr0;	/* 0xe0 Protocol Converter Config 0 */
+	u32	srdspccr1;	/* 0xe4 Protocol Converter Config 1 */
+	u32	srdspccr2;	/* 0xe8 Protocol Converter Config 2 */
+	u32	srdspccr3;	/* 0xec Protocol Converter Config 3 */
+	u32	srdspccr4;	/* 0xf0 Protocol Converter Config 4 */
+	u8	res_f4[0x100-0xf4];
+	struct {
+		u32	lnpssr;	/* 0x100, 0x120, ..., 0x1e0 */
+		u8	res_104[0x120-0x104];
+	} srdslnpssr[8];
+	u8	res_200[0x800-0x200];
+	struct {
+/* fixme: Document is wrong here */
+		u32	gcr0;	/* 0x800 General Control Register 0 */
+		u32	gcr1;	/* 0x804 General Control Register 1 */
+		u32	gcr2;	/* 0x808 General Control Register 2 */
+		u32	res_80c;
+		u32	recr0;	/* 0x810 Receive Equalization Control */
+		u32	res_814;
+		u32	tecr0;	/* 0x818 Transmit Equalization Control */
+		u32	res_81c;
+		u32	ttlcr0;	/* 0x820 Transition Tracking Loop Ctrl 0 */
+		u8	res_824[0x840-0x824];
+	} lane[8];	/* Lane A, B, C, D, E, F, G, H */
+	u8	res_a00[0x1000-0xa00];	/* from 0xa00 to 0xfff */
+} serdes_corenet_t;
+
+#else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
+
 typedef struct serdes_corenet {
 	struct {
 		u32	rstctl;	/* Reset Control Register */

@@ -2464,6 +2552,7 @@ typedef struct serdes_corenet {
 	} lane[24];
 	u32 res6[384];
 } serdes_corenet_t;
+#endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
 
 typedef struct serdes2_corenet {
 	u32	rstctl;	/* Reset Control Register */
Signature · 1 line
1.7.0.4
author
#14 lore raw

PATCH 10/11 powerpc/corenet2: Add SerDes for corenet2

In reply to York Sun

Create new files to handle 2nd generation Chassis as the registers are organized differently.

- Add SerDes protocol parsing and detection
- Add support of 4 SerDes
- Add CPRI protocol in fsl_serdes.h
The Common Public Radio Interface (CPRI) is publicly available specification that standardizes the protocol interface between the radio equipment control (REC) and the radio equipment (RE) in wireless basestations. This allows interoperability of equipment from different vendors,and preserves the software investment made by wireless service providers.

Signed-off-by York Sun <[email protected]>
Signed-off-by Prabhakar Kushwaha <[email protected]>
---
 arch/powerpc/cpu/mpc85xx/Makefile              |    3 +-
 arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c |  159 ++++++++++++++++++++++++
 arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.h |   33 +++++
 arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.h  |   13 --
 arch/powerpc/include/asm/config_mpc85xx.h      |    6 +
 arch/powerpc/include/asm/fsl_serdes.h          |   31 +++++
 arch/powerpc/include/asm/immap_85xx.h          |    5 +-
 7 files changed, 235 insertions(+), 15 deletions(-)
 create mode 100644 arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c
 create mode 100644 arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.h
arch/powerpc/cpu/mpc85xx/Makefile +2 -1
index da51039..c60320c 100644
@@ -87,7 +87,8 @@ COBJS-$(CONFIG_PPC_P5040) += p5040_ids.o
 
 COBJS-$(CONFIG_QE)	+= qe_io.o
 COBJS-$(CONFIG_CPM2)	+= serial_scc.o
-COBJS-$(CONFIG_FSL_CORENET) += fsl_corenet_serdes.o
+COBJS-$(CONFIG_SYS_FSL_QORIQ_CHASSIS1) += fsl_corenet_serdes.o
+COBJS-$(CONFIG_SYS_FSL_QORIQ_CHASSIS2) += fsl_corenet2_serdes.o
 COBJS-$(CONFIG_SECURE_BOOT) += fsl_sfp_snvs.o
 COBJS-$(CONFIG_CMD_ESBC_VALIDATE) += cmd_esbc_validate.o fsl_validate.o
arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c new file +159 -0

159 lines not on this page · raw message

arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.h new file +33 -0
new file mode 100644
index 0000000..6529a83
@@ -0,0 +1,33 @@
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __FSL_CORENET2_SERDES_H
+#define __FSL_CORENET2_SERDES_H
+
+enum srds {
+	FSL_SRDS_1  = 0,
+	FSL_SRDS_2  = 1,
+	FSL_SRDS_3  = 2,
+	FSL_SRDS_4  = 3,
+};
+
+int is_serdes_prtcl_valid(int serdes, u32 prtcl);
+int serdes_lane_enabled(int lane);
+enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane);
+#endif /* __FSL_CORENET2_SERDES_H */
arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.h +0 -13
index 96d14ec..3b9816c 100644
@@ -22,19 +22,6 @@
 #ifndef __FSL_CORENET_SERDES_H
 #define __FSL_CORENET_SERDES_H
 
-#if defined(CONFIG_PPC_P5040)
-/*
- * The fourth SerDes bank is on SerDes2, but U-boot currently only supports
- * one SerDes controller.  For now, pretend that we have three banks and 18
- * lanes.
- */
-#define SRDS_MAX_LANES		18
-#define SRDS_MAX_BANK		3
-#else
-#define SRDS_MAX_LANES		18
-#define SRDS_MAX_BANK		3
-#endif
-
 enum srds_bank {
 	FSL_SRDS_BANK_1  = 0,
 	FSL_SRDS_BANK_2  = 1,
arch/powerpc/include/asm/config_mpc85xx.h +6 -0
index 0b4a519..fe21b61 100644
@@ -313,6 +313,7 @@
 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM	2
 
 #elif defined(CONFIG_PPC_P2041) /* also supports P2040 */
+#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
 #define CONFIG_MAX_CPUS			4
 #define CONFIG_SYS_FSL_NUM_CC_PLLS	2
 #define CONFIG_SYS_FSL_NUM_LAWS		32

@@ -343,6 +344,7 @@
 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
 
 #elif defined(CONFIG_PPC_P3041)
+#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
 #define CONFIG_MAX_CPUS			4
 #define CONFIG_SYS_FSL_NUM_CC_PLLS	2
 #define CONFIG_SYS_FSL_NUM_LAWS		32

@@ -374,6 +376,7 @@
 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
 
 #elif defined(CONFIG_PPC_P3060)
+#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
 #define CONFIG_MAX_CPUS			8
 #define CONFIG_SYS_FSL_NUM_CC_PLLS	4
 #define CONFIG_SYS_FSL_NUM_LAWS		32

@@ -397,6 +400,7 @@
 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000
 
 #elif defined(CONFIG_PPC_P4080) /* also supports P4040 */
+#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
 #define CONFIG_MAX_CPUS			8
 #define CONFIG_SYS_FSL_NUM_CC_PLLS	4
 #define CONFIG_SYS_FSL_NUM_LAWS		32

@@ -436,6 +440,7 @@
 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000
 
 #elif defined(CONFIG_PPC_P5020) /* also supports P5010 */
+#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
 #define CONFIG_MAX_CPUS			2
 #define CONFIG_SYS_FSL_NUM_CC_PLLS	2
 #define CONFIG_SYS_FSL_NUM_LAWS		32

@@ -464,6 +469,7 @@
 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xc0000000
 
 #elif defined(CONFIG_PPC_P5040)
+#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
 #define CONFIG_MAX_CPUS			4
 #define CONFIG_SYS_FSL_NUM_CC_PLLS	3
 #define CONFIG_SYS_FSL_NUM_LAWS		32
arch/powerpc/include/asm/fsl_serdes.h +31 -0
index 22525f1..9a7c3a1 100644
@@ -37,11 +37,17 @@ enum srds_prtcl {
 	SGMII_FM1_DTSEC3,
 	SGMII_FM1_DTSEC4,
 	SGMII_FM1_DTSEC5,
+	SGMII_FM1_DTSEC6,
+	SGMII_FM1_DTSEC9,
+	SGMII_FM1_DTSEC10,
 	SGMII_FM2_DTSEC1,
 	SGMII_FM2_DTSEC2,
 	SGMII_FM2_DTSEC3,
 	SGMII_FM2_DTSEC4,
 	SGMII_FM2_DTSEC5,
+	SGMII_FM2_DTSEC6,
+	SGMII_FM2_DTSEC9,
+	SGMII_FM2_DTSEC10,
 	SGMII_TSEC1,
 	SGMII_TSEC2,
 	SGMII_TSEC3,

@@ -49,6 +55,31 @@ enum srds_prtcl {
 	XAUI_FM1,
 	XAUI_FM2,
 	AURORA,
+	CPRI1,
+	CPRI2,
+	CPRI3,
+	CPRI4,
+	CPRI5,
+	CPRI6,
+	CPRI7,
+	CPRI8,
+	XAUI_FM1_MAC9,
+	XAUI_FM1_MAC10,
+	XAUI_FM2_MAC9,
+	XAUI_FM2_MAC10,
+	HIGIG_FM1_MAC9,
+	HIGIG_FM1_MAC10,
+	HIGIG_FM2_MAC9,
+	HIGIG_FM2_MAC10,
+	QSGMII_FM1_A,		/* A indicates MACs 1-4 */
+	QSGMII_FM1_B,		/* B indicates MACs 5,6,9,10 */
+	QSGMII_FM2_A,
+	QSGMII_FM2_B,
+	XFI_FM1_MAC9,
+	XFI_FM1_MAC10,
+	XFI_FM2_MAC9,
+	XFI_FM2_MAC10,
+	INTERLAKEN,
 };
 
 int is_serdes_configured(enum srds_prtcl device);
arch/powerpc/include/asm/immap_85xx.h +4 -1
index 783bc28..020475b 100644
@@ -2426,6 +2426,8 @@ typedef struct ccsr_gur {
 
 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
 #define MAX_SERDES 4
+#define SRDS_MAX_LANES 8
+#define SRDS_MAX_BANK 2
 typedef struct serdes_corenet {
 	struct {
 		u32	rstctl;	/* Reset Control Register */

@@ -2476,7 +2478,6 @@ typedef struct serdes_corenet {
 	} srdslnpssr[8];
 	u8	res_200[0x800-0x200];
 	struct {
-/* fixme: Document is wrong here */
 		u32	gcr0;	/* 0x800 General Control Register 0 */
 		u32	gcr1;	/* 0x804 General Control Register 1 */
 		u32	gcr2;	/* 0x808 General Control Register 2 */

@@ -2493,6 +2494,8 @@ typedef struct serdes_corenet {
 
 #else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
 
+#define SRDS_MAX_LANES		18
+#define SRDS_MAX_BANK		3
 typedef struct serdes_corenet {
 	struct {
 		u32	rstctl;	/* Reset Control Register */
Signature · 1 line
1.7.0.4
author
#15 lore raw

PATCH 11/11 powerpc/corenet2: fix mismatch DDR sync bit from RCW

In reply to York Sun

Corenet 2nd generation Chassis doesn't have ddr_sync bit in RCW. Only async mode is supported.

Signed-off-by York Sun <[email protected]>
---
 arch/powerpc/cpu/mpc85xx/cpu.c |   10 ++++++++--
 1 files changed, 8 insertions(+), 2 deletions(-)
arch/powerpc/cpu/mpc85xx/cpu.c +8 -2
index 11b83d2..95f435e 100644
@@ -60,7 +60,8 @@ int checkcpu (void)
 	uint major, minor;
 	struct cpu_type *cpu;
 	char buf1[32], buf2[32];
-#if defined(CONFIG_DDR_CLK_FREQ) || defined(CONFIG_FSL_CORENET)
+#if defined(CONFIG_DDR_CLK_FREQ) || \
+	(defined(CONFIG_FSL_CORENET) && !defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2))
 	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 #endif /* CONFIG_FSL_CORENET */
 #ifdef CONFIG_DDR_CLK_FREQ

@@ -68,8 +69,13 @@ int checkcpu (void)
 		>> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
 #else
 #ifdef CONFIG_FSL_CORENET
-	u32 ddr_sync = ((gur->rcwsr[5]) & FSL_CORENET_RCWSR5_DDR_SYNC)
+	u32 ddr_sync ;
+#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
+	ddr_sync = 0;	/* only async mode is supported */
+#else
+	ddr_sync = ((gur->rcwsr[5]) & FSL_CORENET_RCWSR5_DDR_SYNC)
 		>> FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT;
+#endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
 #else
 	u32 ddr_ratio = 0;
 #endif /* CONFIG_FSL_CORENET */
Signature · 1 line
1.7.0.4
#16 lore raw

PATCH 1/11 powerpc/mpc85xx: Enable L2 at the beginning of U-boot for E6500

In reply to York Sun
Quoted 16 lines · York Sun

Using E6500 L1 cache as initram requires L2 cache enabled. Add l2-cache cluster enabling.

Signed-off-by York Sun <[email protected]>
Signed-off-by Kumar Gala <[email protected]>
---
 arch/powerpc/cpu/mpc85xx/cpu_init.c   |   39 ++++++++++++++++++++++-
 arch/powerpc/cpu/mpc85xx/start.S      |   57 +++++++++++++++++++++++++++++++++
 arch/powerpc/include/asm/immap_85xx.h |   43 +++++++++++++++++++++++++
 3 files changed, 138 insertions(+), 1 deletions(-)
arch/powerpc/cpu/mpc85xx/cpu_init.c +0 -0
index 2c78905..1a2858a 100644

arch/powerpc/cpu/mpc85xx/cpu_init.c static void __fsl_serdes__init(void) · line 313

Quoted 5 lines
arch/powerpc/cpu/mpc85xx/cpu_init.c +2 -0
@@ -309,6 +309,34 @@ static void __fsl_serdes__init(void)
 }
 __attribute__((weak, alias("__fsl_serdes__init"))) void fsl_serdes_init(void);
 
+#ifdef CONFIG_E6500
+int enable_cluster_l2(void)

If enabling L2 is required for the stack, how are we enabling it in C code? Is this just for non-boot clusters?

Quoted 5 lines
arch/powerpc/cpu/mpc85xx/cpu_init.c +5 -0
+{
+	int i = 0;
+	u32 cluster;
+	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	struct ccsr_cluster_l2 *l2cache;

arch/powerpc/cpu/mpc85xx/cpu_init.c static void __fsl_serdes__init(void) · line 328

Quoted 10 lines
arch/powerpc/cpu/mpc85xx/cpu_init.c +10 -0
+
+	cluster = in_be32(&gur->tp_cluster[i++].lower);
+	if (cluster & TP_CLUSTER_EOC)
+		return 0;
+
+	do {
+		l2cache = (void *)(CONFIG_SYS_FSL_CLUSTER_1_L2 + i * 0x40000);
+		cluster = in_be32(&gur->tp_cluster[i++].lower);
+
+		printf("enable l2 for cluster %d %p\n", i, l2cache);

This should be a debug message (or removed), not a normal printf.

arch/powerpc/cpu/mpc85xx/cpu_init.c static void __fsl_serdes__init(void) · line 332

Quoted 4 lines
arch/powerpc/cpu/mpc85xx/cpu_init.c +4 -0
+
+		out_be32(&l2cache->l2csr0, L2CSR0_L2FI|L2CSR0_L2LFC);
+		while ((in_be32(&l2cache->l2csr0) & (L2CSR0_L2FI|L2CSR0_L2LFC)) != 0)
+			;

Timeout?

arch/powerpc/cpu/mpc85xx/cpu_init.c int cpu_init_r(void) · line 357

Quoted 9 lines
arch/powerpc/cpu/mpc85xx/cpu_init.c +5 -0
@@ -322,6 +350,11 @@ int cpu_init_r(void)
 #ifdef CONFIG_SYS_LBC_LCRR
 	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
 #endif
+#ifdef CONFIG_L2_CACHE
+	volatile ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR;
+#elif defined(CONFIG_E6500)
+	struct ccsr_cluster_l2 * l2cache = (void *)CONFIG_SYS_FSL_CLUSTER_1_L2;
+#endif

If CONFIG_L2_CACHE doesn't apply to e6500, then CONFIG_L2_CACHE is misnamed.

Quoted 23 lines
arch/powerpc/cpu/mpc85xx/start.S +15 -0
index 2e1d265..739127f 100644
@@ -762,6 +762,63 @@ delete_temp_tlbs:
 	tlbwe
 #endif /* #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS) */
 
+#ifdef CONFIG_E6500
+create_ccsr_l2_tlb:
+	/*
+	 * Create a TLB for the MMR location of CCSR
+	 * to access L2CSR0 register
+	 */
+	lis     r0, FSL_BOOKE_MAS0(0, 0, 0)@h
+	ori     r0, r0, FSL_BOOKE_MAS0(0, 0, 0)@l
+
+	lis     r1, FSL_BOOKE_MAS1(1, 0, 0, 0, BOOKE_PAGESZ_4K)@h
+	ori     r1, r1, FSL_BOOKE_MAS1(1, 0, 0, 0, BOOKE_PAGESZ_4K)@l
+	lis     r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR + 0xC20000, (MAS2_I|MAS2_G))@h
+	ori     r2, r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR + 0xC20000, (MAS2_I|MAS2_G))@l
+	lis     r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS_LOW + 0xC20000, 0, (MAS3_SW|MAS3_SR))@h
+	ori     r3, r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS_LOW + 0xC20000, 0, (MAS3_SW|MAS3_SR))@l

arch/powerpc/cpu/mpc85xx/start.S delete_temp_tlbs: · line 789

Quoted 10 lines
arch/powerpc/cpu/mpc85xx/start.S +10 -0
+	lis	r7, CONFIG_SYS_CCSRBAR_PHYS_HIGH at h
+	ori	r7, r7, CONFIG_SYS_CCSRBAR_PHYS_HIGH at l
+	mtspr   MAS0, r0
+	mtspr   MAS1, r1
+	mtspr   MAS2, r2
+	mtspr   MAS3, r3
+	mtspr   MAS7, r7
+	isync
+	msync
+	tlbwe

Let's make a macro (asm, not cpp) out of this instead of copy and pasting all over the place. And stop misusing r1/r2.

-Scott

author
#17 lore raw

PATCH 1/11 powerpc/mpc85xx: Enable L2 at the beginning of U-boot for E6500

Quoted 20 lines · Scott Wood
Quoted 19 lines · York Sun

Using E6500 L1 cache as initram requires L2 cache enabled. Add l2-cache cluster enabling.

Signed-off-by York Sun <[email protected]>
Signed-off-by Kumar Gala <[email protected]>
---
  arch/powerpc/cpu/mpc85xx/cpu_init.c   |   39 ++++++++++++++++++++++-
  arch/powerpc/cpu/mpc85xx/start.S      |   57 +++++++++++++++++++++++++++++++++
  arch/powerpc/include/asm/immap_85xx.h |   43 +++++++++++++++++++++++++
  3 files changed, 138 insertions(+), 1 deletions(-)
arch/powerpc/cpu/mpc85xx/cpu_init.c +0 -0
index 2c78905..1a2858a 100644
@@ -309,6 +309,34 @@ static void __fsl_serdes__init(void)
  }
  __attribute__((weak, alias("__fsl_serdes__init"))) void fsl_serdes_init(void);
Quoted 5 lines

arch/powerpc/cpu/mpc85xx/cpu_init.c static void __fsl_serdes__init(void) · line 313

Quoted 2 lines
arch/powerpc/cpu/mpc85xx/cpu_init.c +2 -0
+#ifdef CONFIG_E6500
+int enable_cluster_l2(void)

If enabling L2 is required for the stack, how are we enabling it in C code? Is this just for non-boot clusters?

Yes, this is for non-boot clusters. The boot cluster is enabled in start.S.

Quoted 10 lines
Quoted 10 lines
arch/powerpc/cpu/mpc85xx/cpu_init.c +9 -0
+{
+	int i = 0;
+	u32 cluster;
+	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	struct ccsr_cluster_l2 *l2cache;
+
+	cluster = in_be32(&gur->tp_cluster[i++].lower);
+	if (cluster & TP_CLUSTER_EOC)
+		return 0;
Quoted 8 lines

arch/powerpc/cpu/mpc85xx/cpu_init.c static void __fsl_serdes__init(void) · line 328

Quoted 6 lines
arch/powerpc/cpu/mpc85xx/cpu_init.c +6 -0
+
+	do {
+		l2cache = (void *)(CONFIG_SYS_FSL_CLUSTER_1_L2 + i * 0x40000);
+		cluster = in_be32(&gur->tp_cluster[i++].lower);
+
+		printf("enable l2 for cluster %d %p\n", i, l2cache);

This should be a debug message (or removed), not a normal printf.

OK.

Quoted 7 lines

arch/powerpc/cpu/mpc85xx/cpu_init.c static void __fsl_serdes__init(void) · line 332

Quoted 5 lines
arch/powerpc/cpu/mpc85xx/cpu_init.c +4 -0
+
+		out_be32(&l2cache->l2csr0, L2CSR0_L2FI|L2CSR0_L2LFC);
+		while ((in_be32(&l2cache->l2csr0) & (L2CSR0_L2FI|L2CSR0_L2LFC)) != 0)
+			;

Timeout?

I don't have a spec telling me how long.

Quoted 12 lines

arch/powerpc/cpu/mpc85xx/cpu_init.c int cpu_init_r(void) · line 357

Quoted 10 lines
arch/powerpc/cpu/mpc85xx/cpu_init.c +5 -0
@@ -322,6 +350,11 @@ int cpu_init_r(void)
  #ifdef CONFIG_SYS_LBC_LCRR
  	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
  #endif
+#ifdef CONFIG_L2_CACHE
+	volatile ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR;
+#elif defined(CONFIG_E6500)
+	struct ccsr_cluster_l2 * l2cache = (void *)CONFIG_SYS_FSL_CLUSTER_1_L2;
+#endif

If CONFIG_L2_CACHE doesn't apply to e6500, then CONFIG_L2_CACHE is misnamed.

Maybe it's time to introduce a new name?

Quoted 29 lines
Quoted 29 lines
arch/powerpc/cpu/mpc85xx/start.S +20 -0
index 2e1d265..739127f 100644
@@ -762,6 +762,63 @@ delete_temp_tlbs:
  	tlbwe
  #endif /* #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS) */
 
+#ifdef CONFIG_E6500
+create_ccsr_l2_tlb:
+	/*
+	 * Create a TLB for the MMR location of CCSR
+	 * to access L2CSR0 register
+	 */
+	lis     r0, FSL_BOOKE_MAS0(0, 0, 0)@h
+	ori     r0, r0, FSL_BOOKE_MAS0(0, 0, 0)@l
+
+	lis     r1, FSL_BOOKE_MAS1(1, 0, 0, 0, BOOKE_PAGESZ_4K)@h
+	ori     r1, r1, FSL_BOOKE_MAS1(1, 0, 0, 0, BOOKE_PAGESZ_4K)@l
+	lis     r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR + 0xC20000, (MAS2_I|MAS2_G))@h
+	ori     r2, r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR + 0xC20000, (MAS2_I|MAS2_G))@l
+	lis     r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS_LOW + 0xC20000, 0, (MAS3_SW|MAS3_SR))@h
+	ori     r3, r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS_LOW + 0xC20000, 0, (MAS3_SW|MAS3_SR))@l
+	lis	r7, CONFIG_SYS_CCSRBAR_PHYS_HIGH at h
+	ori	r7, r7, CONFIG_SYS_CCSRBAR_PHYS_HIGH at l
+	mtspr   MAS0, r0
+	mtspr   MAS1, r1
+	mtspr   MAS2, r2
Quoted 9 lines

arch/powerpc/cpu/mpc85xx/start.S delete_temp_tlbs: · line 788

Quoted 5 lines
arch/powerpc/cpu/mpc85xx/start.S +5 -0
+	mtspr   MAS3, r3
+	mtspr   MAS7, r7
+	isync
+	msync
+	tlbwe

Let's make a macro (asm, not cpp) out of this instead of copy and pasting all over the place. And stop misusing r1/r2.

That's a good idea. I am also tired of this long copy-n-paste. Using a macro increase the chance of overwriting registers, doesn't it? Any good idea to avoid?

York

#18 lore raw

PATCH 1/11 powerpc/mpc85xx: Enable L2 at the beginning of U-boot for E6500

Quoted 24 lines · York Sun
Quoted 23 lines · Scott Wood
Quoted 22 lines · York Sun

Using E6500 L1 cache as initram requires L2 cache enabled. Add l2-cache cluster enabling.

Signed-off-by York Sun <[email protected]>
Signed-off-by Kumar Gala <[email protected]>
---
  arch/powerpc/cpu/mpc85xx/cpu_init.c   |   39 ++++++++++++++++++++++-
  arch/powerpc/cpu/mpc85xx/start.S      |   57
+++++++++++++++++++++++++++++++++
  arch/powerpc/include/asm/immap_85xx.h |   43 +++++++++++++++++++++++++
  3 files changed, 138 insertions(+), 1 deletions(-)
arch/powerpc/cpu/mpc85xx/cpu_init.c +0 -0
index 2c78905..1a2858a 100644
@@ -309,6 +309,34 @@ static void __fsl_serdes__init(void)
  }
  __attribute__((weak, alias("__fsl_serdes__init"))) void
 fsl_serdes_init(void);
Quoted 7 lines
Quoted 5 lines

arch/powerpc/cpu/mpc85xx/cpu_init.c static void __fsl_serdes__init(void) · line 313

Quoted 2 lines
arch/powerpc/cpu/mpc85xx/cpu_init.c +2 -0
+#ifdef CONFIG_E6500
+int enable_cluster_l2(void)

If enabling L2 is required for the stack, how are we enabling it in C code? Is this just for non-boot clusters?

Yes, this is for non-boot clusters. The boot cluster is enabled in start.S.

OK, maybe put a comment on that first EOC check (which I missed). Anything we can do to help people navigate what's going on during 85xx boot would be welcome.

Quoted 8 lines
Quoted 6 lines

arch/powerpc/cpu/mpc85xx/cpu_init.c static void __fsl_serdes__init(void) · line 332

Quoted 4 lines
arch/powerpc/cpu/mpc85xx/cpu_init.c +3 -0
+        out_be32(&l2cache->l2csr0, L2CSR0_L2FI|L2CSR0_L2LFC);
+        while ((in_be32(&l2cache->l2csr0) &
 (L2CSR0_L2FI|L2CSR0_L2LFC)) != 0)
+            ;

Timeout?

I don't have a spec telling me how long.

You can estimate an upper bound, so we print a message if we get stuck.
It shouldn't take longer than a second, right?

Quoted 15 lines
Quoted 6 lines
Quoted 6 lines
arch/powerpc/cpu/mpc85xx/cpu_init.c +2 -0
@@ -322,6 +350,11 @@ int cpu_init_r(void)
  #ifdef CONFIG_SYS_LBC_LCRR
      volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
  #endif
+#ifdef CONFIG_L2_CACHE
+    volatile ccsr_l2cache_t *l2cache = (void
Quoted 8 lines

arch/powerpc/cpu/mpc85xx/cpu_init.c int cpu_init_r(void) · line 359

Quoted 5 lines
arch/powerpc/cpu/mpc85xx/cpu_init.c +3 -0
 *)CONFIG_SYS_MPC85xx_L2_ADDR;
+#elif defined(CONFIG_E6500)
+    struct ccsr_cluster_l2 * l2cache = (void
 *)CONFIG_SYS_FSL_CLUSTER_1_L2;
+#endif

If CONFIG_L2_CACHE doesn't apply to e6500, then CONFIG_L2_CACHE is misnamed.

Quoted 1 line

Maybe it's time to introduce a new name?

Sure. What is it supposed to refer to?

Quoted 44 lines
Quoted 34 lines
Quoted 34 lines
arch/powerpc/cpu/mpc85xx/start.S +0 -0
index 2e1d265..739127f 100644
@@ -762,6 +762,63 @@ delete_temp_tlbs:
      tlbwe
  #endif /* #if (CONFIG_SYS_CCSRBAR_DEFAULT !=

CONFIG_SYS_CCSRBAR_PHYS) */

arch/powerpc/cpu/mpc85xx/start.S +12 -0
+#ifdef CONFIG_E6500
+create_ccsr_l2_tlb:
+    /*
+     * Create a TLB for the MMR location of CCSR
+     * to access L2CSR0 register
+     */
+    lis     r0, FSL_BOOKE_MAS0(0, 0, 0)@h
+    ori     r0, r0, FSL_BOOKE_MAS0(0, 0, 0)@l
+
+    lis     r1, FSL_BOOKE_MAS1(1, 0, 0, 0, BOOKE_PAGESZ_4K)@h
+    ori     r1, r1, FSL_BOOKE_MAS1(1, 0, 0, 0, BOOKE_PAGESZ_4K)@l
+    lis     r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR + 0xC20000,

(MAS2_I|MAS2_G))@h
+ ori r2, r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR + 0xC20000,
(MAS2_I|MAS2_G))@l
+ lis r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS_LOW +
0xC20000, 0, (MAS3_SW|MAS3_SR))@h
+ ori r3, r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS_LOW +
0xC20000, 0, (MAS3_SW|MAS3_SR))@l

arch/powerpc/cpu/mpc85xx/start.S +5 -0
+    lis    r7, CONFIG_SYS_CCSRBAR_PHYS_HIGH at h
+    ori    r7, r7, CONFIG_SYS_CCSRBAR_PHYS_HIGH at l
+    mtspr   MAS0, r0
+    mtspr   MAS1, r1
+    mtspr   MAS2, r2
Quoted 9 lines

arch/powerpc/cpu/mpc85xx/start.S delete_temp_tlbs: · line 788

Quoted 5 lines
arch/powerpc/cpu/mpc85xx/start.S +5 -0
+    mtspr   MAS3, r3
+    mtspr   MAS7, r7
+    isync
+    msync
+    tlbwe

Let's make a macro (asm, not cpp) out of this instead of copy and pasting all over the place. And stop misusing r1/r2.

Quoted 3 lines

That's a good idea. I am also tired of this long copy-n-paste. Using a macro increase the chance of overwriting registers, doesn't it? Any good idea to avoid?

If you can get away with one or two temporary registers, you could pass the temporaries in as parameters. Otherwise, document what you clobber, and stick to registers that are normally caller-saved.

-Scott