Add gio api support to mx27 (v4)

The gpio api has been tested on an armadeus apf27.

Signed-off-by Philippe Reynes <[email protected]>

---
 arch/arm/cpu/arm926ejs/mx27/generic.c     |   11 +++---
 arch/arm/include/asm/arch-mx27/gpio.h     |   55 +++++++++++++++++++++++++++++
 arch/arm/include/asm/arch-mx27/imx-regs.h |   30 ++++------------
 drivers/gpio/mxc_gpio.c                   |    8 +++--
 4 files changed, 73 insertions(+), 31 deletions(-)
 create mode 100644 arch/arm/include/asm/arch-mx27/gpio.h

arch/arm/cpu/arm926ejs/mx27/generic.c +6 -5

index 65c4813..41bb84b 100644
@@ -24,6 +24,7 @@
 #include <asm/io.h>
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/clock.h>
+#include <asm/arch/gpio.h>
 #ifdef CONFIG_MXC_MMC
 #include <asm/arch/mxcmmc.h>
 #endif

@@ -209,7 +210,7 @@ int cpu_mmc_init(bd_t *bis)
 
 void imx_gpio_mode(int gpio_mode)
 {
-	struct gpio_regs *regs = (struct gpio_regs *)IMX_GPIO_BASE;
+	struct gpio_port_regs *regs = (struct gpio_port_regs *)IMX_GPIO_BASE;
 	unsigned int pin = gpio_mode & GPIO_PIN_MASK;
 	unsigned int port = (gpio_mode & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
 	unsigned int ocr = (gpio_mode & GPIO_OCR_MASK) >> GPIO_OCR_SHIFT;

@@ -228,11 +229,11 @@ void imx_gpio_mode(int gpio_mode)
 
 	/* Data direction */
 	if (gpio_mode & GPIO_OUT) {
-		writel(readl(&regs->port[port].ddir) | 1 << pin,
-				&regs->port[port].ddir);
+		writel(readl(&regs->port[port].gpio_dir) | 1 << pin,
+				&regs->port[port].gpio_dir);
 	} else {
-		writel(readl(&regs->port[port].ddir) & ~(1 << pin),
-				&regs->port[port].ddir);
+		writel(readl(&regs->port[port].gpio_dir) & ~(1 << pin),
+				&regs->port[port].gpio_dir);
 	}
 
 	/* Primary / alternate function */

arch/arm/include/asm/arch-mx27/gpio.h new file +55 -0

new file mode 100644
index 0000000..4b4eb0d
@@ -0,0 +1,55 @@
+/*
+ * Copyright (C) 2012
+ * Philippe Reynes <[email protected]>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#ifndef __ASM_ARCH_MX27_GPIO_H
+#define __ASM_ARCH_MX27_GPIO_H
+
+/* GPIO registers */
+struct gpio_regs {
+	u32 gpio_dir; /* DDIR */
+	u32 ocr1;
+	u32 ocr2;
+	u32 iconfa1;
+	u32 iconfa2;
+	u32 iconfb1;
+	u32 iconfb2;
+	u32 gpio_dr; /* DR */
+	u32 gius;
+	u32 gpio_psr; /* SSR */
+	u32 icr1;
+	u32 icr2;
+	u32 imr;
+	u32 isr;
+	u32 gpr;
+	u32 swr;
+	u32 puen;
+	u32 res[0x2f];
+};
+
+/* This structure is used by the function imx_gpio_mode */
+struct gpio_port_regs {
+	struct gpio_regs port[6];
+};
+
+#endif

arch/arm/include/asm/arch-mx27/imx-regs.h +7 -23

index f7cf85b..f78d5f2 100644
@@ -164,29 +164,6 @@ struct gpt_regs {
 #define PORTE 4
 #define PORTF 5
 
-struct gpio_regs {
-	struct {
-		u32 ddir;
-		u32 ocr1;
-		u32 ocr2;
-		u32 iconfa1;
-		u32 iconfa2;
-		u32 iconfb1;
-		u32 iconfb2;
-		u32 dr;
-		u32 gius;
-		u32 ssr;
-		u32 icr1;
-		u32 icr2;
-		u32 imr;
-		u32 isr;
-		u32 gpr;
-		u32 swr;
-		u32 puen;
-		u32 res[0x2f];
-	} port[6];
-};
-
 /* IIM Control Registers */
 struct iim_regs {
 	u32 iim_stat;

@@ -474,6 +451,13 @@ struct fuse_bank0_regs {
 #define TSTAT_CAPT	(1 << 1)	/* Capture event */
 #define TSTAT_COMP	1		/* Compare event */
 
+#define GPIO1_BASE_ADDR 0x10015000
+#define GPIO2_BASE_ADDR 0x10015100
+#define GPIO3_BASE_ADDR 0x10015200
+#define GPIO4_BASE_ADDR 0x10015300
+#define GPIO5_BASE_ADDR 0x10015400
+#define GPIO6_BASE_ADDR 0x10015500
+
 #define GPIO_PIN_MASK	0x1f
 
 #define GPIO_PORT_SHIFT	5

drivers/gpio/mxc_gpio.c +2 -2

index e9bf278..2c79bff 100644
@@ -41,13 +41,15 @@ static unsigned long gpio_ports[] = {
 	[0] = GPIO1_BASE_ADDR,
 	[1] = GPIO2_BASE_ADDR,
 	[2] = GPIO3_BASE_ADDR,
-#if defined(CONFIG_MX25) || defined(CONFIG_MX51) || defined(CONFIG_MX53) || \
-		defined(CONFIG_MX6Q)
+#if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX51) || \
+		defined(CONFIG_MX53) || defined(CONFIG_MX6Q)
 	[3] = GPIO4_BASE_ADDR,

The gpio api has been tested on an armadeus apf27.

Signed-off-by Philippe Reynes <[email protected]>

---

Signed-off-by Philippe Reynes <[email protected]>

---
 board/logicpd/imx27lite/imx27lite.c |    5 ++---
 include/configs/imx27lite-common.h  |    5 +++++
 2 files changed, 7 insertions(+), 3 deletions(-)

board/logicpd/imx27lite/imx27lite.c +2 -3

index 8a5015c..b38e5ab 100644
@@ -23,12 +23,12 @@
 #include <common.h>
 #include <asm/io.h>
 #include <asm/arch/imx-regs.h>
+#include <asm/gpio.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
 int board_init(void)
 {
-	struct gpio_regs *regs = (struct gpio_regs *)IMX_GPIO_BASE;
 #if defined(CONFIG_SYS_NAND_LARGEPAGE)
 	struct system_control_regs *sc_regs =
 		(struct system_control_regs *)IMX_SYSTEM_CTL_BASE;

@@ -43,8 +43,7 @@ int board_init(void)
 #ifdef CONFIG_FEC_MXC
 	mx27_fec_init_pins();
 	imx_gpio_mode((GPIO_PORTC | GPIO_OUT | GPIO_PUEN | GPIO_GPIO | 31));
-	writel(readl(&regs->port[PORTC].dr) | (1 << 31),
-				&regs->port[PORTC].dr);
+	gpio_set_value(GPIO_PORTC | 31, 1);
 #endif
 #ifdef CONFIG_MXC_MMC
 #if defined(CONFIG_MAGNESIUM)

include/configs/imx27lite-common.h +0 -0

index 7d2876b..2e79a9e 100644
@@ -162,6 +162,11 @@
 #define CONFIG_DOS_PARTITION

Signed-off-by Philippe Reynes <[email protected]>

---
 board/logicpd/imx27lite/imx27lite.c |    5 ++---
 include/configs/imx27lite-common.h  |    5 +++++
 2 files changed, 7 insertions(+), 3 deletions(-)