Skip to contentSkip to conversation

mmc: dw-mmc: add the use_hold_reg in CMD register

PATCH In review Jaehoon Chung 3 participants 7 messages Aug 28, 2012 – Aug 30, 2012

Subsystems (2)
MMC, SD and SDIO Synopsys DesignWare MMC/SD/SDIO driver
lore
Share & tools
lore

Jaehoon Chung

author maintainer
#0 lore raw

PATCH v2 4/5 mmc: dw-mmc: add the use_hold_reg in CMD register

This patch is added the use_hold_reg bit in CMD register.

In upper version than 2.40a, bit[29] of CMD register is used the use_hold_reg. Some SoC is affected by this bit.
(This bit means whether use hold register when send data and cmd.
And related with cclk_in_drv phase)

Now i known that HOLD-register is using only Exynos-SoC. But hold-register is supported basically feature at Synopsys-IP. If Other SoC is used hold regster, we can change the _CLKSEL_REG_.

Signed-off-by Jaehoon Chung <[email protected]>
Signed-off-by Kyungmin Park <[email protected]>
---
 drivers/mmc/host/dw_mmc.c  |   36 ++++++++++++++++++++++++++++++++++++
 drivers/mmc/host/dw_mmc.h  |    1 +
 include/linux/mmc/dw_mmc.h |    3 +++
 3 files changed, 40 insertions(+), 0 deletions(-)
drivers/mmc/host/dw_mmc.c +36 -0
index 437fdf8..3642455 100644
@@ -265,11 +265,45 @@ static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command *cmd)
 static void dw_mci_start_command(struct dw_mci *host,
 				 struct mmc_command *cmd, u32 cmd_flags)
 {
+	struct dw_mci_slot *slot = host->cur_slot;
+	struct mmc_ios *ios = &slot->mmc->ios;
+
 	host->cmd = cmd;
 	dev_vdbg(&host->dev,
 		 "start command: ARGR=0x%08x CMDR=0x%08x\n",
 		 cmd->arg, cmd_flags);
 
+	if (host->quirks & DW_MCI_QUIRK_USE_CLKSEL_REG) {
+		/*
+		 * If use HOLD register and SDR12/SDSR25,
+		 * CMD and DATA sent to card through HOLD regster by default.
+		 * But if mode is SDR50/DDR50/SDR104,
+		 * only use the hold register when cclk_in_drv value is greater than 0.
+		 */
+		switch (ios->timing) {
+		case MMC_TIMING_UHS_SDR50:
+		case MMC_TIMING_UHS_DDR50:
+		case MMC_TIMING_UHS_SDR104:
+			if (host->pdata->get_clk_drv &&
+					host->pdata->get_clk_drv(host) &&
+					host->use_hold_reg) {
+				cmd_flags |= SDMMC_CMD_USE_HOLD_REG;
+				break;
+			}
+
+			cmd_flags &= ~SDMMC_CMD_USE_HOLD_REG;
+			break;
+		case MMC_TIMING_UHS_SDR12:
+		case MMC_TIMING_UHS_SDR25:
+			if (host->use_hold_reg) {
+				cmd_flags |= SDMMC_CMD_USE_HOLD_REG;
+				break;
+			}
+		default:
+			cmd_flags &= ~SDMMC_CMD_USE_HOLD_REG;
+		}
+	}
+
 	mci_writel(host, CMDARG, cmd->arg);
 	wmb();
 

@@ -2015,6 +2049,8 @@ int dw_mci_probe(struct dw_mci *host)
 		host->data_shift = 2;
 	}
 
+	host->use_hold_reg = (mci_readl(host, HCON) >> 22) & 0x1;
+
 	/* Reset all blocks */
 	if (!mci_wait_reset(&host->dev, host))
 		return -ENODEV;
drivers/mmc/host/dw_mmc.h +1 -0
index b6a1a78..cc905ee 100644
@@ -111,6 +111,7 @@
 #define SDMMC_INT_ERROR			0xbfc2
 /* Command register defines */
 #define SDMMC_CMD_START			BIT(31)
+#define SDMMC_CMD_USE_HOLD_REG		BIT(29)
 #define SDMMC_CMD_CCS_EXP		BIT(23)
 #define SDMMC_CMD_CEATA_RD		BIT(22)
 #define SDMMC_CMD_UPD_CLK		BIT(21)
include/linux/mmc/dw_mmc.h +3 -0
index f20979c..803a80d 100644
@@ -156,6 +156,7 @@ struct dw_mci {
 	u32			fifoth_val;
 	u16			verid;
 	u16			data_offset;
+	bool			use_hold_reg;
 	struct device		dev;
 	struct dw_mci_board	*pdata;
 	struct dw_mci_slot	*slot[MAX_MCI_SLOTS];

@@ -201,6 +202,8 @@ struct dw_mci_dma_ops {
 #define DW_MCI_QUIRK_HIGHSPEED			BIT(2)
 /* Unreliable card detection */
 #define DW_MCI_QUIRK_BROKEN_CARD_DETECTION	BIT(3)
+/* To use the CLKSEL register for phase-shift */
+#define DW_MCI_QUIRK_USE_CLKSEL_REG		BIT(4)
 
 
 struct dma_pdata;
Signature · 1 line
1.7.4.1
#1 lore raw
Quoted 70 lines · Jaehoon Chung

This patch is added the use_hold_reg bit in CMD register.

In upper version than 2.40a, bit[29] of CMD register is used the use_hold_reg. Some SoC is affected by this bit.
(This bit means whether use hold register when send data and cmd.
And related with cclk_in_drv phase)

Now i known that HOLD-register is using only Exynos-SoC. But hold-register is supported basically feature at Synopsys-IP. If Other SoC is used hold regster, we can change the _CLKSEL_REG_.

Signed-off-by Jaehoon Chung <[email protected]>
Signed-off-by Kyungmin Park <[email protected]>
---
 drivers/mmc/host/dw_mmc.c  |   36 ++++++++++++++++++++++++++++++++++++
 drivers/mmc/host/dw_mmc.h  |    1 +
 include/linux/mmc/dw_mmc.h |    3 +++
 3 files changed, 40 insertions(+), 0 deletions(-)
drivers/mmc/host/dw_mmc.c +34 -0
index 437fdf8..3642455 100644
@@ -265,11 +265,45 @@ static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command *cmd)
 static void dw_mci_start_command(struct dw_mci *host,
                                 struct mmc_command *cmd, u32 cmd_flags)
 {
+       struct dw_mci_slot *slot = host->cur_slot;
+       struct mmc_ios *ios = &slot->mmc->ios;
+
        host->cmd = cmd;
        dev_vdbg(&host->dev,
                 "start command: ARGR=0x%08x CMDR=0x%08x\n",
                 cmd->arg, cmd_flags);
 
+       if (host->quirks & DW_MCI_QUIRK_USE_CLKSEL_REG) {
+               /*
+                * If use HOLD register and SDR12/SDSR25,
+                * CMD and DATA sent to card through HOLD regster by default.
+                * But if mode is SDR50/DDR50/SDR104,
+                * only use the hold register when cclk_in_drv value is greater than 0.
+                */
+               switch (ios->timing) {
+               case MMC_TIMING_UHS_SDR50:
+               case MMC_TIMING_UHS_DDR50:
+               case MMC_TIMING_UHS_SDR104:
+                       if (host->pdata->get_clk_drv &&
+                                       host->pdata->get_clk_drv(host) &&
+                                       host->use_hold_reg) {
+                               cmd_flags |= SDMMC_CMD_USE_HOLD_REG;
+                               break;
+                       }
+
+                       cmd_flags &= ~SDMMC_CMD_USE_HOLD_REG;
+                       break;
+               case MMC_TIMING_UHS_SDR12:
+               case MMC_TIMING_UHS_SDR25:
+                       if (host->use_hold_reg) {
+                               cmd_flags |= SDMMC_CMD_USE_HOLD_REG;
+                               break;
+                       }
+               default:
+                       cmd_flags &= ~SDMMC_CMD_USE_HOLD_REG;
+               }
+       }
+
        mci_writel(host, CMDARG, cmd->arg);
        wmb();

drivers/mmc/host/dw_mmc.c int dw_mci_probe(struct dw_mci *host) · line 2053

Quoted 5 lines
drivers/mmc/host/dw_mmc.c +2 -0
@@ -2015,6 +2049,8 @@ int dw_mci_probe(struct dw_mci *host)
                host->data_shift = 2;
        }
 
+       host->use_hold_reg = (mci_readl(host, HCON) >> 22) & 0x1;
+

The presence of DW_MCI_QUIRK_USE_CLKSEL_REG quirk should be sufficient condition to know if HOLD_REG bit is supported on not. The setting of host->use_hold_reg as above creates a dependency on the boot loader to setup the controller appropriately.

Thanks,
Thomas.

Quoted 38 lines
drivers/mmc/host/dw_mmc.c +0 -0
        /* Reset all blocks */
        if (!mci_wait_reset(&host->dev, host))
                return -ENODEV;
drivers/mmc/host/dw_mmc.h +1 -0
index b6a1a78..cc905ee 100644
@@ -111,6 +111,7 @@
 #define SDMMC_INT_ERROR                        0xbfc2
 /* Command register defines */
 #define SDMMC_CMD_START                        BIT(31)
+#define SDMMC_CMD_USE_HOLD_REG         BIT(29)
 #define SDMMC_CMD_CCS_EXP              BIT(23)
 #define SDMMC_CMD_CEATA_RD             BIT(22)
 #define SDMMC_CMD_UPD_CLK              BIT(21)
include/linux/mmc/dw_mmc.h +3 -1
index f20979c..803a80d 100644
@@ -156,6 +156,7 @@ struct dw_mci {
        u32                     fifoth_val;
        u16                     verid;
        u16                     data_offset;
+       bool                    use_hold_reg;
        struct device           dev;
        struct dw_mci_board     *pdata;
        struct dw_mci_slot      *slot[MAX_MCI_SLOTS];

@@ -201,6 +202,8 @@ struct dw_mci_dma_ops {
 #define DW_MCI_QUIRK_HIGHSPEED                 BIT(2)
 /* Unreliable card detection */
 #define DW_MCI_QUIRK_BROKEN_CARD_DETECTION     BIT(3)
+/* To use the CLKSEL register for phase-shift */
+#define DW_MCI_QUIRK_USE_CLKSEL_REG            BIT(4)
 
 
 struct dma_pdata;
--

1.7.4.1

author maintainer
#2 lore raw
Quoted 74 lines · Thomas Abraham
Quoted 73 lines · Jaehoon Chung

This patch is added the use_hold_reg bit in CMD register.

In upper version than 2.40a, bit[29] of CMD register is used the use_hold_reg. Some SoC is affected by this bit.
(This bit means whether use hold register when send data and cmd.
And related with cclk_in_drv phase)

Now i known that HOLD-register is using only Exynos-SoC. But hold-register is supported basically feature at Synopsys-IP. If Other SoC is used hold regster, we can change the _CLKSEL_REG_.

Signed-off-by Jaehoon Chung <[email protected]>
Signed-off-by Kyungmin Park <[email protected]>
---
 drivers/mmc/host/dw_mmc.c  |   36 ++++++++++++++++++++++++++++++++++++
 drivers/mmc/host/dw_mmc.h  |    1 +
 include/linux/mmc/dw_mmc.h |    3 +++
 3 files changed, 40 insertions(+), 0 deletions(-)
drivers/mmc/host/dw_mmc.c +34 -0
index 437fdf8..3642455 100644
@@ -265,11 +265,45 @@ static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command *cmd)
 static void dw_mci_start_command(struct dw_mci *host,
                                 struct mmc_command *cmd, u32 cmd_flags)
 {
+       struct dw_mci_slot *slot = host->cur_slot;
+       struct mmc_ios *ios = &slot->mmc->ios;
+
        host->cmd = cmd;
        dev_vdbg(&host->dev,
                 "start command: ARGR=0x%08x CMDR=0x%08x\n",
                 cmd->arg, cmd_flags);
 
+       if (host->quirks & DW_MCI_QUIRK_USE_CLKSEL_REG) {
+               /*
+                * If use HOLD register and SDR12/SDSR25,
+                * CMD and DATA sent to card through HOLD regster by default.
+                * But if mode is SDR50/DDR50/SDR104,
+                * only use the hold register when cclk_in_drv value is greater than 0.
+                */
+               switch (ios->timing) {
+               case MMC_TIMING_UHS_SDR50:
+               case MMC_TIMING_UHS_DDR50:
+               case MMC_TIMING_UHS_SDR104:
+                       if (host->pdata->get_clk_drv &&
+                                       host->pdata->get_clk_drv(host) &&
+                                       host->use_hold_reg) {
+                               cmd_flags |= SDMMC_CMD_USE_HOLD_REG;
+                               break;
+                       }
+
+                       cmd_flags &= ~SDMMC_CMD_USE_HOLD_REG;
+                       break;
+               case MMC_TIMING_UHS_SDR12:
+               case MMC_TIMING_UHS_SDR25:
+                       if (host->use_hold_reg) {
+                               cmd_flags |= SDMMC_CMD_USE_HOLD_REG;
+                               break;
+                       }
+               default:
+                       cmd_flags &= ~SDMMC_CMD_USE_HOLD_REG;
+               }
+       }
+
        mci_writel(host, CMDARG, cmd->arg);
        wmb();
 

@@ -2015,6 +2049,8 @@ int dw_mci_probe(struct dw_mci *host)
                host->data_shift = 2;
        }
Quoted 7 lines

drivers/mmc/host/dw_mmc.c int dw_mci_probe(struct dw_mci *host) · line 2053

Quoted 2 lines
drivers/mmc/host/dw_mmc.c +2 -0
+       host->use_hold_reg = (mci_readl(host, HCON) >> 22) & 0x1;
+

The presence of DW_MCI_QUIRK_USE_CLKSEL_REG quirk should be sufficient condition to know if HOLD_REG bit is supported on not. The setting of host->use_hold_reg as above creates a dependency on the boot loader to setup the controller appropriately.

Dependency on the bootloader? I known that HCON's type is read only. It didn't have any dependency with bootloader.

Quoted 48 lines

Thanks,
Thomas.

Quoted 37 lines
drivers/mmc/host/dw_mmc.c +0 -0
        /* Reset all blocks */
        if (!mci_wait_reset(&host->dev, host))
                return -ENODEV;
drivers/mmc/host/dw_mmc.h +1 -0
index b6a1a78..cc905ee 100644
@@ -111,6 +111,7 @@
 #define SDMMC_INT_ERROR                        0xbfc2
 /* Command register defines */
 #define SDMMC_CMD_START                        BIT(31)
+#define SDMMC_CMD_USE_HOLD_REG         BIT(29)
 #define SDMMC_CMD_CCS_EXP              BIT(23)
 #define SDMMC_CMD_CEATA_RD             BIT(22)
 #define SDMMC_CMD_UPD_CLK              BIT(21)
include/linux/mmc/dw_mmc.h +3 -1
index f20979c..803a80d 100644
@@ -156,6 +156,7 @@ struct dw_mci {
        u32                     fifoth_val;
        u16                     verid;
        u16                     data_offset;
+       bool                    use_hold_reg;
        struct device           dev;
        struct dw_mci_board     *pdata;
        struct dw_mci_slot      *slot[MAX_MCI_SLOTS];

@@ -201,6 +202,8 @@ struct dw_mci_dma_ops {
 #define DW_MCI_QUIRK_HIGHSPEED                 BIT(2)
 /* Unreliable card detection */
 #define DW_MCI_QUIRK_BROKEN_CARD_DETECTION     BIT(3)
+/* To use the CLKSEL register for phase-shift */
+#define DW_MCI_QUIRK_USE_CLKSEL_REG            BIT(4)
 
 
 struct dma_pdata;
--
Quoted 1 line

1.7.4.1

--
To unsubscribe from this list: send the line "unsubscribe linux-mmc" in the body of a message to [email protected]
More majordomo info at http://vger.kernel.org/majordomo-info.html

#3 lore raw
In reply to Jaehoon Chung
Quoted 26 lines · Jaehoon Chung

This patch is added the use_hold_reg bit in CMD register.

In upper version than 2.40a, bit[29] of CMD register is used the use_hold_reg. Some SoC is affected by this bit.
(This bit means whether use hold register when send data and cmd.
And related with cclk_in_drv phase)

Now i known that HOLD-register is using only Exynos-SoC. But hold-register is supported basically feature at Synopsys-IP. If Other SoC is used hold regster, we can change the _CLKSEL_REG_.

Signed-off-by Jaehoon Chung <[email protected]>
Signed-off-by Kyungmin Park <[email protected]>
---
 drivers/mmc/host/dw_mmc.c  |   36 ++++++++++++++++++++++++++++++++++++
 drivers/mmc/host/dw_mmc.h  |    1 +
 include/linux/mmc/dw_mmc.h |    3 +++
 3 files changed, 40 insertions(+), 0 deletions(-)
drivers/mmc/host/dw_mmc.c +0 -0
index 437fdf8..3642455 100644
@@ -265,11 +265,45 @@ static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command *cmd)
 static void dw_mci_start_command(struct dw_mci *host,
 				 struct mmc_command *cmd, u32 cmd_flags)

drivers/mmc/host/dw_mmc.c static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command *cmd) · line 276

Quoted 10 lines
drivers/mmc/host/dw_mmc.c +4 -0
 {
+	struct dw_mci_slot *slot = host->cur_slot;
+	struct mmc_ios *ios = &slot->mmc->ios;
+
 	host->cmd = cmd;
 	dev_vdbg(&host->dev,
 		 "start command: ARGR=0x%08x CMDR=0x%08x\n",
 		 cmd->arg, cmd_flags);
 
+	if (host->quirks & DW_MCI_QUIRK_USE_CLKSEL_REG) {

What is this quirk for?
Could you explain?

Quoted 20 lines
drivers/mmc/host/dw_mmc.c +20 -0
+		/*
+		 * If use HOLD register and SDR12/SDSR25,
+		 * CMD and DATA sent to card through HOLD regster by default.
+		 * But if mode is SDR50/DDR50/SDR104,
+		 * only use the hold register when cclk_in_drv value is greater than 0.
+		 */
+		switch (ios->timing) {
+		case MMC_TIMING_UHS_SDR50:
+		case MMC_TIMING_UHS_DDR50:
+		case MMC_TIMING_UHS_SDR104:
+			if (host->pdata->get_clk_drv &&
+					host->pdata->get_clk_drv(host) &&
+					host->use_hold_reg) {
+				cmd_flags |= SDMMC_CMD_USE_HOLD_REG;
+				break;
+			}
+
+			cmd_flags &= ~SDMMC_CMD_USE_HOLD_REG;
+			break;
+		case MMC_TIMING_UHS_SDR12:

drivers/mmc/host/dw_mmc.c static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command *cmd) · line 306

Quoted 10 lines
drivers/mmc/host/dw_mmc.c +10 -0
+		case MMC_TIMING_UHS_SDR25:
+			if (host->use_hold_reg) {
+				cmd_flags |= SDMMC_CMD_USE_HOLD_REG;
+				break;
+			}
+		default:
+			cmd_flags &= ~SDMMC_CMD_USE_HOLD_REG;
+		}
+	}
+

Considering MMC_TIMING_MMC_HS, MMC_TIMING_SD_HS is omitted. Didn't you consider moving this whole routine to dw_mci_set_ios? When deciding the timing, once seems to be enough.

Thanks,
Seungwon Jeon

Quoted 47 lines
drivers/mmc/host/dw_mmc.c +2 -0
 	mci_writel(host, CMDARG, cmd->arg);
 	wmb();
 

@@ -2015,6 +2049,8 @@ int dw_mci_probe(struct dw_mci *host)
 		host->data_shift = 2;
 	}
 
+	host->use_hold_reg = (mci_readl(host, HCON) >> 22) & 0x1;
+
 	/* Reset all blocks */
 	if (!mci_wait_reset(&host->dev, host))
 		return -ENODEV;
drivers/mmc/host/dw_mmc.h +1 -0
index b6a1a78..cc905ee 100644
@@ -111,6 +111,7 @@
 #define SDMMC_INT_ERROR			0xbfc2
 /* Command register defines */
 #define SDMMC_CMD_START			BIT(31)
+#define SDMMC_CMD_USE_HOLD_REG		BIT(29)
 #define SDMMC_CMD_CCS_EXP		BIT(23)
 #define SDMMC_CMD_CEATA_RD		BIT(22)
 #define SDMMC_CMD_UPD_CLK		BIT(21)
include/linux/mmc/dw_mmc.h +3 -1
index f20979c..803a80d 100644
@@ -156,6 +156,7 @@ struct dw_mci {
 	u32			fifoth_val;
 	u16			verid;
 	u16			data_offset;
+	bool			use_hold_reg;
 	struct device		dev;
 	struct dw_mci_board	*pdata;
 	struct dw_mci_slot	*slot[MAX_MCI_SLOTS];

@@ -201,6 +202,8 @@ struct dw_mci_dma_ops {
 #define DW_MCI_QUIRK_HIGHSPEED			BIT(2)
 /* Unreliable card detection */
 #define DW_MCI_QUIRK_BROKEN_CARD_DETECTION	BIT(3)
+/* To use the CLKSEL register for phase-shift */
+#define DW_MCI_QUIRK_USE_CLKSEL_REG		BIT(4)
 
 
 struct dma_pdata;
--

1.7.4.1

author maintainer
#4 lore raw
Quoted 36 lines · Seungwon Jeon
Quoted 35 lines · Jaehoon Chung

This patch is added the use_hold_reg bit in CMD register.

In upper version than 2.40a, bit[29] of CMD register is used the use_hold_reg. Some SoC is affected by this bit.
(This bit means whether use hold register when send data and cmd.
And related with cclk_in_drv phase)

Now i known that HOLD-register is using only Exynos-SoC. But hold-register is supported basically feature at Synopsys-IP. If Other SoC is used hold regster, we can change the _CLKSEL_REG_.

Signed-off-by Jaehoon Chung <[email protected]>
Signed-off-by Kyungmin Park <[email protected]>
---
 drivers/mmc/host/dw_mmc.c  |   36 ++++++++++++++++++++++++++++++++++++
 drivers/mmc/host/dw_mmc.h  |    1 +
 include/linux/mmc/dw_mmc.h |    3 +++
 3 files changed, 40 insertions(+), 0 deletions(-)
drivers/mmc/host/dw_mmc.c +3 -0
index 437fdf8..3642455 100644
@@ -265,11 +265,45 @@ static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command *cmd)
 static void dw_mci_start_command(struct dw_mci *host,
 				 struct mmc_command *cmd, u32 cmd_flags)
 {
+	struct dw_mci_slot *slot = host->cur_slot;
+	struct mmc_ios *ios = &slot->mmc->ios;
+
 	host->cmd = cmd;
 	dev_vdbg(&host->dev,
 		 "start command: ARGR=0x%08x CMDR=0x%08x\n",
 		 cmd->arg, cmd_flags);
Quoted 2 lines

drivers/mmc/host/dw_mmc.c static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command *cmd) · line 276

Quoted 1 line
drivers/mmc/host/dw_mmc.c +1 -0
+	if (host->quirks & DW_MCI_QUIRK_USE_CLKSEL_REG) {

What is this quirk for?

CLKSEL register is only used at the Exynos-SoC.
I didn't know which SoC is used. I added the quirks for Exynos using the CLKSEL register.

Quoted 25 lines

Could you explain?

Quoted 23 lines
drivers/mmc/host/dw_mmc.c +23 -0
+		/*
+		 * If use HOLD register and SDR12/SDSR25,
+		 * CMD and DATA sent to card through HOLD regster by default.
+		 * But if mode is SDR50/DDR50/SDR104,
+		 * only use the hold register when cclk_in_drv value is greater than 0.
+		 */
+		switch (ios->timing) {
+		case MMC_TIMING_UHS_SDR50:
+		case MMC_TIMING_UHS_DDR50:
+		case MMC_TIMING_UHS_SDR104:
+			if (host->pdata->get_clk_drv &&
+					host->pdata->get_clk_drv(host) &&
+					host->use_hold_reg) {
+				cmd_flags |= SDMMC_CMD_USE_HOLD_REG;
+				break;
+			}
+
+			cmd_flags &= ~SDMMC_CMD_USE_HOLD_REG;
+			break;
+		case MMC_TIMING_UHS_SDR12:
+		case MMC_TIMING_UHS_SDR25:
+			if (host->use_hold_reg) {
+				cmd_flags |= SDMMC_CMD_USE_HOLD_REG;
Quoted 8 lines

drivers/mmc/host/dw_mmc.c static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command *cmd) · line 306

Quoted 7 lines
drivers/mmc/host/dw_mmc.c +7 -0
+				break;
+			}
+		default:
+			cmd_flags &= ~SDMMC_CMD_USE_HOLD_REG;
+		}
+	}
+

Considering MMC_TIMING_MMC_HS, MMC_TIMING_SD_HS is omitted.

Sorry, i will fix.

Quoted 2 lines

Didn't you consider moving this whole routine to dw_mci_set_ios? When deciding the timing, once seems to be enough.

Well, i considered that move the code into dw_mci_set_ios(). But cmd_flags is set before sending the command at every time. Finally, hold_regs bit must be also set at every time. We can prevent to set the cmd_flags at every time.

Best Regards,
Jaehoon Chung

Quoted 57 lines

Thanks,
Seungwon Jeon

Quoted 46 lines
drivers/mmc/host/dw_mmc.c +2 -0
 	mci_writel(host, CMDARG, cmd->arg);
 	wmb();
 

@@ -2015,6 +2049,8 @@ int dw_mci_probe(struct dw_mci *host)
 		host->data_shift = 2;
 	}
 
+	host->use_hold_reg = (mci_readl(host, HCON) >> 22) & 0x1;
+
 	/* Reset all blocks */
 	if (!mci_wait_reset(&host->dev, host))
 		return -ENODEV;
drivers/mmc/host/dw_mmc.h +1 -0
index b6a1a78..cc905ee 100644
@@ -111,6 +111,7 @@
 #define SDMMC_INT_ERROR			0xbfc2
 /* Command register defines */
 #define SDMMC_CMD_START			BIT(31)
+#define SDMMC_CMD_USE_HOLD_REG		BIT(29)
 #define SDMMC_CMD_CCS_EXP		BIT(23)
 #define SDMMC_CMD_CEATA_RD		BIT(22)
 #define SDMMC_CMD_UPD_CLK		BIT(21)
include/linux/mmc/dw_mmc.h +3 -1
index f20979c..803a80d 100644
@@ -156,6 +156,7 @@ struct dw_mci {
 	u32			fifoth_val;
 	u16			verid;
 	u16			data_offset;
+	bool			use_hold_reg;
 	struct device		dev;
 	struct dw_mci_board	*pdata;
 	struct dw_mci_slot	*slot[MAX_MCI_SLOTS];

@@ -201,6 +202,8 @@ struct dw_mci_dma_ops {
 #define DW_MCI_QUIRK_HIGHSPEED			BIT(2)
 /* Unreliable card detection */
 #define DW_MCI_QUIRK_BROKEN_CARD_DETECTION	BIT(3)
+/* To use the CLKSEL register for phase-shift */
+#define DW_MCI_QUIRK_USE_CLKSEL_REG		BIT(4)
 
 
 struct dma_pdata;
--
Quoted 1 line

1.7.4.1

--
To unsubscribe from this list: send the line "unsubscribe linux-mmc" in the body of a message to [email protected]
More majordomo info at http://vger.kernel.org/majordomo-info.html

#5 lore raw
Quoted 38 lines · Jaehoon Chung
Quoted 20 lines · Seungwon Jeon
Quoted 19 lines · Jaehoon Chung

This patch is added the use_hold_reg bit in CMD register.

In upper version than 2.40a, bit[29] of CMD register is used the use_hold_reg. Some SoC is affected by this bit.
(This bit means whether use hold register when send data and cmd.
And related with cclk_in_drv phase)

Now i known that HOLD-register is using only Exynos-SoC. But hold-register is supported basically feature at Synopsys-IP. If Other SoC is used hold regster, we can change the _CLKSEL_REG_.

Signed-off-by Jaehoon Chung <[email protected]>
Signed-off-by Kyungmin Park <[email protected]>
---
 drivers/mmc/host/dw_mmc.c  |   36 ++++++++++++++++++++++++++++++++++++
 drivers/mmc/host/dw_mmc.h  |    1 +
 include/linux/mmc/dw_mmc.h |    3 +++
 3 files changed, 40 insertions(+), 0 deletions(-)
Quoted 5 lines

drivers/mmc/host/dw_mmc.c static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command

Quoted 5 lines
drivers/mmc/host/dw_mmc.c +0 -0
index 437fdf8..3642455 100644
@@ -265,11 +265,45 @@ static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command

*cmd)

Quoted 11 lines
Quoted 11 lines
drivers/mmc/host/dw_mmc.c +3 -0
 static void dw_mci_start_command(struct dw_mci *host,
 				 struct mmc_command *cmd, u32 cmd_flags)
 {
+	struct dw_mci_slot *slot = host->cur_slot;
+	struct mmc_ios *ios = &slot->mmc->ios;
+
 	host->cmd = cmd;
 	dev_vdbg(&host->dev,
 		 "start command: ARGR=0x%08x CMDR=0x%08x\n",
 		 cmd->arg, cmd_flags);
Quoted 4 lines
Quoted 2 lines

drivers/mmc/host/dw_mmc.c static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command *cmd) · line 276

Quoted 1 line
drivers/mmc/host/dw_mmc.c +1 -0
+	if (host->quirks & DW_MCI_QUIRK_USE_CLKSEL_REG) {

What is this quirk for?

CLKSEL register is only used at the Exynos-SoC.
I didn't know which SoC is used. I added the quirks for Exynos using the CLKSEL register.

You wrapped the access to the CLKSEL register by callback function? CLKSEL is just implementation for Synopsys's phase-shift technique in Exynos We don't need to consider this register.
Perhaps, below conditions for hold_reg are only for Exynos? Which manual did you refer to?

Quoted 33 lines
Quoted 25 lines

Could you explain?

Quoted 23 lines
drivers/mmc/host/dw_mmc.c +23 -0
+		/*
+		 * If use HOLD register and SDR12/SDSR25,
+		 * CMD and DATA sent to card through HOLD regster by default.
+		 * But if mode is SDR50/DDR50/SDR104,
+		 * only use the hold register when cclk_in_drv value is greater than 0.
+		 */
+		switch (ios->timing) {
+		case MMC_TIMING_UHS_SDR50:
+		case MMC_TIMING_UHS_DDR50:
+		case MMC_TIMING_UHS_SDR104:
+			if (host->pdata->get_clk_drv &&
+					host->pdata->get_clk_drv(host) &&
+					host->use_hold_reg) {
+				cmd_flags |= SDMMC_CMD_USE_HOLD_REG;
+				break;
+			}
+
+			cmd_flags &= ~SDMMC_CMD_USE_HOLD_REG;
+			break;
+		case MMC_TIMING_UHS_SDR12:
+		case MMC_TIMING_UHS_SDR25:
+			if (host->use_hold_reg) {
+				cmd_flags |= SDMMC_CMD_USE_HOLD_REG;
Quoted 8 lines

drivers/mmc/host/dw_mmc.c static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command *cmd) · line 306

Quoted 7 lines
drivers/mmc/host/dw_mmc.c +7 -0
+				break;
+			}
+		default:
+			cmd_flags &= ~SDMMC_CMD_USE_HOLD_REG;
+		}
+	}
+

Considering MMC_TIMING_MMC_HS, MMC_TIMING_SD_HS is omitted.

Quoted 7 lines

Sorry, i will fix.

Quoted 2 lines

Didn't you consider moving this whole routine to dw_mci_set_ios? When deciding the timing, once seems to be enough.

Well, i considered that move the code into dw_mci_set_ios(). But cmd_flags is set before sending the command at every time. Finally, hold_regs bit must be also set at every time. We can prevent to set the cmd_flags at every time.

Yes, use_hold_regs shoud be set to CMD, whenever sending command. But cmd_flags for use_hold_reg can be set a time.

Thanks,
Seungwon Jeon

Quoted 65 lines

Best Regards,
Jaehoon Chung

Quoted 48 lines

Thanks,
Seungwon Jeon

Quoted 44 lines
drivers/mmc/host/dw_mmc.c +2 -0
 	mci_writel(host, CMDARG, cmd->arg);
 	wmb();
 

@@ -2015,6 +2049,8 @@ int dw_mci_probe(struct dw_mci *host)
 		host->data_shift = 2;
 	}
 
+	host->use_hold_reg = (mci_readl(host, HCON) >> 22) & 0x1;
+
 	/* Reset all blocks */
 	if (!mci_wait_reset(&host->dev, host))
 		return -ENODEV;
drivers/mmc/host/dw_mmc.h +1 -0
index b6a1a78..cc905ee 100644
@@ -111,6 +111,7 @@
 #define SDMMC_INT_ERROR			0xbfc2
 /* Command register defines */
 #define SDMMC_CMD_START			BIT(31)
+#define SDMMC_CMD_USE_HOLD_REG		BIT(29)
 #define SDMMC_CMD_CCS_EXP		BIT(23)
 #define SDMMC_CMD_CEATA_RD		BIT(22)
 #define SDMMC_CMD_UPD_CLK		BIT(21)
include/linux/mmc/dw_mmc.h +3 -0
index f20979c..803a80d 100644
@@ -156,6 +156,7 @@ struct dw_mci {
 	u32			fifoth_val;
 	u16			verid;
 	u16			data_offset;
+	bool			use_hold_reg;
 	struct device		dev;
 	struct dw_mci_board	*pdata;
 	struct dw_mci_slot	*slot[MAX_MCI_SLOTS];

@@ -201,6 +202,8 @@ struct dw_mci_dma_ops {
 #define DW_MCI_QUIRK_HIGHSPEED			BIT(2)
 /* Unreliable card detection */
 #define DW_MCI_QUIRK_BROKEN_CARD_DETECTION	BIT(3)
+/* To use the CLKSEL register for phase-shift */
+#define DW_MCI_QUIRK_USE_CLKSEL_REG		BIT(4)
Quoted 9 lines
Quoted 3 lines
include/linux/mmc/dw_mmc.h +0 -1
 struct dma_pdata;
--

1.7.4.1

--
To unsubscribe from this list: send the line "unsubscribe linux-mmc" in the body of a message to [email protected]
More majordomo info at http://vger.kernel.org/majordomo-info.html

--
To unsubscribe from this list: send the line "unsubscribe linux-mmc" in the body of a message to [email protected]
More majordomo info at http://vger.kernel.org/majordomo-info.html

author maintainer
#6 lore raw
Quoted 39 lines · Seungwon Jeon
Quoted 38 lines · Jaehoon Chung
Quoted 20 lines · Seungwon Jeon
Quoted 19 lines · Jaehoon Chung

This patch is added the use_hold_reg bit in CMD register.

In upper version than 2.40a, bit[29] of CMD register is used the use_hold_reg. Some SoC is affected by this bit.
(This bit means whether use hold register when send data and cmd.
And related with cclk_in_drv phase)

Now i known that HOLD-register is using only Exynos-SoC. But hold-register is supported basically feature at Synopsys-IP. If Other SoC is used hold regster, we can change the _CLKSEL_REG_.

Signed-off-by Jaehoon Chung <[email protected]>
Signed-off-by Kyungmin Park <[email protected]>
---
 drivers/mmc/host/dw_mmc.c  |   36 ++++++++++++++++++++++++++++++++++++
 drivers/mmc/host/dw_mmc.h  |    1 +
 include/linux/mmc/dw_mmc.h |    3 +++
 3 files changed, 40 insertions(+), 0 deletions(-)
Quoted 5 lines

drivers/mmc/host/dw_mmc.c static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command

Quoted 5 lines
drivers/mmc/host/dw_mmc.c +0 -0
index 437fdf8..3642455 100644
@@ -265,11 +265,45 @@ static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command

*cmd)

Quoted 11 lines
Quoted 11 lines
drivers/mmc/host/dw_mmc.c +3 -0
 static void dw_mci_start_command(struct dw_mci *host,
 				 struct mmc_command *cmd, u32 cmd_flags)
 {
+	struct dw_mci_slot *slot = host->cur_slot;
+	struct mmc_ios *ios = &slot->mmc->ios;
+
 	host->cmd = cmd;
 	dev_vdbg(&host->dev,
 		 "start command: ARGR=0x%08x CMDR=0x%08x\n",
 		 cmd->arg, cmd_flags);
Quoted 4 lines
Quoted 4 lines
Quoted 2 lines

drivers/mmc/host/dw_mmc.c static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command *cmd) · line 276

Quoted 1 line
drivers/mmc/host/dw_mmc.c +1 -0
+	if (host->quirks & DW_MCI_QUIRK_USE_CLKSEL_REG) {

What is this quirk for?

CLKSEL register is only used at the Exynos-SoC.
I didn't know which SoC is used. I added the quirks for Exynos using the CLKSEL register.

The quirks could be removed.

Quoted 2 lines

You wrapped the access to the CLKSEL register by callback function? CLKSEL is just implementation for Synopsys's phase-shift technique in Exynos

Right, CLKSEL register is used at EXYNOS.
But it could be presented other clock-phase method at other-SoC

Quoted 2 lines

We don't need to consider this register.
Perhaps, below conditions for hold_reg are only for Exynos?

No, that's generic condition that synopsys manual is mentioned.

Quoted 1 line

Which manual did you refer to?

i refer to dwc_mobile_storage(version 2.50a).

Best regards,
Jaehoon Chung

Quoted 114 lines
Quoted 34 lines
Quoted 26 lines

Could you explain?

Quoted 23 lines
drivers/mmc/host/dw_mmc.c +23 -0
+		/*
+		 * If use HOLD register and SDR12/SDSR25,
+		 * CMD and DATA sent to card through HOLD regster by default.
+		 * But if mode is SDR50/DDR50/SDR104,
+		 * only use the hold register when cclk_in_drv value is greater than 0.
+		 */
+		switch (ios->timing) {
+		case MMC_TIMING_UHS_SDR50:
+		case MMC_TIMING_UHS_DDR50:
+		case MMC_TIMING_UHS_SDR104:
+			if (host->pdata->get_clk_drv &&
+					host->pdata->get_clk_drv(host) &&
+					host->use_hold_reg) {
+				cmd_flags |= SDMMC_CMD_USE_HOLD_REG;
+				break;
+			}
+
+			cmd_flags &= ~SDMMC_CMD_USE_HOLD_REG;
+			break;
+		case MMC_TIMING_UHS_SDR12:
+		case MMC_TIMING_UHS_SDR25:
+			if (host->use_hold_reg) {
+				cmd_flags |= SDMMC_CMD_USE_HOLD_REG;
Quoted 8 lines

drivers/mmc/host/dw_mmc.c static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command *cmd) · line 306

Quoted 7 lines
drivers/mmc/host/dw_mmc.c +7 -0
+				break;
+			}
+		default:
+			cmd_flags &= ~SDMMC_CMD_USE_HOLD_REG;
+		}
+	}
+

Considering MMC_TIMING_MMC_HS, MMC_TIMING_SD_HS is omitted.

Quoted 7 lines

Sorry, i will fix.

Quoted 2 lines

Didn't you consider moving this whole routine to dw_mci_set_ios? When deciding the timing, once seems to be enough.

Well, i considered that move the code into dw_mci_set_ios(). But cmd_flags is set before sending the command at every time. Finally, hold_regs bit must be also set at every time. We can prevent to set the cmd_flags at every time.

Yes, use_hold_regs shoud be set to CMD, whenever sending command. But cmd_flags for use_hold_reg can be set a time.

Thanks,
Seungwon Jeon

Quoted 65 lines

Best Regards,
Jaehoon Chung

Quoted 48 lines

Thanks,
Seungwon Jeon

Quoted 44 lines
drivers/mmc/host/dw_mmc.c +2 -0
 	mci_writel(host, CMDARG, cmd->arg);
 	wmb();
 

@@ -2015,6 +2049,8 @@ int dw_mci_probe(struct dw_mci *host)
 		host->data_shift = 2;
 	}
 
+	host->use_hold_reg = (mci_readl(host, HCON) >> 22) & 0x1;
+
 	/* Reset all blocks */
 	if (!mci_wait_reset(&host->dev, host))
 		return -ENODEV;
drivers/mmc/host/dw_mmc.h +1 -0
index b6a1a78..cc905ee 100644
@@ -111,6 +111,7 @@
 #define SDMMC_INT_ERROR			0xbfc2
 /* Command register defines */
 #define SDMMC_CMD_START			BIT(31)
+#define SDMMC_CMD_USE_HOLD_REG		BIT(29)
 #define SDMMC_CMD_CCS_EXP		BIT(23)
 #define SDMMC_CMD_CEATA_RD		BIT(22)
 #define SDMMC_CMD_UPD_CLK		BIT(21)
include/linux/mmc/dw_mmc.h +3 -0
index f20979c..803a80d 100644
@@ -156,6 +156,7 @@ struct dw_mci {
 	u32			fifoth_val;
 	u16			verid;
 	u16			data_offset;
+	bool			use_hold_reg;
 	struct device		dev;
 	struct dw_mci_board	*pdata;
 	struct dw_mci_slot	*slot[MAX_MCI_SLOTS];

@@ -201,6 +202,8 @@ struct dw_mci_dma_ops {
 #define DW_MCI_QUIRK_HIGHSPEED			BIT(2)
 /* Unreliable card detection */
 #define DW_MCI_QUIRK_BROKEN_CARD_DETECTION	BIT(3)
+/* To use the CLKSEL register for phase-shift */
+#define DW_MCI_QUIRK_USE_CLKSEL_REG		BIT(4)
Quoted 9 lines
Quoted 3 lines
include/linux/mmc/dw_mmc.h +0 -1
 struct dma_pdata;
--

1.7.4.1

--
To unsubscribe from this list: send the line "unsubscribe linux-mmc" in the body of a message to [email protected]
More majordomo info at http://vger.kernel.org/majordomo-info.html

--
To unsubscribe from this list: send the line "unsubscribe linux-mmc" in the body of a message to [email protected]
More majordomo info at http://vger.kernel.org/majordomo-info.html