Prepare for OMAP2+ movement to Common Clk
Subsystems (7)
v4 cover Prepare for OMAP2+ movement to Common Clk
Changes in v4:
* Added *hack* comments around clk_prepare usage in hwmod rebased on 3.6-rc
Changes in v3:
* Fixed various checkpatch warning/errors as reported by Paul W.
Changes in v2:
* Dropped all driver clk_prepare/clk_unprepare changes, will be sent seperately to respective lists
This is a preparatory series for the OMAP Common Clk conversion. They mostly add clk_prepare/clk_unprepare in OMAP platform code. Also gets rid of omap_clk_get_by_name and uses clk_get, and removes all direct 'struct clk' dereferrencing and uses helpers similar to what is provided by Common Clk.
Patches are boot tested on OMAP2430sdp, 3630 Beagle-Xm and 4430/4460 Panda and suspend tested on 3630 Beagle-Xm and 4430 Panda. Patches apply on 3.6-rc3.
Rajendra Nayak (3):
ARM: omap: clk: add clk_prepare and clk_unprepare
ARM: omap: hwmod: get rid of all omap_clk_get_by_name usage
ARM: OMAP2+: clock: Remove all direct dereferencing of struct clk
arch/arm/mach-omap2/board-apollon.c | 4 +- arch/arm/mach-omap2/board-h4.c | 6 +- arch/arm/mach-omap2/board-omap4panda.c | 2 +- arch/arm/mach-omap2/clkt2xxx_apll.c | 2 +- arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c | 10 ++- arch/arm/mach-omap2/clkt34xx_dpll3m2.c | 20 +++--- arch/arm/mach-omap2/clkt_clksel.c | 91 ++++++++++++++++---------- arch/arm/mach-omap2/clkt_dpll.c | 26 ++++---- arch/arm/mach-omap2/clock.c | 11 ++-- arch/arm/mach-omap2/clock2420_data.c | 17 +++++ arch/arm/mach-omap2/clock2430_data.c | 21 ++++++ arch/arm/mach-omap2/clock3xxx.c | 8 +-- arch/arm/mach-omap2/clock3xxx_data.c | 23 +++++++ arch/arm/mach-omap2/clock44xx_data.c | 6 ++ arch/arm/mach-omap2/display.c | 4 +- arch/arm/mach-omap2/dpll3xxx.c | 48 ++++++++------ arch/arm/mach-omap2/gpmc.c | 2 +- arch/arm/mach-omap2/omap_hwmod.c | 45 ++++++++++--- arch/arm/mach-omap2/pm.c | 2 +- arch/arm/plat-omap/clock.c | 27 -------- arch/arm/plat-omap/include/plat/clock.h | 5 ++ arch/arm/plat-omap/omap_device.c | 6 +- 22 files changed, 251 insertions(+), 135 deletions(-)
Signature · 1 line
1.7.9.5
PATCH v4 1/3 ARM: omap: clk: add clk_prepare and clk_unprepare
As part of Common Clk Framework (CCF) the clk_enable() operation was split into a clk_prepare() which could sleep, and a clk_enable() which should never sleep. Similarly the clk_disable() was split into clk_disable() and clk_unprepare(). This was needed to handle complex cases where in a clk gate/ungate would require a slow and a fast part to be implemented. None of the clocks below seem to be in the 'complex' clocks category and are just simple clocks which are enabled/disabled through simple register writes.
Most of the instances also seem to be called in non-atomic context which means its safe to move all of those from using a clk_enable() to clk_prepare_enable() and clk_disable() to clk_disable_unprepare().
For some others, mainly the ones handled through the hwmod framework there is a possibility that they get called in either an atomic or a non-atomic context.
The way these get handled below work only as long as clk_prepare is implemented as a no-op (which is the case today) since this gets called very early at boot while most subsystems are unavailable. Hence these are marked with a *HACK* comment, which says we need to re-visit these once we start doing something meaningful with clk_prepare/clk_unprepare like doing voltage scaling or something that involves i2c.
This is in preparation of OMAP moving to CCF.
Based on initial changes from Mike turquette.
--- arch/arm/mach-omap2/board-apollon.c | 4 ++-- arch/arm/mach-omap2/board-h4.c | 6 +++--- arch/arm/mach-omap2/board-omap4panda.c | 2 +- arch/arm/mach-omap2/clock3xxx.c | 8 ++++---- arch/arm/mach-omap2/display.c | 4 ++-- arch/arm/mach-omap2/gpmc.c | 2 +- arch/arm/mach-omap2/omap_hwmod.c | 27 +++++++++++++++++++++++++++ 7 files changed, 40 insertions(+), 13 deletions(-)
arch/arm/mach-omap2/board-apollon.c +2 -2
@@ -204,7 +204,7 @@ static inline void __init apollon_init_smc91x(void)return ; } -clk_enable (gpmc_fck); +clk_prepare_enable (gpmc_fck); rate =clk_get_rate (gpmc_fck); eth_cs =APOLLON_ETH_CS ;
@@ -248,7 +248,7 @@ static inline void __init apollon_init_smc91x(void)gpmc_cs_free (APOLLON_ETH_CS ); } out: -clk_disable (gpmc_fck); +clk_disable_unprepare (gpmc_fck);clk_put (gpmc_fck); }
arch/arm/mach-omap2/board-h4.c +3 -3
@@ -266,9 +266,9 @@ static inline void __init h4_init_debug(void)return ; } -clk_enable (gpmc_fck); +clk_prepare_enable (gpmc_fck); rate =clk_get_rate (gpmc_fck); -clk_disable (gpmc_fck); +clk_disable_unprepare (gpmc_fck);clk_put (gpmc_fck);if (is_gpmc_muxed ())
@@ -312,7 +312,7 @@ static inline void __init h4_init_debug(void)gpmc_cs_free (eth_cs); out: -clk_disable (gpmc_fck); +clk_disable_unprepare (gpmc_fck);clk_put (gpmc_fck); }
arch/arm/mach-omap2/board-omap4panda.c +1 -1
@@ -172,7 +172,7 @@ static void __init omap4_ehci_init(void)return ; }clk_set_rate (phy_ref_clk,19200000 ); -clk_enable (phy_ref_clk); +clk_prepare_enable (phy_ref_clk);/* disable the power to the usb hub prior to init and reset phy+hub */ ret = gpio_request_array(panda_ehci_gpios,
arch/arm/mach-omap2/clock3xxx.c +4 -4
@@ -64,15 +64,15 @@ void __init omap3_clk_lock_dpll5(void) dpll5_clk =clk_get (NULL ,"dpll5_ck" );clk_set_rate (dpll5_clk,DPLL5_FREQ_FOR_USBHOST ); -clk_enable (dpll5_clk); +clk_prepare_enable (dpll5_clk);/* Program dpll5_m2_clk divider for no division */ dpll5_m2_clk =clk_get (NULL ,"dpll5_m2_ck" ); -clk_enable (dpll5_m2_clk); +clk_prepare_enable (dpll5_m2_clk);clk_set_rate (dpll5_m2_clk,DPLL5_FREQ_FOR_USBHOST ); -clk_disable (dpll5_m2_clk); -clk_disable (dpll5_clk); +clk_disable_unprepare (dpll5_m2_clk); +clk_disable_unprepare (dpll5_clk);return ; }
arch/arm/mach-omap2/display.c +2 -2
@@ -488,7 +488,7 @@ int omap_dss_reset(struct omap_hwmod *oh)for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i >0 ; i--, oc++)if (oc->_clk) -clk_enable (oc->_clk); +clk_prepare_enable (oc->_clk);dispc_disable_outputs ();
@@ -515,7 +515,7 @@ int omap_dss_reset(struct omap_hwmod *oh)for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i >0 ; i--, oc++)if (oc->_clk) -clk_disable (oc->_clk); +clk_disable_unprepare (oc->_clk); r = (c ==MAX_MODULE_SOFTRESET_WAIT ) ? -ETIMEDOUT :0 ;
arch/arm/mach-omap2/gpmc.c +1 -1
@@ -750,7 +750,7 @@ static int __init gpmc_init(void)BUG (); } -clk_enable (gpmc_l3_clk); +clk_prepare_enable (gpmc_l3_clk); l =gpmc_read_reg (GPMC_REVISION );printk (KERN_INFO "GPMC revision %d.%d\n" , (l >>4 ) &0x0f , l &0x0f );
arch/arm/mach-omap2/omap_hwmod.c +27 -0
@@ -683,6 +683,15 @@ static int _init_main_clk(struct omap_hwmod *oh) oh->name, oh->main_clk);return -EINVAL ; } +/* +* HACK: This needs a re-visit once clk_prepare() is implemented +* to do something meaningful. Today its just a no-op. +* If clk_prepare() is used at some point to do things like +* voltage scaling etc, then this would have to be moved to +* some point where subsystems like i2c and pmic become +* available. +*/ +clk_prepare (oh->_clk);if (!oh->_clk->clkdm) pr_warning("omap_hwmod: %s: missing clockdomain for %s.\n",
@@ -720,6 +729,15 @@ static int _init_interface_clks(struct omap_hwmod *oh) ret = -EINVAL ; } os->_clk = c; +/* +* HACK: This needs a re-visit once clk_prepare() is implemented +* to do something meaningful. Today its just a no-op. +* If clk_prepare() is used at some point to do things like +* voltage scaling etc, then this would have to be moved to +* some point where subsystems like i2c and pmic become +* available. +*/ +clk_prepare (os->_clk); }return ret;
@@ -747,6 +765,15 @@ static int _init_opt_clks(struct omap_hwmod *oh) ret = -EINVAL ; } oc->_clk = c; +/* +* HACK: This needs a re-visit once clk_prepare() is implemented +* to do something meaningful. Today its just a no-op. +* If clk_prepare() is used at some point to do things like +* voltage scaling etc, then this would have to be moved to +* some point where subsystems like i2c and pmic become +* available. +*/ +clk_prepare (oc->_clk); }return ret;
Signature · 1 line
1.7.9.5
PATCH v4 1/3 ARM: omap: clk: add clk_prepare and clk_unprepare
Quoted 26 lines · Rajendra Nayak
As part of Common Clk Framework (CCF) the
clk_enable()operation was split into aclk_prepare()which could sleep, and aclk_enable()which should never sleep. Similarly theclk_disable()was split intoclk_disable()andclk_unprepare(). This was needed to handle complex cases where in a clk gate/ungate would require a slow and a fast part to be implemented. None of the clocks below seem to be in the 'complex' clocks category and are just simple clocks which are enabled/disabled through simple register writes.
Most of the instances also seem to be called in non-atomic context which means its safe to move all of those from using aclk_enable()toclk_prepare_enable()andclk_disable()toclk_disable_unprepare().For some others, mainly the ones handled through the hwmod framework there is a possibility that they get called in either an atomic or a non-atomic context.
The way these get handled below work only as long as
clk_prepareis implemented as a no-op (which is the case today) since this gets called very early at boot while most subsystems are unavailable. Hence these are marked with a *HACK* comment, which says we need to re-visit these once we start doing something meaningful with clk_prepare/clk_unprepare like doing voltage scaling or something that involves i2c.
Quoted 5 lines
This is in preparation of OMAP moving to CCF.
Based on initial changes from Mike turquette.
Signed-off-by Rajendra Nayak <[email protected]>
Looks good to me.
Quoted 184 lines
--- arch/arm/mach-omap2/board-apollon.c | 4 ++-- arch/arm/mach-omap2/board-h4.c | 6 +++--- arch/arm/mach-omap2/board-omap4panda.c | 2 +- arch/arm/mach-omap2/clock3xxx.c | 8 ++++---- arch/arm/mach-omap2/display.c | 4 ++-- arch/arm/mach-omap2/gpmc.c | 2 +- arch/arm/mach-omap2/omap_hwmod.c | 27 +++++++++++++++++++++++++++ 7 files changed, 40 insertions(+), 13 deletions(-)arch/arm/mach-omap2/board-apollon.c +2
-2@@ -204,7 +204,7 @@ static inline void __init apollon_init_smc91x(void)return ; } -clk_enable (gpmc_fck); +clk_prepare_enable (gpmc_fck); rate =clk_get_rate (gpmc_fck); eth_cs =APOLLON_ETH_CS ;@@ -248,7 +248,7 @@ static inline void __init apollon_init_smc91x(void)gpmc_cs_free (APOLLON_ETH_CS ); } out: -clk_disable (gpmc_fck); +clk_disable_unprepare (gpmc_fck);clk_put (gpmc_fck); }arch/arm/mach-omap2/board-h4.c +3
-3@@ -266,9 +266,9 @@ static inline void __init h4_init_debug(void)return ; } -clk_enable (gpmc_fck); +clk_prepare_enable (gpmc_fck); rate =clk_get_rate (gpmc_fck); -clk_disable (gpmc_fck); +clk_disable_unprepare (gpmc_fck);clk_put (gpmc_fck);if (is_gpmc_muxed ())@@ -312,7 +312,7 @@ static inline void __init h4_init_debug(void)gpmc_cs_free (eth_cs); out: -clk_disable (gpmc_fck); +clk_disable_unprepare (gpmc_fck);clk_put (gpmc_fck); }arch/arm/mach-omap2/board-omap4panda.c +1
-1@@ -172,7 +172,7 @@ static void __init omap4_ehci_init(void)return ; }clk_set_rate (phy_ref_clk,19200000 ); -clk_enable (phy_ref_clk); +clk_prepare_enable (phy_ref_clk);/* disable the power to the usb hub prior to init and reset phy+hub */ ret = gpio_request_array(panda_ehci_gpios,arch/arm/mach-omap2/clock3xxx.c +4
-4@@ -64,15 +64,15 @@ void __init omap3_clk_lock_dpll5(void) dpll5_clk =clk_get (NULL ,"dpll5_ck" );clk_set_rate (dpll5_clk,DPLL5_FREQ_FOR_USBHOST ); -clk_enable (dpll5_clk); +clk_prepare_enable (dpll5_clk);/* Program dpll5_m2_clk divider for no division */ dpll5_m2_clk =clk_get (NULL ,"dpll5_m2_ck" ); -clk_enable (dpll5_m2_clk); +clk_prepare_enable (dpll5_m2_clk);clk_set_rate (dpll5_m2_clk,DPLL5_FREQ_FOR_USBHOST ); -clk_disable (dpll5_m2_clk); -clk_disable (dpll5_clk); +clk_disable_unprepare (dpll5_m2_clk); +clk_disable_unprepare (dpll5_clk);return ; }arch/arm/mach-omap2/display.c +2
-2@@ -488,7 +488,7 @@ int omap_dss_reset(struct omap_hwmod *oh)for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i >0 ; i--, oc++)if (oc->_clk) -clk_enable (oc->_clk); +clk_prepare_enable (oc->_clk);dispc_disable_outputs ();@@ -515,7 +515,7 @@ int omap_dss_reset(struct omap_hwmod *oh)for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i >0 ; i--, oc++)if (oc->_clk) -clk_disable (oc->_clk); +clk_disable_unprepare (oc->_clk); r = (c ==MAX_MODULE_SOFTRESET_WAIT ) ? -ETIMEDOUT :0 ;arch/arm/mach-omap2/gpmc.c +1
-1@@ -750,7 +750,7 @@ static int __init gpmc_init(void)BUG (); } -clk_enable (gpmc_l3_clk); +clk_prepare_enable (gpmc_l3_clk); l =gpmc_read_reg (GPMC_REVISION );printk (KERN_INFO "GPMC revision %d.%d\n" , (l >>4 ) &0x0f , l &0x0f );arch/arm/mach-omap2/omap_hwmod.c +27
-1@@ -683,6 +683,15 @@ static int _init_main_clk(struct omap_hwmod *oh) oh->name, oh->main_clk);return -EINVAL ; } +/* +* HACK: This needs a re-visit once clk_prepare() is implemented +* to do something meaningful. Today its just a no-op. +* If clk_prepare() is used at some point to do things like +* voltage scaling etc, then this would have to be moved to +* some point where subsystems like i2c and pmic become +* available. +*/ +clk_prepare (oh->_clk);if (!oh->_clk->clkdm) pr_warning("omap_hwmod: %s: missing clockdomain for %s.\n",@@ -720,6 +729,15 @@ static int _init_interface_clks(struct omap_hwmod *oh) ret = -EINVAL ; } os->_clk = c; +/* +* HACK: This needs a re-visit once clk_prepare() is implemented +* to do something meaningful. Today its just a no-op. +* If clk_prepare() is used at some point to do things like +* voltage scaling etc, then this would have to be moved to +* some point where subsystems like i2c and pmic become +* available. +*/ +clk_prepare (os->_clk); }return ret;@@ -747,6 +765,15 @@ static int _init_opt_clks(struct omap_hwmod *oh) ret = -EINVAL ; } oc->_clk = c; +/* +* HACK: This needs a re-visit once clk_prepare() is implemented +* to do something meaningful. Today its just a no-op. +* If clk_prepare() is used at some point to do things like +* voltage scaling etc, then this would have to be moved to +* some point where subsystems like i2c and pmic become +* available. +*/ +clk_prepare (oc->_clk); }return ret; --1.7.9.5
PATCH v4 2/3 ARM: omap: hwmod: get rid of all omap_clk_get_by_name usage
In reply to Rajendra NayakMoving to Common clk framework for OMAP would mean we no longer use internal lookup mechanism like omap_clk_get_by_name(). get rid of all its usage mostly from hwmod and omap_device code.
Also use IS_ERR_OR_NULL() for error checking.
Moving to clk_get() also means the respective platforms need the clkdev tables updated with an entry for all clocks used by hwmod to have clock name same as the alias.
Based on original changes from Mike Turquette.
--- arch/arm/mach-omap2/clock2420_data.c | 17 +++++++++++++++++ arch/arm/mach-omap2/clock2430_data.c | 21 +++++++++++++++++++++ arch/arm/mach-omap2/clock3xxx_data.c | 23 +++++++++++++++++++++++ arch/arm/mach-omap2/clock44xx_data.c | 6 ++++++ arch/arm/mach-omap2/omap_hwmod.c | 12 ++++++------ arch/arm/plat-omap/clock.c | 27 --------------------------- arch/arm/plat-omap/omap_device.c | 6 +++--- 7 files changed, 76 insertions(+), 36 deletions(-)
arch/arm/mach-omap2/clock2420_data.c +17 -0
@@ -1804,6 +1804,7 @@ static struct omap_clk omap2420_clks[] = {CLK (NULL ,"gfx_ick" , &gfx_ick,CK_242X ),/* DSS domain clocks */ CLK ("omapdss_dss" ,"ick" , &dss_ick,CK_242X ), +CLK (NULL ,"dss_ick" , &dss_ick,CK_242X ),CLK (NULL ,"dss1_fck" , &dss1_fck,CK_242X ),CLK (NULL ,"dss2_fck" , &dss2_fck,CK_242X ), CLK(NULL, "dss_54m_fck", &dss_54m_fck, CK_242X),
@@ -1843,12 +1844,16 @@ static struct omap_clk omap2420_clks[] = {CLK (NULL ,"gpt12_ick" , &gpt12_ick,CK_242X ),CLK (NULL ,"gpt12_fck" , &gpt12_fck,CK_242X ),CLK ("omap-mcbsp.1" ,"ick" , &mcbsp1_ick,CK_242X ), +CLK (NULL ,"mcbsp1_ick" , &mcbsp1_ick,CK_242X ),CLK (NULL ,"mcbsp1_fck" , &mcbsp1_fck,CK_242X ),CLK ("omap-mcbsp.2" ,"ick" , &mcbsp2_ick,CK_242X ), +CLK (NULL ,"mcbsp2_ick" , &mcbsp2_ick,CK_242X ),CLK (NULL ,"mcbsp2_fck" , &mcbsp2_fck,CK_242X ),CLK ("omap2_mcspi.1" ,"ick" , &mcspi1_ick,CK_242X ), +CLK (NULL ,"mcspi1_ick" , &mcspi1_ick,CK_242X ),CLK (NULL ,"mcspi1_fck" , &mcspi1_fck,CK_242X ),CLK ("omap2_mcspi.2" ,"ick" , &mcspi2_ick,CK_242X ), +CLK (NULL ,"mcspi2_ick" , &mcspi2_ick,CK_242X ),CLK (NULL ,"mcspi2_fck" , &mcspi2_fck,CK_242X ),CLK (NULL ,"uart1_ick" , &uart1_ick,CK_242X ), CLK(NULL, "uart1_fck", &uart1_fck, CK_242X),
@@ -1859,12 +1864,15 @@ static struct omap_clk omap2420_clks[] = {CLK (NULL ,"gpios_ick" , &gpios_ick,CK_242X ),CLK (NULL ,"gpios_fck" , &gpios_fck,CK_242X ),CLK ("omap_wdt" ,"ick" , &mpu_wdt_ick,CK_242X ), +CLK (NULL ,"mpu_wdt_ick" , &mpu_wdt_ick,CK_242X ),CLK (NULL ,"mpu_wdt_fck" , &mpu_wdt_fck,CK_242X ),CLK (NULL ,"sync_32k_ick" , &sync_32k_ick,CK_242X ),CLK (NULL ,"wdt1_ick" , &wdt1_ick,CK_242X ),CLK (NULL ,"omapctrl_ick" , &omapctrl_ick,CK_242X ),CLK ("omap24xxcam" ,"fck" , &cam_fck,CK_242X ), +CLK (NULL ,"cam_fck" , &cam_fck,CK_242X ),CLK ("omap24xxcam" ,"ick" , &cam_ick,CK_242X ), +CLK (NULL ,"cam_ick" , &cam_ick,CK_242X ),CLK (NULL ,"mailboxes_ick" , &mailboxes_ick,CK_242X ),CLK (NULL ,"wdt4_ick" , &wdt4_ick,CK_242X ), CLK(NULL, "wdt4_fck", &wdt4_fck, CK_242X),
@@ -1873,16 +1881,22 @@ static struct omap_clk omap2420_clks[] = {CLK (NULL ,"mspro_ick" , &mspro_ick,CK_242X ),CLK (NULL ,"mspro_fck" , &mspro_fck,CK_242X ),CLK ("mmci-omap.0" ,"ick" , &mmc_ick,CK_242X ), +CLK (NULL ,"mmc_ick" , &mmc_ick,CK_242X ),CLK ("mmci-omap.0" ,"fck" , &mmc_fck,CK_242X ), +CLK (NULL ,"mmc_fck" , &mmc_fck,CK_242X ),CLK (NULL ,"fac_ick" , &fac_ick,CK_242X ),CLK (NULL ,"fac_fck" , &fac_fck,CK_242X ),CLK (NULL ,"eac_ick" , &eac_ick,CK_242X ),CLK (NULL ,"eac_fck" , &eac_fck,CK_242X ),CLK ("omap_hdq.0" ,"ick" , &hdq_ick,CK_242X ), +CLK (NULL ,"hdq_ick" , &hdq_ick,CK_242X ),CLK ("omap_hdq.0" ,"fck" , &hdq_fck,CK_242X ), +CLK (NULL ,"hdq_fck" , &hdq_fck,CK_242X ),CLK ("omap_i2c.1" ,"ick" , &i2c1_ick,CK_242X ), +CLK (NULL ,"i2c1_ick" , &i2c1_ick,CK_242X ),CLK (NULL ,"i2c1_fck" , &i2c1_fck,CK_242X ),CLK ("omap_i2c.2" ,"ick" , &i2c2_ick,CK_242X ), +CLK (NULL ,"i2c2_ick" , &i2c2_ick,CK_242X ),CLK (NULL ,"i2c2_fck" , &i2c2_fck,CK_242X ),CLK (NULL ,"gpmc_fck" , &gpmc_fck,CK_242X ), CLK(NULL, "sdma_fck", &sdma_fck, CK_242X),
@@ -1892,8 +1906,11 @@ static struct omap_clk omap2420_clks[] = {CLK (NULL ,"vlynq_fck" , &vlynq_fck,CK_242X ),CLK (NULL ,"des_ick" , &des_ick,CK_242X ),CLK ("omap-sham" ,"ick" , &sha_ick,CK_242X ), +CLK (NULL ,"sha_ick" , &sha_ick,CK_242X ),CLK ("omap_rng" ,"ick" , &rng_ick,CK_242X ), +CLK (NULL ,"rng_ick" , &rng_ick,CK_242X ),CLK ("omap-aes" ,"ick" , &aes_ick,CK_242X ), +CLK (NULL ,"aes_ick" , &aes_ick,CK_242X ),CLK (NULL ,"pka_ick" , &pka_ick,CK_242X ),CLK (NULL ,"usb_fck" , &usb_fck,CK_242X ), CLK("musb-hdrc", "fck", &osc_ck, CK_242X),
arch/arm/mach-omap2/clock2430_data.c +21 -0
@@ -1887,6 +1887,7 @@ static struct omap_clk omap2430_clks[] = {CLK (NULL ,"mdm_osc_ck" , &mdm_osc_ck,CK_243X ),/* DSS domain clocks */ CLK ("omapdss_dss" ,"ick" , &dss_ick,CK_243X ), +CLK (NULL ,"dss_ick" , &dss_ick,CK_243X ),CLK (NULL ,"dss1_fck" , &dss1_fck,CK_243X ),CLK (NULL ,"dss2_fck" , &dss2_fck,CK_243X ), CLK(NULL, "dss_54m_fck", &dss_54m_fck, CK_243X),
@@ -1926,20 +1927,28 @@ static struct omap_clk omap2430_clks[] = {CLK (NULL ,"gpt12_ick" , &gpt12_ick,CK_243X ),CLK (NULL ,"gpt12_fck" , &gpt12_fck,CK_243X ),CLK ("omap-mcbsp.1" ,"ick" , &mcbsp1_ick,CK_243X ), +CLK (NULL ,"mcbsp1_ick" , &mcbsp1_ick,CK_243X ),CLK (NULL ,"mcbsp1_fck" , &mcbsp1_fck,CK_243X ),CLK ("omap-mcbsp.2" ,"ick" , &mcbsp2_ick,CK_243X ), +CLK (NULL ,"mcbsp2_ick" , &mcbsp2_ick,CK_243X ),CLK (NULL ,"mcbsp2_fck" , &mcbsp2_fck,CK_243X ),CLK ("omap-mcbsp.3" ,"ick" , &mcbsp3_ick,CK_243X ), +CLK (NULL ,"mcbsp3_ick" , &mcbsp3_ick,CK_243X ),CLK (NULL ,"mcbsp3_fck" , &mcbsp3_fck,CK_243X ),CLK ("omap-mcbsp.4" ,"ick" , &mcbsp4_ick,CK_243X ), +CLK (NULL ,"mcbsp4_ick" , &mcbsp4_ick,CK_243X ),CLK (NULL ,"mcbsp4_fck" , &mcbsp4_fck,CK_243X ),CLK ("omap-mcbsp.5" ,"ick" , &mcbsp5_ick,CK_243X ), +CLK (NULL ,"mcbsp5_ick" , &mcbsp5_ick,CK_243X ),CLK (NULL ,"mcbsp5_fck" , &mcbsp5_fck,CK_243X ),CLK ("omap2_mcspi.1" ,"ick" , &mcspi1_ick,CK_243X ), +CLK (NULL ,"mcspi1_ick" , &mcspi1_ick,CK_243X ),CLK (NULL ,"mcspi1_fck" , &mcspi1_fck,CK_243X ),CLK ("omap2_mcspi.2" ,"ick" , &mcspi2_ick,CK_243X ), +CLK (NULL ,"mcspi2_ick" , &mcspi2_ick,CK_243X ),CLK (NULL ,"mcspi2_fck" , &mcspi2_fck,CK_243X ),CLK ("omap2_mcspi.3" ,"ick" , &mcspi3_ick,CK_243X ), +CLK (NULL ,"mcspi3_ick" , &mcspi3_ick,CK_243X ),CLK (NULL ,"mcspi3_fck" , &mcspi3_fck,CK_243X ),CLK (NULL ,"uart1_ick" , &uart1_ick,CK_243X ), CLK(NULL, "uart1_fck", &uart1_fck, CK_243X),
@@ -1950,13 +1959,16 @@ static struct omap_clk omap2430_clks[] = {CLK (NULL ,"gpios_ick" , &gpios_ick,CK_243X ),CLK (NULL ,"gpios_fck" , &gpios_fck,CK_243X ),CLK ("omap_wdt" ,"ick" , &mpu_wdt_ick,CK_243X ), +CLK (NULL ,"mpu_wdt_ick" , &mpu_wdt_ick,CK_243X ),CLK (NULL ,"mpu_wdt_fck" , &mpu_wdt_fck,CK_243X ),CLK (NULL ,"sync_32k_ick" , &sync_32k_ick,CK_243X ),CLK (NULL ,"wdt1_ick" , &wdt1_ick,CK_243X ),CLK (NULL ,"omapctrl_ick" , &omapctrl_ick,CK_243X ),CLK (NULL ,"icr_ick" , &icr_ick,CK_243X ),CLK ("omap24xxcam" ,"fck" , &cam_fck,CK_243X ), +CLK (NULL ,"cam_fck" , &cam_fck,CK_243X ),CLK ("omap24xxcam" ,"ick" , &cam_ick,CK_243X ), +CLK (NULL ,"cam_ick" , &cam_ick,CK_243X ),CLK (NULL ,"mailboxes_ick" , &mailboxes_ick,CK_243X ),CLK (NULL ,"wdt4_ick" , &wdt4_ick,CK_243X ), CLK(NULL, "wdt4_fck", &wdt4_fck, CK_243X),
@@ -1965,10 +1977,14 @@ static struct omap_clk omap2430_clks[] = {CLK (NULL ,"fac_ick" , &fac_ick,CK_243X ),CLK (NULL ,"fac_fck" , &fac_fck,CK_243X ),CLK ("omap_hdq.0" ,"ick" , &hdq_ick,CK_243X ), +CLK (NULL ,"hdq_ick" , &hdq_ick,CK_243X ),CLK ("omap_hdq.1" ,"fck" , &hdq_fck,CK_243X ), +CLK (NULL ,"hdq_fck" , &hdq_fck,CK_243X ),CLK ("omap_i2c.1" ,"ick" , &i2c1_ick,CK_243X ), +CLK (NULL ,"i2c1_ick" , &i2c1_ick,CK_243X ),CLK (NULL ,"i2chs1_fck" , &i2chs1_fck,CK_243X ),CLK ("omap_i2c.2" ,"ick" , &i2c2_ick,CK_243X ), +CLK (NULL ,"i2c2_ick" , &i2c2_ick,CK_243X ),CLK (NULL ,"i2chs2_fck" , &i2chs2_fck,CK_243X ),CLK (NULL ,"gpmc_fck" , &gpmc_fck,CK_243X ), CLK(NULL, "sdma_fck", &sdma_fck, CK_243X),
@@ -1981,15 +1997,20 @@ static struct omap_clk omap2430_clks[] = {CLK (NULL ,"pka_ick" , &pka_ick,CK_243X ),CLK (NULL ,"usb_fck" , &usb_fck,CK_243X ),CLK ("musb-omap2430" ,"ick" , &usbhs_ick,CK_243X ), +CLK (NULL ,"usbhs_ick" , &usbhs_ick,CK_243X ),CLK ("omap_hsmmc.0" ,"ick" , &mmchs1_ick,CK_243X ), +CLK (NULL ,"mmchs1_ick" , &mmchs1_ick,CK_243X ),CLK (NULL ,"mmchs1_fck" , &mmchs1_fck,CK_243X ),CLK ("omap_hsmmc.1" ,"ick" , &mmchs2_ick,CK_243X ), +CLK (NULL ,"mmchs2_ick" , &mmchs2_ick,CK_243X ),CLK (NULL ,"mmchs2_fck" , &mmchs2_fck,CK_243X ),CLK (NULL ,"gpio5_ick" , &gpio5_ick,CK_243X ),CLK (NULL ,"gpio5_fck" , &gpio5_fck,CK_243X ),CLK (NULL ,"mdm_intc_ick" , &mdm_intc_ick,CK_243X ),CLK ("omap_hsmmc.0" ,"mmchsdb_fck" , &mmchsdb1_fck,CK_243X ), +CLK (NULL ,"mmchsdb1_fck" , &mmchsdb1_fck,CK_243X ),CLK ("omap_hsmmc.1" ,"mmchsdb_fck" , &mmchsdb2_fck,CK_243X ), +CLK (NULL ,"mmchsdb2_fck" , &mmchsdb2_fck,CK_243X ),CLK (NULL ,"timer_32k_ck" , &func_32k_ck,CK_243X ),CLK (NULL ,"timer_sys_ck" , &sys_ck,CK_243X ), CLK(NULL, "timer_ext_ck", &alt_ck, CK_243X),
arch/arm/mach-omap2/clock3xxx_data.c +23 -0
@@ -3247,6 +3247,7 @@ static struct omap_clk omap3xxx_clks[] = {CLK (NULL ,"dpll4_x2_ck" , &dpll4_x2_ck,CK_3XXX ),CLK (NULL ,"omap_192m_alwon_fck" , &omap_192m_alwon_fck,CK_36XX ),CLK (NULL ,"omap_96m_alwon_fck" , &omap_96m_alwon_fck,CK_3XXX ), +CLK (NULL ,"omap_96m_alwon_fck_3630" , &omap_96m_alwon_fck_3630,CK_3XXX ),CLK (NULL ,"omap_96m_fck" , &omap_96m_fck,CK_3XXX ),CLK (NULL ,"cm_96m_fck" , &cm_96m_fck,CK_3XXX ), CLK(NULL, "omap_54m_fck", &omap_54m_fck, CK_3XXX),
@@ -3314,6 +3315,7 @@ static struct omap_clk omap3xxx_clks[] = {CLK (NULL ,"fshostusb_fck" , &fshostusb_fck,CK_3430ES1 ),CLK (NULL ,"core_12m_fck" , &core_12m_fck,CK_3XXX ),CLK ("omap_hdq.0" ,"fck" , &hdq_fck,CK_3XXX ), +CLK (NULL ,"hdq_fck" , &hdq_fck,CK_3XXX ),CLK (NULL ,"ssi_ssr_fck" , &ssi_ssr_fck_3430es1,CK_3430ES1 ),CLK (NULL ,"ssi_ssr_fck" , &ssi_ssr_fck_3430es2,CK_3430ES2PLUS |CK_36XX ), CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es1, CK_3430ES1),
@@ -3321,6 +3323,8 @@ static struct omap_clk omap3xxx_clks[] = {CLK (NULL ,"core_l3_ick" , &core_l3_ick,CK_3XXX ),CLK ("musb-omap2430" ,"ick" , &hsotgusb_ick_3430es1,CK_3430ES1 ),CLK ("musb-omap2430" ,"ick" , &hsotgusb_ick_3430es2,CK_3430ES2PLUS |CK_36XX ), +CLK (NULL ,"hsotgusb_ick" , &hsotgusb_ick_3430es1,CK_3430ES1 ), +CLK (NULL ,"hsotgusb_ick" , &hsotgusb_ick_3430es2,CK_3430ES2PLUS |CK_36XX ),CLK (NULL ,"sdrc_ick" , &sdrc_ick,CK_3XXX ),CLK (NULL ,"gpmc_fck" , &gpmc_fck,CK_3XXX ), CLK(NULL, "security_l3_ick", &security_l3_ick, CK_34XX | CK_36XX),
@@ -3329,27 +3333,40 @@ static struct omap_clk omap3xxx_clks[] = {CLK (NULL ,"usbtll_ick" , &usbtll_ick,CK_3430ES2PLUS |CK_AM35XX |CK_36XX ),CLK ("usbhs_omap" ,"usbtll_ick" , &usbtll_ick,CK_3430ES2PLUS |CK_AM35XX |CK_36XX ),CLK ("omap_hsmmc.2" ,"ick" , &mmchs3_ick,CK_3430ES2PLUS |CK_AM35XX |CK_36XX ), +CLK (NULL ,"mmchs3_ick" , &mmchs3_ick,CK_3430ES2PLUS |CK_AM35XX |CK_36XX ),CLK (NULL ,"icr_ick" , &icr_ick,CK_34XX |CK_36XX ),CLK ("omap-aes" ,"ick" , &aes2_ick,CK_34XX |CK_36XX ),CLK ("omap-sham" ,"ick" , &sha12_ick,CK_34XX |CK_36XX ),CLK (NULL ,"des2_ick" , &des2_ick,CK_34XX |CK_36XX ),CLK ("omap_hsmmc.1" ,"ick" , &mmchs2_ick,CK_3XXX ),CLK ("omap_hsmmc.0" ,"ick" , &mmchs1_ick,CK_3XXX ), +CLK (NULL ,"mmchs2_ick" , &mmchs2_ick,CK_3XXX ), +CLK (NULL ,"mmchs1_ick" , &mmchs1_ick,CK_3XXX ),CLK (NULL ,"mspro_ick" , &mspro_ick,CK_34XX |CK_36XX ),CLK ("omap_hdq.0" ,"ick" , &hdq_ick,CK_3XXX ), +CLK (NULL ,"hdq_ick" , &hdq_ick,CK_3XXX ),CLK ("omap2_mcspi.4" ,"ick" , &mcspi4_ick,CK_3XXX ),CLK ("omap2_mcspi.3" ,"ick" , &mcspi3_ick,CK_3XXX ),CLK ("omap2_mcspi.2" ,"ick" , &mcspi2_ick,CK_3XXX ),CLK ("omap2_mcspi.1" ,"ick" , &mcspi1_ick,CK_3XXX ), +CLK (NULL ,"mcspi4_ick" , &mcspi4_ick,CK_3XXX ), +CLK (NULL ,"mcspi3_ick" , &mcspi3_ick,CK_3XXX ), +CLK (NULL ,"mcspi2_ick" , &mcspi2_ick,CK_3XXX ), +CLK (NULL ,"mcspi1_ick" , &mcspi1_ick,CK_3XXX ),CLK ("omap_i2c.3" ,"ick" , &i2c3_ick,CK_3XXX ),CLK ("omap_i2c.2" ,"ick" , &i2c2_ick,CK_3XXX ),CLK ("omap_i2c.1" ,"ick" , &i2c1_ick,CK_3XXX ), +CLK (NULL ,"i2c3_ick" , &i2c3_ick,CK_3XXX ), +CLK (NULL ,"i2c2_ick" , &i2c2_ick,CK_3XXX ), +CLK (NULL ,"i2c1_ick" , &i2c1_ick,CK_3XXX ),CLK (NULL ,"uart2_ick" , &uart2_ick,CK_3XXX ),CLK (NULL ,"uart1_ick" , &uart1_ick,CK_3XXX ),CLK (NULL ,"gpt11_ick" , &gpt11_ick,CK_3XXX ),CLK (NULL ,"gpt10_ick" , &gpt10_ick,CK_3XXX ),CLK ("omap-mcbsp.5" ,"ick" , &mcbsp5_ick,CK_3XXX ),CLK ("omap-mcbsp.1" ,"ick" , &mcbsp1_ick,CK_3XXX ), +CLK (NULL ,"mcbsp5_ick" , &mcbsp5_ick,CK_3XXX ), +CLK (NULL ,"mcbsp1_ick" , &mcbsp1_ick,CK_3XXX ),CLK (NULL ,"fac_ick" , &fac_ick,CK_3430ES1 ),CLK (NULL ,"mailboxes_ick" , &mailboxes_ick,CK_34XX |CK_36XX ), CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_3XXX),
@@ -3368,7 +3385,9 @@ static struct omap_clk omap3xxx_clks[] = {CLK (NULL ,"dss_96m_fck" , &dss_96m_fck,CK_3XXX ),CLK (NULL ,"dss2_alwon_fck" , &dss2_alwon_fck,CK_3XXX ),CLK ("omapdss_dss" ,"ick" , &dss_ick_3430es1,CK_3430ES1 ), +CLK (NULL ,"dss_ick" , &dss_ick_3430es1,CK_3430ES1 ),CLK ("omapdss_dss" ,"ick" , &dss_ick_3430es2,CK_3430ES2PLUS |CK_AM35XX |CK_36XX ), +CLK (NULL ,"dss_ick" , &dss_ick_3430es2,CK_3430ES2PLUS |CK_AM35XX |CK_36XX ),CLK (NULL ,"cam_mclk" , &cam_mclk,CK_34XX |CK_36XX ),CLK (NULL ,"cam_ick" , &cam_ick,CK_34XX |CK_36XX ), CLK(NULL, "csi2_96m_fck", &csi2_96m_fck, CK_34XX | CK_36XX),
@@ -3393,6 +3412,7 @@ static struct omap_clk omap3xxx_clks[] = {CLK (NULL ,"wkup_l4_ick" , &wkup_l4_ick,CK_34XX |CK_36XX ),CLK (NULL ,"usim_ick" , &usim_ick,CK_3430ES2PLUS |CK_36XX ),CLK ("omap_wdt" ,"ick" , &wdt2_ick,CK_3XXX ), +CLK (NULL ,"wdt2_ick" , &wdt2_ick,CK_3XXX ),CLK (NULL ,"wdt1_ick" , &wdt1_ick,CK_3XXX ),CLK (NULL ,"gpio1_ick" , &gpio1_ick,CK_3XXX ), CLK(NULL, "omap_32ksync_ick", &omap_32ksync_ick, CK_3XXX),
@@ -3438,6 +3458,9 @@ static struct omap_clk omap3xxx_clks[] = {CLK ("omap-mcbsp.2" ,"ick" , &mcbsp2_ick,CK_3XXX ),CLK ("omap-mcbsp.3" ,"ick" , &mcbsp3_ick,CK_3XXX ),CLK ("omap-mcbsp.4" ,"ick" , &mcbsp4_ick,CK_3XXX ), +CLK (NULL ,"mcbsp4_ick" , &mcbsp2_ick,CK_3XXX ), +CLK (NULL ,"mcbsp3_ick" , &mcbsp3_ick,CK_3XXX ), +CLK (NULL ,"mcbsp2_ick" , &mcbsp4_ick,CK_3XXX ),CLK (NULL ,"mcbsp2_fck" , &mcbsp2_fck,CK_3XXX ),CLK (NULL ,"mcbsp3_fck" , &mcbsp3_fck,CK_3XXX ), CLK(NULL, "mcbsp4_fck", &mcbsp4_fck, CK_3XXX),
arch/arm/mach-omap2/clock44xx_data.c +6 -0
@@ -3156,6 +3156,7 @@ static struct omap_clk omap44xx_clks[] = {CLK (NULL ,"dss_tv_clk" , &dss_tv_clk,CK_443X ),CLK (NULL ,"dss_48mhz_clk" , &dss_48mhz_clk,CK_443X ),CLK (NULL ,"dss_dss_clk" , &dss_dss_clk,CK_443X ), +CLK (NULL ,"dss_fck" , &dss_fck,CK_443X ),CLK ("omapdss_dss" ,"ick" , &dss_fck,CK_443X ),CLK (NULL ,"efuse_ctrl_cust_fck" , &efuse_ctrl_cust_fck,CK_443X ), CLK(NULL, "emif1_fck", &emif1_fck, CK_443X),
@@ -3212,6 +3213,7 @@ static struct omap_clk omap44xx_clks[] = {CLK (NULL ,"ocp2scp_usb_phy_phy_48m" , &ocp2scp_usb_phy_phy_48m,CK_443X ),CLK (NULL ,"ocp2scp_usb_phy_ick" , &ocp2scp_usb_phy_ick,CK_443X ),CLK (NULL ,"ocp_wp_noc_ick" , &ocp_wp_noc_ick,CK_443X ), +CLK (NULL ,"rng_ick" , &rng_ick,CK_443X ),CLK ("omap_rng" ,"ick" , &rng_ick,CK_443X ),CLK (NULL ,"sha2md5_fck" , &sha2md5_fck,CK_443X ), CLK(NULL, "sl2if_ick", &sl2if_ick, CK_443X),
@@ -3243,6 +3245,7 @@ static struct omap_clk omap44xx_clks[] = {CLK (NULL ,"uart3_fck" , &uart3_fck,CK_443X ),CLK (NULL ,"uart4_fck" , &uart4_fck,CK_443X ),CLK ("usbhs_omap" ,"fs_fck" , &usb_host_fs_fck,CK_443X ), +CLK (NULL ,"usb_host_fs_fck" , &usb_host_fs_fck,CK_443X ),CLK (NULL ,"utmi_p1_gfclk" , &utmi_p1_gfclk,CK_443X ),CLK (NULL ,"usb_host_hs_utmi_p1_clk" , &usb_host_hs_utmi_p1_clk,CK_443X ), CLK(NULL, "utmi_p2_gfclk", &utmi_p2_gfclk, CK_443X),
@@ -3253,14 +3256,17 @@ static struct omap_clk omap44xx_clks[] = {CLK (NULL ,"usb_host_hs_hsic60m_p2_clk" , &usb_host_hs_hsic60m_p2_clk,CK_443X ),CLK (NULL ,"usb_host_hs_hsic480m_p2_clk" , &usb_host_hs_hsic480m_p2_clk,CK_443X ),CLK (NULL ,"usb_host_hs_func48mclk" , &usb_host_hs_func48mclk,CK_443X ), +CLK (NULL ,"usb_host_hs_fck" , &usb_host_hs_fck,CK_443X ),CLK ("usbhs_omap" ,"hs_fck" , &usb_host_hs_fck,CK_443X ),CLK (NULL ,"otg_60m_gfclk" , &otg_60m_gfclk,CK_443X ),CLK (NULL ,"usb_otg_hs_xclk" , &usb_otg_hs_xclk,CK_443X ), +CLK (NULL ,"usb_otg_hs_ick" , &usb_otg_hs_ick,CK_443X ),CLK ("musb-omap2430" ,"ick" , &usb_otg_hs_ick,CK_443X ),CLK (NULL ,"usb_phy_cm_clk32k" , &usb_phy_cm_clk32k,CK_443X ),CLK (NULL ,"usb_tll_hs_usb_ch2_clk" , &usb_tll_hs_usb_ch2_clk,CK_443X ),CLK (NULL ,"usb_tll_hs_usb_ch0_clk" , &usb_tll_hs_usb_ch0_clk,CK_443X ),CLK (NULL ,"usb_tll_hs_usb_ch1_clk" , &usb_tll_hs_usb_ch1_clk,CK_443X ), +CLK (NULL ,"usb_tll_hs_ick" , &usb_tll_hs_ick,CK_443X ),CLK ("usbhs_omap" ,"usbtll_ick" , &usb_tll_hs_ick,CK_443X ),CLK (NULL ,"usim_ck" , &usim_ck,CK_443X ), CLK(NULL, "usim_fclk", &usim_fclk, CK_443X),
arch/arm/mach-omap2/omap_hwmod.c +6 -6
@@ -677,8 +677,8 @@ static int _init_main_clk(struct omap_hwmod *oh)if (!oh->main_clk)return 0 ; - oh->_clk =omap_clk_get_by_name (oh->main_clk); -if (!oh->_clk) { + oh->_clk =clk_get (NULL , oh->main_clk); +if (IS_ERR_OR_NULL (oh->_clk)) {pr_warning ("omap_hwmod: %s: cannot clk_get main_clk %s\n" , oh->name, oh->main_clk);return -EINVAL ;
@@ -722,8 +722,8 @@ static int _init_interface_clks(struct omap_hwmod *oh)if (!os->clk)continue ; - c =omap_clk_get_by_name (os->clk); -if (!c) { + c =clk_get (NULL , os->clk); +if (IS_ERR_OR_NULL (c)) {pr_warning ("omap_hwmod: %s: cannot clk_get interface_clk %s\n" , oh->name, os->clk); ret = -EINVAL ;
@@ -758,8 +758,8 @@ static int _init_opt_clks(struct omap_hwmod *oh)int ret =0 ;for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i >0 ; i--, oc++) { - c =omap_clk_get_by_name (oc->clk); -if (!c) { + c =clk_get (NULL , oc->clk); +if (IS_ERR_OR_NULL (c)) {pr_warning ("omap_hwmod: %s: cannot clk_get opt_clk %s\n" , oh->name, oc->clk); ret = -EINVAL ;
arch/arm/plat-omap/clock.c +0 -27
@@ -312,33 +312,6 @@ void clk_enable_init_clocks(void) } } -/** -* omap_clk_get_by_name - locate OMAP struct clk by its name -* @name: name of the struct clk to locate -* -* Locate an OMAP struct clk by its name. Assumes that struct clk -* names are unique. Returns NULL if not found or a pointer to the -* struct clk if found. -*/ -struct clk *omap_clk_get_by_name (const char *name) -{ -struct clk *c; -struct clk *ret =NULL ; - -mutex_lock (&clocks_mutex); - -list_for_each_entry (c, &clocks, node) { -if (!strcmp (c->name, name)) { - ret = c; -break ; - } - } - -mutex_unlock (&clocks_mutex); - -return ret; -} -int omap_clk_enable_autoidle_all (void ) {struct clk *c;
arch/arm/plat-omap/omap_device.c +3 -3
@@ -266,10 +266,10 @@ static void _add_clkdev(struct omap_device *od, const char *clk_alias,return ; } - r =omap_clk_get_by_name (clk_name); -if (IS_ERR (r)) { + r =clk_get (NULL , clk_name); +if (IS_ERR_OR_NULL (r)) {dev_err (&od->pdev->dev, -"omap_clk_get_by_name for %s failed\n" , clk_name); +"clk_get for %s failed\n" , clk_name);return ; }
Signature · 1 line
1.7.9.5
PATCH v4 2/3 ARM: omap: hwmod: get rid of all omap_clk_get_by_name usage
Quoted 6 lines · Rajendra Nayak
Moving to Common clk framework for OMAP would mean we no longer use internal lookup mechanism like
omap_clk_get_by_name(). get rid of all its usage mostly from hwmod andomap_devicecode.Also use
IS_ERR_OR_NULL()for error checking.
This is wrong. IS_ERR() is the only check you should ever use with clk_get().
PATCH v4 2/3 ARM: omap: hwmod: get rid of all omap_clk_get_by_name usage
Quoted 9 lines · Russell King - ARM Linux
Quoted 6 lines · Rajendra Nayak
Moving to Common clk framework for OMAP would mean we no longer use internal lookup mechanism like
omap_clk_get_by_name(). get rid of all its usage mostly from hwmod andomap_devicecode.Also use
IS_ERR_OR_NULL()for error checking.This is wrong.
IS_ERR()is the only check you should ever use withclk_get().
okay, thanks, will fix.
PATCH v4 2/3 ARM: omap: hwmod: get rid of all omap_clk_get_by_name usage
In reply to Rajendra Nayakarch/arm/mach-omap2/clock44xx_data.c static struct omap_clk omap44xx_clks[] = { · line 3160
Quoted 10 lines · Rajendra Nayak
arch/arm/mach-omap2/clock44xx_data.c +1
-0@@ -3156,6 +3156,7 @@ static struct omap_clk omap44xx_clks[] = {CLK (NULL ,"dss_tv_clk" , &dss_tv_clk,CK_443X ),CLK (NULL ,"dss_48mhz_clk" , &dss_48mhz_clk,CK_443X ),CLK (NULL ,"dss_dss_clk" , &dss_dss_clk,CK_443X ), +CLK (NULL ,"dss_fck" , &dss_fck,CK_443X ), CLK("omapdss_dss", "ick", &dss_fck, CK_443X),
Is it right to re-use dss_fck for the "ick" here? I think it is due to omap4 modulemode stuff but I don't have DM in front of me and wanted a double-check...
Regards,
Mike
PATCH v4 2/3 ARM: omap: hwmod: get rid of all omap_clk_get_by_name usage
Quoted 15 lines · Mike
arch/arm/mach-omap2/clock44xx_data.c static struct omap_clk omap44xx_clks[] = { · line 3160
Quoted 10 lines · Rajendra Nayak
arch/arm/mach-omap2/clock44xx_data.c +1
-0@@ -3156,6 +3156,7 @@ static struct omap_clk omap44xx_clks[] = {CLK (NULL ,"dss_tv_clk" ,&dss_tv_clk,CK_443X ),CLK (NULL ,"dss_48mhz_clk" ,&dss_48mhz_clk,CK_443X ),CLK (NULL ,"dss_dss_clk" ,&dss_dss_clk,CK_443X ), +CLK (NULL ,"dss_fck" ,&dss_fck,CK_443X ), CLK("omapdss_dss", "ick",&dss_fck, CK_443X),Is it right to re-use
dss_fckfor the "ick" here? I think it is due to omap4 modulemode stuff but I don't have DM in front of me and wanted a double-check...
yes, its because of the wierdness of DSS clocks where a so-called optional clock is actually a function clock.
Quoted 3 lines
Regards,
Mike
PATCH v4 2/3 ARM: omap: hwmod: get rid of all omap_clk_get_by_name usage
Quoted 18 lines · Rajendra Nayak
Quoted 16 lines · Mike
arch/arm/mach-omap2/clock44xx_data.c static struct omap_clk omap44xx_clks[] = { · line 3160
Quoted 11 lines · Rajendra Nayak
arch/arm/mach-omap2/clock44xx_data.c +1
-0@@ -3156,6 +3156,7 @@ static struct omap_clk omap44xx_clks[] = {CLK (NULL ,"dss_tv_clk" ,&dss_tv_clk,CK_443X ),CLK (NULL ,"dss_48mhz_clk" ,&dss_48mhz_clk,CK_443X ),CLK (NULL ,"dss_dss_clk" ,&dss_dss_clk,CK_443X ), +CLK (NULL ,"dss_fck" ,&dss_fck,CK_443X ), CLK("omapdss_dss", "ick",&dss_fck, CK_443X),Is it right to re-use
dss_fckfor the "ick" here? I think it is due to omap4 modulemode stuff but I don't have DM in front of me and wanted a double-check...
Quoted 2 lines
yes, its because of the wierdness of DSS clocks where a so-called optional clock is actually a function clock.
Not only, it is a hack to allow the DSS to be enabled whenever a DSS submodule has to be enabled. Since they are sharing the ick, it will enable the modulemode when the DISPC will be enabled.
That hack should disappear as soon as the DSS will be able to handle the PM dependency between DSS submodules and the DSS itself using pm_runtime parent/child link.
And then we will have to remove this fake ick modulemode clock node and let hwmod handle that properly.
Tomi already cleaned the DSS part, I guess it should be upstreamed soon, if this is not already the case.
Regards,
Benoit
PATCH v4 2/3 ARM: omap: hwmod: get rid of all omap_clk_get_by_name usage
Quoted 26 lines · Benoit Cousson
Quoted 18 lines · Rajendra Nayak
Quoted 16 lines · Mike
arch/arm/mach-omap2/clock44xx_data.c static struct omap_clk omap44xx_clks[] = { · line 3160
Quoted 11 lines · Rajendra Nayak
arch/arm/mach-omap2/clock44xx_data.c +1
-0@@ -3156,6 +3156,7 @@ static struct omap_clk omap44xx_clks[] = {CLK (NULL ,"dss_tv_clk" ,&dss_tv_clk,CK_443X ),CLK (NULL ,"dss_48mhz_clk" ,&dss_48mhz_clk,CK_443X ),CLK (NULL ,"dss_dss_clk" ,&dss_dss_clk,CK_443X ), +CLK (NULL ,"dss_fck" ,&dss_fck,CK_443X ), CLK("omapdss_dss", "ick",&dss_fck, CK_443X),Is it right to re-use
dss_fckfor the "ick" here? I think it is due to omap4 modulemode stuff but I don't have DM in front of me and wanted a double-check...Quoted 2 lines
yes, its because of the wierdness of DSS clocks where a so-called optional clock is actually a function clock.
Not only, it is a hack to allow the DSS to be enabled whenever a DSS submodule has to be enabled. Since they are sharing the ick, it will enable the modulemode when the DISPC will be enabled.
Quoted 8 lines
That hack should disappear as soon as the DSS will be able to handle the PM dependency between DSS submodules and the DSS itself using
pm_runtimeparent/child link.
And then we will have to remove this fake ick modulemode clock node and let hwmod handle that properly.Tomi already cleaned the DSS part, I guess it should be upstreamed soon, if this is not already the case.
This is in 3.5. omapdss_dss is now the parent for the rest of the dss submodules, and runtime PM is being used.
I think we should now revisit this dss clock handling to see if there are any other changes required in the omapdss side, but I hope they are already according to our discussions and correct.
Tomi
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PATCH v4 2/3 ARM: omap: hwmod: get rid of all omap_clk_get_by_name usage
Quoted 36 lines · Tomi Valkeinen
Quoted 26 lines · Benoit Cousson
Quoted 18 lines · Rajendra Nayak
Quoted 16 lines · Mike
arch/arm/mach-omap2/clock44xx_data.c static struct omap_clk omap44xx_clks[] = { · line 3160
Quoted 11 lines · Rajendra Nayak
arch/arm/mach-omap2/clock44xx_data.c +1
-0@@ -3156,6 +3156,7 @@ static struct omap_clk omap44xx_clks[] = {CLK (NULL ,"dss_tv_clk" ,&dss_tv_clk,CK_443X ),CLK (NULL ,"dss_48mhz_clk" ,&dss_48mhz_clk,CK_443X ),CLK (NULL ,"dss_dss_clk" ,&dss_dss_clk,CK_443X ), +CLK (NULL ,"dss_fck" ,&dss_fck,CK_443X ), CLK("omapdss_dss", "ick",&dss_fck, CK_443X),Is it right to re-use
dss_fckfor the "ick" here? I think it is due to omap4 modulemode stuff but I don't have DM in front of me and wanted a double-check...Quoted 2 lines
yes, its because of the wierdness of DSS clocks where a so-called optional clock is actually a function clock.
Not only, it is a hack to allow the DSS to be enabled whenever a DSS submodule has to be enabled. Since they are sharing the ick, it will enable the modulemode when the DISPC will be enabled.
Quoted 8 lines
That hack should disappear as soon as the DSS will be able to handle the PM dependency between DSS submodules and the DSS itself using
pm_runtimeparent/child link.
And then we will have to remove this fake ick modulemode clock node and let hwmod handle that properly.Tomi already cleaned the DSS part, I guess it should be upstreamed soon, if this is not already the case.
Quoted 6 lines
This is in 3.5.
omapdss_dssis now the parent for the rest of the dss submodules, and runtime PM is being used.I think we should now revisit this dss clock handling to see if there are any other changes required in the omapdss side, but I hope they are already according to our discussions and correct.
The only little problem was that during bootup, when hwmods are setup, only the 'parent' hwmod was able to get reset properly, all the other 'child' hwmods don't have modulemode bits tied to them, and hence weren't able to reset. So we got some error prints.
Once DSS driver kicks in, the driver ensures the parent is enabled for any child to be enabled, so we don't face the issue again.
So, if DSS driver is not built in, and if the bootloader left DSS in a bad state, the DSS clocks might remain messed up all the time since hwmod fwk wasn't able to reset them.
I think this is why we didn't proceed with remove "dss_fck" as a slave clock. If this issue is minor, we could go ahead and remove it.
Archit
PATCH v4 2/3 ARM: omap: hwmod: get rid of all omap_clk_get_by_name usage
Quoted 8 lines · Archit Taneja
The only little problem was that during bootup, when hwmods are setup, only the 'parent' hwmod was able to get reset properly, all the other 'child' hwmods don't have modulemode bits tied to them, and hence weren't able to reset. So we got some error prints.
Once DSS driver kicks in, the driver ensures the parent is enabled for any child to be enabled, so we don't face the issue again.
Quoted 6 lines
So, if DSS driver is not built in, and if the bootloader left DSS in a bad state, the DSS clocks might remain messed up all the time since hwmod fwk wasn't able to reset them.
I think this is why we didn't proceed with remove "
dss_fck" as a slave clock. If this issue is minor, we could go ahead and remove it.
I wonder if we could handle this with a custom reset function. We already have a reset func for dss core. If I remember right, the main point for that is the fact that omap4 doesn't have a softreset for dss core, so we manually write the default values to registers.
For omap2/3 this would be simple: skip the resets for all other dss submodules, and dss core's reset would enable all the clocks and set the softreset bit. This would reset all the submodules also.
Omap4 is more tricky. I guess we'd need to enable all the clocks, clear manually dss core's registers, and then set softreset bits in all the submodules. So in this case dss core would need to have information about the other submodules.
Tomi
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PATCH v4 2/3 ARM: omap: hwmod: get rid of all omap_clk_get_by_name usage
Quoted 22 lines · Tomi Valkeinen
Quoted 8 lines · Archit Taneja
The only little problem was that during bootup, when hwmods are setup, only the 'parent' hwmod was able to get reset properly, all the other 'child' hwmods don't have modulemode bits tied to them, and hence weren't able to reset. So we got some error prints.
Once DSS driver kicks in, the driver ensures the parent is enabled for any child to be enabled, so we don't face the issue again.
Quoted 6 lines
So, if DSS driver is not built in, and if the bootloader left DSS in a bad state, the DSS clocks might remain messed up all the time since hwmod fwk wasn't able to reset them.
I think this is why we didn't proceed with remove "
dss_fck" as a slave clock. If this issue is minor, we could go ahead and remove it.I wonder if we could handle this with a custom reset function. We already have a reset func for dss core. If I remember right, the main point for that is the fact that omap4 doesn't have a softreset for dss core, so we manually write the default values to registers.
Quoted 8 lines
For omap2/3 this would be simple: skip the resets for all other dss submodules, and dss core's reset would enable all the clocks and set the softreset bit. This would reset all the submodules also.
Omap4 is more tricky. I guess we'd need to enable all the clocks, clear manually dss core's registers, and then set softreset bits in all the submodules. So in this case dss core would need to have information about the other submodules.
The is a good idea. I don't clearly understand your approach though. Are you saying we have a custom reset function for only dss core? And reset the submodules in it manually?
An alternative approach would be to implement custom reset functions for each submodule(or each hwmod), and in the beginning of every reset function, add a hack to enable MODULEMODE bits(since we don't want hwmod fwk to touch MODULEMODE for the DSS submodules), and then set the soft reset bits.
Your approach would ensure that we get a clean reset of DSS, but it would still give the annoying prints when each of the submodule tries to reset itself.
Archit
PATCH v4 2/3 ARM: omap: hwmod: get rid of all omap_clk_get_by_name usage
Quoted 27 lines · Archit Taneja
Quoted 26 lines · Tomi Valkeinen
Quoted 8 lines · Archit Taneja
The only little problem was that during bootup, when hwmods are setup, only the 'parent' hwmod was able to get reset properly, all the other 'child' hwmods don't have modulemode bits tied to them, and hence weren't able to reset. So we got some error prints.
Once DSS driver kicks in, the driver ensures the parent is enabled for any child to be enabled, so we don't face the issue again.
Quoted 6 lines
So, if DSS driver is not built in, and if the bootloader left DSS in a bad state, the DSS clocks might remain messed up all the time since hwmod fwk wasn't able to reset them.
I think this is why we didn't proceed with remove "
dss_fck" as a slave clock. If this issue is minor, we could go ahead and remove it.I wonder if we could handle this with a custom reset function. We already have a reset func for dss core. If I remember right, the main point for that is the fact that omap4 doesn't have a softreset for dss core, so we manually write the default values to registers.
For omap2/3 this would be simple: skip the resets for all other dss submodules, and dss core's reset would enable all the clocks and set the softreset bit. This would reset all the submodules also.
Quoted 8 lines
Quoted 4 lines
Omap4 is more tricky. I guess we'd need to enable all the clocks, clear manually dss core's registers, and then set softreset bits in all the submodules. So in this case dss core would need to have information about the other submodules.
The is a good idea. I don't clearly understand your approach though. Are you saying we have a custom reset function for only dss core? And reset the submodules in it manually?
Yes.
Quoted 5 lines
An alternative approach would be to implement custom reset functions for each submodule(or each hwmod), and in the beginning of every reset function, add a hack to enable MODULEMODE bits(since we don't want hwmod fwk to touch MODULEMODE for the DSS submodules), and then set the soft reset bits.
I thought about that also. We'd need reset functions for all of them, and for omap2/3 we'd just reset the submodules again as they have already been reset with the dss core reset.
The dss submodule resets are a bit linked. For omap2/3 the connection is obvious as dss core reset resets also the submodules, and for omap4 we have this requirement for the modulemode. That's why I though it'd be perhaps cleaner to handle the reset of the DSS block as a whole, in one place.
Quoted 3 lines
Your approach would ensure that we get a clean reset of DSS, but it would still give the annoying prints when each of the submodule tries to reset itself.
The other submodules would not be reset by the hwmod framework at all, so there wouldn't be prints. I think there's a flag for that.
Tomi
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PATCH v4 2/3 ARM: omap: hwmod: get rid of all omap_clk_get_by_name usage
Quoted 55 lines · Tomi Valkeinen
Quoted 27 lines · Archit Taneja
Quoted 26 lines · Tomi Valkeinen
Quoted 8 lines · Archit Taneja
The only little problem was that during bootup, when hwmods are setup, only the 'parent' hwmod was able to get reset properly, all the other 'child' hwmods don't have modulemode bits tied to them, and hence weren't able to reset. So we got some error prints.
Once DSS driver kicks in, the driver ensures the parent is enabled for any child to be enabled, so we don't face the issue again.
Quoted 6 lines
So, if DSS driver is not built in, and if the bootloader left DSS in a bad state, the DSS clocks might remain messed up all the time since hwmod fwk wasn't able to reset them.
I think this is why we didn't proceed with remove "
dss_fck" as a slave clock. If this issue is minor, we could go ahead and remove it.I wonder if we could handle this with a custom reset function. We already have a reset func for dss core. If I remember right, the main point for that is the fact that omap4 doesn't have a softreset for dss core, so we manually write the default values to registers.
For omap2/3 this would be simple: skip the resets for all other dss submodules, and dss core's reset would enable all the clocks and set the softreset bit. This would reset all the submodules also.
Quoted 8 lines
Quoted 4 lines
Omap4 is more tricky. I guess we'd need to enable all the clocks, clear manually dss core's registers, and then set softreset bits in all the submodules. So in this case dss core would need to have information about the other submodules.
The is a good idea. I don't clearly understand your approach though. Are you saying we have a custom reset function for only dss core? And reset the submodules in it manually?
Yes.
Quoted 5 lines
An alternative approach would be to implement custom reset functions for each submodule(or each hwmod), and in the beginning of every reset function, add a hack to enable MODULEMODE bits(since we don't want hwmod fwk to touch MODULEMODE for the DSS submodules), and then set the soft reset bits.
I thought about that also. We'd need reset functions for all of them, and for omap2/3 we'd just reset the submodules again as they have already been reset with the dss core reset.
The dss submodule resets are a bit linked. For omap2/3 the connection is obvious as dss core reset resets also the submodules, and for omap4 we have this requirement for the modulemode. That's why I though it'd be perhaps cleaner to handle the reset of the DSS block as a whole, in one place.
Quoted 6 lines
Quoted 3 lines
Your approach would ensure that we get a clean reset of DSS, but it would still give the annoying prints when each of the submodule tries to reset itself.
The other submodules would not be reset by the hwmod framework at all, so there wouldn't be prints. I think there's a flag for that.
Oh, yeah. I didn't think of it that way, we could just 'not reset' the DSS submodule hwmod using this flag.
If we do that, then your approach sounds good.
Archit
OMAP4 clock/pm fixes [was: [PATCH v4 2/3] ARM: omap: hwmod: get rid of all omap_clk_get_by_name usage
Hi,
Quoted 57 lines · Archit Taneja
Quoted 56 lines · Tomi Valkeinen
Quoted 28 lines · Archit Taneja
Quoted 27 lines · Tomi Valkeinen
Quoted 8 lines · Archit Taneja
The only little problem was that during bootup, when hwmods are setup, only the 'parent' hwmod was able to get reset properly, all the other 'child' hwmods don't have modulemode bits tied to them, and hence weren't able to reset. So we got some error prints.
Once DSS driver kicks in, the driver ensures the parent is enabled for any child to be enabled, so we don't face the issue again.
Quoted 6 lines
So, if DSS driver is not built in, and if the bootloader left DSS in a bad state, the DSS clocks might remain messed up all the time since hwmod fwk wasn't able to reset them.
I think this is why we didn't proceed with remove "
dss_fck" as a slave clock. If this issue is minor, we could go ahead and remove it.I wonder if we could handle this with a custom reset function. We already have a reset func for dss core. If I remember right, the main point for that is the fact that omap4 doesn't have a softreset for dss core, so we manually write the default values to registers.
For omap2/3 this would be simple: skip the resets for all other dss submodules, and dss core's reset would enable all the clocks and set the
softreset bit. This would reset all the submodules also.Quoted 8 lines
Quoted 4 lines
Omap4 is more tricky. I guess we'd need to enable all the clocks, clear manually dss core's registers, and then set softreset bits in all the submodules. So in this case dss core would need to have information about the other submodules.
The is a good idea. I don't clearly understand your approach though. Are you saying we have a custom reset function for only dss core? And reset the submodules in it manually?
Yes.
Quoted 5 lines
An alternative approach would be to implement custom reset functions for each submodule(or each hwmod), and in the beginning of every reset function, add a hack to enable MODULEMODE bits(since we don't want hwmod fwk to touch MODULEMODE for the DSS submodules), and then set the soft reset bits.
I thought about that also. We'd need reset functions for all of them, and for omap2/3 we'd just reset the submodules again as they have already been reset with the dss core reset.
The dss submodule resets are a bit linked. For omap2/3 the connection is obvious as dss core reset resets also the submodules, and for omap4 we have this requirement for the modulemode. That's why I though it'd be perhaps cleaner to handle the reset of the DSS block as a whole, in one place.
Quoted 6 lines
Quoted 6 lines
Quoted 3 lines
Your approach would ensure that we get a clean reset of DSS, but it would still give the annoying prints when each of the submodule tries to reset itself.
The other submodules would not be reset by the hwmod framework at all, so there wouldn't be prints. I think there's a flag for that.
Sorry for bringing up an old thread. I was working on cleaning up the OMAP4 DSS related clock/pm issues, hence brought it up.
We were discussing here on how to setting up and reset the OMAP4 DSS submodules correctly without tying the MODULEMODE bits to the corresponding hwmods.
Tomi, your suggestion was to do soft resets for the submodules manually in the dss_core hwmod's custom reset function itself, and use the flag HWMOD_INIT_NO_RESET to prevent _reset() being called.
However, this won't still resolve the issue of the errors we see a bootup. The function _setup_reset() looks like this:
static int _setup_reset(struct omap_hwmod *oh)
{
...
r = _enable(oh);
if (r) {
pr_warning("omap_hwmod: %s: cannot be enabled for
reset (%d)\n", oh->name, oh->_state);
return -EINVAL;
}
...
if (!(oh->flags & HWMOD_INIT_NO_RESET))
r = _reset(oh);
...
}So, even if we have ask hwmod not to reset the DSS submodules, it will still try to enable them, and we can't enable them since MODULEMODE isn't tied to them. I don't see how we can get a clean reset done for the DSS submodules without making some changes in hwmod framework.
Archit
OMAP4 clock/pm fixes [was: [PATCH v4 2/3] ARM: omap: hwmod: get rid of all omap_clk_get_by_name usage
Hi Archit,
Quoted 79 lines · Archit Taneja
Hi,
Quoted 65 lines · Archit Taneja
Quoted 64 lines · Tomi Valkeinen
Quoted 38 lines · Archit Taneja
Quoted 31 lines · Tomi Valkeinen
Quoted 10 lines · Archit Taneja
The only little problem was that during bootup, when hwmods are setup,
only the 'parent' hwmod was able to get reset properly, all the other 'child' hwmods don't have modulemode bits tied to them, and hence weren't able to reset. So we got some error prints.Once DSS driver kicks in, the driver ensures the parent is enabled for
any child to be enabled, so we don't face the issue again.Quoted 8 lines
So, if DSS driver is not built in, and if the bootloader left DSS in a
bad state, the DSS clocks might remain messed up all the time since hwmod fwk wasn't able to reset them.I think this is why we didn't proceed with remove "
dss_fck" as a slave
clock. If this issue is minor, we could go ahead and remove it.I wonder if we could handle this with a custom reset function. We already have a reset func for dss core. If I remember right, the main point for that is the fact that omap 4 doesn't have a softreset for dss core, so we manually write the default values to registers.
For omap2/3 this would be simple: skip the resets for all other dss submodules, and dss core's reset would enable all the clocks and set the
softreset bit. This would reset all the submodules also.Quoted 5 lines
Omap4 is more tricky. I guess we'd need to enable all the clocks, clear
manually dss core's registers, and then set softreset bits in all the submodules. So in this case dss core would need to have information about the other submodules.Quoted 4 lines
The is a good idea. I don't clearly understand your approach though. Are
you saying we have a custom reset function for only dss core? And reset the submodules in it manually?Yes.
Quoted 7 lines
An alternative approach would be to implement custom reset functions for
each submodule(or each hwmod), and in the beginning of every reset function, add a hack to enable MODULEMODE bits(since we don't want hwmod
fwk to touch MODULEMODE for the DSS submodules), and then set the soft reset bits.I thought about that also. We'd need reset functions for all of them, and for omap2/3 we'd just reset the submodules again as they have already been reset with the dss core reset.
The dss submodule resets are a bit linked. For omap2/3 the connection is obvious as dss core reset resets also the submodules, and for omap4 we have this requirement for the modulemode. That's why I though it'd be perhaps cleaner to handle the reset of the DSS block as a whole, in one place.
Quoted 7 lines
Quoted 7 lines
Quoted 4 lines
Your approach would ensure that we get a clean reset of DSS, but it would still give the annoying prints when each of the submodule tries to
reset itself.The other submodules would not be reset by the hwmod framework at all, so there wouldn't be prints. I think there's a flag for that.
Sorry for bringing up an old thread. I was working on cleaning up the OMAP4 DSS related clock/pm issues, hence brought it up.
Quoted 7 lines
We were discussing here on how to setting up and reset the OMAP4 DSS submodules correctly without tying the MODULEMODE bits to the corresponding hwmods.
Tomi, your suggestion was to do soft resets for the submodules manually in the
dss_corehwmod's custom reset function itself, and use the flagHWMOD_INIT_NO_RESETto prevent_reset()being called.
Yep, that's the right approach.
Quoted 20 lines
However, this won't still resolve the issue of the errors we see a bootup. The function
_setup_reset()looks like this:static int
_setup_reset(struct omap_hwmod *oh){ ... r = _enable(oh); if (r) { pr_warning("omap_hwmod: %s: cannot be enabled for reset (%d)\n", oh->name, oh->_state); return -EINVAL; } ... if (!(oh->flags & HWMOD_INIT_NO_RESET)) r = _reset(oh); ... }
Quoted 4 lines
So, even if we have ask hwmod not to reset the DSS submodules, it will still try to enable them, and we can't enable them since MODULEMODE isn't tied to them. I don't see how we can get a clean reset done for the DSS submodules without making some changes in hwmod framework.
Yeah, I do agree. Some module cannot but enabled automatically in the fmwk due to PM dependency. This is the case as well for MCPDM, IPU, DSP, ISS, FDIF...
In that case the early setup should just be skipped and the DSS driver should take care of that during probe / pm_runtime_enable.
I already have a WIP series that delay the setup until the driver probe the device. It will allow the setup to work properly in the case of the DSS assuming the DISPC and other sub IPs are setup in the context of DSS probe. At that time the DSS will be enabled already and thus every sub IPs will be able to get enabled.
It is done in the context of DT boot, but should work as well for legacy boot.
I can share the current crappy patches as soon as I fixed a couple of regression introduced by the patches :-(
Regards,
Benoit
OMAP4 clock/pm fixes [was: [PATCH v4 2/3] ARM: omap: hwmod: get rid of all omap_clk_get_by_name usage
Quoted 120 lines · Benoit Cousson
Hi Archit,
Quoted 79 lines · Archit Taneja
Hi,
Quoted 65 lines · Archit Taneja
Quoted 64 lines · Tomi Valkeinen
Quoted 38 lines · Archit Taneja
Quoted 31 lines · Tomi Valkeinen
Quoted 10 lines · Archit Taneja
The only little problem was that during bootup, when hwmods are setup,
only the 'parent' hwmod was able to get reset properly, all the other 'child' hwmods don't have modulemode bits tied to them, and hence weren't able to reset. So we got some error prints.Once DSS driver kicks in, the driver ensures the parent is enabled for
any child to be enabled, so we don't face the issue again.Quoted 8 lines
So, if DSS driver is not built in, and if the bootloader left DSS in a
bad state, the DSS clocks might remain messed up all the time since hwmod fwk wasn't able to reset them.I think this is why we didn't proceed with remove "
dss_fck" as a slave
clock. If this issue is minor, we could go ahead and remove it.I wonder if we could handle this with a custom reset function. We already have a reset func for dss core. If I remember right, the main point for that is the fact that omap 4 doesn't have a softreset for dss core, so we manually write the default values to registers.
For omap2/3 this would be simple: skip the resets for all other dss submodules, and dss core's reset would enable all the clocks and set the
softreset bit. This would reset all the submodules also.Quoted 5 lines
Omap4 is more tricky. I guess we'd need to enable all the clocks, clear
manually dss core's registers, and then set softreset bits in all the submodules. So in this case dss core would need to have information about the other submodules.Quoted 4 lines
The is a good idea. I don't clearly understand your approach though. Are
you saying we have a custom reset function for only dss core? And reset the submodules in it manually?Yes.
Quoted 7 lines
An alternative approach would be to implement custom reset functions for
each submodule(or each hwmod), and in the beginning of every reset function, add a hack to enable MODULEMODE bits(since we don't want hwmod
fwk to touch MODULEMODE for the DSS submodules), and then set the soft reset bits.I thought about that also. We'd need reset functions for all of them, and for omap2/3 we'd just reset the submodules again as they have already been reset with the dss core reset.
The dss submodule resets are a bit linked. For omap2/3 the connection is obvious as dss core reset resets also the submodules, and for omap4 we have this requirement for the modulemode. That's why I though it'd be perhaps cleaner to handle the reset of the DSS block as a whole, in one place.
Quoted 7 lines
Quoted 7 lines
Quoted 4 lines
Your approach would ensure that we get a clean reset of DSS, but it would still give the annoying prints when each of the submodule tries to
reset itself.The other submodules would not be reset by the hwmod framework at all, so there wouldn't be prints. I think there's a flag for that.
Sorry for bringing up an old thread. I was working on cleaning up the OMAP4 DSS related clock/pm issues, hence brought it up.
Quoted 7 lines
We were discussing here on how to setting up and reset the OMAP4 DSS submodules correctly without tying the MODULEMODE bits to the corresponding hwmods.
Tomi, your suggestion was to do soft resets for the submodules manually in the
dss_corehwmod's custom reset function itself, and use the flagHWMOD_INIT_NO_RESETto prevent_reset()being called.Yep, that's the right approach.
Quoted 20 lines
However, this won't still resolve the issue of the errors we see a bootup. The function
_setup_reset()looks like this:static int
_setup_reset(struct omap_hwmod *oh){ ... r = _enable(oh); if (r) { pr_warning("omap_hwmod: %s: cannot be enabled for reset (%d)\n", oh->name, oh->_state); return -EINVAL; } ... if (!(oh->flags & HWMOD_INIT_NO_RESET)) r = _reset(oh); ... }Quoted 4 lines
So, even if we have ask hwmod not to reset the DSS submodules, it will still try to enable them, and we can't enable them since MODULEMODE isn't tied to them. I don't see how we can get a clean reset done for the DSS submodules without making some changes in hwmod framework.
Yeah, I do agree. Some module cannot but enabled automatically in the fmwk due to PM dependency. This is the case as well for MCPDM, IPU, DSP, ISS, FDIF...
Quoted 6 lines
In that case the early setup should just be skipped and the DSS driver should take care of that during probe /
pm_runtime_enable.I already have a WIP series that delay the setup until the driver probe the device. It will allow the setup to work properly in the case of the DSS assuming the DISPC and other sub IPs are setup in the context of DSS probe. At that time the DSS will be enabled already and thus every sub IPs will be able to get enabled.
It is done in the context of DT boot, but should work as well for legacy boot.
I can share the current crappy patches as soon as I fixed a couple of regression introduced by the patches :-(
Ah, that will be great!
The other not so good option to make DSS PM work would be to add OCPIF_SWSUP_IDLE flag to our l3_main_2__dss_* slave interfaces(which have the hack "dss_fck" as slave clock). I gave this approach a try, that too isn't working so well. When I disable DSS, I get CM_DSS_DSS_CLKCTRL.IDLEST as 0x1, and CM_DSS_CLKSTCTRL.CLKACTIVITY_DSS_L3_ICLK is set. I wonder why that's happening.
Thanks,
Archit
OMAP4 clock/pm fixes [was: [PATCH v4 2/3] ARM: omap: hwmod: get rid of all omap_clk_get_by_name usage
Quoted 7 lines · Archit Taneja
The other not so good option to make DSS PM work would be to add
OCPIF_SWSUP_IDLEflag to our l3_main_2__dss_* slaveinterfaces(which have the hack "dss_fck" as slave clock). I gave this approach a try, that too isn't working so well. When I disable DSS, I get CM_DSS_DSS_CLKCTRL.IDLEST as0x1, and CM_DSS_CLKSTCTRL.CLKACTIVITY_DSS_L3_ICLK is set. I wonder why that's happening.
I have seen DSS get stuck in transition, with just a clkdm state toggle (from say HWSUP to SWWKUP) while its optional clocks are not running. Thats probably whats happening now.
Did you try keeping the modulemode enabled and see if it really gates DSS/system sleep. I remember testing with Teros CORE ret/off patches and I was always seeing DSS modulemode enabled but it wasn't gating sleep.
OMAP4 clock/pm fixes [was: [PATCH v4 2/3] ARM: omap: hwmod: get rid of all omap_clk_get_by_name usage
Quoted 9 lines · Rajendra Nayak
Quoted 7 lines · Archit Taneja
The other not so good option to make DSS PM work would be to add
OCPIF_SWSUP_IDLEflag to our l3_main_2__dss_* slaveinterfaces(which have the hack "dss_fck" as slave clock). I gave this approach a try, that too isn't working so well. When I disable DSS, I get CM_DSS_DSS_CLKCTRL.IDLEST as0x1, and CM_DSS_CLKSTCTRL.CLKACTIVITY_DSS_L3_ICLK is set. I wonder why that's happening.
Quoted 3 lines
I have seen DSS get stuck in transition, with just a clkdm state toggle (from say HWSUP to SWWKUP) while its optional clocks are not running. Thats probably whats happening now.
Oh ok, I can notice that too. So in the _idle() path, the clocks are disabled first, and then we try to change the clkdm state. I guess that could be the reason why DSS doesn't sleep.
But then, I don't understand why this problem isn't seen if I try the alternative option of removing the fake dss_fck slave clock, and tie modulemode to only the parent hwmod. There DSS IDLEST is 0x3 when I disable DSS.
I think with this approach, the problem is with _disable_clocks(), in disable_clocks, main_clk is disabled first, and then the slave clocks. That translates to DSS_FCK opt clock getting disabled first, and then MODULEMODE bits. I think DSS doesn't transition to sleep with this disable sequence.
Quoted 5 lines
Did you try keeping the modulemode enabled and see if it really gates DSS/system sleep. I remember testing with Teros CORE ret/off patches and I was always seeing DSS modulemode enabled but it wasn't gating sleep.
If the clkdm is in HW_AUTO, I can get DSS in sleep(STBYST and IDLEST all set). Is this helpful? Can we just leave modulemode on all the time? That'll be the best :)
Anyway, I guess it would be the best to have a custom _setup function(or skip them all together) for DSS as Benoit suggested.
Archit
OMAP4 clock/pm fixes [was: [PATCH v4 2/3] ARM: omap: hwmod: get rid of all omap_clk_get_by_name usage
Quoted 3 lines
If the clkdm is in
HW_AUTO, I can get DSS in sleep(STBYST and IDLEST all set). Is this helpful? Can we just leave modulemode on all the time? That'll be the best :)
Is everything around DSS enabled by default in omap2plus? If so, I haven't seen Tero (who has been working on getting OMAP4 to sleep) complain about DSS causing him any trouble. So you should be good with whats already there atleast from 'not-gating-sleep' point of view.
OMAP4 clock/pm fixes [was: [PATCH v4 2/3] ARM: omap: hwmod: get rid of all omap_clk_get_by_name usage
Quoted 9 lines · Rajendra Nayak
Quoted 3 lines
If the clkdm is in
HW_AUTO, I can get DSS in sleep(STBYST and IDLEST all set). Is this helpful? Can we just leave modulemode on all the time? That'll be the best :)Is everything around DSS enabled by default in omap2plus? If so, I haven't seen Tero (who has been working on getting OMAP4 to sleep) complain about DSS causing him any trouble. So you should be good with whats already there atleast from 'not-gating-sleep' point of view.
DSS is selected only as a module in omap2plus_defconfig, so the DSS driver would never kick in with the defconfig.
The DSS hwmods would be initialised though. If I boot up linux-next with omap2plus_defconfig, I get:
CM_DSS_CLKSTCTRL 0x3CM_DSS_DSS_CLKCTRL 0x00060002
So the module is in standby, but IDLEST is 0x2, which says DSS is idle only with respect to the interconnect. In the bootloader, IDLEST was 0x3. So I don't know if that's a good thing or not.
Archit
OMAP4 clock/pm fixes [was: [PATCH v4 2/3] ARM: omap: hwmod: get rid of all omap_clk_get_by_name usage
In reply to Archit TanejaQuoted 30 lines · Archit Taneja
Quoted 9 lines · Rajendra Nayak
Quoted 7 lines · Archit Taneja
The other not so good option to make DSS PM work would be to add
OCPIF_SWSUP_IDLEflag to our l3_main_2__dss_* slaveinterfaces(which have the hack "dss_fck" as slave clock). I gave this approach a try, that too isn't working so well. When I disable DSS, I get CM_DSS_DSS_CLKCTRL.IDLEST as0x1, and CM_DSS_CLKSTCTRL.CLKACTIVITY_DSS_L3_ICLK is set. I wonder why that's happening.Quoted 3 lines
I have seen DSS get stuck in transition, with just a clkdm state toggle (from say HWSUP to SWWKUP) while its optional clocks are not running. Thats probably whats happening now.
Oh ok, I can notice that too. So in the
_idle()path, the clocks are disabled first, and then we try to change the clkdm state. I guess that could be the reason why DSS doesn't sleep.But then, I don't understand why this problem isn't seen if I try the alternative option of removing the fake
dss_fckslave clock, and tie modulemode to only the parent hwmod. There DSS IDLEST is0x3when I disable DSS.I think with this approach, the problem is with
_disable_clocks(), indisable_clocks,main_clkis disabled first, and then the slave clocks. That translates toDSS_FCKopt clock getting disabled first, and then MODULEMODE bits. I think DSS doesn't transition to sleep with this disable sequence.Quoted 1 line
Quoted 8 lines
Quoted 4 lines
Did you try keeping the modulemode enabled and see if it really gates DSS/system sleep. I remember testing with Teros CORE ret/off patches and I was always seeing DSS modulemode enabled but it wasn't gating sleep.
If the clkdm is in
HW_AUTO, I can get DSS in sleep(STBYST and IDLEST all set). Is this helpful? Can we just leave modulemode on all the time? That'll be the best :)
Well, it is true that in the case of the DSS the modulemode is only managing the interface clock. And since the interface clock is doing autogating, it will not prevent clockdomain transition.
But I will not recommend using that, it should not be useful assuming the clocks are properly managed by the DSS.
I think we still have issue dur to the presence of that fake modulemode clock node.
Regards,
Benoit
Paul Walmsley
maintainerPATCH v4 2/3 ARM: omap: hwmod: get rid of all omap_clk_get_by_name usage
In reply to Rajendra NayakQuoted 7 lines · Rajendra Nayak
Moving to Common clk framework for OMAP would mean we no longer use internal lookup mechanism like
omap_clk_get_by_name(). get rid of all its usage mostly from hwmod andomap_devicecode.Also use
IS_ERR_OR_NULL()for error checking.
Quoted 7 lines
Moving to
clk_get()also means the respective platforms need the clkdev tables updated with an entry for all clocks used by hwmod to have clock name same as the alias.Based on original changes from Mike Turquette.
Signed-off-by Rajendra Nayak <[email protected]>
Updated this one to include several missing clock aliases and to fix a bug it introduced with omap_96m_alwon_fck_3630; modified patch below.
- Paul
From: Rajendra Nayak <[email protected]>
Date: Sat, 22 Sep 2012 02:24:16 -0600
Subject: [PATCH] ARM: OMAP2+: hwmod: get rid of all omap_clk_get_by_name
usage
Moving to Common clk framework for OMAP would mean we no longer use internal lookup mechanism like omap_clk_get_by_name(). get rid of all its usage mostly from hwmod and omap_device code.
Moving to clk_get() also means the respective platforms need the clkdev tables updated with an entry for all clocks used by hwmod to have clock name same as the alias.
Based on original changes from Mike Turquette.
[paul at pwsan.com: removed IS_ERR_OR_NULL() conversion (rmk comment);
restricted omap_96m_alwon_fck_3630 to OMAP36xx; added missing AM35xx clock aliases for emac_fck, emac_ick, vpfe_ick, vpfe_fck; added aliases rng_ick and several emulation clocks]
--- arch/arm/mach-omap2/clock2420_data.c | 17 +++++++++++++++++ arch/arm/mach-omap2/clock2430_data.c | 22 ++++++++++++++++++++++ arch/arm/mach-omap2/clock3xxx_data.c | 31 +++++++++++++++++++++++++++++++ arch/arm/mach-omap2/clock44xx_data.c | 6 ++++++ arch/arm/mach-omap2/omap_hwmod.c | 12 ++++++------ arch/arm/plat-omap/clock.c | 27 --------------------------- arch/arm/plat-omap/omap_device.c | 4 ++-- 7 files changed, 84 insertions(+), 35 deletions(-)
arch/arm/mach-omap2/clock2420_data.c +17 -0
@@ -1804,6 +1804,7 @@ static struct omap_clk omap2420_clks[] = {CLK (NULL ,"gfx_ick" , &gfx_ick,CK_242X ),/* DSS domain clocks */ CLK ("omapdss_dss" ,"ick" , &dss_ick,CK_242X ), +CLK (NULL ,"dss_ick" , &dss_ick,CK_242X ),CLK (NULL ,"dss1_fck" , &dss1_fck,CK_242X ),CLK (NULL ,"dss2_fck" , &dss2_fck,CK_242X ), CLK(NULL, "dss_54m_fck", &dss_54m_fck, CK_242X),
@@ -1843,12 +1844,16 @@ static struct omap_clk omap2420_clks[] = {CLK (NULL ,"gpt12_ick" , &gpt12_ick,CK_242X ),CLK (NULL ,"gpt12_fck" , &gpt12_fck,CK_242X ),CLK ("omap-mcbsp.1" ,"ick" , &mcbsp1_ick,CK_242X ), +CLK (NULL ,"mcbsp1_ick" , &mcbsp1_ick,CK_242X ),CLK (NULL ,"mcbsp1_fck" , &mcbsp1_fck,CK_242X ),CLK ("omap-mcbsp.2" ,"ick" , &mcbsp2_ick,CK_242X ), +CLK (NULL ,"mcbsp2_ick" , &mcbsp2_ick,CK_242X ),CLK (NULL ,"mcbsp2_fck" , &mcbsp2_fck,CK_242X ),CLK ("omap2_mcspi.1" ,"ick" , &mcspi1_ick,CK_242X ), +CLK (NULL ,"mcspi1_ick" , &mcspi1_ick,CK_242X ),CLK (NULL ,"mcspi1_fck" , &mcspi1_fck,CK_242X ),CLK ("omap2_mcspi.2" ,"ick" , &mcspi2_ick,CK_242X ), +CLK (NULL ,"mcspi2_ick" , &mcspi2_ick,CK_242X ),CLK (NULL ,"mcspi2_fck" , &mcspi2_fck,CK_242X ),CLK (NULL ,"uart1_ick" , &uart1_ick,CK_242X ), CLK(NULL, "uart1_fck", &uart1_fck, CK_242X),
@@ -1859,12 +1864,15 @@ static struct omap_clk omap2420_clks[] = {CLK (NULL ,"gpios_ick" , &gpios_ick,CK_242X ),CLK (NULL ,"gpios_fck" , &gpios_fck,CK_242X ),CLK ("omap_wdt" ,"ick" , &mpu_wdt_ick,CK_242X ), +CLK (NULL ,"mpu_wdt_ick" , &mpu_wdt_ick,CK_242X ),CLK (NULL ,"mpu_wdt_fck" , &mpu_wdt_fck,CK_242X ),CLK (NULL ,"sync_32k_ick" , &sync_32k_ick,CK_242X ),CLK (NULL ,"wdt1_ick" , &wdt1_ick,CK_242X ),CLK (NULL ,"omapctrl_ick" , &omapctrl_ick,CK_242X ),CLK ("omap24xxcam" ,"fck" , &cam_fck,CK_242X ), +CLK (NULL ,"cam_fck" , &cam_fck,CK_242X ),CLK ("omap24xxcam" ,"ick" , &cam_ick,CK_242X ), +CLK (NULL ,"cam_ick" , &cam_ick,CK_242X ),CLK (NULL ,"mailboxes_ick" , &mailboxes_ick,CK_242X ),CLK (NULL ,"wdt4_ick" , &wdt4_ick,CK_242X ), CLK(NULL, "wdt4_fck", &wdt4_fck, CK_242X),
@@ -1873,16 +1881,22 @@ static struct omap_clk omap2420_clks[] = {CLK (NULL ,"mspro_ick" , &mspro_ick,CK_242X ),CLK (NULL ,"mspro_fck" , &mspro_fck,CK_242X ),CLK ("mmci-omap.0" ,"ick" , &mmc_ick,CK_242X ), +CLK (NULL ,"mmc_ick" , &mmc_ick,CK_242X ),CLK ("mmci-omap.0" ,"fck" , &mmc_fck,CK_242X ), +CLK (NULL ,"mmc_fck" , &mmc_fck,CK_242X ),CLK (NULL ,"fac_ick" , &fac_ick,CK_242X ),CLK (NULL ,"fac_fck" , &fac_fck,CK_242X ),CLK (NULL ,"eac_ick" , &eac_ick,CK_242X ),CLK (NULL ,"eac_fck" , &eac_fck,CK_242X ),CLK ("omap_hdq.0" ,"ick" , &hdq_ick,CK_242X ), +CLK (NULL ,"hdq_ick" , &hdq_ick,CK_242X ),CLK ("omap_hdq.0" ,"fck" , &hdq_fck,CK_242X ), +CLK (NULL ,"hdq_fck" , &hdq_fck,CK_242X ),CLK ("omap_i2c.1" ,"ick" , &i2c1_ick,CK_242X ), +CLK (NULL ,"i2c1_ick" , &i2c1_ick,CK_242X ),CLK (NULL ,"i2c1_fck" , &i2c1_fck,CK_242X ),CLK ("omap_i2c.2" ,"ick" , &i2c2_ick,CK_242X ), +CLK (NULL ,"i2c2_ick" , &i2c2_ick,CK_242X ),CLK (NULL ,"i2c2_fck" , &i2c2_fck,CK_242X ),CLK (NULL ,"gpmc_fck" , &gpmc_fck,CK_242X ), CLK(NULL, "sdma_fck", &sdma_fck, CK_242X),
@@ -1892,8 +1906,11 @@ static struct omap_clk omap2420_clks[] = {CLK (NULL ,"vlynq_fck" , &vlynq_fck,CK_242X ),CLK (NULL ,"des_ick" , &des_ick,CK_242X ),CLK ("omap-sham" ,"ick" , &sha_ick,CK_242X ), +CLK (NULL ,"sha_ick" , &sha_ick,CK_242X ),CLK ("omap_rng" ,"ick" , &rng_ick,CK_242X ), +CLK (NULL ,"rng_ick" , &rng_ick,CK_242X ),CLK ("omap-aes" ,"ick" , &aes_ick,CK_242X ), +CLK (NULL ,"aes_ick" , &aes_ick,CK_242X ),CLK (NULL ,"pka_ick" , &pka_ick,CK_242X ),CLK (NULL ,"usb_fck" , &usb_fck,CK_242X ), CLK("musb-hdrc", "fck", &osc_ck, CK_242X),
arch/arm/mach-omap2/clock2430_data.c +22 -0
@@ -1888,6 +1888,7 @@ static struct omap_clk omap2430_clks[] = {CLK (NULL ,"mdm_osc_ck" , &mdm_osc_ck,CK_243X ),/* DSS domain clocks */ CLK ("omapdss_dss" ,"ick" , &dss_ick,CK_243X ), +CLK (NULL ,"dss_ick" , &dss_ick,CK_243X ),CLK (NULL ,"dss1_fck" , &dss1_fck,CK_243X ),CLK (NULL ,"dss2_fck" , &dss2_fck,CK_243X ), CLK(NULL, "dss_54m_fck", &dss_54m_fck, CK_243X),
@@ -1927,20 +1928,28 @@ static struct omap_clk omap2430_clks[] = {CLK (NULL ,"gpt12_ick" , &gpt12_ick,CK_243X ),CLK (NULL ,"gpt12_fck" , &gpt12_fck,CK_243X ),CLK ("omap-mcbsp.1" ,"ick" , &mcbsp1_ick,CK_243X ), +CLK (NULL ,"mcbsp1_ick" , &mcbsp1_ick,CK_243X ),CLK (NULL ,"mcbsp1_fck" , &mcbsp1_fck,CK_243X ),CLK ("omap-mcbsp.2" ,"ick" , &mcbsp2_ick,CK_243X ), +CLK (NULL ,"mcbsp2_ick" , &mcbsp2_ick,CK_243X ),CLK (NULL ,"mcbsp2_fck" , &mcbsp2_fck,CK_243X ),CLK ("omap-mcbsp.3" ,"ick" , &mcbsp3_ick,CK_243X ), +CLK (NULL ,"mcbsp3_ick" , &mcbsp3_ick,CK_243X ),CLK (NULL ,"mcbsp3_fck" , &mcbsp3_fck,CK_243X ),CLK ("omap-mcbsp.4" ,"ick" , &mcbsp4_ick,CK_243X ), +CLK (NULL ,"mcbsp4_ick" , &mcbsp4_ick,CK_243X ),CLK (NULL ,"mcbsp4_fck" , &mcbsp4_fck,CK_243X ),CLK ("omap-mcbsp.5" ,"ick" , &mcbsp5_ick,CK_243X ), +CLK (NULL ,"mcbsp5_ick" , &mcbsp5_ick,CK_243X ),CLK (NULL ,"mcbsp5_fck" , &mcbsp5_fck,CK_243X ),CLK ("omap2_mcspi.1" ,"ick" , &mcspi1_ick,CK_243X ), +CLK (NULL ,"mcspi1_ick" , &mcspi1_ick,CK_243X ),CLK (NULL ,"mcspi1_fck" , &mcspi1_fck,CK_243X ),CLK ("omap2_mcspi.2" ,"ick" , &mcspi2_ick,CK_243X ), +CLK (NULL ,"mcspi2_ick" , &mcspi2_ick,CK_243X ),CLK (NULL ,"mcspi2_fck" , &mcspi2_fck,CK_243X ),CLK ("omap2_mcspi.3" ,"ick" , &mcspi3_ick,CK_243X ), +CLK (NULL ,"mcspi3_ick" , &mcspi3_ick,CK_243X ),CLK (NULL ,"mcspi3_fck" , &mcspi3_fck,CK_243X ),CLK (NULL ,"uart1_ick" , &uart1_ick,CK_243X ), CLK(NULL, "uart1_fck", &uart1_fck, CK_243X),
@@ -1951,13 +1960,16 @@ static struct omap_clk omap2430_clks[] = {CLK (NULL ,"gpios_ick" , &gpios_ick,CK_243X ),CLK (NULL ,"gpios_fck" , &gpios_fck,CK_243X ),CLK ("omap_wdt" ,"ick" , &mpu_wdt_ick,CK_243X ), +CLK (NULL ,"mpu_wdt_ick" , &mpu_wdt_ick,CK_243X ),CLK (NULL ,"mpu_wdt_fck" , &mpu_wdt_fck,CK_243X ),CLK (NULL ,"sync_32k_ick" , &sync_32k_ick,CK_243X ),CLK (NULL ,"wdt1_ick" , &wdt1_ick,CK_243X ),CLK (NULL ,"omapctrl_ick" , &omapctrl_ick,CK_243X ),CLK (NULL ,"icr_ick" , &icr_ick,CK_243X ),CLK ("omap24xxcam" ,"fck" , &cam_fck,CK_243X ), +CLK (NULL ,"cam_fck" , &cam_fck,CK_243X ),CLK ("omap24xxcam" ,"ick" , &cam_ick,CK_243X ), +CLK (NULL ,"cam_ick" , &cam_ick,CK_243X ),CLK (NULL ,"mailboxes_ick" , &mailboxes_ick,CK_243X ),CLK (NULL ,"wdt4_ick" , &wdt4_ick,CK_243X ), CLK(NULL, "wdt4_fck", &wdt4_fck, CK_243X),
@@ -1966,10 +1978,14 @@ static struct omap_clk omap2430_clks[] = {CLK (NULL ,"fac_ick" , &fac_ick,CK_243X ),CLK (NULL ,"fac_fck" , &fac_fck,CK_243X ),CLK ("omap_hdq.0" ,"ick" , &hdq_ick,CK_243X ), +CLK (NULL ,"hdq_ick" , &hdq_ick,CK_243X ),CLK ("omap_hdq.1" ,"fck" , &hdq_fck,CK_243X ), +CLK (NULL ,"hdq_fck" , &hdq_fck,CK_243X ),CLK ("omap_i2c.1" ,"ick" , &i2c1_ick,CK_243X ), +CLK (NULL ,"i2c1_ick" , &i2c1_ick,CK_243X ),CLK (NULL ,"i2chs1_fck" , &i2chs1_fck,CK_243X ),CLK ("omap_i2c.2" ,"ick" , &i2c2_ick,CK_243X ), +CLK (NULL ,"i2c2_ick" , &i2c2_ick,CK_243X ),CLK (NULL ,"i2chs2_fck" , &i2chs2_fck,CK_243X ),CLK (NULL ,"gpmc_fck" , &gpmc_fck,CK_243X ), CLK(NULL, "sdma_fck", &sdma_fck, CK_243X),
@@ -1978,19 +1994,25 @@ static struct omap_clk omap2430_clks[] = {CLK (NULL ,"des_ick" , &des_ick,CK_243X ),CLK ("omap-sham" ,"ick" , &sha_ick,CK_243X ),CLK ("omap_rng" ,"ick" , &rng_ick,CK_243X ), +CLK (NULL ,"rng_ick" , &rng_ick,CK_243X ),CLK ("omap-aes" ,"ick" , &aes_ick,CK_243X ),CLK (NULL ,"pka_ick" , &pka_ick,CK_243X ),CLK (NULL ,"usb_fck" , &usb_fck,CK_243X ),CLK ("musb-omap2430" ,"ick" , &usbhs_ick,CK_243X ), +CLK (NULL ,"usbhs_ick" , &usbhs_ick,CK_243X ),CLK ("omap_hsmmc.0" ,"ick" , &mmchs1_ick,CK_243X ), +CLK (NULL ,"mmchs1_ick" , &mmchs1_ick,CK_243X ),CLK (NULL ,"mmchs1_fck" , &mmchs1_fck,CK_243X ),CLK ("omap_hsmmc.1" ,"ick" , &mmchs2_ick,CK_243X ), +CLK (NULL ,"mmchs2_ick" , &mmchs2_ick,CK_243X ),CLK (NULL ,"mmchs2_fck" , &mmchs2_fck,CK_243X ),CLK (NULL ,"gpio5_ick" , &gpio5_ick,CK_243X ),CLK (NULL ,"gpio5_fck" , &gpio5_fck,CK_243X ),CLK (NULL ,"mdm_intc_ick" , &mdm_intc_ick,CK_243X ),CLK ("omap_hsmmc.0" ,"mmchsdb_fck" , &mmchsdb1_fck,CK_243X ), +CLK (NULL ,"mmchsdb1_fck" , &mmchsdb1_fck,CK_243X ),CLK ("omap_hsmmc.1" ,"mmchsdb_fck" , &mmchsdb2_fck,CK_243X ), +CLK (NULL ,"mmchsdb2_fck" , &mmchsdb2_fck,CK_243X ),CLK (NULL ,"timer_32k_ck" , &func_32k_ck,CK_243X ),CLK (NULL ,"timer_sys_ck" , &sys_ck,CK_243X ), CLK(NULL, "timer_ext_ck", &alt_ck, CK_243X),
arch/arm/mach-omap2/clock3xxx_data.c +31 -0
@@ -3242,11 +3242,13 @@ static struct omap_clk omap3xxx_clks[] = {CLK (NULL ,"dpll3_m2x2_ck" , &dpll3_m2x2_ck,CK_3XXX ),CLK (NULL ,"dpll3_m3_ck" , &dpll3_m3_ck,CK_3XXX ),CLK (NULL ,"dpll3_m3x2_ck" , &dpll3_m3x2_ck,CK_3XXX ), +CLK (NULL ,"emu_core_alwon_ck" , &emu_core_alwon_ck,CK_3XXX ),CLK ("etb" ,"emu_core_alwon_ck" , &emu_core_alwon_ck,CK_3XXX ),CLK (NULL ,"dpll4_ck" , &dpll4_ck,CK_3XXX ),CLK (NULL ,"dpll4_x2_ck" , &dpll4_x2_ck,CK_3XXX ),CLK (NULL ,"omap_192m_alwon_fck" , &omap_192m_alwon_fck,CK_36XX ),CLK (NULL ,"omap_96m_alwon_fck" , &omap_96m_alwon_fck,CK_3XXX ), +CLK (NULL ,"omap_96m_alwon_fck_3630" , &omap_96m_alwon_fck_3630,CK_36XX ),CLK (NULL ,"omap_96m_fck" , &omap_96m_fck,CK_3XXX ),CLK (NULL ,"cm_96m_fck" , &cm_96m_fck,CK_3XXX ), CLK(NULL, "omap_54m_fck", &omap_54m_fck, CK_3XXX),
@@ -3262,6 +3264,7 @@ static struct omap_clk omap3xxx_clks[] = {CLK (NULL ,"dpll4_m5x2_ck" , &dpll4_m5x2_ck,CK_3XXX ),CLK (NULL ,"dpll4_m6_ck" , &dpll4_m6_ck,CK_3XXX ),CLK (NULL ,"dpll4_m6x2_ck" , &dpll4_m6x2_ck,CK_3XXX ), +CLK (NULL ,"emu_per_alwon_ck" , &emu_per_alwon_ck,CK_3XXX ),CLK ("etb" ,"emu_per_alwon_ck" , &emu_per_alwon_ck,CK_3XXX ),CLK (NULL ,"dpll5_ck" , &dpll5_ck,CK_3430ES2PLUS |CK_AM35XX |CK_36XX ), CLK(NULL, "dpll5_m2_ck", &dpll5_m2_ck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
@@ -3271,6 +3274,7 @@ static struct omap_clk omap3xxx_clks[] = {CLK (NULL ,"dpll1_fck" , &dpll1_fck,CK_3XXX ),CLK (NULL ,"mpu_ck" , &mpu_ck,CK_3XXX ),CLK (NULL ,"arm_fck" , &arm_fck,CK_3XXX ), +CLK (NULL ,"emu_mpu_alwon_ck" , &emu_mpu_alwon_ck,CK_3XXX ),CLK ("etb" ,"emu_mpu_alwon_ck" , &emu_mpu_alwon_ck,CK_3XXX ),CLK (NULL ,"dpll2_fck" , &dpll2_fck,CK_34XX |CK_36XX ), CLK(NULL, "iva2_ck", &iva2_ck, CK_34XX | CK_36XX),
@@ -3315,6 +3319,7 @@ static struct omap_clk omap3xxx_clks[] = {CLK (NULL ,"fshostusb_fck" , &fshostusb_fck,CK_3430ES1 ),CLK (NULL ,"core_12m_fck" , &core_12m_fck,CK_3XXX ),CLK ("omap_hdq.0" ,"fck" , &hdq_fck,CK_3XXX ), +CLK (NULL ,"hdq_fck" , &hdq_fck,CK_3XXX ),CLK (NULL ,"ssi_ssr_fck" , &ssi_ssr_fck_3430es1,CK_3430ES1 ),CLK (NULL ,"ssi_ssr_fck" , &ssi_ssr_fck_3430es2,CK_3430ES2PLUS |CK_36XX ), CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es1, CK_3430ES1),
@@ -3322,6 +3327,8 @@ static struct omap_clk omap3xxx_clks[] = {CLK (NULL ,"core_l3_ick" , &core_l3_ick,CK_3XXX ),CLK ("musb-omap2430" ,"ick" , &hsotgusb_ick_3430es1,CK_3430ES1 ),CLK ("musb-omap2430" ,"ick" , &hsotgusb_ick_3430es2,CK_3430ES2PLUS |CK_36XX ), +CLK (NULL ,"hsotgusb_ick" , &hsotgusb_ick_3430es1,CK_3430ES1 ), +CLK (NULL ,"hsotgusb_ick" , &hsotgusb_ick_3430es2,CK_3430ES2PLUS |CK_36XX ),CLK (NULL ,"sdrc_ick" , &sdrc_ick,CK_3XXX ),CLK (NULL ,"gpmc_fck" , &gpmc_fck,CK_3XXX ), CLK(NULL, "security_l3_ick", &security_l3_ick, CK_34XX | CK_36XX),
@@ -3331,27 +3338,40 @@ static struct omap_clk omap3xxx_clks[] = {CLK ("usbhs_omap" ,"usbtll_ick" , &usbtll_ick,CK_3430ES2PLUS |CK_AM35XX |CK_36XX ),CLK ("usbhs_tll" ,"usbtll_ick" , &usbtll_ick,CK_3430ES2PLUS |CK_AM35XX |CK_36XX ),CLK ("omap_hsmmc.2" ,"ick" , &mmchs3_ick,CK_3430ES2PLUS |CK_AM35XX |CK_36XX ), +CLK (NULL ,"mmchs3_ick" , &mmchs3_ick,CK_3430ES2PLUS |CK_AM35XX |CK_36XX ),CLK (NULL ,"icr_ick" , &icr_ick,CK_34XX |CK_36XX ),CLK ("omap-aes" ,"ick" , &aes2_ick,CK_34XX |CK_36XX ),CLK ("omap-sham" ,"ick" , &sha12_ick,CK_34XX |CK_36XX ),CLK (NULL ,"des2_ick" , &des2_ick,CK_34XX |CK_36XX ),CLK ("omap_hsmmc.1" ,"ick" , &mmchs2_ick,CK_3XXX ),CLK ("omap_hsmmc.0" ,"ick" , &mmchs1_ick,CK_3XXX ), +CLK (NULL ,"mmchs2_ick" , &mmchs2_ick,CK_3XXX ), +CLK (NULL ,"mmchs1_ick" , &mmchs1_ick,CK_3XXX ),CLK (NULL ,"mspro_ick" , &mspro_ick,CK_34XX |CK_36XX ),CLK ("omap_hdq.0" ,"ick" , &hdq_ick,CK_3XXX ), +CLK (NULL ,"hdq_ick" , &hdq_ick,CK_3XXX ),CLK ("omap2_mcspi.4" ,"ick" , &mcspi4_ick,CK_3XXX ),CLK ("omap2_mcspi.3" ,"ick" , &mcspi3_ick,CK_3XXX ),CLK ("omap2_mcspi.2" ,"ick" , &mcspi2_ick,CK_3XXX ),CLK ("omap2_mcspi.1" ,"ick" , &mcspi1_ick,CK_3XXX ), +CLK (NULL ,"mcspi4_ick" , &mcspi4_ick,CK_3XXX ), +CLK (NULL ,"mcspi3_ick" , &mcspi3_ick,CK_3XXX ), +CLK (NULL ,"mcspi2_ick" , &mcspi2_ick,CK_3XXX ), +CLK (NULL ,"mcspi1_ick" , &mcspi1_ick,CK_3XXX ),CLK ("omap_i2c.3" ,"ick" , &i2c3_ick,CK_3XXX ),CLK ("omap_i2c.2" ,"ick" , &i2c2_ick,CK_3XXX ),CLK ("omap_i2c.1" ,"ick" , &i2c1_ick,CK_3XXX ), +CLK (NULL ,"i2c3_ick" , &i2c3_ick,CK_3XXX ), +CLK (NULL ,"i2c2_ick" , &i2c2_ick,CK_3XXX ), +CLK (NULL ,"i2c1_ick" , &i2c1_ick,CK_3XXX ),CLK (NULL ,"uart2_ick" , &uart2_ick,CK_3XXX ),CLK (NULL ,"uart1_ick" , &uart1_ick,CK_3XXX ),CLK (NULL ,"gpt11_ick" , &gpt11_ick,CK_3XXX ),CLK (NULL ,"gpt10_ick" , &gpt10_ick,CK_3XXX ),CLK ("omap-mcbsp.5" ,"ick" , &mcbsp5_ick,CK_3XXX ),CLK ("omap-mcbsp.1" ,"ick" , &mcbsp1_ick,CK_3XXX ), +CLK (NULL ,"mcbsp5_ick" , &mcbsp5_ick,CK_3XXX ), +CLK (NULL ,"mcbsp1_ick" , &mcbsp1_ick,CK_3XXX ),CLK (NULL ,"fac_ick" , &fac_ick,CK_3430ES1 ),CLK (NULL ,"mailboxes_ick" , &mailboxes_ick,CK_34XX |CK_36XX ), CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_3XXX),
@@ -3370,7 +3390,9 @@ static struct omap_clk omap3xxx_clks[] = {CLK (NULL ,"dss_96m_fck" , &dss_96m_fck,CK_3XXX ),CLK (NULL ,"dss2_alwon_fck" , &dss2_alwon_fck,CK_3XXX ),CLK ("omapdss_dss" ,"ick" , &dss_ick_3430es1,CK_3430ES1 ), +CLK (NULL ,"dss_ick" , &dss_ick_3430es1,CK_3430ES1 ),CLK ("omapdss_dss" ,"ick" , &dss_ick_3430es2,CK_3430ES2PLUS |CK_AM35XX |CK_36XX ), +CLK (NULL ,"dss_ick" , &dss_ick_3430es2,CK_3430ES2PLUS |CK_AM35XX |CK_36XX ),CLK (NULL ,"cam_mclk" , &cam_mclk,CK_34XX |CK_36XX ),CLK (NULL ,"cam_ick" , &cam_ick,CK_34XX |CK_36XX ), CLK(NULL, "csi2_96m_fck", &csi2_96m_fck, CK_34XX | CK_36XX),
@@ -3397,6 +3419,7 @@ static struct omap_clk omap3xxx_clks[] = {CLK (NULL ,"wkup_l4_ick" , &wkup_l4_ick,CK_34XX |CK_36XX ),CLK (NULL ,"usim_ick" , &usim_ick,CK_3430ES2PLUS |CK_36XX ),CLK ("omap_wdt" ,"ick" , &wdt2_ick,CK_3XXX ), +CLK (NULL ,"wdt2_ick" , &wdt2_ick,CK_3XXX ),CLK (NULL ,"wdt1_ick" , &wdt1_ick,CK_3XXX ),CLK (NULL ,"gpio1_ick" , &gpio1_ick,CK_3XXX ), CLK(NULL, "omap_32ksync_ick", &omap_32ksync_ick, CK_3XXX),
@@ -3442,9 +3465,13 @@ static struct omap_clk omap3xxx_clks[] = {CLK ("omap-mcbsp.2" ,"ick" , &mcbsp2_ick,CK_3XXX ),CLK ("omap-mcbsp.3" ,"ick" , &mcbsp3_ick,CK_3XXX ),CLK ("omap-mcbsp.4" ,"ick" , &mcbsp4_ick,CK_3XXX ), +CLK (NULL ,"mcbsp4_ick" , &mcbsp2_ick,CK_3XXX ), +CLK (NULL ,"mcbsp3_ick" , &mcbsp3_ick,CK_3XXX ), +CLK (NULL ,"mcbsp2_ick" , &mcbsp4_ick,CK_3XXX ),CLK (NULL ,"mcbsp2_fck" , &mcbsp2_fck,CK_3XXX ),CLK (NULL ,"mcbsp3_fck" , &mcbsp3_fck,CK_3XXX ),CLK (NULL ,"mcbsp4_fck" , &mcbsp4_fck,CK_3XXX ), +CLK (NULL ,"emu_src_ck" , &emu_src_ck,CK_3XXX ),CLK ("etb" ,"emu_src_ck" , &emu_src_ck,CK_3XXX ),CLK (NULL ,"pclk_fck" , &pclk_fck,CK_3XXX ), CLK(NULL, "pclkx2_fck", &pclkx2_fck, CK_3XXX),
@@ -3460,8 +3487,12 @@ static struct omap_clk omap3xxx_clks[] = {CLK (NULL ,"ipss_ick" , &ipss_ick,CK_AM35XX ),CLK (NULL ,"rmii_ck" , &rmii_ck,CK_AM35XX ),CLK (NULL ,"pclk_ck" , &pclk_ck,CK_AM35XX ), +CLK (NULL ,"emac_ick" , &emac_ick,CK_AM35XX ), +CLK (NULL ,"emac_fck" , &emac_fck,CK_AM35XX ),CLK ("davinci_emac.0" ,NULL , &emac_ick,CK_AM35XX ),CLK ("davinci_mdio.0" ,NULL , &emac_fck,CK_AM35XX ), +CLK (NULL ,"vpfe_ick" , &emac_ick,CK_AM35XX ), +CLK (NULL ,"vpfe_fck" , &emac_fck,CK_AM35XX ),CLK ("vpfe-capture" ,"master" , &vpfe_ick,CK_AM35XX ),CLK ("vpfe-capture" ,"slave" , &vpfe_fck,CK_AM35XX ), CLK(NULL, "hsotgusb_ick", &hsotgusb_ick_am35xx, CK_AM35XX),
arch/arm/mach-omap2/clock44xx_data.c +6 -0
@@ -3156,6 +3156,7 @@ static struct omap_clk omap44xx_clks[] = {CLK (NULL ,"dss_tv_clk" , &dss_tv_clk,CK_443X ),CLK (NULL ,"dss_48mhz_clk" , &dss_48mhz_clk,CK_443X ),CLK (NULL ,"dss_dss_clk" , &dss_dss_clk,CK_443X ), +CLK (NULL ,"dss_fck" , &dss_fck,CK_443X ),CLK ("omapdss_dss" ,"ick" , &dss_fck,CK_443X ),CLK (NULL ,"efuse_ctrl_cust_fck" , &efuse_ctrl_cust_fck,CK_443X ), CLK(NULL, "emif1_fck", &emif1_fck, CK_443X),
@@ -3212,6 +3213,7 @@ static struct omap_clk omap44xx_clks[] = {CLK (NULL ,"ocp2scp_usb_phy_phy_48m" , &ocp2scp_usb_phy_phy_48m,CK_443X ),CLK (NULL ,"ocp2scp_usb_phy_ick" , &ocp2scp_usb_phy_ick,CK_443X ),CLK (NULL ,"ocp_wp_noc_ick" , &ocp_wp_noc_ick,CK_443X ), +CLK (NULL ,"rng_ick" , &rng_ick,CK_443X ),CLK ("omap_rng" ,"ick" , &rng_ick,CK_443X ),CLK (NULL ,"sha2md5_fck" , &sha2md5_fck,CK_443X ), CLK(NULL, "sl2if_ick", &sl2if_ick, CK_443X),
@@ -3243,6 +3245,7 @@ static struct omap_clk omap44xx_clks[] = {CLK (NULL ,"uart3_fck" , &uart3_fck,CK_443X ),CLK (NULL ,"uart4_fck" , &uart4_fck,CK_443X ),CLK ("usbhs_omap" ,"fs_fck" , &usb_host_fs_fck,CK_443X ), +CLK (NULL ,"usb_host_fs_fck" , &usb_host_fs_fck,CK_443X ),CLK (NULL ,"utmi_p1_gfclk" , &utmi_p1_gfclk,CK_443X ),CLK (NULL ,"usb_host_hs_utmi_p1_clk" , &usb_host_hs_utmi_p1_clk,CK_443X ), CLK(NULL, "utmi_p2_gfclk", &utmi_p2_gfclk, CK_443X),
@@ -3253,14 +3256,17 @@ static struct omap_clk omap44xx_clks[] = {CLK (NULL ,"usb_host_hs_hsic60m_p2_clk" , &usb_host_hs_hsic60m_p2_clk,CK_443X ),CLK (NULL ,"usb_host_hs_hsic480m_p2_clk" , &usb_host_hs_hsic480m_p2_clk,CK_443X ),CLK (NULL ,"usb_host_hs_func48mclk" , &usb_host_hs_func48mclk,CK_443X ), +CLK (NULL ,"usb_host_hs_fck" , &usb_host_hs_fck,CK_443X ),CLK ("usbhs_omap" ,"hs_fck" , &usb_host_hs_fck,CK_443X ),CLK (NULL ,"otg_60m_gfclk" , &otg_60m_gfclk,CK_443X ),CLK (NULL ,"usb_otg_hs_xclk" , &usb_otg_hs_xclk,CK_443X ), +CLK (NULL ,"usb_otg_hs_ick" , &usb_otg_hs_ick,CK_443X ),CLK ("musb-omap2430" ,"ick" , &usb_otg_hs_ick,CK_443X ),CLK (NULL ,"usb_phy_cm_clk32k" , &usb_phy_cm_clk32k,CK_443X ),CLK (NULL ,"usb_tll_hs_usb_ch2_clk" , &usb_tll_hs_usb_ch2_clk,CK_443X ),CLK (NULL ,"usb_tll_hs_usb_ch0_clk" , &usb_tll_hs_usb_ch0_clk,CK_443X ),CLK (NULL ,"usb_tll_hs_usb_ch1_clk" , &usb_tll_hs_usb_ch1_clk,CK_443X ), +CLK (NULL ,"usb_tll_hs_ick" , &usb_tll_hs_ick,CK_443X ),CLK ("usbhs_omap" ,"usbtll_ick" , &usb_tll_hs_ick,CK_443X ),CLK ("usbhs_tll" ,"usbtll_ick" , &usb_tll_hs_ick,CK_443X ), CLK(NULL, "usim_ck", &usim_ck, CK_443X),
arch/arm/mach-omap2/omap_hwmod.c +6 -6
@@ -679,8 +679,8 @@ static int _init_main_clk(struct omap_hwmod *oh)if (!oh->main_clk)return 0 ; - oh->_clk =omap_clk_get_by_name (oh->main_clk); -if (!oh->_clk) { + oh->_clk =clk_get (NULL , oh->main_clk); +if (IS_ERR (oh->_clk)) {pr_warning ("omap_hwmod: %s: cannot clk_get main_clk %s\n" , oh->name, oh->main_clk);return -EINVAL ;
@@ -724,8 +724,8 @@ static int _init_interface_clks(struct omap_hwmod *oh)if (!os->clk)continue ; - c =omap_clk_get_by_name (os->clk); -if (!c) { + c =clk_get (NULL , os->clk); +if (IS_ERR (c)) {pr_warning ("omap_hwmod: %s: cannot clk_get interface_clk %s\n" , oh->name, os->clk); ret = -EINVAL ;
@@ -760,8 +760,8 @@ static int _init_opt_clks(struct omap_hwmod *oh)int ret =0 ;for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i >0 ; i--, oc++) { - c =omap_clk_get_by_name (oc->clk); -if (!c) { + c =clk_get (NULL , oc->clk); +if (IS_ERR (c)) {pr_warning ("omap_hwmod: %s: cannot clk_get opt_clk %s\n" , oh->name, oc->clk); ret = -EINVAL ;
arch/arm/plat-omap/clock.c +0 -27
@@ -312,33 +312,6 @@ void clk_enable_init_clocks(void) } } -/** -* omap_clk_get_by_name - locate OMAP struct clk by its name -* @name: name of the struct clk to locate -* -* Locate an OMAP struct clk by its name. Assumes that struct clk -* names are unique. Returns NULL if not found or a pointer to the -* struct clk if found. -*/ -struct clk *omap_clk_get_by_name (const char *name) -{ -struct clk *c; -struct clk *ret =NULL ; - -mutex_lock (&clocks_mutex); - -list_for_each_entry (c, &clocks, node) { -if (!strcmp (c->name, name)) { - ret = c; -break ; - } - } - -mutex_unlock (&clocks_mutex); - -return ret; -} -int omap_clk_enable_autoidle_all (void ) {struct clk *c;
arch/arm/plat-omap/omap_device.c +2 -2
@@ -266,10 +266,10 @@ static void _add_clkdev(struct omap_device *od, const char *clk_alias,return ; } - r =omap_clk_get_by_name (clk_name); + r =clk_get (NULL , clk_name);if (IS_ERR (r)) {dev_err (&od->pdev->dev, -"omap_clk_get_by_name for %s failed\n" , clk_name); +"clk_get for %s failed\n" , clk_name);return ; }
Signature · 1 line
1.7.10.4
PATCH v4 2/3 ARM: omap: hwmod: get rid of all omap_clk_get_by_name usage
Quoted 2 lines · Paul Walmsley
Updated this one to include several missing clock aliases and to fix a bug it introduced with
omap_96m_alwon_fck_3630; modified patch below.
Thanks Paul, for the updates and the fix. Updated patch looks good to me.
regards,
Rajendra
PATCH v4 3/3 ARM: OMAP2+: clock: Remove all direct dereferencing of struct clk
In reply to Rajendra NayakWhile we move to Common Clk Framework (CCF), direct deferencing of struct clk wouldn't be possible anymore. Hence get rid of all such instances in the current clock code and use macros/helpers similar to the ones that are provided by CCF.
While here also concatenate some strings split across multiple lines which seem to be needed anyway.
[paul at pwsan.com: simplified some compound expressions; reformatted some
messages]
--- arch/arm/mach-omap2/clkt2xxx_apll.c | 2 +- arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c | 10 ++- arch/arm/mach-omap2/clkt34xx_dpll3m2.c | 20 +++--- arch/arm/mach-omap2/clkt_clksel.c | 91 ++++++++++++++++---------- arch/arm/mach-omap2/clkt_dpll.c | 26 ++++---- arch/arm/mach-omap2/clock.c | 11 ++-- arch/arm/mach-omap2/dpll3xxx.c | 48 ++++++++------ arch/arm/mach-omap2/omap_hwmod.c | 6 +- arch/arm/mach-omap2/pm.c | 2 +- arch/arm/plat-omap/include/plat/clock.h | 5 ++ 10 files changed, 135 insertions(+), 86 deletions(-)
arch/arm/mach-omap2/clkt2xxx_apll.c +1 -1
@@ -59,7 +59,7 @@ static int omap2_clk_apll_enable(struct clk *clk, u32 status_mask)omap2_cm_write_mod_reg (cval,PLL_MOD ,CM_CLKEN );omap2_cm_wait_idlest (cm_idlest_pll, status_mask, -OMAP24XX_CM_IDLEST_VAL , clk->name); +OMAP24XX_CM_IDLEST_VAL ,__clk_get_name (clk));/* * REVISIT: Should we return an error code if omap2_wait_clock_ready()
arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c +7 -3
@@ -68,14 +68,15 @@ unsigned long omap2_table_mpu_recalc(struct clk *clk)long omap2_round_to_table_rate (struct clk *clk,unsigned long rate) {const struct prcm_config *ptr; -long highest_rate; +long highest_rate, sys_clk_rate; highest_rate = -EINVAL ; + sys_clk_rate =__clk_get_rate (sclk);for (ptr = rate_table; ptr->mpu_speed; ptr++) {if (!(ptr->flags & cpu_mask))continue ; -if (ptr->xtal_speed != sclk->rate) +if (ptr->xtal_speed != sys_clk_rate)continue ; highest_rate = ptr->mpu_speed;
@@ -94,12 +95,15 @@ int omap2_select_table_rate(struct clk *clk, unsigned long rate)const struct prcm_config *prcm;unsigned long found_speed =0 ;unsigned long flags; +long sys_clk_rate; + + sys_clk_rate =__clk_get_rate (sclk);for (prcm = rate_table; prcm->mpu_speed; prcm++) {if (!(prcm->flags & cpu_mask))continue ; -if (prcm->xtal_speed != sclk->rate) +if (prcm->xtal_speed != sys_clk_rate)continue ;if (prcm->mpu_speed <= rate) {
arch/arm/mach-omap2/clkt34xx_dpll3m2.c +11 -9
@@ -56,6 +56,7 @@ int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)struct omap_sdrc_params *sdrc_cs0;struct omap_sdrc_params *sdrc_cs1;int ret; +unsigned long clkrate;if (!clk || !rate)return -EINVAL ;
@@ -64,11 +65,12 @@ int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)if (validrate != rate)return -EINVAL ; - sdrcrate = sdrc_ick_p->rate; -if (rate > clk->rate) - sdrcrate <<= ((rate / clk->rate) >>1 ); + sdrcrate =__clk_get_rate (sdrc_ick_p); + clkrate =__clk_get_rate (clk); +if (rate > clkrate) + sdrcrate <<= ((rate / clkrate) >>1 );else - sdrcrate >>= ((clk->rate / rate) >>1 ); + sdrcrate >>= ((clkrate / rate) >>1 ); ret =omap2_sdrc_get_params (sdrcrate, &sdrc_cs0, &sdrc_cs1);if (ret)
@@ -82,7 +84,7 @@ int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)/* * XXX This only needs to be done when the CPU frequency changes */ - _mpurate = arm_fck_p->rate /CYCLES_PER_MHZ ; + _mpurate =__clk_get_rate (arm_fck_p) /CYCLES_PER_MHZ ; c = (_mpurate <<SDRC_MPURATE_SCALE ) >>SDRC_MPURATE_BASE_SHIFT ; c +=1 ;/* for safety */ c *=SDRC_MPURATE_LOOPS ;
@@ -90,8 +92,8 @@ int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)if (c ==0 ) c =1 ; -pr_debug ("clock: changing CORE DPLL rate from %lu to %lu\n" , clk->rate, - validrate); +pr_debug ("clock: changing CORE DPLL rate from %lu to %lu\n" , + clkrate, validrate); pr_debug("clock: SDRC CS0 timing params used:" " RFR %08x CTRLA %08x CTRLB %08x MR %08x\n", sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
@@ -104,14 +106,14 @@ int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)if (sdrc_cs1)omap3_configure_core_dpll ( - new_div, unlock_dll, c, rate > clk->rate, + new_div, unlock_dll, c, rate > clkrate, sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla, sdrc_cs0->actim_ctrlb, sdrc_cs0->mr, sdrc_cs1->rfr_ctrl, sdrc_cs1->actim_ctrla, sdrc_cs1->actim_ctrlb, sdrc_cs1->mr);else omap3_configure_core_dpll ( - new_div, unlock_dll, c, rate > clk->rate, + new_div, unlock_dll, c, rate > clkrate, sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla, sdrc_cs0->actim_ctrlb, sdrc_cs0->mr,0 ,0 ,0 ,0 );
arch/arm/mach-omap2/clkt_clksel.c +57 -34
220 lines not on this page · raw message
arch/arm/mach-omap2/clkt_dpll.c +15 -11
@@ -87,7 +87,7 @@ static int _dpll_test_fint(struct clk *clk, u8 n) dd = clk->dpll_data;/* DPLL divider must result in a valid jitter correction val */ - fint = clk->parent->rate / n; + fint =__clk_get_rate (__clk_get_parent (clk)) / n;if (cpu_is_omap24xx ()) {/* Should not be called for OMAP2, so warn if it is called */
@@ -252,16 +252,16 @@ u32 omap2_get_dpll_rate(struct clk *clk)if (cpu_is_omap24xx ()) {if (v ==OMAP2XXX_EN_DPLL_LPBYPASS || v ==OMAP2XXX_EN_DPLL_FRBYPASS ) -return dd->clk_bypass->rate; +return __clk_get_rate (dd->clk_bypass); }else if (cpu_is_omap34xx ()) {if (v ==OMAP3XXX_EN_DPLL_LPBYPASS || v ==OMAP3XXX_EN_DPLL_FRBYPASS ) -return dd->clk_bypass->rate; +return __clk_get_rate (dd->clk_bypass); }else if (cpu_is_omap44xx ()) {if (v ==OMAP4XXX_EN_DPLL_LPBYPASS || v ==OMAP4XXX_EN_DPLL_FRBYPASS || v ==OMAP4XXX_EN_DPLL_MNBYPASS ) -return dd->clk_bypass->rate; +return __clk_get_rate (dd->clk_bypass); } v =__raw_readl (dd->mult_div1_reg);
@@ -270,7 +270,7 @@ u32 omap2_get_dpll_rate(struct clk *clk) dpll_div = v & dd->div1_mask; dpll_div >>=__ffs (dd->div1_mask); - dpll_clk = (long long )dd->clk_ref->rate * dpll_mult; + dpll_clk = (long long )__clk_get_rate (dd->clk_ref) * dpll_mult;do_div (dpll_clk, dpll_div +1 );return dpll_clk;
@@ -296,16 +296,20 @@ long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate)unsigned long scaled_rt_rp;unsigned long new_rate =0 ;struct dpll_data *dd; +unsigned long ref_rate; +const char *clk_name;if (!clk || !clk->dpll_data)return ~0 ; dd = clk->dpll_data; + ref_rate =__clk_get_rate (dd->clk_ref); + clk_name =__clk_get_name (clk);pr_debug ("clock: %s: starting DPLL round_rate, target rate %ld\n" , - clk->name, target_rate); + clk_name, target_rate); - scaled_rt_rp = target_rate / (dd->clk_ref->rate /DPLL_SCALE_FACTOR ); + scaled_rt_rp = target_rate / (ref_rate /DPLL_SCALE_FACTOR ); scaled_max_m = dd->max_multiplier *DPLL_SCALE_FACTOR ; dd->last_rounded_rate =0 ;
@@ -332,14 +336,14 @@ long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate)break ; r =_dpll_test_mult (&m, n, &new_rate, target_rate, - dd->clk_ref->rate); + ref_rate);/* m can't be set low enough for this n - try with a larger n */ if (r ==DPLL_MULT_UNDERFLOW )continue ;pr_debug ("clock: %s: m = %d: n = %d: new_rate = %ld\n" , - clk->name, m, n, new_rate); + clk_name, m, n, new_rate);if (target_rate == new_rate) { dd->last_rounded_m = m;
@@ -350,8 +354,8 @@ long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate) }if (target_rate != new_rate) { -pr_debug ("clock: %s: cannot round to rate %ld\n" , clk->name, - target_rate); +pr_debug ("clock: %s: cannot round to rate %ld\n" , + clk_name, target_rate);return ~0 ; }
arch/arm/mach-omap2/clock.c +7 -4
@@ -76,7 +76,7 @@ static void _omap2_module_wait_ready(struct clk *clk) clk->ops->find_idlest (clk, &idlest_reg, &idlest_bit, &idlest_val);omap2_cm_wait_idlest (idlest_reg, (1 << idlest_bit), idlest_val, - clk->name); +__clk_get_name (clk)); }/* Public functions */
@@ -92,18 +92,21 @@ static void _omap2_module_wait_ready(struct clk *clk)void omap2_init_clk_clkdm (struct clk *clk) {struct clockdomain *clkdm; +const char *clk_name;if (!clk->clkdm_name)return ; + clk_name =__clk_get_name (clk); + clkdm =clkdm_lookup (clk->clkdm_name);if (clkdm) {pr_debug ("clock: associated clk %s to clkdm %s\n" , - clk->name, clk->clkdm_name); + clk_name, clk->clkdm_name); clk->clkdm = clkdm; }else { -pr_debug ("clock: could not associate clk %s to " -"clkdm %s\n" , clk->name, clk->clkdm_name); +pr_debug ("clock: could not associate clk %s to clkdm %s\n" , + clk_name, clk->clkdm_name); } }
arch/arm/mach-omap2/dpll3xxx.c +28 -20
162 lines not on this page · raw message
arch/arm/mach-omap2/omap_hwmod.c +3 -3
@@ -695,7 +695,7 @@ static int _init_main_clk(struct omap_hwmod *oh)if (!oh->_clk->clkdm)pr_warning ("omap_hwmod: %s: missing clockdomain for %s.\n" , - oh->main_clk, oh->_clk->name); + oh->name, oh->main_clk);return ret; }
@@ -852,7 +852,7 @@ static void _enable_optional_clocks(struct omap_hwmod *oh)for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i >0 ; i--, oc++)if (oc->_clk) {pr_debug ("omap_hwmod: enable %s:%s\n" , oc->role, - oc->_clk->name); +__clk_get_name (oc->_clk));clk_enable (oc->_clk); } }
@@ -867,7 +867,7 @@ static void _disable_optional_clocks(struct omap_hwmod *oh)for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i >0 ; i--, oc++)if (oc->_clk) {pr_debug ("omap_hwmod: disable %s:%s\n" , oc->role, - oc->_clk->name); +__clk_get_name (oc->_clk));clk_disable (oc->_clk); } }
arch/arm/mach-omap2/pm.c +1 -1
@@ -188,7 +188,7 @@ static int __init omap2_set_init_voltage(char *vdd_name, char *clk_name, goto exit; } - freq = clk->rate; + freq =clk_get_rate (clk);clk_put (clk);rcu_read_lock ();
arch/arm/plat-omap/include/plat/clock.h +5 -0
@@ -19,6 +19,11 @@ struct module;struct clk ;struct clockdomain ; +/* Temporary, needed during the common clock framework conversion */ +#define __clk_get_name (clk) (clk->name) +#define __clk_get_parent (clk) (clk->parent) +#define __clk_get_rate (clk) (clk->rate) +/** * struct clkops - some clock function pointers * @enable: fn ptr that enables the current clock in hardware
Signature · 1 line
1.7.9.5
Paul Walmsley
maintainerv4 cover Prepare for OMAP2+ movement to Common Clk
In reply to Rajendra NayakHi Rajendra
Quoted 3 lines · Rajendra Nayak
Changes in v4:
* Added *hack* comments aroundclk_prepareusage in hwmod rebased on 3.6-rc
Assuming this is so (haven't looked closely at this series yet), and after the existing comments are taken into consideration and a new version reposted, will queue this series for 3.7.
Care to respin your series that converts the data also, on top of your new version of this series? We should try to get that into 3.7 also. BTW are you still waiting for something from Vaibhav Hiremath for this? Or can the scripts convert the existing clock33xx_data.c also?
- Paul
v4 cover Prepare for OMAP2+ movement to Common Clk
Quoted 8 lines · Paul Walmsley
Hi Rajendra
Quoted 3 lines · Rajendra Nayak
Changes in v4:
* Added *hack* comments aroundclk_prepareusage in hwmod rebased on 3.6-rc
Quoted 9 lines
Assuming this is so (haven't looked closely at this series yet), and after the existing comments are taken into consideration and a new version reposted, will queue this series for 3.7.
Care to respin your series that converts the data also, on top of your new version of this series? We should try to get that into 3.7 also. BTW are you still waiting for something from Vaibhav Hiremath for this? Or can the scripts convert the existing
clock33xx_data.calso?
I believe I have already shared all the patches with Rajendra, so please let me know if anything is pending on me.
Thanks,
Vaibhav
Quoted 8 lines
- Paul
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