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MX28: SPI: Fix CTRL0 not being written at end of DMA transfer

PATCH New Marek Vasut 2 participants 3 messages Aug 29, 2012 – Sep 1, 2012

Subsystems (2)
Arm i.MX and Layerscape SPI
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Marek Vasut

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#0 lore raw

PATCH 1/1 MX28: SPI: Fix CTRL0 not being written at end of DMA transfer

The final DMA descriptor doesn't properly write CTRL0 register during the DMA transfer. Properly write CTRL0 to make sure the transmission is complete.

Signed-off-by Marek Vasut <[email protected]>
Cc Fabio Estevam <[email protected]>
Cc Otavio Salvador <[email protected]>
Cc Stefano Babic <[email protected]>
---
 drivers/spi/mxs_spi.c |   20 +++++++++++++++++---
 1 file changed, 17 insertions(+), 3 deletions(-)
drivers/spi/mxs_spi.c +17 -3
index 168dbe4..5ee0ea1 100644
@@ -226,6 +226,7 @@ static int mxs_spi_xfer_dma(struct mxs_spi_slave *slave,
 	uint32_t cache_data_count;
 	int dmach;
 	int tl;
+	int ret = 0;
 
 	ALLOC_CACHE_ALIGN_BUFFER(struct mxs_dma_desc, desc, desc_count);
 

@@ -302,12 +303,25 @@ static int mxs_spi_xfer_dma(struct mxs_spi_slave *slave,
 			MXS_DMA_DESC_IRQ | MXS_DMA_DESC_DEC_SEM;
 	if (flags & SPI_XFER_END) {
 		ctrl0 &= ~SSP_CTRL0_LOCK_CS;
-		dp->cmd.pio_words[0] = ctrl0 | SSP_CTRL0_IGNORE_CRC;
+		ctrl0 |= SSP_CTRL0_IGNORE_CRC;
+		dp->cmd.pio_words[0] = ctrl0;
 	}
 	mxs_dma_desc_append(dmach, dp);
 
 	if (mxs_dma_go(dmach))
-		return -EINVAL;
+		ret = -EINVAL;
+
+	/*
+	 * The DMA contains further hidden gems, like the last transfer
+	 * not writing the CTRL0 PIO word properly. Write the PIO word
+	 * directly here for proper operation. This issue was detected
+	 * on S25FL064P chip by issuing:
+	 *
+	 *   sf probe 2:0 ; sf read 0x42000000 0 0x800000 ; sf probe 2:0
+	 *
+	 * This resulted in garbled subsequent probe.
+	 */
+	writel(ctrl0, &ssp_regs->hw_ssp_ctrl0_reg);
 
 	/* The data arrived into DRAM, invalidate cache over them */
 	if (!write) {

@@ -315,7 +329,7 @@ static int mxs_spi_xfer_dma(struct mxs_spi_slave *slave,
 			(uint32_t)(data + cache_data_count));
 	}
 
-	return 0;
+	return ret;
 }
 
 int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
Signature · 1 line
1.7.10.4
author
#1 lore raw

PATCH 1/1 MX28: SPI: Fix CTRL0 not being written at end of DMA transfer

Quoted 8 lines

The final DMA descriptor doesn't properly write CTRL0 register during the DMA transfer. Properly write CTRL0 to make sure the transmission is complete.

Signed-off-by Marek Vasut <[email protected]>
Cc Fabio Estevam <[email protected]>
Cc Otavio Salvador <[email protected]>
Cc Stefano Babic <[email protected]>

!!

Please discard

Quoted 45 lines
---
 drivers/spi/mxs_spi.c |   20 +++++++++++++++++---
 1 file changed, 17 insertions(+), 3 deletions(-)
drivers/spi/mxs_spi.c +16 -2
index 168dbe4..5ee0ea1 100644
@@ -226,6 +226,7 @@ static int mxs_spi_xfer_dma(struct mxs_spi_slave
 *slave, uint32_t cache_data_count;
 	int dmach;
 	int tl;
+	int ret = 0;
 
 	ALLOC_CACHE_ALIGN_BUFFER(struct mxs_dma_desc, desc, desc_count);
 

@@ -302,12 +303,25 @@ static int mxs_spi_xfer_dma(struct mxs_spi_slave
 *slave, MXS_DMA_DESC_IRQ | MXS_DMA_DESC_DEC_SEM;
 	if (flags & SPI_XFER_END) {
 		ctrl0 &= ~SSP_CTRL0_LOCK_CS;
-		dp->cmd.pio_words[0] = ctrl0 | SSP_CTRL0_IGNORE_CRC;
+		ctrl0 |= SSP_CTRL0_IGNORE_CRC;
+		dp->cmd.pio_words[0] = ctrl0;
 	}
 	mxs_dma_desc_append(dmach, dp);
 
 	if (mxs_dma_go(dmach))
-		return -EINVAL;
+		ret = -EINVAL;
+
+	/*
+	 * The DMA contains further hidden gems, like the last transfer
+	 * not writing the CTRL0 PIO word properly. Write the PIO word
+	 * directly here for proper operation. This issue was detected
+	 * on S25FL064P chip by issuing:
+	 *
+	 *   sf probe 2:0 ; sf read 0x42000000 0 0x800000 ; sf probe 2:0
+	 *
+	 * This resulted in garbled subsequent probe.
+	 */
+	writel(ctrl0, &ssp_regs->hw_ssp_ctrl0_reg);
 
 	/* The data arrived into DRAM, invalidate cache over them */
 	if (!write) {

drivers/spi/mxs_spi.c static int mxs_spi_xfer_dma(struct mxs_spi_slave · line 335

Quoted 8 lines
drivers/spi/mxs_spi.c +1 -1
@@ -315,7 +329,7 @@ static int mxs_spi_xfer_dma(struct mxs_spi_slave
 *slave, (uint32_t)(data + cache_data_count));
 	}
 
-	return 0;
+	return ret;
 }
 
 int spi_xfer(struct spi_slave *slave, unsigned int bitlen,

Best regards,
Marek Vasut

#2 lore raw

PATCH 1/1 MX28: SPI: Fix CTRL0 not being written at end of DMA transfer

Quoted 4 lines · Marek Vasut
Quoted 4 lines

The final DMA descriptor doesn't properly write CTRL0 register during the DMA transfer. Properly write CTRL0 to make sure the transmission is complete.

Quoted 9 lines
Quoted 4 lines
Signed-off-by Marek Vasut <[email protected]>
Cc Fabio Estevam <[email protected]>
Cc Otavio Salvador <[email protected]>
Cc Stefano Babic <[email protected]>

!!

Please discard

Done !

Stefano

Signature · 5 lines
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