Skip to contentSkip to conversation

eb_cpux9k2: fix chip select

PATCH New Jens Scharsig 3 participants 3 messages Apr 29, 2012 – Sep 3, 2012

lore
Share & tools
lore

Jens Scharsig

author
#0 lore raw

PATCH 1/1 eb_cpux9k2: fix chip select

* fix chip select initialization for frame buffer, this will be increase frame buffer access speed

Signed-off-by Jens Scharsig <[email protected]>
---
 board/BuS/eb_cpux9k2/cpux9k2.c |    6 +++---
 1 files changed, 3 insertions(+), 3 deletions(-)
board/BuS/eb_cpux9k2/cpux9k2.c +3 -3
index 54f9b64..15a31be 100644
@@ -269,9 +269,9 @@ int drv_video_init(void)
 		display_height = 256;
 	printf("%ld x %ld pixel matrix\n", display_width, display_height);
 
-	/* RWH = 7 | RWS =7  | TDF = 15 | NWS = 0x7F */
-	csr =	AT91_SMC_CSR_RWHOLD(7) | AT91_SMC_CSR_RWSETUP(7) |
-		AT91_SMC_CSR_TDF(15) | AT91_SMC_CSR_NWS(127) |
+	/* RWH = 2 | RWS =2  | TDF = 4 | NWS = 0x6 */
+	csr =	AT91_SMC_CSR_RWHOLD(2) | AT91_SMC_CSR_RWSETUP(2) |
+		AT91_SMC_CSR_TDF(4) | AT91_SMC_CSR_NWS(6) |
 		AT91_SMC_CSR_ACSS_STANDARD | AT91_SMC_CSR_DBW_16 |
 		AT91_SMC_CSR_BAT_16 | AT91_SMC_CSR_WSEN;
 	writel(csr, &mc->smc.csr[2]);
Signature · 1 line
1.7.7
#1 lore raw

PATCH 1/1 eb_cpux9k2: fix chip select

Dear Andreas Bie?mann,

Please could you apply this open patch.
I've just tested this against the current atmel and master tree. It works.

best regards

Jens Scharsig

Quoted 26 lines

* fix chip select initialization for frame buffer, this will be increase frame buffer access speed

Signed-off-by Jens Scharsig <[email protected]>
---
 board/BuS/eb_cpux9k2/cpux9k2.c |    6 +++---
 1 files changed, 3 insertions(+), 3 deletions(-)
board/BuS/eb_cpux9k2/cpux9k2.c +3 -3
index 54f9b64..15a31be 100644
@@ -269,9 +269,9 @@ int drv_video_init(void)
 		display_height = 256;
 	printf("%ld x %ld pixel matrix\n", display_width, display_height);
 
-	/* RWH = 7 | RWS =7  | TDF = 15 | NWS = 0x7F */
-	csr =	AT91_SMC_CSR_RWHOLD(7) | AT91_SMC_CSR_RWSETUP(7) |
-		AT91_SMC_CSR_TDF(15) | AT91_SMC_CSR_NWS(127) |
+	/* RWH = 2 | RWS =2  | TDF = 4 | NWS = 0x6 */
+	csr =	AT91_SMC_CSR_RWHOLD(2) | AT91_SMC_CSR_RWSETUP(2) |
+		AT91_SMC_CSR_TDF(4) | AT91_SMC_CSR_NWS(6) |
 		AT91_SMC_CSR_ACSS_STANDARD | AT91_SMC_CSR_DBW_16 |
 		AT91_SMC_CSR_BAT_16 | AT91_SMC_CSR_WSEN;
 	writel(csr, &mc->smc.csr[2]);