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powerpc/mpc85xx: fix Unicode characters in release.S

PATCH New Timur Tabi 4 participants 10 messages Aug 31, 2012 – Sep 11, 2012

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Timur Tabi

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#0 lore raw

PATCH 1/5 powerpc/mpc85xx: fix Unicode characters in release.S

The previous commit unintentionally used the Unicode version of the apostrophy. Replace it with the normal ASCII version.

Signed-off-by Timur Tabi <[email protected]>
---
 arch/powerpc/cpu/mpc85xx/release.S |   24 ++++++++++++------------
 1 files changed, 12 insertions(+), 12 deletions(-)
arch/powerpc/cpu/mpc85xx/release.S +12 -12
index 22e73e0..8662ae4 100644
@@ -159,20 +159,20 @@ __secondary_start_page:
 /*
  * PIR definition for E6500
  * 0-17 Reserved (logic 0s)
- * 8-19 CHIP_ID,    2?b00      - SoC 1
+ * 8-19 CHIP_ID,    2'b00      - SoC 1
  *                  all others - reserved
- * 20-24 CLUSTER_ID 5?b00000   - CCM 1
+ * 20-24 CLUSTER_ID 5'b00000   - CCM 1
  *                  all others - reserved
- * 25-26 CORE_CLUSTER_ID 2?b00 - cluster 1
- *                       2?b01 - cluster 2
- *                       2?b10 - cluster 3
- *                       2?b11 - cluster 4
- * 27-28 CORE_ID         2?b00 - core 0
- *                       2?b01 - core 1
- *                       2?b10 - core 2
- *                       2?b11 - core 3
- * 29-31 THREAD_ID       3?b000 - thread 0
- *                       3?b001 - thread 1
+ * 25-26 CORE_CLUSTER_ID 2'b00 - cluster 1
+ *                       2'b01 - cluster 2
+ *                       2'b10 - cluster 3
+ *                       2'b11 - cluster 4
+ * 27-28 CORE_ID         2'b00 - core 0
+ *                       2'b01 - core 1
+ *                       2'b10 - core 2
+ *                       2'b11 - core 3
+ * 29-31 THREAD_ID       3'b000 - thread 0
+ *                       3'b001 - thread 1
  */
 	rlwinm  r4,r0,29,25,31
 #elif	defined(CONFIG_E500MC)
Signature · 1 line
1.7.3.4
author
#1 lore raw

PATCH 2/5 powerpc/85xx: introduce SET_PCI_LIODN_BASE, for setting PCI LIODNs

From: Laurentiu Tudor <[email protected]>

The liodn for the new PCIE controller included in P5040DS is no longer set through a register in the guts register block but with one in the PCIE register block itself. Update the PCIE CCSR structure to add the new liodn register and add a new dedicated SET_PCI_LIODN_BASE macro that puts the liodn in the correct register.

Signed-off-by Laurentiu Tudor <[email protected]>
Signed-off-by Timur Tabi <[email protected]>
---
 arch/powerpc/include/asm/fsl_liodn.h  |    5 +++++
 arch/powerpc/include/asm/immap_85xx.h |    4 +++-
 2 files changed, 8 insertions(+), 1 deletions(-)
arch/powerpc/include/asm/fsl_liodn.h +5 -0
index a9973b8..a37983e 100644
@@ -94,6 +94,11 @@ extern void fdt_fixup_liodn(void *blob);
 	SET_GUTS_LIODN(compat, liodn, pex##pciNum##liodnr,\
 		CONFIG_SYS_MPC85xx_PCIE##pciNum##_OFFSET)
 
+#define SET_PCI_LIODN_BASE(compat, pciNum, liodn) \
+	SET_LIODN_ENTRY_1(compat, liodn,\
+		offsetof(ccsr_pcix_t, liodn_base) + CONFIG_SYS_MPC85xx_PCIE##pciNum##_OFFSET,\
+		CONFIG_SYS_MPC85xx_PCIE##pciNum##_OFFSET)
+
 /* reg nodes for DMA start @ 0x300 */
 #define SET_DMA_LIODN(dmaNum, liodn) \
 	SET_GUTS_LIODN("fsl,eloplus-dma", liodn, dma##dmaNum##liodnr,\
arch/powerpc/include/asm/immap_85xx.h +3 -1
index 7de33a7..6c11178 100644
@@ -296,7 +296,9 @@ typedef struct ccsr_pcix {
 	u32	cfg_addr;	/* PCIX Configuration Addr */
 	u32	cfg_data;	/* PCIX Configuration Data */
 	u32	int_ack;	/* PCIX IRQ Acknowledge */
-	u8	res1[3060];
+	u8	res000c[52];
+	u32	liodn_base;	/* PCIX LIODN base register */
+	u8	res0044[3004];
 	u32	potar0;		/* PCIX Outbound Transaction Addr 0 */
 	u32	potear0;	/* PCIX Outbound Translation Extended Addr 0 */
 	u32	powbar0;	/* PCIX Outbound Window Base Addr 0 */
Signature · 1 line
1.7.3.4
author
#2 lore raw

PATCH 3/5 powerpc/85xx: move SRIO configuration out of corenet_ds.h

In reply to Timur Tabi

The P5040 does not have SRIO, so don't put the SRIO definitions in corenet_ds.h. They belong in the board-specific header files.

Signed-off-by Timur Tabi <[email protected]>
---
 include/configs/P3041DS.h    |    4 ++++
 include/configs/P4080DS.h    |    4 ++++
 include/configs/P5020DS.h    |    4 ++++
 include/configs/corenet_ds.h |    4 ----
 4 files changed, 12 insertions(+), 4 deletions(-)
include/configs/P3041DS.h +4 -0
index 98e7a42..cf184e7 100644
@@ -36,6 +36,10 @@
 #define CONFIG_PCIE4
 #define CONFIG_SYS_DPAA_RMAN
 
+#define CONFIG_SYS_SRIO
+#define CONFIG_SRIO1			/* SRIO port 1 */
+#define CONFIG_SRIO2			/* SRIO port 2 */
+
 #define CONFIG_ICS307_REFCLK_HZ		25000000  /* ICS307 ref clk freq */
 
 #include "corenet_ds.h"
include/configs/P4080DS.h +4 -0
index d6f2f5c..53979dd 100644
@@ -33,6 +33,10 @@
 #define CONFIG_MMC
 #define CONFIG_PCIE3
 
+#define CONFIG_SYS_SRIO
+#define CONFIG_SRIO1			/* SRIO port 1 */
+#define CONFIG_SRIO2			/* SRIO port 2 */
+
 #define CONFIG_ICS307_REFCLK_HZ		33333000  /* ICS307 ref clk freq */
 
 #include "corenet_ds.h"
include/configs/P5020DS.h +4 -0
index 8625f76..7018d7a 100644
@@ -37,6 +37,10 @@
 #define CONFIG_SYS_FSL_RAID_ENGINE
 #define CONFIG_SYS_DPAA_RMAN
 
+#define CONFIG_SYS_SRIO
+#define CONFIG_SRIO1			/* SRIO port 1 */
+#define CONFIG_SRIO2			/* SRIO port 2 */
+
 #define CONFIG_ICS307_REFCLK_HZ		25000000  /* ICS307 ref clk freq */
 
 #include "corenet_ds.h"
include/configs/corenet_ds.h +0 -4
index f4f9bd1..0f59fb2 100644
@@ -76,10 +76,6 @@
 #define CONFIG_FSL_PCI_INIT		/* Use common FSL init code */
 #define CONFIG_SYS_PCI_64BIT		/* enable 64-bit PCI resources */
 
-#define CONFIG_SYS_SRIO
-#define CONFIG_SRIO1			/* SRIO port 1 */
-#define CONFIG_SRIO2			/* SRIO port 2 */
-
 #define CONFIG_FSL_LAW			/* Use common FSL init code */
 
 #define CONFIG_ENV_OVERWRITE
Signature · 1 line
1.7.3.4
author
#3 lore raw

PATCH 4/5 powerpc/85xx: Add P5040 processor support

In reply to Timur Tabi

Add support for the Freescale P5040 SOC, which is similar to the P5020. Features of the P5040 are:

Four P5040 single-threaded e5500 cores built
Up to 2.4 GHz with 64-bit ISA support
Three levels of instruction: user, supervisor, hypervisor
CoreNet platform cache (CPC)
2.0 MB configures as dual 1 MB blocks hierarchical interconnect fabric
Two 64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving
support Up to 1600MT/s
Memory pre-fetch engine
DPAA incorporating acceleration for the following functions
Packet parsing, classification, and distribution (FMAN) Queue management for scheduling, packet sequencing and congestion management (QMAN)
Hardware buffer management for buffer allocation and de-allocation (BMAN)
Cryptography acceleration (SEC 5.0) at up to 40 Gbps SerDes 20 lanes at up to 5 Gbps
Supports SGMII, XAUI, PCIe rev1.1/2.0, SATA Ethernet interfaces Two 10 Gbps Ethernet MACs
Ten 1 Gbps Ethernet MACs
High-speed peripheral interfaces
Two PCI Express 2.0/3.0 controllers
Additional peripheral interfaces
Two serial ATA (SATA 2.0) controllers
Two high-speed USB 2.0 controllers with integrated PHY Enhanced secure digital host controller (SD/MMC/eMMC) Enhanced serial peripheral interface (eSPI)
Two I2C controllers
Four UARTs
Integrated flash controller supporting NAND and NOR flash
DMA
Dual four channel
Support for hardware virtualization and partitioning enforcement
Extra privileged level for hypervisor support
QorIQ Trust Architecture 1.1
Secure boot, secure debug, tamper detection, volatile key storage

Signed-off-by Timur Tabi <[email protected]>
---
 arch/powerpc/cpu/mpc85xx/Makefile             |    3 +
 arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c |   43 ++++++++
 arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.h |   11 ++
 arch/powerpc/cpu/mpc85xx/p5040_ids.c          |  131 +++++++++++++++++++++++++
 arch/powerpc/cpu/mpc85xx/p5040_serdes.c       |  110 +++++++++++++++++++++
 arch/powerpc/cpu/mpc85xx/speed.c              |    2 +
 arch/powerpc/cpu/mpc8xxx/cpu.c                |    2 +
 arch/powerpc/include/asm/config_mpc85xx.h     |   28 +++++
 arch/powerpc/include/asm/immap_85xx.h         |   12 +++
 arch/powerpc/include/asm/processor.h          |    2 +
 10 files changed, 344 insertions(+), 0 deletions(-)
 create mode 100644 arch/powerpc/cpu/mpc85xx/p5040_ids.c
 create mode 100644 arch/powerpc/cpu/mpc85xx/p5040_serdes.c
arch/powerpc/cpu/mpc85xx/Makefile +3 -0
index 33e93c8..aad50f3 100644
@@ -66,6 +66,7 @@ COBJS-$(CONFIG_PPC_P2041)	+= ddr-gen3.o
 COBJS-$(CONFIG_PPC_P3041)	+= ddr-gen3.o
 COBJS-$(CONFIG_PPC_P4080)	+= ddr-gen3.o
 COBJS-$(CONFIG_PPC_P5020)	+= ddr-gen3.o
+COBJS-$(CONFIG_PPC_P5040)	+= ddr-gen3.o
 COBJS-$(CONFIG_BSC9131)		+= ddr-gen3.o
 
 COBJS-$(CONFIG_CPM2)	+= ether_fcc.o

@@ -80,6 +81,7 @@ COBJS-$(CONFIG_PPC_P2041) += p2041_ids.o
 COBJS-$(CONFIG_PPC_P3041) += p3041_ids.o
 COBJS-$(CONFIG_PPC_P4080) += p4080_ids.o
 COBJS-$(CONFIG_PPC_P5020) += p5020_ids.o
+COBJS-$(CONFIG_PPC_P5040) += p5040_ids.o
 
 COBJS-$(CONFIG_QE)	+= qe_io.o
 COBJS-$(CONFIG_CPM2)	+= serial_scc.o

@@ -110,6 +112,7 @@ COBJS-$(CONFIG_PPC_P2041) += p2041_serdes.o
 COBJS-$(CONFIG_PPC_P3041) += p3041_serdes.o
 COBJS-$(CONFIG_PPC_P4080) += p4080_serdes.o
 COBJS-$(CONFIG_PPC_P5020) += p5020_serdes.o
+COBJS-$(CONFIG_PPC_P5040) += p5040_serdes.o
 
 COBJS	= $(COBJS-y)
 COBJS	+= cpu.o
arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c +43 -0

59 lines not on this page · raw message

arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.h +11 -0
index f261351..96d14ec 100644
@@ -22,13 +22,24 @@
 #ifndef __FSL_CORENET_SERDES_H
 #define __FSL_CORENET_SERDES_H
 
+#if defined(CONFIG_PPC_P5040)
+/*
+ * The fourth SerDes bank is on SerDes2, but U-boot currently only supports
+ * one SerDes controller.  For now, pretend that we have three banks and 18
+ * lanes.
+ */
 #define SRDS_MAX_LANES		18
 #define SRDS_MAX_BANK		3
+#else
+#define SRDS_MAX_LANES		18
+#define SRDS_MAX_BANK		3
+#endif
 
 enum srds_bank {
 	FSL_SRDS_BANK_1  = 0,
 	FSL_SRDS_BANK_2  = 1,
 	FSL_SRDS_BANK_3  = 2,
+	FSL_SRDS_BANK_4  = 3,
 };
 
 int is_serdes_prtcl_valid(u32 prtcl);
arch/powerpc/cpu/mpc85xx/p5040_ids.c new file +131 -0

131 lines not on this page · raw message

arch/powerpc/cpu/mpc85xx/p5040_serdes.c new file +110 -0

110 lines not on this page · raw message

arch/powerpc/cpu/mpc85xx/speed.c +2 -0
index abfeb26..6dd9e8d 100644
@@ -112,6 +112,8 @@ void get_sys_info (sys_info_t * sysInfo)
 #define HWA_ASYNC_DIV	0x04000000
 #if (CONFIG_SYS_FSL_NUM_CC_PLLS == 2)
 #define HWA_CC_PLL	1
+#elif (CONFIG_SYS_FSL_NUM_CC_PLLS == 3)
+#define HWA_CC_PLL	2
 #elif (CONFIG_SYS_FSL_NUM_CC_PLLS == 4)
 #define HWA_CC_PLL	2
 #else
arch/powerpc/cpu/mpc8xxx/cpu.c +2 -0
index 78a8f92..3dfdd4b 100644
@@ -73,6 +73,8 @@ struct cpu_type cpu_type_list [] = {
 	CPU_TYPE_ENTRY(P4080, P4080, 8),
 	CPU_TYPE_ENTRY(P5010, P5010, 1),
 	CPU_TYPE_ENTRY(P5020, P5020, 2),
+	CPU_TYPE_ENTRY(P5021, P5021, 2),
+ 	CPU_TYPE_ENTRY(P5040, P5040, 4),
 	CPU_TYPE_ENTRY(BSC9130, 9130, 1),
 	CPU_TYPE_ENTRY(BSC9131, 9131, 1),
 #elif defined(CONFIG_MPC86xx)
arch/powerpc/include/asm/config_mpc85xx.h +28 -0
index aa27741..a70fffa 100644
@@ -433,6 +433,34 @@
 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV	0x10
 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xc0000000
 
+#elif defined(CONFIG_PPC_P5040)
+#define CONFIG_MAX_CPUS			4
+#define CONFIG_SYS_FSL_NUM_CC_PLLS	3
+#define CONFIG_SYS_FSL_NUM_LAWS		32
+#define CONFIG_SYS_FSL_SEC_COMPAT	4
+#define CONFIG_SYS_NUM_FMAN		2
+#define CONFIG_SYS_NUM_FM1_DTSEC	5
+#define CONFIG_SYS_NUM_FM1_10GEC	1
+#define CONFIG_SYS_NUM_FM2_DTSEC	5
+#define CONFIG_SYS_NUM_FM2_10GEC	1
+#define CONFIG_NUM_DDR_CONTROLLERS	2
+#define CONFIG_SYS_FM_MURAM_SIZE	0x28000
+#define CONFIG_SYS_FSL_TBCLK_DIV	16
+#define CONFIG_SYS_FSL_PCIE_COMPAT	"fsl,qoriq-pcie-v2.4"
+#define CONFIG_SYS_CCSRBAR_DEFAULT	0xfe000000
+#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
+#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
+#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
+#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
+#define CONFIG_SYS_FSL_ERRATUM_USB138
+#define CONFIG_SYS_FSL_ERRATUM_DDR_A003
+#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
+#define CONFIG_SYS_FSL_ERRATUM_A004699
+#define CONFIG_SYS_FSL_ELBC_MULTIBIT_ECC
+#define CONFIG_SYS_FSL_ERRATUM_A004510
+#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV	0x10
+#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
+
 #elif defined(CONFIG_BSC9131)
 #define CONFIG_MAX_CPUS			1
 #define CONFIG_FSL_SDHC_V2_3
arch/powerpc/include/asm/immap_85xx.h +12 -0
index 6c11178..75e663f 100644
@@ -1761,6 +1761,7 @@ typedef struct ccsr_gur {
 #define FSL_CORENET_RCWSR5_DDR_SYNC		0x00000080
 #define FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT		 7
 #define FSL_CORENET_RCWSR5_SRDS_EN		0x00002000
+#define FSL_CORENET_RCWSR5_SRDS2_EN		0x00001000
 #define FSL_CORENET_RCWSR6_BOOT_LOC	0x0f800000
 #define FSL_CORENET_RCWSRn_SRDS_LPD_B2		0x3c000000 /* bits 162..165 */
 #define FSL_CORENET_RCWSRn_SRDS_LPD_B3		0x003c0000 /* bits 170..173 */

@@ -1786,6 +1787,15 @@ typedef struct ccsr_gur {
 #define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC5_MII		0x00100000
 #define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC5_NONE		0x00180000
 #endif
+#if defined(CONFIG_PPC_P5040)
+#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC5_RGMII        0x00000000
+#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC5_MII          0x00800000
+#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC5_NONE         0x00c00000
+#define FSL_CORENET_RCWSR11_EC2                 0x00180000 /* bits 363..364 */
+#define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_RGMII        0x00000000
+#define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_MII          0x00100000
+#define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_NONE         0x00180000
+#endif
 	u8	res18[192];
 	u32	scratchrw[4];	/* Scratch Read/Write */
 	u8	res19[240];

@@ -2395,6 +2405,7 @@ typedef struct serdes_corenet {
 #define SRDS_RSTCTL_SDPD	0x00000020
 		u32	pllcr0; /* PLL Control Register 0 */
 #define SRDS_PLLCR0_RFCK_SEL_MASK	0x30000000
+#define SRDS_PLLCR0_PVCOCNT_EN		0x02000000
 #define SRDS_PLLCR0_RFCK_SEL_100	0x00000000
 #define SRDS_PLLCR0_RFCK_SEL_125	0x10000000
 #define SRDS_PLLCR0_RFCK_SEL_156_25	0x20000000

@@ -2423,6 +2434,7 @@ typedef struct serdes_corenet {
 		u32	gcr0;	/* General Control Register 0 */
 #define SRDS_GCR0_RRST			0x00400000
 #define SRDS_GCR0_1STLANE		0x00010000
+#define SRDS_GCR0_UOTHL			0x00100000
 		u32	gcr1;	/* General Control Register 1 */
 #define SRDS_GCR1_REIDL_CTL_MASK	0x001f0000
 #define SRDS_GCR1_REIDL_CTL_PCIE	0x00100000
arch/powerpc/include/asm/processor.h +2 -0
index 36695e2..fd0160a 100644
@@ -1095,6 +1095,8 @@
 #define SVR_P4080	0x820000
 #define SVR_P5010	0x822100
 #define SVR_P5020	0x822000
+#define SVR_P5021	0X820500
+#define SVR_P5040	0x820400
 
 #define SVR_8610	0x80A000
 #define SVR_8641	0x809000
Signature · 1 line
1.7.3.4
#4 lore raw

PATCH 4/5 powerpc/85xx: Add P5040 processor support

arch/powerpc/cpu/mpc85xx/p5040_ids.c line 65

Quoted 3 lines · Timur Tabi
arch/powerpc/cpu/mpc85xx/p5040_ids.c new file +3 -0
+	SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 1, 193),
+	SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 2, 194),
+	SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 3, 195),

You're only allowing for one LIODN per PCIe controller, which defeats the purpose of the new PCIe LIODN mechanism.

Please allocate several contiguous LIODNs per controller, set the base to the first one, and enumerate the rest in a device tree property for the OS to use.

-Scott

#5 lore raw

PATCH 4/5 powerpc/85xx: Add P5040 processor support

In reply to Timur Tabi
Quoted 18 lines · On Fri, 31 Aug 2012 15:25:35 -0500 Timur Tabi <[email protected]> wrote:

Add support for the Freescale P5040 SOC, which is similar to the P5020. Features of the P5040 are:

Four P5040 single-threaded e5500 cores built
Up to 2.4 GHz with 64-bit ISA support
Three levels of instruction: user, supervisor, hypervisor
CoreNet platform cache (CPC)
2.0 MB configures as dual 1 MB blocks hierarchical interconnect fabric
Two 64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving
support Up to 1600MT/s
Memory pre-fetch engine
DPAA incorporating acceleration for the following functions
Packet parsing, classification, and distribution (FMAN) Queue management for scheduling, packet sequencing and congestion management (QMAN)
Hardware buffer management for buffer allocation and de-allocation (BMAN)
Cryptography acceleration (SEC 5.0) at up to 40 Gbps SerDes

it's a SEC 5.2, but...

Quoted 12 lines

20 lanes at up to 5 Gbps
Supports SGMII, XAUI, PCIe rev1.1/2.0, SATA Ethernet interfaces Two 10 Gbps Ethernet MACs
Ten 1 Gbps Ethernet MACs
High-speed peripheral interfaces
Two PCI Express 2.0/3.0 controllers
Additional peripheral interfaces
Two serial ATA (SATA 2.0) controllers
Two high-speed USB 2.0 controllers with integrated PHY Enhanced secure digital host controller (SD/MMC/eMMC) Enhanced serial peripheral interface (eSPI)
Two I2C controllers

Quoted 8 lines

Four UARTs
Integrated flash controller supporting NAND and NOR flash
DMA
Dual four channel
Support for hardware virtualization and partitioning enforcement
Extra privileged level for hypervisor support
QorIQ Trust Architecture 1.1
Secure boot, secure debug, tamper detection, volatile key storage

...do we really need all this marketing text duplication anyway? How about mentioning supported components in u-boot, as of this patch?

arch/powerpc/cpu/mpc85xx/p5040_ids.c line 107

Quoted 12 lines
arch/powerpc/cpu/mpc85xx/p5040_ids.c new file +12 -0
+struct liodn_id_table sec_liodn_tbl[] = {
+	SET_SEC_JR_LIODN_ENTRY(0, 129, 130),
+	SET_SEC_JR_LIODN_ENTRY(1, 131, 132),
+	SET_SEC_JR_LIODN_ENTRY(2, 133, 134),
+	SET_SEC_JR_LIODN_ENTRY(3, 135, 136),
+	SET_SEC_RTIC_LIODN_ENTRY(a, 154),
+	SET_SEC_RTIC_LIODN_ENTRY(b, 155),
+	SET_SEC_RTIC_LIODN_ENTRY(c, 156),
+	SET_SEC_RTIC_LIODN_ENTRY(d, 157),
+	SET_SEC_DECO_LIODN_ENTRY(0, 97, 98),
+	SET_SEC_DECO_LIODN_ENTRY(1, 99, 100),
+};

The SEC on the P5040 has four DECOs, not two. Plus, AFAICT, these aren't the right values for these LIODN assignments.

Kim

#6 lore raw

PATCH 4/5 powerpc/85xx: Add P5040 processor support

Quoted 3 lines · Kim Phillips
Quoted 1 line

Cryptography acceleration (SEC 5.0) at up to 40 Gbps SerDes

it's a SEC 5.2, but...

Ok.

Quoted 7 lines
Quoted 5 lines

Dual four channel
Support for hardware virtualization and partitioning enforcement
Extra privileged level for hypervisor support
QorIQ Trust Architecture 1.1
Secure boot, secure debug, tamper detection, volatile key storage

...do we really need all this marketing text duplication anyway?

I like to provide this information when introducing new boards.

Quoted 2 lines

How about mentioning supported components in u-boot, as of this patch?

Ok.

Quoted 7 lines
Quoted 7 lines
arch/powerpc/cpu/mpc85xx/p5040_ids.c new file +7 -0
+struct liodn_id_table sec_liodn_tbl[] = {
+	SET_SEC_JR_LIODN_ENTRY(0, 129, 130),
+	SET_SEC_JR_LIODN_ENTRY(1, 131, 132),
+	SET_SEC_JR_LIODN_ENTRY(2, 133, 134),
+	SET_SEC_JR_LIODN_ENTRY(3, 135, 136),
+	SET_SEC_RTIC_LIODN_ENTRY(a, 154),
+	SET_SEC_RTIC_LIODN_ENTRY(b, 155),
Quoted 8 lines

arch/powerpc/cpu/mpc85xx/p5040_ids.c line 107

Quoted 5 lines
arch/powerpc/cpu/mpc85xx/p5040_ids.c new file +5 -0
+	SET_SEC_RTIC_LIODN_ENTRY(c, 156),
+	SET_SEC_RTIC_LIODN_ENTRY(d, 157),
+	SET_SEC_DECO_LIODN_ENTRY(0, 97, 98),
+	SET_SEC_DECO_LIODN_ENTRY(1, 99, 100),
+};

The SEC on the P5040 has four DECOs, not two. Plus, AFAICT, these aren't the right values for these LIODN assignments.

This is the latest code from the SDK that we've been using for months. I thought you reviewed these values already.

Signature · 2 lines
Timur Tabi
Linux kernel developer at Freescale
#7 lore raw

PATCH 4/5 powerpc/85xx: Add P5040 processor support

Quoted 17 lines · On Mon, 10 Sep 2012 18:30:33 -0500 Tabi Timur-B04825 <[email protected]>…
Quoted 7 lines · Kim Phillips
Quoted 7 lines
arch/powerpc/cpu/mpc85xx/p5040_ids.c new file +7 -0
+struct liodn_id_table sec_liodn_tbl[] = {
+	SET_SEC_JR_LIODN_ENTRY(0, 129, 130),
+	SET_SEC_JR_LIODN_ENTRY(1, 131, 132),
+	SET_SEC_JR_LIODN_ENTRY(2, 133, 134),
+	SET_SEC_JR_LIODN_ENTRY(3, 135, 136),
+	SET_SEC_RTIC_LIODN_ENTRY(a, 154),
+	SET_SEC_RTIC_LIODN_ENTRY(b, 155),
Quoted 8 lines

arch/powerpc/cpu/mpc85xx/p5040_ids.c line 107

Quoted 5 lines
arch/powerpc/cpu/mpc85xx/p5040_ids.c new file +5 -0
+	SET_SEC_RTIC_LIODN_ENTRY(c, 156),
+	SET_SEC_RTIC_LIODN_ENTRY(d, 157),
+	SET_SEC_DECO_LIODN_ENTRY(0, 97, 98),
+	SET_SEC_DECO_LIODN_ENTRY(1, 99, 100),
+};

The SEC on the P5040 has four DECOs, not two. Plus, AFAICT, these aren't the right values for these LIODN assignments.

Quoted 1 line

This is the latest code from the SDK that we've been using for months. I

relevance? that doesn't mean they're accurate.

Quoted 1 line

thought you reviewed these values already.

no, my patch to add the two extra DECOs was rejected because the values chosen were based on those in this patch, which were deemed incorrect by people familiar with LIODN assignment expertise (not me - I've just identified these values equal to those that were identified as wrong). Plus, if I'd had reviewed this, it would have four DECOs by now.

Kim

author
#8 lore raw

PATCH 4/5 powerpc/85xx: Add P5040 processor support

Quoted 6 lines · Kim Phillips

no, my patch to add the two extra DECOs was rejected because the values chosen were based on those in this patch, which were deemed incorrect by people familiar with LIODN assignment expertise (not me - I've just identified these values equal to those that were identified as wrong). Plus, if I'd had reviewed this, it would have four DECOs by now.

Ok, I'll just wait until someone tells me what changes to make to this code.

Signature · 2 lines
Timur Tabi
Linux kernel developer at Freescale
author
#9 lore raw

PATCH 5/5 powerpc/85xx: add support for the Freescale P5040DS Superhydra reference board

In reply to Timur Tabi

The P5040DS reference board (a.k.a "Superhydra") is an enhanced version of P3041DS/P5020DS ("Hydra") reference board.

Signed-off-by Timur Tabi <[email protected]>
---
 board/freescale/common/Makefile             |    2 +
 board/freescale/corenet_ds/Makefile         |    2 +
 board/freescale/corenet_ds/eth_superhydra.c |  722 +++++++++++++++++++++++++++
 board/freescale/corenet_ds/p5040ds_ddr.c    |   18 +
 boards.cfg                                  |    1 +
 drivers/net/fm/Makefile                     |    1 +
 drivers/net/fm/p5040.c                      |  113 +++++
 include/configs/P5040DS.h                   |   40 ++
 8 files changed, 899 insertions(+), 0 deletions(-)
 create mode 100644 board/freescale/corenet_ds/eth_superhydra.c
 create mode 100644 board/freescale/corenet_ds/p5040ds_ddr.c
 create mode 100644 drivers/net/fm/p5040.c
 create mode 100644 include/configs/P5040DS.h
board/freescale/common/Makefile +2 -0
index 54cb098..dd93b32 100644
@@ -53,12 +53,14 @@ COBJS-$(CONFIG_P2020DS)		+= ics307_clk.o
 COBJS-$(CONFIG_P3041DS)		+= ics307_clk.o
 COBJS-$(CONFIG_P4080DS)		+= ics307_clk.o
 COBJS-$(CONFIG_P5020DS)		+= ics307_clk.o
+COBJS-$(CONFIG_P5040DS)		+= ics307_clk.o
 
 # deal with common files for P-series corenet based devices
 SUBLIB-$(CONFIG_P2041RDB)	+= p_corenet/libp_corenet.o
 SUBLIB-$(CONFIG_P3041DS)	+= p_corenet/libp_corenet.o
 SUBLIB-$(CONFIG_P4080DS)	+= p_corenet/libp_corenet.o
 SUBLIB-$(CONFIG_P5020DS)	+= p_corenet/libp_corenet.o
+SUBLIB-$(CONFIG_P5040DS)	+= p_corenet/libp_corenet.o
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS-y))
board/freescale/corenet_ds/Makefile +2 -0
index 1fdf8b7..d79193a 100644
@@ -31,9 +31,11 @@ COBJS-y	+= ddr.o
 COBJS-$(CONFIG_P3041DS)	+= eth_hydra.o
 COBJS-$(CONFIG_P4080DS)	+= eth_p4080.o
 COBJS-$(CONFIG_P5020DS)	+= eth_hydra.o
+COBJS-$(CONFIG_P5040DS)	+= eth_superhydra.o
 COBJS-$(CONFIG_P3041DS)	+= p3041ds_ddr.o
 COBJS-$(CONFIG_P4080DS)	+= p4080ds_ddr.o
 COBJS-$(CONFIG_P5020DS)	+= p5020ds_ddr.o
+COBJS-$(CONFIG_P5040DS)	+= p5040ds_ddr.o
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS-y))
board/freescale/corenet_ds/eth_superhydra.c new file +722 -0

722 lines not on this page · raw message

board/freescale/corenet_ds/p5040ds_ddr.c new file +18 -0
new file mode 100644
index 0000000..e65de36
@@ -0,0 +1,18 @@
+/*
+ * Copyright 2009-2010 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ */
+
+#include <common.h>
+#include <asm/fsl_ddr_sdram.h>
+
+fixed_ddr_parm_t fixed_ddr_parm_0[] = {
+	{0, 0, NULL}
+};
+
+fixed_ddr_parm_t fixed_ddr_parm_1[] = {
+	{0, 0, NULL}
+};
boards.cfg +1 -0
index dce754f..68eb5b5 100644
@@ -805,6 +805,7 @@ P5020DS_SDCARD		     powerpc     mpc85xx     corenet_ds          freescale
 P5020DS_SECURE_BOOT          powerpc     mpc85xx     corenet_ds          freescale      -           P5020DS:SECURE_BOOT
 P5020DS_SPIFLASH	     powerpc     mpc85xx     corenet_ds          freescale      -           P5020DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000
 P5020DS_SRIO_PCIE_BOOT          powerpc     mpc85xx     corenet_ds          freescale      -           P5020DS:SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000
+P5040DS                      powerpc     mpc85xx     corenet_ds          freescale
 BSC9131RDB_SPIFLASH          powerpc     mpc85xx     bsc9131rdb          freescale      -           BSC9131RDB:BSC9131RDB,SPIFLASH
 stxgp3                       powerpc     mpc85xx     stxgp3              stx
 stxssa                       powerpc     mpc85xx     stxssa              stx            -           stxssa
drivers/net/fm/Makefile +1 -0
index cc57354..da552b6 100644
@@ -40,6 +40,7 @@ COBJS-$(CONFIG_PPC_P2041) += p5020.o
 COBJS-$(CONFIG_PPC_P3041) += p5020.o
 COBJS-$(CONFIG_PPC_P4080) += p4080.o
 COBJS-$(CONFIG_PPC_P5020) += p5020.o
+COBJS-$(CONFIG_PPC_P5040) += p5040.o
 endif
 
 COBJS	:= $(COBJS-y)
drivers/net/fm/p5040.c new file +113 -0

113 lines not on this page · raw message

include/configs/P5040DS.h new file +40 -0
new file mode 100644
index 0000000..daf8f41
@@ -0,0 +1,40 @@
+/*
+ * Copyright 2009-2011 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * P5020 DS board configuration file
+ *
+ */
+#define CONFIG_P5040DS
+#define CONFIG_PHYS_64BIT
+#define CONFIG_PPC_P5040
+
+#define CONFIG_FSL_NGPIXIS		/* use common ngPIXIS code */
+
+#define CONFIG_MMC
+#define CONFIG_NAND_FSL_ELBC
+#define CONFIG_PCIE3
+#define CONFIG_SYS_FSL_RAID_ENGINE
+
+#define CONFIG_ICS307_REFCLK_HZ		25000000  /* ICS307 ref clk freq */
+
+#include "corenet_ds.h"
Signature · 1 line
1.7.3.4