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powerpc mpc85xx: Synchronization Required for mmucsr0 spr

PATCH New Laurent Joye 2 participants 2 messages Sep 7, 2012 1 message not in the archive PowerPC

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Laurent Joye

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#1 lore raw

PATCH 1/1 powerpc mpc85xx: Synchronization Required for mmucsr0 spr

As explained in the PowerPC e500 Core Family Reference Manual (Synchronization Requirements for SPRs), an isync instruction is required after a mtspr mmucsr0 instruction.

Signed-off-by Laurent Joye <[email protected]>
---
 arch/powerpc/cpu/mpc85xx/tlb.c |    1 +
 1 file changed, 1 insertion(+)
(quoted diff) +0 -0

b/arch/powerpc/cpu/mpc85xx/tlb.c
index 929f6a6..c548f67 100644

arch/powerpc/cpu/mpc85xx/tlb.c +1 -0
@@ -38,6 +38,7 @@ void invalidate_tlb(u8 tlb)
                mtspr(MMUCSR0, 0x4);
        if (tlb == 1)
                mtspr(MMUCSR0, 0x2);
+       asm volatile("isync");
 }
 
 void init_tlbs(void)
Signature · 1 line
1.7.10.4
#2 lore raw

PATCH 1/1 powerpc mpc85xx: Synchronization Required for mmucsr0 spr

Quoted 16 lines · Laurent Joye

As explained in the PowerPC e500 Core Family Reference Manual (Synchronization Requirements for SPRs), an isync instruction is required after a mtspr mmucsr0 instruction.

Signed-off-by Laurent Joye <[email protected]>
---
 arch/powerpc/cpu/mpc85xx/tlb.c |    1 +
 1 file changed, 1 insertion(+)
arch/powerpc/cpu/mpc85xx/tlb.c +0 -0
index 929f6a6..c548f67 100644

arch/powerpc/cpu/mpc85xx/tlb.c void invalidate_tlb(u8 tlb) · line 44

Quoted 7 lines
arch/powerpc/cpu/mpc85xx/tlb.c +1 -0
@@ -38,6 +38,7 @@ void invalidate_tlb(u8 tlb)
                mtspr(MMUCSR0, 0x4);
        if (tlb == 1)
                mtspr(MMUCSR0, 0x2);
+       asm volatile("isync");
 }
 
 void init_tlbs(void)

We can probably just get rid of that function. It only affects non-IPROT entries, of which we shouldn't have any. As of "powerpc/85xx:
clear out TLB on boot" we shouldn't have any stale TLB1 entries from before U-Boot took over.

-Scott