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Corrupted NAND Flash access on KARO TX25 modules.

PATCH New Daniel Gachet 3 participants 7 messages Aug 2, 2012 – Sep 23, 2012

Subsystems (4)
Arm i.MX and Layerscape Memory technology devices (MTD) NAND flash Arm/actions semi architecture
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Daniel Gachet

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#0 lore raw

PATCH v5 1/1 Corrupted NAND Flash access on KARO TX25 modules.

The mxc_nand driver uses the symmetric mode to access the NAND Flash, but the devices populated on the KARO TX25 only support ann asymmetic mode (MX25: bit 8 within NAND_FLAHS_CONFIG1 register cleared).

This patch enables to selected the NAND Flash access mode with the configuration flag CONFIG_SYS_NAND_MXC_NFC_TWO_CYCLES.

Signed-off-by Daniel Gachet <[email protected]>
---
 drivers/mtd/nand/mxc_nand.c |   13 +++++++++++++
 include/configs/tx25.h      |    1 +
 2 files changed, 14 insertions(+)
drivers/mtd/nand/mxc_nand.c +13 -0
index 936186f..08fbb12 100644
@@ -48,6 +48,17 @@
  * 	Reading or writing a 2K or 4K page requires only 1 FDI/FDO cycle.
  *      Also some of registers are moved and/or changed meaning as seen below.
  */
+/*
+ * NAND Flash access mode on MX25
+ *
+ * The MX25 NAND Flash Controller supports two modes to access the Flash:
+ *   a) symmetric mode (one Flash clock cycle per access) or
+ *   b) asymmetric mode (two Flash clock cycles per access)
+ *
+ * By default the NAND Flash Controller is configured in the symmetric mode.
+ * To select the asymmetric mode, the configuration option
+ * CONFIG_SYS_NAND_MXC_NFC_TWO_CYCLES has to be selected.
+ */
 #if defined(CONFIG_MX31) || defined(CONFIG_MX27)
 #define MXC_NFC_V1
 #elif defined(CONFIG_MX25) || defined(CONFIG_MX35)

@@ -1290,7 +1301,9 @@ static void mxc_setup_config1(void)
 	uint16_t tmp;
 
 	tmp = readw(&host->regs->nfc_config1);
+#ifndef CONFIG_SYS_NAND_MXC_NFC_TWO_CYCLES
 	tmp |= NFC_ONE_CYCLE;
+#endif
 	tmp |= NFC_4_8N_ECC;
 	writew(tmp, &host->regs->nfc_config1);
 	if (host->pagesize_2k)
include/configs/tx25.h +1 -0
index 6821528..8fa51cb 100644
@@ -109,6 +109,7 @@
 /* NAND */
 #define CONFIG_NAND_MXC
 #define CONFIG_NAND_MXC_V1_1
+#define CONFIG_SYS_NAND_MXC_NFC_TWO_CYCLES /* 2 cycles to access NAND Flash */
 #define CONFIG_MXC_NAND_REGS_BASE	(0xBB000000)
 #define CONFIG_SYS_MAX_NAND_DEVICE	1
 #define CONFIG_SYS_NAND_BASE		(0xBB000000)
Signature · 1 line
1.7.9.5
#1 lore raw

PATCH v5 1/1 Corrupted NAND Flash access on KARO TX25 modules.

Dear Daniel,

Quoted 67 lines · Daniel Gachet

The mxc_nand driver uses the symmetric mode to access the NAND Flash, but the
devices populated on the KARO TX25 only support ann asymmetic mode (MX25: bit 8 within NAND_FLAHS_CONFIG1 register cleared).

This patch enables to selected the NAND Flash access mode with the configuration flag CONFIG_SYS_NAND_MXC_NFC_TWO_CYCLES.

Signed-off-by Daniel Gachet <[email protected]>
---
 drivers/mtd/nand/mxc_nand.c |   13 +++++++++++++
 include/configs/tx25.h      |    1 +
 2 files changed, 14 insertions(+)
drivers/mtd/nand/mxc_nand.c +4 -0
index 936186f..08fbb12 100644
@@ -48,6 +48,17 @@
  * 	Reading or writing a 2K or 4K page requires only 1 FDI/FDO
  cycle.
  *      Also some of registers are moved and/or changed meaning as
  seen below.
  */
+/*
+ * NAND Flash access mode on MX25
+ *
+ * The MX25 NAND Flash Controller supports two modes to access the

Flash:
+ * a) symmetric mode (one Flash clock cycle per access) or
+ * b) asymmetric mode (two Flash clock cycles per access)
+ *
+ * By default the NAND Flash Controller is configured in the symmetric mode.
+ * To select the asymmetric mode, the configuration option
+ * CONFIG_SYS_NAND_MXC_NFC_TWO_CYCLES has to be selected.
+ */
#if defined(CONFIG_MX31) || defined(CONFIG_MX27) #define MXC_NFC_V1
#elif defined(CONFIG_MX25) || defined(CONFIG_MX35)

drivers/mtd/nand/mxc_nand.c +2 -0
@@ -1290,7 +1301,9 @@ static void mxc_setup_config1(void)
 	uint16_t tmp;
 
 	tmp = readw(&host->regs->nfc_config1);
+#ifndef CONFIG_SYS_NAND_MXC_NFC_TWO_CYCLES
 	tmp |= NFC_ONE_CYCLE;
+#endif
 	tmp |= NFC_4_8N_ECC;
 	writew(tmp, &host->regs->nfc_config1);
 	if (host->pagesize_2k)
include/configs/tx25.h +1 -0
index 6821528..8fa51cb 100644
@@ -109,6 +109,7 @@
 /* NAND */
 #define CONFIG_NAND_MXC
 #define CONFIG_NAND_MXC_V1_1
+#define CONFIG_SYS_NAND_MXC_NFC_TWO_CYCLES /* 2 cycles to access

NAND Flash */
#define CONFIG_MXC_NAND_REGS_BASE (0xBB000000)
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE (0xBB000000)
--
1.7.9.5

Quoted 5 lines

_______________________________________________
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Why don't you simply add a factor of two to the CCM NFC divider in lowlevel_init.S?

Best regards,
Beno?t

#2 lore raw

PATCH v5 1/1 Corrupted NAND Flash access on KARO TX25 modules.

Dear Daniel, Scott,

Quoted 9 lines · Beno?t Th?baudeau
Quoted 8 lines · Daniel Gachet

The mxc_nand driver uses the symmetric mode to access the NAND Flash,
but the
devices populated on the KARO TX25 only support ann asymmetic mode (MX25: bit 8 within NAND_FLAHS_CONFIG1 register cleared).

This patch enables to selected the NAND Flash access mode with the configuration flag CONFIG_SYS_NAND_MXC_NFC_TWO_CYCLES.

[snip]

Quoted 2 lines

Why don't you simply add a factor of two to the CCM NFC divider in lowlevel_init.S?

To be more specific, I also have hardware based on the i.MX25 that does not use the NAND Flash from the reference design. It works fine with the symmetric mode as long as the NFC prescaler is set up appropriately in the MMC. I don't think that it is possible that a NAND Flash device does not support symmetric mode. So there should not be any need for a CONFIG_SYS_NAND_MXC_NFC_TWO_CYCLES config option.

All you have to do is to set the appropriate value in PER8 DIV in PCDR2 (address 0x53f80020). This can easily be added as a single line to the init_clocks macro in board/karo/tx25/lowlevel_init.S. Since the TX25 board does not set this register, it is left at its reset value, which is 0x01010101, so the line to add would be (dividing the NFC clock twice more):

	write32 0x53f80020, 0x01010103

This patch is interfering with a patch series that I'd like to post today or tomorrow, so please make a quick decision about this, so that I can know if I should take this patch into account for my series or if I should ignore it.

Best regards,
Beno?t

#3 lore raw

PATCH v5 1/1 Corrupted NAND Flash access on KARO TX25 modules.

Dear Daniel, Scott,

Quoted 37 lines · Beno?t Th?baudeau
Quoted 11 lines · Beno?t Th?baudeau
Quoted 10 lines · Daniel Gachet

The mxc_nand driver uses the symmetric mode to access the NAND Flash,
but the
devices populated on the KARO TX25 only support ann asymmetic mode
(MX25: bit 8 within NAND_FLAHS_CONFIG1 register cleared).

This patch enables to selected the NAND Flash access mode with the
configuration flag CONFIG_SYS_NAND_MXC_NFC_TWO_CYCLES.

[snip]

Quoted 2 lines

Why don't you simply add a factor of two to the CCM NFC divider in lowlevel_init.S?

To be more specific, I also have hardware based on the i.MX25 that does not use
the NAND Flash from the reference design. It works fine with the symmetric mode
as long as the NFC prescaler is set up appropriately in the MMC. I don't think
that it is possible that a NAND Flash device does not support symmetric mode. So
there should not be any need for a CONFIG_SYS_NAND_MXC_NFC_TWO_CYCLES config
option.

All you have to do is to set the appropriate value in PER8 DIV in PCDR2 (address
0x53f80020). This can easily be added as a single line to the init_clocks macro
in board/karo/tx25/lowlevel_init.S. Since the TX25 board does not set this
register, it is left at its reset value, which is 0x01010101, so the line to add
would be (dividing the NFC clock twice more):

Quoted 8 lines
	write32 0x53f80020, 0x01010103

This patch is interfering with a patch series that I'd like to post today or
tomorrow, so please make a quick decision about this, so that I can know if I
should take this patch into account for my series or if I should ignore it.

Did you have a chance to test my suggestion on Karo TX25? Do you want me to send a patch for it?

Except if adding this config option to the driver adds a real benefit compared to my suggestion, it is probably better to tune the board files first.

Best regards,
Beno?t

#4 lore raw

PATCH 1/1 KARO TX25: Fix NAND Flash R/W cycle times

The NAND Flash of the KARO TX25 board is a Samsung K9F1G08U0B with 25-ns R/W cycle times. However, the NFC clock for this board was set to 66.5 MHz, so using the NFC driver in symmetric mode (i.e. 1 NFC clock cycle = 1 NF R/W cycle) resulted in NF R/W cycle times of 15 ns, hence corrupted NF accesses.

This patch fixes this issue by setting the NFC clock to the highest frequency complying to the 25-ns NF R/W cycle times specification, i.e. 33.25 MHz.

Signed-off-by Beno?t Th?baudeau <[email protected]>
Cc John Rigby <[email protected]>
Cc Scott Wood <[email protected]>
Cc Stefano Babic <[email protected]>
Cc Daniel Gachet <[email protected]>

---
This patch is a replacement solution that I suggest instead of
http://patchwork.ozlabs.org/patch/174735/ since there is no need for a CONFIG_SYS_NAND_MXC_NFC_TWO_CYCLES config option in the NFC driver.

It still has to be tested by someone having this board, but I'm very confident that it works since I have another PCB design based on the i.MX25 with a NAND Flash with the same timings that works fine using these clock settings.

 .../board/karo/tx25/lowlevel_init.S                |    8 ++++++++
 1 file changed, 8 insertions(+)
board/karo/tx25/lowlevel_init.S +8 -0
index 823df10..eb3f187 100644
@@ -67,6 +67,14 @@
 	write32	0x53f80008, 0x20034000
 
 	/*
+	 * PCDR2: NFC = 33.25 MHz
+	 * This is required for the NAND Flash of this board, which is a Samsung
+	 * K9F1G08U0B with 25-ns R/W cycle times, in order to make it work with
+	 * the NFC driver in symmetric (i.e. one-cycle) mode.
+	 */
+	write32	0x53f80020, 0x01010103
+
+	/*
 	 * enable all implemented clocks in all three
 	 * clock control registers
 	 */
#5 lore raw

PATCH 1/1 KARO TX25: Fix NAND Flash R/W cycle times

Quoted 31 lines · Beno?t Th?baudeau

The NAND Flash of the KARO TX25 board is a Samsung K9F1G08U0B with 25-ns R/W cycle times. However, the NFC clock for this board was set to 66.5 MHz, so using the NFC driver in symmetric mode (i.e. 1 NFC clock cycle = 1 NF R/W cycle) resulted in NF R/W cycle times of 15 ns, hence corrupted NF accesses.

This patch fixes this issue by setting the NFC clock to the highest frequency complying to the 25-ns NF R/W cycle times specification, i.e. 33.25 MHz.

Signed-off-by Beno?t Th?baudeau <[email protected]>
Cc John Rigby <[email protected]>
Cc Scott Wood <[email protected]>
Cc Stefano Babic <[email protected]>
Cc Daniel Gachet <[email protected]>

---
This patch is a replacement solution that I suggest instead of
http://patchwork.ozlabs.org/patch/174735/ since there is no need for a CONFIG_SYS_NAND_MXC_NFC_TWO_CYCLES config option in the NFC driver.

It still has to be tested by someone having this board, but I'm very confident that it works since I have another PCB design based on the i.MX25 with a NAND Flash with the same timings that works fine using these clock settings.

 .../board/karo/tx25/lowlevel_init.S                |    8 ++++++++
 1 file changed, 8 insertions(+)
board/karo/tx25/lowlevel_init.S +0 -0
index 823df10..eb3f187 100644
@@ -67,6 +67,14 @@
 	write32	0x53f80008, 0x20034000

board/karo/tx25/lowlevel_init.S line 77

Quoted 10 lines
board/karo/tx25/lowlevel_init.S +8 -0
 
 	/*
+	 * PCDR2: NFC = 33.25 MHz
+	 * This is required for the NAND Flash of this board, which is a Samsung
+	 * K9F1G08U0B with 25-ns R/W cycle times, in order to make it work with
+	 * the NFC driver in symmetric (i.e. one-cycle) mode.
+	 */
+	write32	0x53f80020, 0x01010103
+
+	/*

This is a very local change, only for the Karo-TX25. I see no problem with it.

Acked-by Stefano Babic <[email protected]>

Best regards,
Stefano Babic

Signature · 5 lines
=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
#6 lore raw

PATCH 1/1 KARO TX25: Fix NAND Flash R/W cycle times

In reply to Benoît Thébaudeau
Quoted 8 lines · Beno?t Th?baudeau

The NAND Flash of the KARO TX25 board is a Samsung K9F1G08U0B with 25-ns R/W cycle times. However, the NFC clock for this board was set to 66.5 MHz, so using the NFC driver in symmetric mode (i.e. 1 NFC clock cycle = 1 NF R/W cycle) resulted in NF R/W cycle times of 15 ns, hence corrupted NF accesses.

This patch fixes this issue by setting the NFC clock to the highest frequency complying to the 25-ns NF R/W cycle times specification, i.e. 33.25 MHz.

Applied to u-boot-imx(fix), thanks.

Best regards,
Stefano Babic

Signature · 5 lines
=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================