Add T30 Cardhu support

arch/arm/cpu/arm720t/tegra30/cpu.c +7 -0

+static void adjust_pllp_out_freqs(void)
+{
+	struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+	struct clk_pll *pll = &clkrst->crc_pll[CLOCK_ID_PERIPH];
+	u32 reg;
+
+	/* Set T30 PLLP_OUT1, 2, 3 & 4 freqs to 9.6, 48, 102 & 204MHz */

arch/arm/cpu/arm720t/tegra30/cpu.c +22 -0

+void tegra_i2c_ll_write_addr(uint addr, uint config)
+{
+	struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE;
+
+	writel(addr, &reg->cmd_addr0);
+	writel(config, &reg->cnfg);
+}
+
+void tegra_i2c_ll_write_data(uint data, uint config)
+{
+	struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE;
+
+	writel(data, &reg->cmd_data1);
+	writel(config, &reg->cnfg);
+}
+
+static void enable_cpu_power_rail(void)
+{
+	struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
+	u32 reg;
+
+	debug("enable_cpu_power_rail entry\n");

arch/arm/cpu/arm720t/tegra30/cpu.c +9 -0

+	int mask = crc_rst_cpu | crc_rst_de | crc_rst_debug;
+	int num_cpus = get_num_cpus();
+	int cpu;
+
+	debug("reset_a9_cpu entry\n");
+	/* Hold CPUs 1 onwards in reset, and CPU 0 if asked */
+	for (cpu = 1; cpu < num_cpus; cpu++)
+		reset_cmplx_set_enable(cpu, mask, 1);
+	reset_cmplx_set_enable(0, mask, reset);

Quoted 4 lines · Tom Warren

This provides SPL support for T30 boards - AVP early init, plus CPU (A9) init/jump to main U-Boot.

arch/arm/cpu/arm720t/tegra30/cpu.c +0 -0

arch/arm/cpu/arm720t/tegra30/cpu.c line 45

Quoted 6 lines

arch/arm/cpu/arm720t/tegra30/cpu.c +6 -0

+/*
+ * Timing tables for each SOC for all four oscillator options.
+ */
+static struct clk_pll_table tegra_pll_x_table[TEGRA_SOC_COUNT]
+                                             [CLOCK_OSC_FREQ_COUNT] = {
+     /* T20: 1 GHz */

This is odd; it's a Tegra30-specific file, yet has data tables for Tegra20 too, and various code that only makes sense to differentiate Tegra20 and Tegra30 at runtime.

Either everything in this file should be Tegra30-specific, or whatever new code is being added here should be added to a file in tegra-common if it needs to handle both SoCs.

arch/arm/cpu/arm720t/tegra30/cpu.c line 92

Quoted 7 lines

arch/arm/cpu/arm720t/tegra30/cpu.c +7 -0

+static int get_chip_type(void)
+{
+     /*
+      * T30 has two options. We will return TEGRA_SOC_T30 until
+      * we have the fdt set up when it may change to
+      * TEGRA_SOC_T30_408MHZ depending on what we set PLLP to.
+      */

I'm not sure what the FDT has to do with it? Certainly at this point in the series, I doubt that comment is accurate. Do we actually reprogram the PLLs based on FDT later?

arch/arm/cpu/arm720t/tegra30/cpu.c line 96

Quoted 5 lines

arch/arm/cpu/arm720t/tegra30/cpu.c +4 -0

+     if (clock_get_rate(CLOCK_ID_PERIPH) == 408000000)
+             return TEGRA_SOC_T30_408MHZ;
+     else
+             return TEGRA_SOC_T30;

I thought we'd decided not to support one of those options, but perhaps it's used somewhere...

Quoted 13 lines

arch/arm/cpu/arm720t/tegra30/cpu.c +12 -0

+static void adjust_pllp_out_freqs(void)
+{
+     struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+     struct clk_pll *pll = &clkrst->crc_pll[CLOCK_ID_PERIPH];
+     u32 reg;
+
+     /* Set T30 PLLP_OUT1, 2, 3 & 4 freqs to 9.6, 48, 102 & 204MHz */
+     reg = readl(&pll->pll_out[0]);     /* OUTA, contains OUT2 / OUT1 */
+     reg |= (IN_408_OUT_48_DIVISOR << PLLP_OUT2_RATIO) | PLLP_OUT2_OVR
+             | (IN_408_OUT_9_6_DIVISOR << PLLP_OUT1_RATIO) | PLLP_OUT1_OVR;
+     writel(reg, &pll->pll_out[0]);
+

arch/arm/cpu/arm720t/tegra30/cpu.c line 136

Quoted 5 lines

arch/arm/cpu/arm720t/tegra30/cpu.c +5 -0

+     reg = readl(&pll->pll_out[1]);   /* OUTB, contains OUT4 / OUT3 */
+     reg |= (IN_408_OUT_204_DIVISOR << PLLP_OUT4_RATIO) | PLLP_OUT4_OVR
+             | (IN_408_OUT_102_DIVISOR << PLLP_OUT3_RATIO) | PLLP_OUT3_OVR;
+     writel(reg, &pll->pll_out[1]);
+}

I don't think that code is ever used, since init_pllx() below is only ever called with slow==1, so never calls it.

Quoted 23 lines

arch/arm/cpu/arm720t/tegra30/cpu.c +22 -0

+void tegra_i2c_ll_write_addr(uint addr, uint config)
+{
+     struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE;
+
+     writel(addr, &reg->cmd_addr0);
+     writel(config, &reg->cnfg);
+}
+
+void tegra_i2c_ll_write_data(uint data, uint config)
+{
+     struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE;
+
+     writel(data, &reg->cmd_data1);
+     writel(config, &reg->cnfg);
+}
+
+static void enable_cpu_power_rail(void)
+{
+     struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
+     u32 reg;
+
+     debug("enable_cpu_power_rail entry\n");

arch/arm/cpu/arm720t/tegra30/cpu.c line 339

Quoted 10 lines

arch/arm/cpu/arm720t/tegra30/cpu.c +10 -0

+     reg = readl(&pmc->pmc_cntrl);
+     reg |= CPUPWRREQ_OE;
+     writel(reg, &pmc->pmc_cntrl);
+
+     /*
+      * Pulse PWRREQ via I2C.  We need to find out what this is
+      * doing, tidy up the code and maybe find a better place for it.
+      */
+     tegra_i2c_ll_write_addr(0x005a, 0x0002);
+     tegra_i2c_ll_write_data(0x2328, 0x0a02);

With a TPS65911x attached to the DVC I2C bus, that sets VDD to 1.4V (I assume that's both the VDD1 and VDD2 outputs, but the PMIC datasheet isn't too clear on that at a quick glance), and:

arch/arm/cpu/arm720t/tegra30/cpu.c line 341

Quoted 2 lines

arch/arm/cpu/arm720t/tegra30/cpu.c +2 -0

+     udelay(1000);
+     tegra_i2c_ll_write_data(0x0127, 0x0a02);

... and this enables the VDD regulator.

So, this is:
a) Entirely specific to a TPS65911x regulator. I think this warrants a very large FIXME comment.
b) Nothing to do with pulsing PWRREQ via I2C.
c) Really should be done via programming the EEPROM on the PMIC so that SW doesn't have to do this, but I guess that didn't happen.

arch/arm/cpu/arm720t/tegra30/cpu.c line 353

Quoted 10 lines

arch/arm/cpu/arm720t/tegra30/cpu.c +9 -0

+static void reset_A9_cpu(int reset)
+{
+     /*
+     * NOTE:  Regardless of whether the request is to hold the CPU in reset
+     *        or take it out of reset, every processor in the CPU complex
+     *        except the master (CPU 0) will be held in reset because the
+     *        AVP only talks to the master. The AVP does not know that there
+     *        are multiple processors in the CPU complex.
+     */

At least the last sentence there is false; this code is running on the AVP and there's explicit code above that determines the number of CPUs in the main CPU complex (get_num_cpus) and sets separate reset bits for each of them (enable_cpu_clock). Oh, and ~7 lines below, there's a loop over num_cpus:

arch/arm/cpu/arm720t/tegra30/cpu.c line 362

Quoted 10 lines

arch/arm/cpu/arm720t/tegra30/cpu.c +9 -0

+     int mask = crc_rst_cpu | crc_rst_de | crc_rst_debug;
+     int num_cpus = get_num_cpus();
+     int cpu;
+
+     debug("reset_a9_cpu entry\n");
+     /* Hold CPUs 1 onwards in reset, and CPU 0 if asked */
+     for (cpu = 1; cpu < num_cpus; cpu++)
+             reset_cmplx_set_enable(cpu, mask, 1);
+     reset_cmplx_set_enable(0, mask, reset);

Quoted 4 lines · Tom Warren

This provides SPL support for T30 boards - AVP early init, plus CPU (A9) init/jump to main U-Boot.

arch/arm/cpu/arm720t/tegra30/cpu.c +0 -0

arch/arm/cpu/arm720t/tegra30/cpu.c line 92

Quoted 7 lines

arch/arm/cpu/arm720t/tegra30/cpu.c +7 -0

+static int get_chip_type(void)
+{
+     /*
+      * T30 has two options. We will return TEGRA_SOC_T30 until
+      * we have the fdt set up when it may change to
+      * TEGRA_SOC_T30_408MHZ depending on what we set PLLP to.
+      */

I'm not sure what the FDT has to do with it? Certainly at this point in the series, I doubt that comment is accurate. Do we actually reprogram the PLLs based on FDT later?

arch/arm/cpu/arm720t/tegra30/cpu.c line 96

Quoted 5 lines

arch/arm/cpu/arm720t/tegra30/cpu.c +4 -0

+     if (clock_get_rate(CLOCK_ID_PERIPH) == 408000000)
+             return TEGRA_SOC_T30_408MHZ;
+     else
+             return TEGRA_SOC_T30;

I thought we'd decided not to support one of those options, but perhaps it's used somewhere...

Quoted 13 lines

arch/arm/cpu/arm720t/tegra30/cpu.c +12 -0

+static void adjust_pllp_out_freqs(void)
+{
+     struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+     struct clk_pll *pll = &clkrst->crc_pll[CLOCK_ID_PERIPH];
+     u32 reg;
+
+     /* Set T30 PLLP_OUT1, 2, 3 & 4 freqs to 9.6, 48, 102 & 204MHz */
+     reg = readl(&pll->pll_out[0]);     /* OUTA, contains OUT2 / OUT1 */
+     reg |= (IN_408_OUT_48_DIVISOR << PLLP_OUT2_RATIO) | PLLP_OUT2_OVR
+             | (IN_408_OUT_9_6_DIVISOR << PLLP_OUT1_RATIO) | PLLP_OUT1_OVR;
+     writel(reg, &pll->pll_out[0]);
+

arch/arm/cpu/arm720t/tegra30/cpu.c line 136

Quoted 5 lines

arch/arm/cpu/arm720t/tegra30/cpu.c +5 -0

+     reg = readl(&pll->pll_out[1]);   /* OUTB, contains OUT4 / OUT3 */
+     reg |= (IN_408_OUT_204_DIVISOR << PLLP_OUT4_RATIO) | PLLP_OUT4_OVR
+             | (IN_408_OUT_102_DIVISOR << PLLP_OUT3_RATIO) | PLLP_OUT3_OVR;
+     writel(reg, &pll->pll_out[1]);
+}

I don't think that code is ever used, since init_pllx() below is only ever called with slow==1, so never calls it.

Quoted 6 lines

arch/arm/cpu/arm720t/tegra30/cpu.c +5 -0

+void tegra_i2c_ll_write_addr(uint addr, uint config)
+{
+     struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE;
+
+     writel(addr, &reg->cmd_addr0);

arch/arm/cpu/arm720t/tegra30/cpu.c line 322

Quoted 10 lines

arch/arm/cpu/arm720t/tegra30/cpu.c +10 -0

+     writel(config, &reg->cnfg);
+}
+
+void tegra_i2c_ll_write_data(uint data, uint config)
+{
+     struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE;
+
+     writel(data, &reg->cmd_data1);
+     writel(config, &reg->cnfg);
+}

Quoted 7 lines

arch/arm/cpu/arm720t/tegra30/cpu.c +7 -0

+
+static void enable_cpu_power_rail(void)
+{
+     struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
+     u32 reg;
+
+     debug("enable_cpu_power_rail entry\n");

arch/arm/cpu/arm720t/tegra30/cpu.c line 339

Quoted 10 lines

arch/arm/cpu/arm720t/tegra30/cpu.c +10 -0

+     reg = readl(&pmc->pmc_cntrl);
+     reg |= CPUPWRREQ_OE;
+     writel(reg, &pmc->pmc_cntrl);
+
+     /*
+      * Pulse PWRREQ via I2C.  We need to find out what this is
+      * doing, tidy up the code and maybe find a better place for it.
+      */
+     tegra_i2c_ll_write_addr(0x005a, 0x0002);
+     tegra_i2c_ll_write_data(0x2328, 0x0a02);

With a TPS65911x attached to the DVC I2C bus, that sets VDD to 1.4V (I assume that's both the VDD1 and VDD2 outputs, but the PMIC datasheet isn't too clear on that at a quick glance), and:

arch/arm/cpu/arm720t/tegra30/cpu.c line 341

Quoted 2 lines

arch/arm/cpu/arm720t/tegra30/cpu.c +2 -0

+     udelay(1000);
+     tegra_i2c_ll_write_data(0x0127, 0x0a02);

... and this enables the VDD regulator.

So, this is:
a) Entirely specific to a TPS65911x regulator. I think this warrants a very large FIXME comment.
b) Nothing to do with pulsing PWRREQ via I2C.
c) Really should be done via programming the EEPROM on the PMIC so that SW doesn't have to do this, but I guess that didn't happen.

arch/arm/cpu/arm720t/tegra30/cpu.c line 353

Quoted 9 lines

arch/arm/cpu/arm720t/tegra30/cpu.c +9 -0

+static void reset_A9_cpu(int reset)
+{
+     /*
+     * NOTE:  Regardless of whether the request is to hold the CPU in reset
+     *        or take it out of reset, every processor in the CPU complex
+     *        except the master (CPU 0) will be held in reset because the
+     *        AVP only talks to the master. The AVP does not know that there
+     *        are multiple processors in the CPU complex.
+     */

At least the last sentence there is false; this code is running on the AVP and there's explicit code above that determines the number of CPUs in the main CPU complex (get_num_cpus) and sets separate reset bits for each of them (enable_cpu_clock). Oh, and ~7 lines below, there's a loop over num_cpus:

arch/arm/cpu/arm720t/tegra30/cpu.c line 362

Quoted 9 lines

arch/arm/cpu/arm720t/tegra30/cpu.c +9 -0

+     int mask = crc_rst_cpu | crc_rst_de | crc_rst_debug;
+     int num_cpus = get_num_cpus();
+     int cpu;
+
+     debug("reset_a9_cpu entry\n");
+     /* Hold CPUs 1 onwards in reset, and CPU 0 if asked */
+     for (cpu = 1; cpu < num_cpus; cpu++)
+             reset_cmplx_set_enable(cpu, mask, 1);
+     reset_cmplx_set_enable(0, mask, reset);

_______________________________________________
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U-Boot at lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

This provides SPL support for T30 boards - AVP early init, plus CPU (A9) init/jump to main U-Boot.

Signed-off-by Tom Warren <[email protected]>

---
 arch/arm/cpu/arm720t/tegra-common/cpu.h            |   48 +--
 arch/arm/cpu/arm720t/tegra-common/spl.c            |    3 +-
 .../arm/cpu/arm720t/tegra30}/Makefile              |   20 +-
 arch/arm/cpu/arm720t/tegra30/config.mk             |   19 +
 arch/arm/cpu/arm720t/tegra30/cpu.c                 |  516 ++++++++++++++++++++
 5 files changed, 554 insertions(+), 52 deletions(-)
 copy {board/compal/paz00 => arch/arm/cpu/arm720t/tegra30}/Makefile (68%)
 create mode 100644 arch/arm/cpu/arm720t/tegra30/config.mk
 create mode 100644 arch/arm/cpu/arm720t/tegra30/cpu.c

arch/arm/cpu/arm720t/tegra-common/cpu.h +0 -0

index 6804cd7..0d9a3c2 100644

arch/arm/cpu/arm720t/tegra30/cpu.c new file +74 -0

new file mode 100644
index 0000000..e0821ef
@@ -0,0 +1,516 @@
+/*
+ * Copyright (c) 2010-2012, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/flow.h>
+#include <asm/arch/pinmux.h>
+#include <asm/arch/tegra.h>
+#include <asm/arch-tegra/clk_rst.h>
+#include <asm/arch-tegra/fuse.h>
+#include <asm/arch-tegra/pmc.h>
+#include <asm/arch-tegra/scu.h>
+#include <asm/arch-tegra/tegra_i2c.h>
+#include "../tegra-common/cpu.h"
+
+struct clk_pll_table {
+       u16             n;
+       u16             m;
+       u8              p;
+       u8              cpcon;
+};
+
+/* ~0=uninitialized/unknown, 0=false, 1=true */
+uint32_t is_tegra_processor_reset = 0xffffffff;
+
+/*
+ * Timing tables for each SOC for all four oscillator options.
+ */
+static struct clk_pll_table tegra_pll_x_table[TEGRA_SOC_COUNT]
+                                               [CLOCK_OSC_FREQ_COUNT] = {
+       /* T20: 1 GHz */
+       {{ 1000, 13, 0, 12},    /* OSC 13M */
+        { 625,  12, 0, 8},     /* OSC 19.2M */
+        { 1000, 12, 0, 12},    /* OSC 12M */
+        { 1000, 26, 0, 12},    /* OSC 26M */
+       },
+
+       /* T25: 1.2 GHz */
+       {{ 923, 10, 0, 12},
+        { 750, 12, 0, 8},
+        { 600,  6, 0, 12},
+        { 600, 13, 0, 12},
+       },
+
+       /* T30(slow): 1.0 GHz */
+       {{ 1000,  13, 0, 8},
+        { 625,  12, 0, 4},
+        { 1000, 12, 0, 8},
+        { 1000,  26, 0, 8},
+       },
+
+       /* T30(high): 1.4 GHz */
+       {{ 862, 8, 0, 8},
+        { 583, 8, 0, 4},
+        { 700, 6, 0, 8},
+        { 700, 13, 0, 8},
+       },
+
+       /* TEGRA_SOC2_SLOW: 312 MHz */
+       {{ 312, 13, 0, 12},     /* OSC 13M */

arch/arm/cpu/arm720t/tegra30/cpu.c new file +55 -0

+
+static int get_chip_type(void)
+{
+       /*
+        * T30 has two options. We will return TEGRA_SOC_T30 until
+        * we have the fdt set up when it may change to
+        * TEGRA_SOC_T30_408MHZ depending on what we set PLLP to.
+        */
+       if (clock_get_rate(CLOCK_ID_PERIPH) == 408000000)
+               return TEGRA_SOC_T30_408MHZ;
+       else
+               return TEGRA_SOC_T30;
+}
+
+static enum tegra_family_t get_family(void)
+{
+       u32 reg, chip_id;
+
+       debug("tegra_get_family entry\n");
+       reg = readl(NV_PA_APB_MISC_BASE + GP_HIDREV);
+
+       chip_id = reg >> 8;
+       chip_id &= 0xff;
+       debug("  tegra_get_family: chip_id = %x\n", chip_id);
+       if (chip_id == 0x30)
+               return TEGRA_FAMILY_T3x;
+       else
+               return TEGRA_FAMILY_T2x;
+}
+
+int get_num_cpus(void)
+{
+       return get_family() == TEGRA_FAMILY_T3x ? 4 : 2;
+}
+
+static void adjust_pllp_out_freqs(void)
+{
+       struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+       struct clk_pll *pll = &clkrst->crc_pll[CLOCK_ID_PERIPH];
+       u32 reg;
+
+       /* Set T30 PLLP_OUT1, 2, 3 & 4 freqs to 9.6, 48, 102 & 204MHz */
+       reg = readl(&pll->pll_out[0]);     /* OUTA, contains OUT2 / OUT1 */
+       reg |= (IN_408_OUT_48_DIVISOR << PLLP_OUT2_RATIO) | PLLP_OUT2_OVR
+               | (IN_408_OUT_9_6_DIVISOR << PLLP_OUT1_RATIO) | PLLP_OUT1_OVR;
+       writel(reg, &pll->pll_out[0]);
+
+       reg = readl(&pll->pll_out[1]);   /* OUTB, contains OUT4 / OUT3 */
+       reg |= (IN_408_OUT_204_DIVISOR << PLLP_OUT4_RATIO) | PLLP_OUT4_OVR
+               | (IN_408_OUT_102_DIVISOR << PLLP_OUT3_RATIO) | PLLP_OUT3_OVR;
+       writel(reg, &pll->pll_out[1]);
+}
+
+static int pllx_set_rate(struct clk_pll_simple *pll , u32 divn, u32 divm,
+               u32 divp, u32 cpcon)

arch/arm/cpu/armv7/tegra30/Makefile line 22

Quoted 9 lines · Tom Warren

These files are for code that runs on the CPU (A9) on T30 boards. At this time, it's only the RCM (Recovery Mode) cmd file, which is in tegra-common. As T30-specific run-time code is added, it'll go here.

arch/arm/cpu/armv7/tegra30/Makefile renamed from arch/arm/cpu/arm720t/tegra30/Makefile +1 -1

 
-LIB  = $(obj)lib$(SOC).o
+LIB  =  $(obj)lib$(SOC).o

Looks like there are two spaces after the = there.

arch/arm/cpu/armv7/tegra30/Makefile line 28

Quoted 2 lines

arch/arm/cpu/armv7/tegra30/Makefile renamed from arch/arm/cpu/arm720t/tegra30/Makefile +1 -1

-all: $(obj).depend $(LIB)
+all:  $(obj).depend $(LIB)

And a space after the TAB there.

Does U-Boot compile at this point in the series? Hopefully "git bisect" is maintained across the series. I suppose there aren't any boards.cfg entries for Tegra30 yet, so the fact that e.g. CONFIG_ARCH_DEVICE_TREE points at a file that doesn't yet exist is impossible to notice.

These files are used by both SPL and main U-Boot. Also made minor changes to shared Tegra code to support T30 differences.

arch/arm/cpu/tegra-common/ap.c +2 -0

@@ -58,6 +62,20 @@ int tegra_get_chip_type(void)
 			return TEGRA_SOC_T25;
 		}
 		break;
+	case CHIPID_TEGRA30:
+		switch (tegra_sku_id) {

arch/arm/cpu/tegra-common/board.c +0 -1

@@ -59,9 +59,12 @@ unsigned int query_sdram_size(void)
 	case 1:
 		return 0x10000000;	/* 256 MB */
 	case 2:
-	default:

Quoted 18 lines · Tom Warren

These files are used by both SPL and main U-Boot. Also made minor changes to shared Tegra code to support T30 differences.

arch/arm/cpu/tegra-common/ap.c +8 -0

@@ -58,6 +62,20 @@ int tegra_get_chip_type(void)
                      return TEGRA_SOC_T25;
              }
              break;
+     case CHIPID_TEGRA30:
+             switch (tegra_sku_id) {
+             case SKU_ID_T30:
+                     /*
+                      * T30 has two options. We will return TEGRA_SOC_T30
+                      * until we have the fdt set up when it may change to
+                      * TEGRA_SOC_T30_408MHZ depending on the PLLP freq.
+                      */

arch/arm/cpu/tegra-common/ap.c int tegra_get_chip_type(void) · line 76

Quoted 4 lines

arch/arm/cpu/tegra-common/ap.c +4 -0

+                     if (clock_get_rate(CLOCK_ID_PERIPH) == 408000000)
+                             return TEGRA_SOC_T30_408MHZ;
+                     else
+                             return TEGRA_SOC_T30;

Hmmm. I wonder why this doesn't return just the actual chip type; isn't the different in PLL_P rates a SW option and not a facet of the HW? The whole TEGRA_SOC_T30_408MHZ thing seems strange to me.

Quoted 8 lines

arch/arm/cpu/tegra-common/board.c +0 -1

@@ -59,9 +59,12 @@ unsigned int query_sdram_size(void)
      case 1:
              return 0x10000000;      /* 256 MB */
      case 2:
-     default:

arch/arm/cpu/tegra-common/board.c unsigned int query_sdram_size(void) · line 70

Quoted 10 lines

arch/arm/cpu/tegra-common/board.c +5 -1

              return 0x20000000;      /* 512 MB */
-     case 3:
+     case 4:
+             return 0x40000000;      /* 1GB */
+     case 8:
+             return 0x7ff00000;      /* 2GB - 1MB */
+     default:
              return 0x40000000;      /* 1GB */
      }
 }

I think we should be a little more explicit about the Tegra20/Tegra30 differences here. At least for case 0, there's a difference in what this field means for the two chips.

Value   Tegra20 Tegra30
0       512     256
1       256     256
2       512     512
3       1024    768
4       undef   1024
5       undef   undef
6       undef   undef
7       undef   undef
8       n/a     2048-1

At least the Toshiba AC100 uses value "0" in this field and has 512MB not 1GB of RAM.

I also note that for Tegra30, this field is bits 31:28, whereas for Tegra20 it's bits 30:28; we aren't masking off the top bit as we should in the current code. Again, the Toshiba AC100 appears to set this extra top bit, and only succeeds in getting 512M as the result of this function because of the default case.

arch/arm/cpu/tegra30-common/pinmux.c

Quoted 2 lines

arch/arm/cpu/tegra30-common/pinmux.c +0 -0

Hmmm. The header file this relies on doesn't exist yet. But perhaps this is OK since there's no boards.cfg entry for Tegra30 yet.

arch/arm/cpu/tegra30-common/pinmux.c line 62

Quoted 3 lines

arch/arm/cpu/tegra30-common/pinmux.c +2 -0

+const struct tegra_pingroup_desc tegra_soc_pingroups[PINGRP_COUNT] = {
+     /*  NAME        VDD     f0      f1      f2      f3      fSafe   io */

"fSafe io" should be deleted; those columns don't exist in the table.

I compared this table to that in the upstream kernel, which I spent a lot of time on correlating with the various documentation sources and our downstream kernel. Some changes should be made:

arch/arm/cpu/tegra30-common/pinmux.c line 78

Quoted 4 lines

arch/arm/cpu/tegra30-common/pinmux.c +4 -0

+     PINI(DAP3_FS,     BB,      I2S2,        RSVD1,     DISPA,   DISPB),
+     PINI(DAP3_DIN,    BB,      I2S2,        RSVD1,     DISPA,   DISPB),
+     PINI(DAP3_DOUT,   BB,      I2S2,        RSVD1,     DISPA,   DISPB),
+     PINI(DAP3_SCLK,   BB,      I2S2,        RSVD1,     DISPA,   DISPB),

In the kernel at least, the RSVD values are only used in particular slots, i.e. RSVD1 always yields function 0, RSVD2==func1, RSVD3==func2, RSVD4==func3. That way, when representing the "safe" value, one can use RSVDn to guarantee to get func(n-1). I suspect, it'd be a good idea for U-Boot to adopt the same policy. So, s/RSVD1/RSVD2/ above, and make similar changes throughout this table.

arch/arm/cpu/tegra30-common/pinmux.c line 80

Quoted 2 lines

arch/arm/cpu/tegra30-common/pinmux.c +2 -0

+     PINI(GPIO_PV0,    BB,      RSVD,        RSVD,      RSVD,    RSVD),
+     PINI(GPIO_PV1,    BB,      RSVD,        RSVD,      RSVD,    RSVD),

And likewise, plain "RSVD" doesn't exist. If you duplicate RSVD into each column of the table, there's no way to know which function pinmux_set_func(foo, RSVD) might pick, since it matches them all.

arch/arm/cpu/tegra30-common/pinmux.c line 86

Quoted 6 lines

arch/arm/cpu/tegra30-common/pinmux.c +6 -0

+     PINI(SDMMC1_CLK,  SDMMC1,  SDMMC1,      RSVD1,     RSVD2,   BAD),
+     PINI(SDMMC1_CMD,  SDMMC1,  SDMMC1,      RSVD1,     RSVD2,   BAD),
+     PINI(SDMMC1_DAT3, SDMMC1,  SDMMC1,      RSVD1,     UARTE,   BAD),
+     PINI(SDMMC1_DAT2, SDMMC1,  SDMMC1,      RSVD1,     UARTE,   BAD),
+     PINI(SDMMC1_DAT1, SDMMC1,  SDMMC1,      RSVD1,     UARTE,   BAD),
+     PINI(SDMMC1_DAT0, SDMMC1,  SDMMC1,      RSVD1,     UARTE,   BAD),

I believe the final column for all those entries should be UARTA.

Quoted 1 line

+ PINI(GPIO_PV3, SDMMC1, BAD, RSVD1, RSVD2, RSVD3),

BAD should be CLK_12M_OUT.

arch/arm/cpu/tegra30-common/pinmux.c line 99

Quoted 5 lines

arch/arm/cpu/tegra30-common/pinmux.c +5 -0

+     PINO(LCD_PWR2,    LCD,     DISPA,       DISPB,    SPI5,     BAD),
+     PINO(LCD_SDOUT,   LCD,     DISPA,       DISPB,    SPI5,     BAD),
+     PINO(LCD_WR_N,    LCD,     DISPA,       DISPB,    SPI5,     BAD),
+     PINO(LCD_SCK,     LCD,     DISPA,       DISPB,    SPI5,     BAD),
+     PINO(LCD_PWR0,    LCD,     DISPA,       DISPB,    SPI5,     BAD),

BAD should be HDCP for all of those.

Quoted 1 line

+ PINI(HDMI_INT, LCD, RSVD, RSVD, RSVD, RSVD),

The first reserved should be HDMI.

arch/arm/cpu/tegra30-common/pinmux.c line 145

Quoted 10 lines

arch/arm/cpu/tegra30-common/pinmux.c +10 -0

+     PINI(VI_D0,       VI,      BAD,         RSVD1,     VI,      RSVD2),
+     PINI(VI_D1,       VI,      BAD,         SDMMC2,    VI,      RSVD1),
+     PINI(VI_D2,       VI,      BAD,         SDMMC2,    VI,      RSVD1),
+     PINI(VI_D3,       VI,      BAD,         SDMMC2,    VI,      RSVD1),
+     PINI(VI_D4,       VI,      BAD,         SDMMC2,    VI,      RSVD1),
+     PINI(VI_D5,       VI,      BAD,         SDMMC2,    VI,      RSVD1),
+     PINI(VI_D6,       VI,      BAD,         SDMMC2,    VI,      RSVD1),
+     PINI(VI_D7,       VI,      BAD,         SDMMC2,    VI,      RSVD1),
+     PINI(VI_D8,       VI,      BAD,         SDMMC2,    VI,      RSVD1),
+     PINI(VI_D9,       VI,      BAD,         SDMMC2,    VI,      RSVD1),

 +      PINI(VI_D10,      VI,      BAD,         RSVD1,     VI,      RSVD2),
> +     PINI(VI_D11,      VI,      BAD,         RSVD1,     VI,      RSVD2),

BAD should be DDR for all of those.

Quoted 1 line

+ PINI(VI_MCLK, VI, VI, BAD, BAD, BAD),

All the functions for this pin select VI.

arch/arm/cpu/tegra30-common/pinmux.c line 151

Quoted 2 lines

arch/arm/cpu/tegra30-common/pinmux.c +2 -0

+     PINI(VI_VSYNC,    VI,      BAD,         RSVD1,     VI,      RSVD2),
+     PINI(VI_HSYNC,    VI,      BAD,         RSVD1,     VI,      RSVD2),

BAD should be DDR for both of those.

arch/arm/cpu/tegra30-common/pinmux.c line 153

Quoted 2 lines

arch/arm/cpu/tegra30-common/pinmux.c +2 -0

+     PINI(UART2_RXD,   UART,    IRDA,        SPDIF,     UARTA,   SPI4),
+     PINI(UART2_TXD,   UART,    IRDA,        SPDIF,     UARTA,   SPI4),

IRDA just means UARTB, so I think remove IRDA, and replace all usage with UARTB everywhere.

arch/arm/cpu/tegra30-common/pinmux.c line 205

Quoted 3 lines

arch/arm/cpu/tegra30-common/pinmux.c +3 -0

+     PINI(GMI_CS0_N,   GMI,     RSVD1,       NAND,      GMI,     BAD),
+     PINI(GMI_A17,     GMI,     UARTD,       SPI4,      GMI,     BAD),
+     PINI(GMI_A18,     GMI,     UARTD,       SPI4,      GMI,     BAD),

BAD should be DTV in all of those.

arch/arm/cpu/tegra30-common/pinmux.c line 212

Quoted 2 lines

arch/arm/cpu/tegra30-common/pinmux.c +2 -0

+     PINI(GEN2_I2C_SCL, GMI,    I2C2,        BAD,       GMI,     RSVD3),
+     PINI(GEN2_I2C_SDA, GMI,    I2C2,        BAD,       GMI,     RSVD3),

BAD should be HDCP in both of those.

Quoted 1 line

+ PINI(CAM_MCLK, CAM, VI, BAD, VI_ALT2, POPSDMMC4),

We should rename POPSDMMC4 to just SDMMC4 throughout; there's just a single SDMMC4 controller; no a separate POPSDMMC4 controller.

arch/arm/cpu/tegra30-common/pinmux.c line 228

Quoted 2 lines

arch/arm/cpu/tegra30-common/pinmux.c +2 -0

+     PINI(CAM_I2C_SCL, CAM,     BAD,         I2C3,      RSVD2,   POPSDMMC4),
+     PINI(CAM_I2C_SDA, CAM,     BAD,         I2C3,      RSVD2,   POPSDMMC4),

BAD should be VGP1 and VGP2 in those two lines.

Quoted 1 line

+ PINI(KB_ROW3, SYS, KBC, BAD, RSVD2, BAD),

For all of KBC_ROW* and KBC_COL*, the BAD in func1 (i.e. the first BAD) should be NAND.

The second BAD there should be RSVD4.

arch/arm/cpu/tegra30-common/pinmux.c line 253

Quoted 10 lines

arch/arm/cpu/tegra30-common/pinmux.c +10 -0

+     PINI(KB_ROW6,     SYS,     KBC,         BAD,       SDMMC2,  BAD),
+     PINI(KB_ROW7,     SYS,     KBC,         BAD,       SDMMC2,  BAD),
+     PINI(KB_ROW8,     SYS,     KBC,         BAD,       SDMMC2,  BAD),
+     PINI(KB_ROW9,     SYS,     KBC,         BAD,       SDMMC2,  BAD),
+     PINI(KB_ROW10,    SYS,     KBC,         BAD,       SDMMC2,  BAD),
+     PINI(KB_ROW11,    SYS,     KBC,         BAD,       SDMMC2,  BAD),
+     PINI(KB_ROW12,    SYS,     KBC,         BAD,       SDMMC2,  BAD),
+     PINI(KB_ROW13,    SYS,     KBC,         BAD,       SDMMC2,  BAD),
+     PINI(KB_ROW14,    SYS,     KBC,         BAD,       SDMMC2,  BAD),
+     PINI(KB_ROW15,    SYS,     KBC,         BAD,       SDMMC2,  BAD),

The second bad (final column) for all of those should be MIO.

arch/arm/cpu/tegra30-common/pinmux.c line 255

Quoted 2 lines

arch/arm/cpu/tegra30-common/pinmux.c +2 -0

+     PINI(KB_COL0,     SYS,     KBC,         BAD,       TRACE,   BAD),
+     PINI(KB_COL1,     SYS,     KBC,         BAD,       TRACE,   BAD),

The second bad (final column) for both of those should be TEST.

arch/arm/cpu/tegra30-common/pinmux.c line 261

Quoted 2 lines

arch/arm/cpu/tegra30-common/pinmux.c +2 -0

+     PINI(KB_COL6,     SYS,     KBC,         BAD,       TRACE,   BAD),
+     PINI(KB_COL7,     SYS,     KBC,         BAD,       TRACE,   BAD),

The second bad (final column) for both of those should be MIO.

Quoted 1 line

+ PINI(CORE_PWR_REQ, SYS, RSVD, RSVD, RSVD, RSVD),

func0 (the first RSVD) should be CORE_PWR_REQ.

Quoted 1 line

+ PINI(CPU_PWR_REQ, SYS, RSVD, RSVD, RSVD, RSVD),

func0 (the first RSVD) should be CPU_PWR_REQ.

Quoted 1 line

+ PINI(PWR_INT_N, SYS, RSVD, RSVD, RSVD, RSVD),

func0 (the first RSVD) should be PWR_INT_N.

Quoted 1 line

+ PINI(CLK_32K_IN, SYS, RSVD, RSVD, RSVD, RSVD),

func0 (the first RSVD) should be CLK_32K_IN.

Quoted 1 line

+ PINI(OWR, SYS, OWR, RSVD, RSVD, RSVD),

func1 (the first RSVD) should be CEC.

arch/arm/cpu/tegra30-common/pinmux.c line 276

Quoted 2 lines

arch/arm/cpu/tegra30-common/pinmux.c +2 -0

+     PINI(SPDIF_IN,    AUDIO,   SPDIF,       HDA,       BAD,     DAPSDMMC2),
+     PINI(SPDIF_OUT,   AUDIO,   SPDIF,       RSVD1,     BAD,     DAPSDMMC2),

BAD should be I2C1 for both of those.

Rename DAPSDMMC2 to SDMMC2.

arch/arm/cpu/tegra30-common/pinmux.c line 284

Quoted 4 lines

arch/arm/cpu/tegra30-common/pinmux.c +4 -0

+     PINI(SPI2_MOSI,   AUDIO,   SPI6,        SPI2,      BAD,     GMI),
+     PINI(SPI2_MISO,   AUDIO,   SPI6,        SPI2,      BAD,     GMI),
+     PINI(SPI2_CS0_N,  AUDIO,   SPI6,        SPI2,      BAD,     GMI),
+     PINI(SPI2_SCK,    AUDIO,   SPI6,        SPI2,      BAD,     GMI),

BAD should be GMI for all of those.

arch/arm/cpu/tegra30-common/pinmux.c line 288

Quoted 4 lines

arch/arm/cpu/tegra30-common/pinmux.c +4 -0

+     PINI(SPI1_MOSI,   AUDIO,   SPI2,        SPI1,      BAD,     GMI),
+     PINI(SPI1_SCK,    AUDIO,   SPI2,        SPI1,      BAD,     GMI),
+     PINI(SPI1_CS0_N,  AUDIO,   SPI2,        SPI1,      BAD,     GMI),
+     PINI(SPI1_MISO,   AUDIO,   BAD,         SPI1,      BAD,     RSVD3),

SPI1_MISO's first BAD should be SPI3.

For all of those 4, func2's BAD should be SPI2 or rather SPI2_ALT.

arch/arm/cpu/tegra30-common/pinmux.c line 290

Quoted 2 lines

arch/arm/cpu/tegra30-common/pinmux.c +2 -0

+     PINI(SPI2_CS1_N,  AUDIO,   BAD,         SPI2,      BAD,     BAD),
+     PINI(SPI2_CS2_N,  AUDIO,   BAD,         SPI2,      BAD,     BAD),

In both of those, the first BAD should be SPI3, the second BAD SPI2_ALT, and the third BAD I2C1.

Quoted 1 line

+ PINI(SDMMC3_CLK, SDMMC3, UARTA, PWM2, SDMMC3, BAD),

BAD should be SPI3.

Quoted 1 line

+ PINI(SDMMC3_CMD, SDMMC3, UARTA, PWM3, SDMMC3, BAD),

BAD should be SPI2.

arch/arm/cpu/tegra30-common/pinmux.c line 296

Quoted 4 lines

arch/arm/cpu/tegra30-common/pinmux.c +4 -0

+     PINI(SDMMC3_DAT0, SDMMC3,  RSVD0,       RSVD1,     SDMMC3,  BAD),
+     PINI(SDMMC3_DAT1, SDMMC3,  RSVD0,       RSVD1,     SDMMC3,  BAD),
+     PINI(SDMMC3_DAT2, SDMMC3,  RSVD0,       PWM1,      SDMMC3,  BAD),
+     PINI(SDMMC3_DAT3, SDMMC3,  RSVD0,       PWM0,      SDMMC3,  BAD),

BAD should be SPI3 in all of those.

arch/arm/cpu/tegra30-common/pinmux.c line 300

Quoted 4 lines

arch/arm/cpu/tegra30-common/pinmux.c +4 -0

+     PINI(SDMMC3_DAT4, SDMMC3,  PWM1,        BAD,       SDMMC3,  BAD),
+     PINI(SDMMC3_DAT5, SDMMC3,  PWM0,        BAD,       SDMMC3,  BAD),
+     PINI(SDMMC3_DAT6, SDMMC3,  SPDIF,       BAD,       SDMMC3,  BAD),
+     PINI(SDMMC3_DAT7, SDMMC3,  SPDIF,       BAD,       SDMMC3,  BAD),

func1's BAD should be SPI4 in all of those.

func3's BAD should be SPI2 in all of those.

arch/arm/cpu/tegra30-common/pinmux.c line 376

Quoted 9 lines

arch/arm/cpu/tegra30-common/pinmux.c +7 -0

+void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func)
 
+     /* Handle special values */
+     if (func == PMUX_FUNC_SAFE)
+             func = tegra_soc_pingroups[pin].func_safe;
+
+     if (func & PMUX_FUNC_RSVD) {
+             mux = func & 0x3;

Indeed, this is the way the code should work, but in order for this code to work correctly, RSVD1 must only be used in the func0 column in the data, RSVD2 in the func1 column, etc.

arch/arm/cpu/tegra30-common/pinmux.c line 430

Quoted 8 lines

arch/arm/cpu/tegra30-common/pinmux.c +6 -0

+static int pinmux_set_lock(enum pmux_pingrp pin, enum pmux_pin_lock lock)
 
+     reg = readl(pin_lock);
+     reg &= ~(0x1 << PMUX_LOCK_SHIFT);
+     if (lock == PMUX_PIN_LOCK_ENABLE)
+             reg |= (0x1 << PMUX_LOCK_SHIFT);
+     writel(reg, pin_lock);

Note that the LOCK bit, once set, can never be set back to zero. Perhaps a diagnostic should be issued and/or an error returned if this is attempted? The kernel does that.

arch/arm/include/asm/arch-tegra30/funcmux.h +6 -0

 
+/**
+ * Select a config for a particular peripheral.
+ *
+ * Each peripheral can operate through a number of configurations,
+ * which are sets of pins that it uses to bring out its signals.
+ * The basic config is 0, and higher numbers indicate different

arch/arm/include/asm/arch-tegra/gp_padctrl.h line 31

Quoted 12 lines · Tom Warren

Common Tegra files are in arch-tegra, shared between T20 and T30. Tegra30-specific headers are in arch-tegra30. Note that some of these will be filled in as more T30 support is added (drivers, WB/LP0 support, etc.).

arch/arm/include/asm/arch-tegra/gp_padctrl.h +5 -0

 
+/* bit fields definitions for APB_MISC_GP_HIDREV register */
+#define HIDREV_CHIPID_SHIFT          8
+#define HIDREV_CHIPID_MASK           (0xff << HIDREV_CHIPID_SHIFT)
+#define HIDREV_MAJORPREV_SHIFT               4
+#define HIDREV_MAJORPREV_MASK                (0xf << HIDREV_MAJORPREV_SHIFT)

Patch 1 added the following:

#define GP_HIDREV 0x804

... to arch/arm/cpu/arm720t/tegra-common/cpu.h. I wonder if that line wouldn't be better place here, alongside the macros that allow you to use it?

arch/arm/include/asm/arch-tegra30/emc.h

Quoted 2 lines

arch/arm/include/asm/arch-tegra30/emc.h +0 -0

This file seems to be:

a) An exact duplicate of the Tegra20 file. Did the register layout really not change at all? That seems unlikely. If so, shouldn't the file be shared?

b) Not used by anything in this patch series, so shouldn't be needed.

c) Incorrect; struct emc_ctlr doesn't actually match the register layout for Tegra20 or Tegra30 (at least, offset 0 is interrupt status in HW in both chips, not cfg as in the struct). Some fields match though.

Quoted 9 lines

arch/arm/include/asm/arch-tegra30/funcmux.h +6 -0

 
+/**
+ * Select a config for a particular peripheral.
+ *
+ * Each peripheral can operate through a number of configurations,
+ * which are sets of pins that it uses to bring out its signals.
+ * The basic config is 0, and higher numbers indicate different

arch/arm/include/asm/arch-tegra30/funcmux.h line 45

Quoted 10 lines

arch/arm/include/asm/arch-tegra30/funcmux.h +10 -0

+ * pinmux settings to bring the peripheral out on other pins,
+ *
+ * This function also disables tristate for the function's pins,
+ * so that they operate in normal mode.
+ *
+ * @param id         Peripheral id
+ * @param config     Configuration to use (FUNCMUX_...), 0 for default
+ * @return 0 if ok, -1 on error (e.g. incorrect id or config)
+ */
+int funcmux_select(enum periph_id id, int config);

That prototype is identical to Tegra20. Shouldn't there be a common funcmux.h that defines the prototype, either include from the SoC-specific file, or itself including the SoC-specific file? This is important since common code (stuff that's not specific to Tegra20 or Tegra30) calls this function, so it shouldn't be prototyped in multiple places (with associated possibility of divergence) even if the implementation is entirely separate for the two SoCs.

arch/arm/include/asm/arch-tegra30/gpio.h line 22

Quoted 5 lines

arch/arm/include/asm/arch-tegra30/gpio.h +2 -0

 
+ * The Tegra 3x GPIO controller has 246 GPIOS in 8 banks of 4 ports,
+ *  each with 8 GPIOs.

Extra space there after *.

arch/arm/include/asm/arch-tegra30/hardware.h

Quoted 1 line

arch/arm/include/asm/arch-tegra30/hardware.h +0 -0

This file is empty except for comments. Is it really useful? The Tegra20 file is empty too

arch/arm/include/asm/arch-tegra30/pinmux-config-common.h

Quoted 2 lines

arch/arm/include/asm/arch-tegra30/pinmux-config-common.h +0 -0

The content of this file presumably describes Cardhu (which revision?) Surely it should be in board/nvidia/cardhu/*.c?

arch/arm/include/asm/arch-tegra30/pinmux.h line 339

Quoted 13 lines

arch/arm/include/asm/arch-tegra30/pinmux.h +10 -0

 
+/*
+ * Functions which can be assigned to each of the pin groups. The values here
+ * bear no relation to the values programmed into pinmux registers and are
+ * purely a convenience. The translation is done through a table search.
+ */
+enum pmux_func {
+     PMUX_FUNC_RSVD = 0x8000,
+     PMUX_FUNC_RSVD0 = PMUX_FUNC_RSVD,
+     PMUX_FUNC_BAD = 0x4000,         /* Invalid! */
+     PMUX_FUNC_NONE = 0,

I think all four of those should be deleted.

arch/arm/include/asm/arch-tegra30/pinmux.h line 358

Quoted 3 lines

arch/arm/include/asm/arch-tegra30/pinmux.h +2 -0

+     PMUX_FUNC_I2C,
+     PMUX_FUNC_I2C1 = PMUX_FUNC_I2C,

I don't think there's a need for duplicate names for any of these.

Stephen,

Quoted 5 lines · Stephen Warren

Quoted 4 lines · Tom Warren

Common Tegra files are in arch-tegra, shared between T20 and T30. Tegra30-specific headers are in arch-tegra30. Note that some of these will be filled in as more T30 support is added (drivers, WB/LP0 support, etc.).

Quoted 10 lines

arch/arm/include/asm/arch-tegra30/emc.h

Quoted 1 line

arch/arm/include/asm/arch-tegra30/emc.h +0 -0

This file seems to be:

a) An exact duplicate of the Tegra20 file. Did the register layout really not change at all? That seems unlikely. If so, shouldn't the file be shared?

b) Not used by anything in this patch series, so shouldn't be needed.

Quoted 3 lines

c) Incorrect; struct emc_ctlr doesn't actually match the register layout for Tegra20 or Tegra30 (at least, offset 0 is interrupt status in HW in both chips, not cfg as in the struct). Some fields match though.

I'll revisit it in our internal U-Boot source. I tried to go through all the include files and make sure any not used on T30 initially were removed, but if it's used in a common file, I didn't want to add #if defined(CONFIG_TEGRA20) fencing if not necessary.

Quoted 11 lines

arch/arm/include/asm/arch-tegra30/gpio.h line 22

Quoted 4 lines

arch/arm/include/asm/arch-tegra30/gpio.h +2 -0

 
+ * The Tegra 3x GPIO controller has 246 GPIOS in 8 banks of 4 ports,
+ *  each with 8 GPIOs.

Extra space there after *.

arch/arm/include/asm/arch-tegra30/hardware.h

Quoted 1 line

arch/arm/include/asm/arch-tegra30/hardware.h +0 -0

This file is empty except for comments. Is it really useful? The Tegra20 file is empty too

It's included from include/asm/hardware.h, which is included in 3 or so arm720t files, so it's mandatory. I hate empty files, but I don't see a way around it without polluting some arm720t files with #ifdef's. the integratorap_cm720t does the same thing.

Quoted 4 lines

arch/arm/include/asm/arch-tegra30/pinmux-config-common.h

Quoted 1 line

arch/arm/include/asm/arch-tegra30/pinmux-config-common.h +0 -0

The content of this file presumably describes Cardhu (which revision?) Surely it should be in board/nvidia/cardhu/*.c?

On the previous review cycle (before I commonized Tegra files), this file lived in board/nvidia/cardhu, and I think it was Tom Rini (or maybe Simon) that pointed out that it had no 'cardhu' identifiers in it, so it should be moved to a more Tegra30-centric area, hence the move to arch-tegra30. Again, this is from our internal repo, and I don't believe there's any rev info in that file (except for commented-out tables that aren't used, so I removed them). I think it's valid to say this file is common to all Tegra30 builds, and additional sparse pinmux tables could be added in board files/areas for board-specific / rev-specific mux changes.

These are stripped down for bringup, They'll be filled out later to match-up with the kernel DT contents, and/or as devices are brought up (mmc, usb, spi, etc.).

Signed-off-by Tom Warren <[email protected]>

---
 arch/arm/dts/tegra30.dtsi           |   30 ++++++++++++++++++++++++++++++
 board/nvidia/dts/tegra30-cardhu.dts |   35 +++++++++++++++++++++++++++++++++++
 2 files changed, 65 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/dts/tegra30.dtsi
 create mode 100644 board/nvidia/dts/tegra30-cardhu.dts

arch/arm/dts/tegra30.dtsi new file +30 -0

new file mode 100644
index 0000000..122c134
@@ -0,0 +1,30 @@
+/include/ "skeleton.dtsi"
+
+/ {
+	model = "NVIDIA Tegra30";
+	compatible = "nvidia,tegra30";
+
+	clocks {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		osc: clock {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+		};
+	};
+
+	gpio: gpio at 6000d000 {
+		compatible = "nvidia,tegra30-gpio", "nvidia,tegra20-gpio";
+		reg = <0x6000d000 0x1000>;
+		#gpio-cells = <2>;
+		gpio-controller;
+	};
+
+	serial at 70006000 {
+		compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
+		reg = <0x70006000 0x40>;
+		reg-shift = <2>;
+		status = "disabled";
+	};
+};

board/nvidia/dts/tegra30-cardhu.dts new file +19 -0

new file mode 100644
index 0000000..68563e8
@@ -0,0 +1,35 @@
+/dts-v1/;
+
+/memreserve/ 0x1c000000 0x04000000;
+/include/ ARCH_CPU_DTS
+
+/ {
+	model = "NVIDIA Cardhu";
+	compatible = "nvidia,cardhu", "nvidia,tegra30";
+
+	aliases {
+	};
+
+        memory {
+                device_type = "memory";
+                reg = <0x80000000 0xc0000000>;
+        };
+
+	clocks {
+		clk_32k: clk_32k {

board/nvidia/dts/tegra30-cardhu.dts new file +6 -0

+
+	serial at 70006000 {
+		status = "ok";
+		clock-frequency = < 216000000 >;
+	};
+};

Am Dienstag, den 02.10.2012, 15:45 -0700 schrieb Tom Warren:

Quoted 77 lines

These are stripped down for bringup, They'll be filled out later to match-up with the kernel DT contents, and/or as devices are brought up (mmc, usb, spi, etc.).

Signed-off-by Tom Warren <[email protected]>

---
 arch/arm/dts/tegra30.dtsi           |   30 ++++++++++++++++++++++++++++++
 board/nvidia/dts/tegra30-cardhu.dts |   35 +++++++++++++++++++++++++++++++++++
 2 files changed, 65 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/dts/tegra30.dtsi
 create mode 100644 board/nvidia/dts/tegra30-cardhu.dts

arch/arm/dts/tegra30.dtsi new file +30 -0

new file mode 100644
index 0000000..122c134
@@ -0,0 +1,30 @@
+/include/ "skeleton.dtsi"
+
+/ {
+     model = "NVIDIA Tegra30";
+     compatible = "nvidia,tegra30";
+
+     clocks {
+             #address-cells = <1>;
+             #size-cells = <0>;
+
+             osc: clock {
+                     compatible = "fixed-clock";
+                     #clock-cells = <0>;
+             };
+     };
+
+     gpio: gpio at 6000d000 {
+             compatible = "nvidia,tegra30-gpio", "nvidia,tegra20-gpio";
+             reg = <0x6000d000 0x1000>;
+             #gpio-cells = <2>;
+             gpio-controller;
+     };
+
+     serial at 70006000 {
+             compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
+             reg = <0x70006000 0x40>;
+             reg-shift = <2>;
+             status = "disabled";
+     };
+};

board/nvidia/dts/tegra30-cardhu.dts new file +23 -0

new file mode 100644
index 0000000..68563e8
@@ -0,0 +1,35 @@
+/dts-v1/;
+
+/memreserve/ 0x1c000000 0x04000000;
+/include/ ARCH_CPU_DTS
+
+/ {
+     model = "NVIDIA Cardhu";
+     compatible = "nvidia,cardhu", "nvidia,tegra30";
+
+     aliases {
+     };
+
+        memory {
+                device_type = "memory";
+                reg = <0x80000000 0xc0000000>;
+        };
+
+     clocks {
+             clk_32k: clk_32k {
+                     clock_frequency = <32000>;
+             };
+             osc {
+                     clock-frequency = <12000000>;

board/nvidia/dts/tegra30-cardhu.dts line 29

Quoted 6 lines

board/nvidia/dts/tegra30-cardhu.dts new file +6 -0

+             };
+     };
+
+     clock at 60006000 {
+             clocks = <&clk_32k &osc>;
+     };

Is this clock thing really needed? I don't think we are doing anything with those DT entries.

Quoted 7 lines

board/nvidia/dts/tegra30-cardhu.dts new file +6 -0

+
+     serial at 70006000 {
+             status = "ok";
+             clock-frequency = < 216000000 >;
+     };
+};

These are stripped down for bringup, They'll be filled out later to match-up with the kernel DT contents, and/or as devices are brought up (mmc, usb, spi, etc.).

arch/arm/dts/tegra30.dtsi +5 -0

 
+/include/ "skeleton.dtsi"
+
+/ {
+	model = "NVIDIA Tegra30";
+	compatible = "nvidia,tegra30";

board/nvidia/dts/tegra30-cardhu.dts new file +1 -0

new file mode 100644
index 0000000..68563e8
@@ -0,0 +1,35 @@
+/dts-v1/;

board/nvidia/dts/tegra30-cardhu.dts new file +9 -0

+
+	clocks {
+		clk_32k: clk_32k {
+			clock_frequency = <32000>;
+		};
+		osc {
+			clock-frequency = <12000000>;
+		};
+	};

Quoted 11 lines · Tom Warren

These are stripped down for bringup, They'll be filled out later to match-up with the kernel DT contents, and/or as devices are brought up (mmc, usb, spi, etc.).

arch/arm/dts/tegra30.dtsi +5 -0

 
+/include/ "skeleton.dtsi"
+
+/ {
+     model = "NVIDIA Tegra30";
+     compatible = "nvidia,tegra30";

arch/arm/dts/tegra30.dtsi line 15

Quoted 10 lines

arch/arm/dts/tegra30.dtsi +10 -0

+
+     clocks {
+             #address-cells = <1>;
+             #size-cells = <0>;
+
+             osc: clock {
+                     compatible = "fixed-clock";
+                     #clock-cells = <0>;
+             };
+     };

Nothing uses any of the clock stuff; I don't think we should add this until it's needed.

arch/arm/dts/tegra30.dtsi line 22

Quoted 6 lines

arch/arm/dts/tegra30.dtsi +6 -0

+     gpio: gpio at 6000d000 {
+             compatible = "nvidia,tegra30-gpio", "nvidia,tegra20-gpio";
+             reg = <0x6000d000 0x1000>;
+             #gpio-cells = <2>;
+             gpio-controller;
+     };

Similarly, nothing uses this.

arch/arm/dts/tegra30.dtsi line 27

Quoted 4 lines

arch/arm/dts/tegra30.dtsi +4 -0

+     serial at 70006000 {
+             compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
+             reg = <0x70006000 0x40>;
+             reg-shift = <2>;

This needs the following extra line here:

                interrupts = <0 36 0x04>;

arch/arm/dts/tegra30.dtsi

Quoted 2 lines

arch/arm/dts/tegra30.dtsi +2 -0

+             status = "disabled";
+     };

Although again, nothing uses this, so may as well omit it.

Quoted 7 lines

board/nvidia/dts/tegra30-cardhu.dts new file +1 -0

new file mode 100644
index 0000000..68563e8
@@ -0,0 +1,35 @@
+/dts-v1/;

board/nvidia/dts/tegra30-cardhu.dts line 11

Quoted 10 lines

board/nvidia/dts/tegra30-cardhu.dts new file +10 -0

+
+/memreserve/ 0x1c000000 0x04000000;
+/include/ ARCH_CPU_DTS
+
+/ {
+     model = "NVIDIA Cardhu";
+     compatible = "nvidia,cardhu", "nvidia,tegra30";
+
+     aliases {
+     };

May as well leave that out until it's needed.

board/nvidia/dts/tegra30-cardhu.dts line 16

Quoted 4 lines

board/nvidia/dts/tegra30-cardhu.dts new file +4 -0

+        memory {
+                device_type = "memory";
+                reg = <0x80000000 0xc0000000>;
+        };

There's an indentation error there.

Quoted 13 lines

board/nvidia/dts/tegra30-cardhu.dts new file +13 -0

+
+     clocks {
+             clk_32k: clk_32k {
+                     clock_frequency = <32000>;
+             };
+             osc {
+                     clock-frequency = <12000000>;
+             };
+     };
+
+     clock at 60006000 {
+             clocks = <&clk_32k &osc>;
+     };

board/nvidia/dts/tegra30-cardhu.dts line 35

Quoted 6 lines

board/nvidia/dts/tegra30-cardhu.dts new file +6 -0

+
+     serial at 70006000 {
+             status = "ok";
+             clock-frequency = < 216000000 >;
+     };
+};

Similarly, I don't think anything uses any of that.