arm: armv7: omap3: Fix restore sequence in lowlevel_init
Subsystems (2)
PATCH v2 1/1 arm: armv7: omap3: Fix restore sequence in lowlevel_init
The restore sequence in lowlevel_init was in the wrong order, causing lr to lose its original value and be set equal to ip instead. Also, its use of the stack clashes with that of s_init, so move the s_init call after the restore and turn it into a tail-optimized branch.
---
V2: move s_init call after restore and tail-optimize it into a branch
V1: fix order of restores
arch/arm/cpu/armv7/omap3/lowlevel_init.S | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-)
arch/arm/cpu/armv7/omap3/lowlevel_init.S +4 -5
@@ -214,7 +214,7 @@ pll_div_val5: ENTRY(lowlevel_init) ldr sp, SRAM_STACK - str ip, [sp] /* stash old link register */ + str ip, [sp] /* stash ip register */ mov ip, lr /* save link reg across call */ #if !defined(CONFIG_SYS_NAND_BOOT) && !defined(CONFIG_SYS_ONENAND_BOOT) /*
@@ -224,12 +224,11 @@ ENTRY(lowlevel_init) ldr r1, =SRAM_CLK_CODE bl cpy_clk_code #endif /* NAND Boot */ - bl s_init /* go setup pll, mux, memory */ - ldr ip, [sp] /* restore save ip */ mov lr, ip /* restore link reg */ + ldr ip, [sp] /* restore save ip */ + /* tail-call s_init to setup pll, mux, memory */ + b s_init - /* back to arch calling code */ - mov pc, lr ENDPROC(lowlevel_init) /* the literal pools origin */
Signature · 1 line
1.7.9.5
PATCH v2 1/1 arm: armv7: omap3: Fix restore sequence in lowlevel_init
Quoted 33 lines · Albert ARIBAUD
The restore sequence in
lowlevel_initwas in the wrong order, causing lr to lose its original value and be set equal to ip instead. Also, its use of the stack clashes with that ofs_init, so move thes_initcall after the restore and turn it into a tail-optimized branch.Signed-off-by Albert ARIBAUD <[email protected]>---
V2: moves_initcall after restore and tail-optimize it into a branch
V1: fix order of restoresarch/arm/cpu/armv7/omap3/lowlevel_init.S | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-)arch/arm/cpu/armv7/omap3/lowlevel_init.S +1
-3@@ -214,7 +214,7 @@ pll_div_val5: ENTRY(lowlevel_init) ldr sp, SRAM_STACK - str ip, [sp] /* stash old link register */ + str ip, [sp] /* stash ip register */ mov ip, lr /* save link reg across call */ #if !defined(CONFIG_SYS_NAND_BOOT) && !defined(CONFIG_SYS_ONENAND_BOOT) /*@@ -224,12 +224,11 @@ ENTRY(lowlevel_init) ldr r1, =SRAM_CLK_CODE bl cpy_clk_code #endif /* NAND Boot */ - bl s_init /* go setup pll, mux, memory */ - ldr ip, [sp] /* restore save ip */
arch/arm/cpu/armv7/omap3/lowlevel_init.S ENTRY(lowlevel_init) · line 234
Quoted 10 lines
arch/arm/cpu/armv7/omap3/lowlevel_init.S +3
-2mov lr, ip /* restore link reg */ + ldr ip, [sp] /* restore save ip */ + /* tail-call s_init to setup pll, mux, memory */ + b s_init - /* back to arch calling code */ - mov pc, lr ENDPROC(lowlevel_init) /* the literal pools origin */
on a tam3517 SOM (am3517 mcu) derived board.
Regards,
Jeroen
PATCH v2 1/1 arm: armv7: omap3: Fix restore sequence in lowlevel_init
In reply to Albert ARIBAUDQuoted 8 lines · Albert ARIBAUD
The restore sequence in
lowlevel_initwas in the wrong order, causing lr to lose its original value and be set equal to ip instead. Also, its use of the stack clashes with that ofs_init, so move thes_initcall after the restore and turn it into a tail-optimized branch.Signed-off-by Albert ARIBAUD <[email protected]>Tested-by Jeroen Hofstee <[email protected]>
Applied to u-boot/master, thanks!
Signature · 8 lines
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