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U-Boot Superseded Troy Kisky 11 participants 202 messages Sep 19, 2012 – Dec 4, 2012 Page 2 of 2

Subsystems (5)

Arm (32-bit) Arm i.MX and Layerscape Kbuild GPIO +1 more subsystems

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Troy Kisky

author

2012-11-28 01:31 UTC #118 lore raw

PATCH v4 6/11 imximage: move set_imx_hdr to struct data_src

In reply to Troy Kisky

Signed-off-by Troy Kisky <[email protected]>

---
v3: new patch

---
 tools/imximage.c |   13 ++++++-------
 tools/imximage.h |    1 +
 2 files changed, 7 insertions(+), 7 deletions(-)

tools/imximage.c +6 -7

index ddac95f..30f3c81 100644
@@ -67,7 +67,6 @@ static table_entry_t imximage_versions[] = {
 
 static set_dcd_val_t set_dcd_val;
 static set_dcd_rst_t set_dcd_rst;
-static set_imx_hdr_t set_imx_hdr;
 static uint32_t max_dcd_entries;
 static uint32_t *header_size_ptr;
 static uint32_t g_flash_offset;

@@ -253,19 +252,19 @@ static int set_imx_hdr_v2(struct data_src *ds, uint32_t dcd_len,
 	return header_length;
 }
 
-static void set_hdr_func(struct imx_header *imxhdr, uint32_t imximage_version)
+static void set_hdr_func(struct data_src *ds, uint32_t imximage_version)
 {
 	switch (imximage_version) {
 	case IMXIMAGE_V1:
 		set_dcd_val = set_dcd_val_v1;
 		set_dcd_rst = set_dcd_rst_v1;
-		set_imx_hdr = set_imx_hdr_v1;
+		ds->set_imx_hdr = set_imx_hdr_v1;
 		max_dcd_entries = MAX_HW_CFG_SIZE_V1;
 		break;
 	case IMXIMAGE_V2:
 		set_dcd_val = set_dcd_val_v2;
 		set_dcd_rst = set_dcd_rst_v2;
-		set_imx_hdr = set_imx_hdr_v2;
+		ds->set_imx_hdr = set_imx_hdr_v2;
 		max_dcd_entries = MAX_HW_CFG_SIZE_V2;
 		break;
 	default:

@@ -346,7 +345,7 @@ static void parse_cfg_cmd(struct data_src *ds, int32_t cmd, char *token,
 			exit(EXIT_FAILURE);
 		}
 		cmd_ver_first = 1;
-		set_hdr_func(ds->imxhdr, imximage_version);
+		set_hdr_func(ds, imximage_version);
 		break;
 	case CMD_BOOT_FROM:
 		g_flash_offset = get_table_entry_id(imximage_bootops,

@@ -431,7 +430,7 @@ static int parse_cfg_file(struct imx_header *imxhdr, char *name,
 	 * by adding VERSION command into it, here need
 	 * set up function ptr group to V1 by default.
 	 */
-	set_hdr_func(imxhdr, IMXIMAGE_V1);
+	set_hdr_func(&ds, IMXIMAGE_V1);
 	fd = fopen(name, "r");
 	if (fd == 0) {
 		fprintf(stderr, "Error: %s - Can't open DCD file\n", name);

@@ -474,7 +473,7 @@ static int parse_cfg_file(struct imx_header *imxhdr, char *name,
 		exit(EXIT_FAILURE);
 	}
 	/* Set the imx header */
-	return (*set_imx_hdr)(&ds, dcd_len, entry_point, g_flash_offset);
+	return (*ds.set_imx_hdr)(&ds, dcd_len, entry_point, g_flash_offset);
 }
 
 static int imximage_check_image_types(uint8_t type)

tools/imximage.h +1 -0

index 3054d55..f27a2ef 100644
@@ -174,5 +174,6 @@ typedef int (*set_imx_hdr_t)(struct data_src *ds, uint32_t dcd_len,
 
 struct data_src {
 	struct imx_header *imxhdr;
+	set_imx_hdr_t set_imx_hdr;
 };
 #endif /* _IMXIMAGE_H_ */

Signature · 1 line

1.7.9.5

Troy Kisky

author

2012-11-28 01:31 UTC #120 lore raw

PATCH v4 7/11 imximage: move set_dcd_val to struct data_src

In reply to Troy Kisky

Signed-off-by Troy Kisky <[email protected]>

---
v3: new patch

---
 tools/imximage.c |    9 ++++-----
 tools/imximage.h |    1 +
 2 files changed, 5 insertions(+), 5 deletions(-)

tools/imximage.c +4 -5

index 30f3c81..6d5cfa7 100644
@@ -65,7 +65,6 @@ static table_entry_t imximage_versions[] = {
 	{-1,            "",     " (Invalid)",                 },
 };
 
-static set_dcd_val_t set_dcd_val;
 static set_dcd_rst_t set_dcd_rst;
 static uint32_t max_dcd_entries;
 static uint32_t *header_size_ptr;

@@ -256,13 +255,13 @@ static void set_hdr_func(struct data_src *ds, uint32_t imximage_version)
 {
 	switch (imximage_version) {
 	case IMXIMAGE_V1:
-		set_dcd_val = set_dcd_val_v1;
+		ds->set_dcd_val = set_dcd_val_v1;
 		set_dcd_rst = set_dcd_rst_v1;
 		ds->set_imx_hdr = set_imx_hdr_v1;
 		max_dcd_entries = MAX_HW_CFG_SIZE_V1;
 		break;
 	case IMXIMAGE_V2:
-		set_dcd_val = set_dcd_val_v2;
+		ds->set_dcd_val = set_dcd_val_v2;
 		set_dcd_rst = set_dcd_rst_v2;
 		ds->set_imx_hdr = set_imx_hdr_v2;
 		max_dcd_entries = MAX_HW_CFG_SIZE_V2;

@@ -360,7 +359,7 @@ static void parse_cfg_cmd(struct data_src *ds, int32_t cmd, char *token,
 		break;
 	case CMD_DATA:
 		value = get_cfg_value(token, name, lineno);
-		(*set_dcd_val)(ds, name, lineno, fld, value, dcd_len);
+		(*ds->set_dcd_val)(ds, name, lineno, fld, value, dcd_len);
 		if (unlikely(cmd_ver_first != 1))
 			cmd_ver_first = 0;
 		break;

@@ -391,7 +390,7 @@ static void parse_cfg_fld(struct data_src *ds, int32_t *cmd,
 			return;
 
 		value = get_cfg_value(token, name, lineno);
-		(*set_dcd_val)(ds, name, lineno, fld, value, *dcd_len);
+		(*ds->set_dcd_val)(ds, name, lineno, fld, value, *dcd_len);
 
 		if (fld == CFG_REG_VALUE) {
 			(*dcd_len)++;

tools/imximage.h +1 -0

index f27a2ef..444ddce 100644
@@ -175,5 +175,6 @@ typedef int (*set_imx_hdr_t)(struct data_src *ds, uint32_t dcd_len,
 struct data_src {
 	struct imx_header *imxhdr;
 	set_imx_hdr_t set_imx_hdr;
+	set_dcd_val_t set_dcd_val;
 };
 #endif /* _IMXIMAGE_H_ */

Signature · 1 line

1.7.9.5

Troy Kisky

author

2012-11-28 01:31 UTC #122 lore raw

PATCH v4 8/11 imximage: enable word writes for version2 header

In reply to Troy Kisky

Before, only 1 write_dcd_command table was built.
Now, a new table is built when the size changes.

Signed-off-by Troy Kisky <[email protected]>

---
v3: moved static variables together

---
 tools/imximage.c |  143 ++++++++++++++++++++++++++----------------------------
 tools/imximage.h |   18 +++----
 2 files changed, 76 insertions(+), 85 deletions(-)

tools/imximage.c +69 ~~-74~~

index 6d5cfa7..2f5ee14 100644
@@ -65,8 +65,6 @@ static table_entry_t imximage_versions[] = {
 	{-1,            "",     " (Invalid)",                 },
 };
 
-static set_dcd_rst_t set_dcd_rst;
-static uint32_t max_dcd_entries;
 static uint32_t *header_size_ptr;
 static uint32_t g_flash_offset;

@@ -115,7 +113,7 @@ static void err_imximage_version(int version)
 }
 
 static void set_dcd_val_v1(struct data_src *ds, char *name, int lineno,
-					int fld, uint32_t value, uint32_t off)
+					int fld, uint32_t value)
 {
 	dcd_v1_t *dcd_v1 = &ds->imxhdr->header.hdr_v1.dcd_table;

@@ -128,13 +126,15 @@ static void set_dcd_val_v1(struct data_src *ds, char *name, int lineno,
 				name, lineno, value);
 			exit(EXIT_FAILURE);
 		}
-		dcd_v1->addr_data[off].type = value;
+		*ds->p_entry++ = value;
 		break;
 	case CFG_REG_ADDRESS:
-		dcd_v1->addr_data[off].addr = value;
+		*ds->p_entry++ = value;
 		break;
 	case CFG_REG_VALUE:
-		dcd_v1->addr_data[off].value = value;
+		*ds->p_entry++ = value;
+		dcd_v1->preamble.length = (char *)ds->p_entry
+				- (char *)&dcd_v1->addr_data[0].type;
 		break;
 	default:
 		break;

@@ -143,16 +143,42 @@ static void set_dcd_val_v1(struct data_src *ds, char *name, int lineno,
 }
 
 static void set_dcd_val_v2(struct data_src *ds, char *name, int lineno,
-					int fld, uint32_t value, uint32_t off)
+					int fld, uint32_t value)
 {
+	uint32_t len;
 	dcd_v2_t *dcd_v2 = &ds->imxhdr->header.hdr_v2.dcd_table;
 
 	switch (fld) {
+	case CFG_REG_SIZE:
+		/* Byte, halfword, word */
+		if ((value != 1) && (value != 2) && (value != 4)) {
+			fprintf(stderr, "Error: %s[%d] - "
+				"Invalid register size " "(%d)\n",
+				name, lineno, value);
+			exit(EXIT_FAILURE);
+		}
+		if (ds->p_dcd && (ds->p_dcd->param == value))
+			break;
+		if (!ds->p_dcd) {
+			dcd_v2->header.tag = DCD_HEADER_TAG;
+			dcd_v2->header.version = DCD_VERSION;
+			ds->p_dcd = &dcd_v2->write_dcd_command;
+		} else {
+			ds->p_dcd = (write_dcd_command_t *)ds->p_entry;
+		}
+		ds->p_dcd->param = value;
+		ds->p_dcd->tag = DCD_COMMAND_TAG;
+		ds->p_entry = (uint32_t *)(ds->p_dcd + 1);
+		break;
 	case CFG_REG_ADDRESS:
-		dcd_v2->addr_data[off].addr = cpu_to_be32(value);
+		*ds->p_entry++ = cpu_to_be32(value);
 		break;
 	case CFG_REG_VALUE:
-		dcd_v2->addr_data[off].value = cpu_to_be32(value);
+		*ds->p_entry++ = cpu_to_be32(value);
+		len = (char *)ds->p_entry - (char *)&dcd_v2->header;
+		dcd_v2->header.length = cpu_to_be16(len);
+		len = (char *)ds->p_entry - (char *)ds->p_dcd;
+		ds->p_dcd->length = cpu_to_be16(len);
 		break;
 	default:
 		break;

@@ -160,47 +186,14 @@ static void set_dcd_val_v2(struct data_src *ds, char *name, int lineno,
 	}
 }
 
-/*
- * Complete setting up the rest field of DCD of V1
- * such as barker code and DCD data length.
- */
-static void set_dcd_rst_v1(struct imx_header *imxhdr, uint32_t dcd_len,
-						char *name, int lineno)
-{
-	dcd_v1_t *dcd_v1 = &imxhdr->header.hdr_v1.dcd_table;
-
-	dcd_v1->preamble.barker = DCD_BARKER;
-	dcd_v1->preamble.length = dcd_len * sizeof(dcd_type_addr_data_t);
-}
-
-/*
- * Complete setting up the reset field of DCD of V2
- * such as DCD tag, version, length, etc.
- */
-static void set_dcd_rst_v2(struct imx_header *imxhdr, uint32_t dcd_len,
-						char *name, int lineno)
-{
-	dcd_v2_t *dcd_v2 = &imxhdr->header.hdr_v2.dcd_table;
-
-	dcd_v2->header.tag = DCD_HEADER_TAG;
-	dcd_v2->header.length = cpu_to_be16(
-			dcd_len * sizeof(dcd_addr_data_t) + 8);
-	dcd_v2->header.version = DCD_VERSION;
-	dcd_v2->write_dcd_command.tag = DCD_COMMAND_TAG;
-	dcd_v2->write_dcd_command.length = cpu_to_be16(
-			dcd_len * sizeof(dcd_addr_data_t) + 4);
-	dcd_v2->write_dcd_command.param = DCD_COMMAND_PARAM;
-}
-
-static int set_imx_hdr_v1(struct data_src *ds, uint32_t dcd_len,
+static int set_imx_hdr_v1(struct data_src *ds,
 		uint32_t entry_point, uint32_t flash_offset)
 {
 	imx_header_v1_t *hdr_v1 = &ds->imxhdr->header.hdr_v1;
 	flash_header_v1_t *fhdr_v1 = &hdr_v1->fhdr;
-	dcd_v1_t *dcd_v1 = &hdr_v1->dcd_table;
 	uint32_t hdr_base;
-	uint32_t header_length = (((char *)&dcd_v1->addr_data[dcd_len].addr)
-			- ((char *)ds->imxhdr));
+	uint32_t header_length = ((char *)ds->p_entry) + 4
+			- ((char *)ds->imxhdr);
 
 	/* Set magic number */
 	fhdr_v1->app_code_barker = APP_CODE_BARKER;

@@ -220,15 +213,13 @@ static int set_imx_hdr_v1(struct data_src *ds, uint32_t dcd_len,
 	return header_length;
 }
 
-static int set_imx_hdr_v2(struct data_src *ds, uint32_t dcd_len,
+static int set_imx_hdr_v2(struct data_src *ds,
 		uint32_t entry_point, uint32_t flash_offset)
 {
 	imx_header_v2_t *hdr_v2 = &ds->imxhdr->header.hdr_v2;
 	flash_header_v2_t *fhdr_v2 = &hdr_v2->fhdr;
 	uint32_t hdr_base;
-	uint32_t header_length = (dcd_len) ?
-		(char *)&hdr_v2->dcd_table.addr_data[dcd_len] -
-		((char *)ds->imxhdr) : offsetof(imx_header_v2_t, dcd_table);
+	uint32_t header_length = ((char *)ds->p_entry) - ((char *)ds->imxhdr);
 
 	/* Set magic number */
 	fhdr_v2->header.tag = IVT_HEADER_TAG; /* 0xD1 */

@@ -239,7 +230,7 @@ static int set_imx_hdr_v2(struct data_src *ds, uint32_t dcd_len,
 	fhdr_v2->reserved1 = fhdr_v2->reserved2 = 0;
 	fhdr_v2->self = hdr_base = entry_point - header_length;
 
-	fhdr_v2->dcd_ptr = (dcd_len) ? hdr_base
+	fhdr_v2->dcd_ptr = (ds->p_dcd) ? hdr_base
 			+ offsetof(imx_header_v2_t, dcd_table) : 0;
 	fhdr_v2->boot_data_ptr = hdr_base
 			+ offsetof(imx_header_v2_t, boot_data);

@@ -256,15 +247,20 @@ static void set_hdr_func(struct data_src *ds, uint32_t imximage_version)
 	switch (imximage_version) {
 	case IMXIMAGE_V1:
 		ds->set_dcd_val = set_dcd_val_v1;
-		set_dcd_rst = set_dcd_rst_v1;
 		ds->set_imx_hdr = set_imx_hdr_v1;
-		max_dcd_entries = MAX_HW_CFG_SIZE_V1;
+		ds->p_entry = &ds->imxhdr->header.hdr_v1.dcd_table
+				.addr_data[0].type;
+		ds->p_max_dcd = &ds->imxhdr->header.hdr_v1.dcd_table
+				.addr_data[MAX_HW_CFG_SIZE_V1].type;
+		ds->imxhdr->header.hdr_v1.dcd_table.preamble.barker =
+				DCD_BARKER;
 		break;
 	case IMXIMAGE_V2:
 		ds->set_dcd_val = set_dcd_val_v2;
-		set_dcd_rst = set_dcd_rst_v2;
 		ds->set_imx_hdr = set_imx_hdr_v2;
-		max_dcd_entries = MAX_HW_CFG_SIZE_V2;
+		ds->p_entry = (uint32_t *)&ds->imxhdr->header.hdr_v2.dcd_table;
+		ds->p_max_dcd = (uint32_t *)
+				((char *)ds->imxhdr + MAX_HEADER_SIZE);
 		break;
 	default:
 		err_imximage_version(imximage_version);

@@ -328,7 +324,7 @@ static void print_hdr_v2(struct imx_header *imx_hdr)
 }
 
 static void parse_cfg_cmd(struct data_src *ds, int32_t cmd, char *token,
-				char *name, int lineno, int fld, int dcd_len)
+				char *name, int lineno, int fld)
 {
 	int value;
 	static int cmd_ver_first = ~0;

@@ -359,7 +355,7 @@ static void parse_cfg_cmd(struct data_src *ds, int32_t cmd, char *token,
 		break;
 	case CMD_DATA:
 		value = get_cfg_value(token, name, lineno);
-		(*ds->set_dcd_val)(ds, name, lineno, fld, value, dcd_len);
+		(*ds->set_dcd_val)(ds, name, lineno, fld, value);
 		if (unlikely(cmd_ver_first != 1))
 			cmd_ver_first = 0;
 		break;

@@ -367,7 +363,7 @@ static void parse_cfg_cmd(struct data_src *ds, int32_t cmd, char *token,
 }
 
 static void parse_cfg_fld(struct data_src *ds, int32_t *cmd,
-		char *token, char *name, int lineno, int fld, int *dcd_len)
+		char *token, char *name, int lineno, int fld)
 {
 	int value;

@@ -382,7 +378,7 @@ static void parse_cfg_fld(struct data_src *ds, int32_t *cmd,
 		}
 		break;
 	case CFG_REG_SIZE:
-		parse_cfg_cmd(ds, *cmd, token, name, lineno, fld, *dcd_len);
+		parse_cfg_cmd(ds, *cmd, token, name, lineno, fld);
 		break;
 	case CFG_REG_ADDRESS:
 	case CFG_REG_VALUE:

@@ -390,16 +386,14 @@ static void parse_cfg_fld(struct data_src *ds, int32_t *cmd,
 			return;
 
 		value = get_cfg_value(token, name, lineno);
-		(*ds->set_dcd_val)(ds, name, lineno, fld, value, *dcd_len);
-
-		if (fld == CFG_REG_VALUE) {
-			(*dcd_len)++;
-			if (*dcd_len > max_dcd_entries) {
-				fprintf(stderr, "Error: %s[%d] -"
-					"DCD table exceeds maximum size(%d)\n",
-					name, lineno, max_dcd_entries);
-				exit(EXIT_FAILURE);
-			}
+		(*ds->set_dcd_val)(ds, name, lineno, fld, value);
+		if (ds->p_entry > ds->p_max_dcd) {
+			uint32_t size = (char *)ds->p_max_dcd -
+					(char *)ds->imxhdr;
+			fprintf(stderr, "Error: %s[%d] -"
+					"header exceeds maximum size(%d)\n",
+					name, lineno, size);
+			exit(EXIT_FAILURE);
 		}
 		break;
 	default:

@@ -417,7 +411,6 @@ static int parse_cfg_file(struct imx_header *imxhdr, char *name,
 	int lineno = 0;
 	int fld;
 	size_t len;
-	int dcd_len = 0;
 	int32_t cmd;
 
 	/* Be able to detect if the cfg file has no BOOT_FROM tag */

@@ -458,12 +451,10 @@ static int parse_cfg_file(struct imx_header *imxhdr, char *name,
 				break;
 
 			parse_cfg_fld(&ds, &cmd, token, name,
-					lineno, fld, &dcd_len);
+					lineno, fld);
 		}
 
 	}
-
-	(*set_dcd_rst)(imxhdr, dcd_len, name, lineno);
 	fclose(fd);
 
 	/* Exit if there is no BOOT_FROM field specifying the flash_offset */

@@ -472,7 +463,7 @@ static int parse_cfg_file(struct imx_header *imxhdr, char *name,
 		exit(EXIT_FAILURE);
 	}
 	/* Set the imx header */
-	return (*ds.set_imx_hdr)(&ds, dcd_len, entry_point, g_flash_offset);
+	return (*ds.set_imx_hdr)(&ds, entry_point, g_flash_offset);
 }
 
 static int imximage_check_image_types(uint8_t type)

@@ -517,7 +508,11 @@ int imximage_vrec_header(struct mkimage_params *params,
 {
 	struct imx_header *imxhdr;
 
-	imxhdr = calloc(1, MAX_HEADER_SIZE);
+	/*
+	 * A little extra space to avoid access violation on dcd table overflow.
+	 * Overflow is checked after entry is added.
+	 */
+	imxhdr = calloc(1, MAX_HEADER_SIZE + 32);
 	if (!imxhdr) {
 		fprintf(stderr, "Error: out of memory\n");
 		exit(EXIT_FAILURE);

tools/imximage.h +7 ~~-11~~

index 444ddce..196bb51 100644
@@ -47,7 +47,6 @@
 #define DCD_HEADER_TAG 0xD2
 #define DCD_COMMAND_TAG 0xCC
 #define DCD_VERSION 0x40
-#define DCD_COMMAND_PARAM 0x4
 
 enum imximage_cmd {
 	CMD_INVALID,

@@ -160,21 +159,18 @@ struct imx_header {
 };
 
 struct data_src;
-typedef void (*set_dcd_val_t)(struct data_src *ds,
-					char *name, int lineno,
-					int fld, uint32_t value,
-					uint32_t off);
+typedef void (*set_dcd_val_t)(struct data_src *ds, char *name,
+		int lineno, int fld, uint32_t value);
 
-typedef void (*set_dcd_rst_t)(struct imx_header *imxhdr,
-					uint32_t dcd_len,
-					char *name, int lineno);
-
-typedef int (*set_imx_hdr_t)(struct data_src *ds, uint32_t dcd_len,
-		uint32_t entry_point, uint32_t flash_offset);
+typedef int (*set_imx_hdr_t)(struct data_src *ds, uint32_t entry_point,
+		uint32_t flash_offset);
 
 struct data_src {
 	struct imx_header *imxhdr;
 	set_imx_hdr_t set_imx_hdr;
 	set_dcd_val_t set_dcd_val;
+	uint32_t *p_max_dcd;
+	uint32_t *p_entry;
+	write_dcd_command_t *p_dcd;
 };
 #endif /* _IMXIMAGE_H_ */

Signature · 1 line

1.7.9.5

Wolfgang Denk

2012-11-28 09:39 UTC #123 lore raw

PATCH v4 8/11 imximage: enable word writes for version2 header

Dear Troy Kisky,

Quoted 2 lines · In message <[email protected]>…

Before, only 1 write_dcd_command table was built.
Now, a new table is built when the size changes.

I cannot see how the Subject: and the actual commit message (and code) are related.

Best regards,

Wolfgang Denk

Signature · 5 lines

DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
If a group of N persons implements a COBOL compiler,  there  will  be
N-1 passes. Someone in the group has to be the manager. - T. Cheatham

Troy Kisky

author

2012-11-28 20:40 UTC #124 lore raw

PATCH v4 8/11 imximage: enable word writes for version2 header

Quoted 12 lines · Wolfgang Denk

Dear Troy Kisky,
Quoted 2 lines · In message <[email protected]>…
Before, only 1 write_dcd_command table was built.
Now, a new table is built when the size changes.
I cannot see how the Subject: and the actual commit message (and code) are related.
Best regards,
Wolfgang Denk

How about this for the commit message

Before, only 1 write_dcd_command table was built.
Now, a new table is built when the size changes.

i.e. before this patch, the sequence
DATA 4 0x83FD9014 0x00000000
DATA 2 0x83FC8000 0x00fe

was only valid for Version 1 headers, now it is valid for Version 2 headers as well.

Parameters were changed for set_dcd_val_t to accomplish this. So, set_dcd_val_v1 for version 1 was also slightly modified. But no new functionality was added for version 1.

No current config files use this functionality, but this patch removes more lines than it adds.
_________________________________________________________

Stefano Babic

2012-12-04 08:23 UTC #125 lore raw

PATCH v4 8/11 imximage: enable word writes for version2 header

Quoted 20 lines · Troy Kisky

Quoted 5 lines · Wolfgang Denk
Dear Troy Kisky,
In message <[email protected]> you wrote:
Quoted 9 lines
Quoted 2 lines
Before, only 1 write_dcd_command table was built.
Now, a new table is built when the size changes.
I cannot see how the Subject: and the actual commit message (and code) are related.
Best regards,
Wolfgang Denk
How about this for the commit message
Before, only 1 write_dcd_command table was built.
Now, a new table is built when the size changes.

Quoted 6 lines

i.e. before this patch, the sequence
DATA 4 0x83FD9014 0x00000000
DATA 2 0x83FC8000 0x00fe
was only valid for Version 1 headers, now it is valid for Version 2 headers as well.

Much better ! Maybe you can also change the title of the patch, telling that you are fixing a bug (the fact that first parameter was not correctly interpreted for V2 *is* a bug). And the example explains very well the issue.

Quoted 7 lines

Parameters were changed for set_dcd_val_t to accomplish this. So, set_dcd_val_v1 for version 1 was also slightly modified. But no new functionality was added for version 1.
No current config files use this functionality, but this patch removes more lines than it adds.

Best regards,
Stefano Babic

Signature · 5 lines

=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

Liu Hui-R64343

2012-11-28 10:47 UTC #126 lore raw

PATCH v4 8/11 imximage: enable word writes for version2 header

In reply to Troy Kisky

Quoted 8 lines

-----Original Message-----
From: Troy Kisky [mailto:troy.kisky at boundarydevices.com]
Sent: Wednesday, November 28, 2012 9:32 AM
To: sbabic at denx.de
Cc: dirk.behme at googlemail.com; u-boot at lists.denx.de; Liu Hui-R64343; festevam at gmail.com; Troy Kisky
Subject: [PATCH V4 08/11] imximage: enable word writes for version2 header

Quoted 4 lines

Before, only 1 write_dcd_command table was built.
Now, a new table is built when the size changes.
Signed-off-by Troy Kisky <[email protected]>

Acked-by Jason Liu <[email protected]>

Quoted 353 lines

---
v3: moved static variables together
---
tools/imximage.c | 143 ++++++++++++++++++++++++++----------------------------
tools/imximage.h | 18 +++----

2 files changed, 76 insertions(+), 85 deletions(-)

tools/imximage.c index 6d5cfa7..2f5ee14 renamed from tools/imximage.c +0 -0

100644

tools/imximage.c +6 -6

@@ -65,8 +65,6 @@ static table_entry_t imximage_versions[] = {
 	{-1,            "",     " (Invalid)",                 },
 };
 
-static set_dcd_rst_t set_dcd_rst;
-static uint32_t max_dcd_entries;
 static uint32_t *header_size_ptr;
 static uint32_t g_flash_offset;

@@ -115,7 +113,7 @@ static void err_imximage_version(int version)  }
 
 static void set_dcd_val_v1(struct data_src *ds, char *name, int lineno,
-					int fld, uint32_t value, uint32_t off)
+					int fld, uint32_t value)
 {
 	dcd_v1_t *dcd_v1 = &ds->imxhdr->header.hdr_v1.dcd_table;

@@ -128,13 +126,15 @@ static void set_dcd_val_v1(struct data_src *ds, char
 *name, int lineno,
 				name, lineno, value);
 			exit(EXIT_FAILURE);
 		}
-		dcd_v1->addr_data[off].type = value;
+		*ds->p_entry++ = value;
 		break;
 	case CFG_REG_ADDRESS:
-		dcd_v1->addr_data[off].addr = value;
+		*ds->p_entry++ = value;
 		break;
 	case CFG_REG_VALUE:
-		dcd_v1->addr_data[off].value = value;
+		*ds->p_entry++ = value;
+		dcd_v1->preamble.length = (char *)ds->p_entry
+				- (char *)&dcd_v1->addr_data[0].type;
 		break;
 	default:

		break;

tools/imximage.c +32 ~~-39~~

@@ -143,16 +143,42 @@ static void set_dcd_val_v1(struct data_src *ds, char
 *name, int lineno,  }
 
 static void set_dcd_val_v2(struct data_src *ds, char *name, int lineno,
-					int fld, uint32_t value, uint32_t off)
+					int fld, uint32_t value)
 {
+	uint32_t len;
 	dcd_v2_t *dcd_v2 = &ds->imxhdr->header.hdr_v2.dcd_table;
 
 	switch (fld) {
+	case CFG_REG_SIZE:
+		/* Byte, halfword, word */
+		if ((value != 1) && (value != 2) && (value != 4)) {
+			fprintf(stderr, "Error: %s[%d] - "
+				"Invalid register size " "(%d)\n",
+				name, lineno, value);
+			exit(EXIT_FAILURE);
+		}
+		if (ds->p_dcd && (ds->p_dcd->param == value))
+			break;
+		if (!ds->p_dcd) {
+			dcd_v2->header.tag = DCD_HEADER_TAG;
+			dcd_v2->header.version = DCD_VERSION;
+			ds->p_dcd = &dcd_v2->write_dcd_command;
+		} else {
+			ds->p_dcd = (write_dcd_command_t *)ds->p_entry;
+		}
+		ds->p_dcd->param = value;
+		ds->p_dcd->tag = DCD_COMMAND_TAG;
+		ds->p_entry = (uint32_t *)(ds->p_dcd + 1);
+		break;
 	case CFG_REG_ADDRESS:
-		dcd_v2->addr_data[off].addr = cpu_to_be32(value);
+		*ds->p_entry++ = cpu_to_be32(value);
 		break;
 	case CFG_REG_VALUE:
-		dcd_v2->addr_data[off].value = cpu_to_be32(value);
+		*ds->p_entry++ = cpu_to_be32(value);
+		len = (char *)ds->p_entry - (char *)&dcd_v2->header;
+		dcd_v2->header.length = cpu_to_be16(len);
+		len = (char *)ds->p_entry - (char *)ds->p_dcd;
+		ds->p_dcd->length = cpu_to_be16(len);
 		break;
 	default:
 		break;

@@ -160,47 +186,14 @@ static void set_dcd_val_v2(struct data_src *ds, char
 *name, int lineno,
 	}
 }
 
-/*
- * Complete setting up the rest field of DCD of V1
- * such as barker code and DCD data length.
- */
-static void set_dcd_rst_v1(struct imx_header *imxhdr, uint32_t dcd_len,
-						char *name, int lineno)
-{
-	dcd_v1_t *dcd_v1 = &imxhdr->header.hdr_v1.dcd_table;
-
-	dcd_v1->preamble.barker = DCD_BARKER;
-	dcd_v1->preamble.length = dcd_len * sizeof(dcd_type_addr_data_t);
-}
-
-/*
- * Complete setting up the reset field of DCD of V2
- * such as DCD tag, version, length, etc.
- */
-static void set_dcd_rst_v2(struct imx_header *imxhdr, uint32_t dcd_len,
-						char *name, int lineno)
-{
-	dcd_v2_t *dcd_v2 = &imxhdr->header.hdr_v2.dcd_table;
-
-	dcd_v2->header.tag = DCD_HEADER_TAG;
-	dcd_v2->header.length = cpu_to_be16(
-			dcd_len * sizeof(dcd_addr_data_t) + 8);
-	dcd_v2->header.version = DCD_VERSION;
-	dcd_v2->write_dcd_command.tag = DCD_COMMAND_TAG;
-	dcd_v2->write_dcd_command.length = cpu_to_be16(
-			dcd_len * sizeof(dcd_addr_data_t) + 4);
-	dcd_v2->write_dcd_command.param = DCD_COMMAND_PARAM;
-}
-
-static int set_imx_hdr_v1(struct data_src *ds, uint32_t dcd_len,
+static int set_imx_hdr_v1(struct data_src *ds,
 		uint32_t entry_point, uint32_t flash_offset)  {
 	imx_header_v1_t *hdr_v1 = &ds->imxhdr->header.hdr_v1;
 	flash_header_v1_t *fhdr_v1 = &hdr_v1->fhdr;
-	dcd_v1_t *dcd_v1 = &hdr_v1->dcd_table;
 	uint32_t hdr_base;
-	uint32_t header_length = (((char *)&dcd_v1-
 >addr_data[dcd_len].addr)
-			- ((char *)ds->imxhdr));
+	uint32_t header_length = ((char *)ds->p_entry) + 4
+			- ((char *)ds->imxhdr);
 
 	/* Set magic number */

	fhdr_v1->app_code_barker = APP_CODE_BARKER; @@ -220,15
+213,13 @@ static int set_imx_hdr_v1(struct data_src *ds, uint32_t dcd_len,
	return header_length;
}

tools/imximage.c +1 -1

-static int set_imx_hdr_v2(struct data_src *ds, uint32_t dcd_len,
+static int set_imx_hdr_v2(struct data_src *ds,

		uint32_t entry_point, uint32_t flash_offset)  {
	imx_header_v2_t *hdr_v2 = &ds->imxhdr->header.hdr_v2;
	flash_header_v2_t *fhdr_v2 = &hdr_v2->fhdr;
	uint32_t hdr_base;

tools/imximage.c +1 -3

-	uint32_t header_length = (dcd_len) ?
-		(char *)&hdr_v2->dcd_table.addr_data[dcd_len] -
-		((char *)ds->imxhdr) : offsetof(imx_header_v2_t, dcd_table);
+	uint32_t header_length = ((char *)ds->p_entry) - ((char *)ds->imxhdr);

	/* Set magic number */
	fhdr_v2->header.tag = IVT_HEADER_TAG; /* 0xD1 */ @@ -239,7
+230,7 @@ static int set_imx_hdr_v2(struct data_src *ds, uint32_t dcd_len,
	fhdr_v2->reserved1 = fhdr_v2->reserved2 = 0;
	fhdr_v2->self = hdr_base = entry_point - header_length;

tools/imximage.c +1 -1

-	fhdr_v2->dcd_ptr = (dcd_len) ? hdr_base
+	fhdr_v2->dcd_ptr = (ds->p_dcd) ? hdr_base

+ offsetof(imx_header_v2_t, dcd_table) : 0;
fhdr_v2->boot_data_ptr = hdr_base
+ offsetof(imx_header_v2_t, boot_data); @@ -256,15
+247,20 @@ static void set_hdr_func(struct data_src *ds, uint32_t imximage_version)

	switch (imximage_version) {
	case IMXIMAGE_V1:
		ds->set_dcd_val = set_dcd_val_v1;

tools/imximage.c +0 -1

-		set_dcd_rst = set_dcd_rst_v1;

		ds->set_imx_hdr = set_imx_hdr_v1;

tools/imximage.c +6 -1

-		max_dcd_entries = MAX_HW_CFG_SIZE_V1;
+		ds->p_entry = &ds->imxhdr->header.hdr_v1.dcd_table
+				.addr_data[0].type;
+		ds->p_max_dcd = &ds->imxhdr->header.hdr_v1.dcd_table
+				.addr_data[MAX_HW_CFG_SIZE_V1].type;
+		ds->imxhdr->header.hdr_v1.dcd_table.preamble.barker =
+				DCD_BARKER;

		break;
	case IMXIMAGE_V2:
		ds->set_dcd_val = set_dcd_val_v2;

tools/imximage.c +0 -1

-		set_dcd_rst = set_dcd_rst_v2;

		ds->set_imx_hdr = set_imx_hdr_v2;

tools/imximage.c +1 -1

-		max_dcd_entries = MAX_HW_CFG_SIZE_V2;
+		ds->p_entry = (uint32_t *)&ds->imxhdr-

Quoted 1 line

header.hdr_v2.dcd_table;

tools/imximage.c +2 -0

+		ds->p_max_dcd = (uint32_t *)
+				((char *)ds->imxhdr + MAX_HEADER_SIZE);

		break;
	default:
		err_imximage_version(imximage_version);

tools/imximage.c +2 -2

@@ -328,7 +324,7 @@ static void print_hdr_v2(struct imx_header
 *imx_hdr)  }
 
 static void parse_cfg_cmd(struct data_src *ds, int32_t cmd, char *token,
-				char *name, int lineno, int fld, int dcd_len)
+				char *name, int lineno, int fld)
 {
 	int value;
 	static int cmd_ver_first = ~0;

@@ -359,7 +355,7 @@ static void parse_cfg_cmd(struct data_src *ds, int32_t
 cmd, char *token,
 		break;
 	case CMD_DATA:
 		value = get_cfg_value(token, name, lineno);
-		(*ds->set_dcd_val)(ds, name, lineno, fld, value, dcd_len);
+		(*ds->set_dcd_val)(ds, name, lineno, fld, value);
 		if (unlikely(cmd_ver_first != 1))
 			cmd_ver_first = 0;

		break;

tools/imximage.c +2 -2

@@ -367,7 +363,7 @@ static void parse_cfg_cmd(struct data_src *ds, int32_t
 cmd, char *token,  }
 
 static void parse_cfg_fld(struct data_src *ds, int32_t *cmd,
-		char *token, char *name, int lineno, int fld, int *dcd_len)
+		char *token, char *name, int lineno, int fld)
 {
 	int value;

@@ -382,7 +378,7 @@ static void parse_cfg_fld(struct data_src *ds, int32_t
 *cmd,
 		}
 		break;
 	case CFG_REG_SIZE:
-		parse_cfg_cmd(ds, *cmd, token, name, lineno, fld, *dcd_len);
+		parse_cfg_cmd(ds, *cmd, token, name, lineno, fld);
 		break;
 	case CFG_REG_ADDRESS:

case CFG_REG_VALUE:

tools/imximage.c +8 ~~-10~~

@@ -390,16 +386,14 @@ static void parse_cfg_fld(struct data_src *ds,
 int32_t *cmd,
 			return;
 
 		value = get_cfg_value(token, name, lineno);
-		(*ds->set_dcd_val)(ds, name, lineno, fld, value, *dcd_len);
-
-		if (fld == CFG_REG_VALUE) {
-			(*dcd_len)++;
-			if (*dcd_len > max_dcd_entries) {
-				fprintf(stderr, "Error: %s[%d] -"
-					"DCD table exceeds maximum size(%d)\n",
-					name, lineno, max_dcd_entries);
-				exit(EXIT_FAILURE);
-			}
+		(*ds->set_dcd_val)(ds, name, lineno, fld, value);
+		if (ds->p_entry > ds->p_max_dcd) {
+			uint32_t size = (char *)ds->p_max_dcd -
+					(char *)ds->imxhdr;
+			fprintf(stderr, "Error: %s[%d] -"
+					"header exceeds maximum size(%d)\n",
+					name, lineno, size);
+			exit(EXIT_FAILURE);
 		}
 		break;

default:

tools/imximage.c +0 -1

@@ -417,7 +411,6 @@ static int parse_cfg_file(struct imx_header *imxhdr,
 char *name,
 	int lineno = 0;
 	int fld;
 	size_t len;
-	int dcd_len = 0;
 	int32_t cmd;

	/* Be able to detect if the cfg file has no BOOT_FROM tag */ @@ -
458,12 +451,10 @@ static int parse_cfg_file(struct imx_header *imxhdr, char
*name,
				break;

			parse_cfg_fld(&ds, &cmd, token, name,

tools/imximage.c +1 -1

-					lineno, fld, &dcd_len);
+					lineno, fld);

		}

	}

tools/imximage.c +0 -2

-
-	(*set_dcd_rst)(imxhdr, dcd_len, name, lineno);

	fclose(fd);

	/* Exit if there is no BOOT_FROM field specifying the flash_offset */

tools/imximage.c +1 -1

@@ -472,7 +463,7 @@ static int parse_cfg_file(struct imx_header *imxhdr,
 char *name,
 		exit(EXIT_FAILURE);
 	}
 	/* Set the imx header */
-	return (*ds.set_imx_hdr)(&ds, dcd_len, entry_point, g_flash_offset);
+	return (*ds.set_imx_hdr)(&ds, entry_point, g_flash_offset);
 }

static int imximage_check_image_types(uint8_t type) @@ -517,7 +508,11

@@ int imximage_vrec_header(struct mkimage_params *params,  {
	struct imx_header *imxhdr;

tools/imximage.c +5 -1

-	imxhdr = calloc(1, MAX_HEADER_SIZE);
+	/*
+	 * A little extra space to avoid access violation on dcd table overflow.
+	 * Overflow is checked after entry is added.
+	 */
+	imxhdr = calloc(1, MAX_HEADER_SIZE + 32);

	if (!imxhdr) {
		fprintf(stderr, "Error: out of memory\n");
		exit(EXIT_FAILURE);

tools/imximage.h index 444ddce..196bb51 renamed from tools/imximage.h +0 -0

100644

tools/imximage.h +7 ~~-12~~

@@ -47,7 +47,6 @@
 #define DCD_HEADER_TAG 0xD2
 #define DCD_COMMAND_TAG 0xCC
 #define DCD_VERSION 0x40
-#define DCD_COMMAND_PARAM 0x4
 
 enum imximage_cmd {
 	CMD_INVALID,

@@ -160,21 +159,18 @@ struct imx_header {  };
 
 struct data_src;
-typedef void (*set_dcd_val_t)(struct data_src *ds,
-					char *name, int lineno,
-					int fld, uint32_t value,
-					uint32_t off);
+typedef void (*set_dcd_val_t)(struct data_src *ds, char *name,
+		int lineno, int fld, uint32_t value);
 
-typedef void (*set_dcd_rst_t)(struct imx_header *imxhdr,
-					uint32_t dcd_len,
-					char *name, int lineno);
-
-typedef int (*set_imx_hdr_t)(struct data_src *ds, uint32_t dcd_len,
-		uint32_t entry_point, uint32_t flash_offset);
+typedef int (*set_imx_hdr_t)(struct data_src *ds, uint32_t entry_point,
+		uint32_t flash_offset);
 
 struct data_src {
 	struct imx_header *imxhdr;
 	set_imx_hdr_t set_imx_hdr;
 	set_dcd_val_t set_dcd_val;
+	uint32_t *p_max_dcd;
+	uint32_t *p_entry;
+	write_dcd_command_t *p_dcd;
 };
 #endif /* _IMXIMAGE_H_ */
--

1.7.9.5

Troy Kisky

author

2012-11-28 01:31 UTC #127 lore raw

PATCH v4 9/11 tools: add parse_helper file

In reply to Troy Kisky

This file can help you parse
configuration files.

Signed-off-by Troy Kisky <[email protected]>

---
 tools/Makefile       |    2 +
 tools/parse_helper.c |  173 ++++++++++++++++++++++++++++++++++++++++++++++++++
 tools/parse_helper.h |   28 ++++++++
 3 files changed, 203 insertions(+)
 create mode 100644 tools/parse_helper.c
 create mode 100644 tools/parse_helper.h

tools/Makefile +2 -0

index 686840a..db3b247 100644
@@ -94,6 +94,7 @@ NOPED_OBJ_FILES-y += aisimage.o
 NOPED_OBJ_FILES-y += kwbimage.o
 NOPED_OBJ_FILES-y += pblimage.o
 NOPED_OBJ_FILES-y += imximage.o
+NOPED_OBJ_FILES-y += parse_helper.o
 NOPED_OBJ_FILES-y += omapimage.o
 NOPED_OBJ_FILES-y += mkenvimage.o
 NOPED_OBJ_FILES-y += mkimage.o

@@ -208,6 +209,7 @@ $(obj)mkimage$(SFX):	$(obj)aisimage.o \
 			$(obj)fit_image.o \
 			$(obj)image.o \
 			$(obj)imximage.o \
+			$(obj)parse_helper.o \
 			$(obj)kwbimage.o \
 			$(obj)pblimage.o \
 			$(obj)md5.o \

tools/parse_helper.c new file +173 -0

173 lines not on this page · raw message

tools/parse_helper.h new file +28 -0

new file mode 100644
index 0000000..1ff98a3
@@ -0,0 +1,28 @@
+/*
+ * (C) Copyright 20012  Boundary Devices Inc, troy.kisky at boundarydevices.com
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#ifndef _PARSE_HELPER_H_
+#define _PARSE_HELPER_H_
+
+struct parse_helper {
+	char *line;
+	size_t len;
+	FILE *fd;
+	int lineno;
+	char cmd_started;
+	char *filename;
+	char *p;
+};
+
+int ph_open(struct parse_helper *ph, char *filename);
+void ph_close(struct parse_helper *ph);
+int ph_skip_separators(struct parse_helper *ph);
+int ph_skip_comma(struct parse_helper *ph);
+int ph_get_value(struct parse_helper *ph, uint32_t *pval);
+int ph_get_array(struct parse_helper *ph, uint32_t *data, int cnt);
+int ph_get_table_entry_id(struct parse_helper *ph,
+		const table_entry_t *table, const char *table_name);
+#endif

Signature · 1 line

1.7.9.5

Wolfgang Denk

2012-11-28 09:41 UTC #128 lore raw

PATCH v4 9/11 tools: add parse_helper file

Dear Troy Kisky,

Quoted 2 lines · In message <1354066303-29762-10-git-send-email-troy.kisky@boundarydevices.com>…

This file can help you parse
configuration files.

If this is intended to be useful, you need to add documentation, for example what your definition of "configuration files" is, and which data format[s] is/are supported, etc.

As is, this cannot be reused.

Best regards,

Wolfgang Denk

Signature · 5 lines

DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Wenn das dann in die Hose geht, nehme ich es auf meine Kappe.
                                         -- Rudi V?ller, 15. Nov 2003

Liu Hui-R64343

2012-11-28 10:48 UTC #129 lore raw

PATCH v4 9/11 tools: add parse_helper file

In reply to Troy Kisky

Quoted 10 lines

-----Original Message-----
From: Troy Kisky [mailto:troy.kisky at boundarydevices.com]
Sent: Wednesday, November 28, 2012 9:32 AM
To: sbabic at denx.de
Cc: dirk.behme at googlemail.com; u-boot at lists.denx.de; Liu Hui-R64343; festevam at gmail.com; Troy Kisky
Subject: [PATCH V4 09/11] tools: add parse_helper file
This file can help you parse
configuration files.

One line is enough. :)

Quoted 2 lines

Signed-off-by Troy Kisky <[email protected]>

Acked-by Jason Liu <[email protected]>

Quoted 234 lines

---
tools/Makefile | 2 +
tools/parse_helper.c | 173
++++++++++++++++++++++++++++++++++++++++++++++++++
tools/parse_helper.h | 28 ++++++++

3 files changed, 203 insertions(+)

create mode 100644 tools/parse_helper.c create mode 100644 tools/parse_helper.h

tools/Makefile +1 -0

@@ -94,6 +94,7 @@ NOPED_OBJ_FILES-y += aisimage.o  NOPED_OBJ_FILES-y
+= kwbimage.o  NOPED_OBJ_FILES-y += pblimage.o  NOPED_OBJ_FILES-y +=

imximage.o
+NOPED_OBJ_FILES-y += parse_helper.o
NOPED_OBJ_FILES-y += omapimage.o
NOPED_OBJ_FILES-y += mkenvimage.o
NOPED_OBJ_FILES-y += mkimage.o

tools/Makefile +1 -0

@@ -208,6 +209,7 @@ $(obj)mkimage$(SFX):	$(obj)aisimage.o \
 			$(obj)fit_image.o \
 			$(obj)image.o \
 			$(obj)imximage.o \
+			$(obj)parse_helper.o \
 			$(obj)kwbimage.o \
 			$(obj)pblimage.o \
 			$(obj)md5.o \

tools/parse_helper.c new file +44 -0

index 0000000..0a5c5f6
@@ -0,0 +1,173 @@
+/*
+ * (C) Copyright 20012  Boundary Devices Inc,
+troy.kisky at boundarydevices.com
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+/* Required to obtain the getline prototype from stdio.h */ #define
+_GNU_SOURCE
+
+#include "mkimage.h"
+#include <image.h>
+#include "parse_helper.h"
+
+int ph_open(struct parse_helper *ph, char *filename) {
+	ph->line = NULL;
+	ph->len = 0;
+	ph->fd = fopen(filename, "r");
+	ph->lineno = 0;
+	ph->cmd_started = 0;
+	ph->filename = filename;
+	ph->p = NULL;
+	return (!ph->fd) ? -1 : 0;
+}
+
+void ph_close(struct parse_helper *ph)
+{
+	fclose(ph->fd);
+	ph->fd = NULL;
+}
+
+int ph_skip_separators(struct parse_helper *ph) {
+	int line_no = ph->lineno;
+	char *p = ph->p;
+
+	for (;;) {
+		char c;
+		if (!p) {
+			if (getline(&ph->line, &ph->len, ph->fd) <= 0)
+				return -1;
+			ph->lineno++;
+			p = ph->line;
+			if (ph->cmd_started) {
+				fprintf(stderr, "warning: continuing command

on"

tools/parse_helper.c new file +122 -0

+						" next line, line %s[%d](%s)\n",
+						ph->filename, ph->lineno, p);
+			}
+		}
+		c = *p;
+		if ((c == ' ') || (c == '\t')) {
+			p++;
+			continue;
+		}
+		/* Drop all text starting with '#' as comments */
+		if ((c == '#') || (c == '\r') || (c == '\n')
+				|| !c) {
+			p = NULL;
+			continue;
+		}
+		if (c == ';') {
+			if (ph->cmd_started) {
+				fprintf(stderr, "Error: command not "
+						"finished:%s[%d](%s)\n",
+						ph->filename, ph->lineno, p);
+				exit(EXIT_FAILURE);
+			}
+			p++;
+			continue;
+		}
+		if (!ph->cmd_started && line_no == ph->lineno) {
+			fprintf(stderr, "Error: extra data at end "
+					"of line %s[%d](%s)\n",
+					ph->filename, ph->lineno, p);
+			exit(EXIT_FAILURE);
+		}
+		ph->p = p;
+		return 0;
+	}
+}
+
+int ph_skip_comma(struct parse_helper *ph) {
+	char *p = ph->p;
+
+	for (;;) {
+		char c = *p++;
+		if ((c == '#') || (c == '\r') || (c == '\n') || !c)
+			return 0;
+		if (c == ',') {
+			ph->p = p;
+			ph_skip_separators(ph);
+			return 1;
+		}
+		if ((c != ' ') && (c == '\t'))
+			return 0;
+	}
+}
+
+int ph_get_value(struct parse_helper *ph, uint32_t *pval) {
+	char *endptr;
+	uint32_t value;
+
+	if (ph_skip_separators(ph))
+		return -1;
+	errno = 0;
+	value = strtoul(ph->p, &endptr, 16);
+	if (errno || (ph->p == endptr))
+		return -1;
+	*pval = value;
+	ph->p = endptr;
+	return 0;
+}
+
+/*
+ * Comma separator optional
+ * Input:
+ * ph - input source
+ * data - array to fill in
+ * cnt - exact number of elements to parse
+ * Return: number of elements parsed, or error  */ int
+ph_get_array(struct parse_helper *ph, uint32_t *data, int cnt) {
+	int i = 0;
+
+	for (;;) {
+		int ret = ph_get_value(ph, &data[i++]);
+		if (ret)
+			return ret;
+		if (i >= cnt)
+			break;
+		ph_skip_comma(ph);		/* comma is optional */
+	}
+	return i;
+}
+
+static char *grab_token(char *dest, int size, char *src) {
+	while (size) {
+		char c = *src;
+		if ((c == ' ') || (c == '\t') || (c == '\r') || (c == '\n')
+				|| (c == '#') || !c)
+			break;
+		*dest++ = c;
+		size--;
+		src++;
+	}
+	if (!size)
+		return NULL;
+	*dest = 0;
+	return src;
+}
+
+int ph_get_table_entry_id(struct parse_helper *ph,
+		const table_entry_t *table, const char *table_name) {
+	int val;
+	char token[16];
+	char *p;
+
+	if (ph_skip_separators(ph))
+		return -1;
+	p = grab_token(token, sizeof(token), ph->p);
+	if (!p)
+		return -1;
+	val = get_table_entry_id(table, table_name, token);
+	if (val != -1)
+		ph->p = p;
+	return val;
+}
+

tools/parse_helper.h new file mode renamed from tools/parse_helper.h +0 -0

100644 index 0000000..1ff98a3

tools/parse_helper.h new file +27 -1

@@ -0,0 +1,28 @@
+/*
+ * (C) Copyright 20012  Boundary Devices Inc,
+troy.kisky at boundarydevices.com
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#ifndef _PARSE_HELPER_H_
+#define _PARSE_HELPER_H_
+
+struct parse_helper {
+	char *line;
+	size_t len;
+	FILE *fd;
+	int lineno;
+	char cmd_started;
+	char *filename;
+	char *p;
+};
+
+int ph_open(struct parse_helper *ph, char *filename); void
+ph_close(struct parse_helper *ph); int ph_skip_separators(struct
+parse_helper *ph); int ph_skip_comma(struct parse_helper *ph); int
+ph_get_value(struct parse_helper *ph, uint32_t *pval); int
+ph_get_array(struct parse_helper *ph, uint32_t *data, int cnt); int
+ph_get_table_entry_id(struct parse_helper *ph,
+		const table_entry_t *table, const char *table_name); #endif
--

1.7.9.5

Troy Kisky

author

2012-11-28 01:31 UTC #130 lore raw

PATCH v4 10/11 imximage: use parse_helper functions

In reply to Troy Kisky

Use parse_helper functions to pulling tokens instead of pushing them.
Remove need for switch statements to process commands.

Signed-off-by Troy Kisky <[email protected]>

---
v2: uses file parse_helper added in previous patch changed patch subject, was cleanup parsing

---
 tools/imximage.c |  267 +++++++++++++++++++-----------------------------------
 tools/imximage.h |   17 ++--
 2 files changed, 101 insertions(+), 183 deletions(-)

tools/imximage.c +95 ~~-172~~

index 2f5ee14..5147989 100644
@@ -25,9 +25,6 @@
  * MA 02111-1307 USA
  */
 
-/* Required to obtain the getline prototype from stdio.h */
-#define _GNU_SOURCE
-
 #include "mkimage.h"
 #include <image.h>
 #include "imximage.h"

@@ -70,21 +67,6 @@ static uint32_t g_flash_offset;
 
 static struct image_type_params imximage_params;
 
-static uint32_t get_cfg_value(char *token, char *name,  int linenr)
-{
-	char *endptr;
-	uint32_t value;
-
-	errno = 0;
-	value = strtoul(token, &endptr, 16);
-	if (errno || (token == endptr)) {
-		fprintf(stderr, "Error: %s[%d] - Invalid hex data(%s)\n",
-			name,  linenr, token);
-		exit(EXIT_FAILURE);
-	}
-	return value;
-}
-
 static uint32_t detect_imximage_version(struct imx_header *imx_hdr)
 {
 	imx_header_v1_t *hdr_v1 = &imx_hdr->header.hdr_v1;

@@ -112,53 +94,36 @@ static void err_imximage_version(int version)
 	exit(EXIT_FAILURE);
 }
 
-static void set_dcd_val_v1(struct data_src *ds, char *name, int lineno,
-					int fld, uint32_t value)
+static int set_dcd_val_v1(struct data_src *ds, uint32_t *data)
 {
 	dcd_v1_t *dcd_v1 = &ds->imxhdr->header.hdr_v1.dcd_table;
+	uint32_t val = *data++;
 
-	switch (fld) {
-	case CFG_REG_SIZE:
-		/* Byte, halfword, word */
-		if ((value != 1) && (value != 2) && (value != 4)) {
-			fprintf(stderr, "Error: %s[%d] - "
-				"Invalid register size " "(%d)\n",
-				name, lineno, value);
-			exit(EXIT_FAILURE);
-		}
-		*ds->p_entry++ = value;
-		break;
-	case CFG_REG_ADDRESS:
-		*ds->p_entry++ = value;
-		break;
-	case CFG_REG_VALUE:
-		*ds->p_entry++ = value;
-		dcd_v1->preamble.length = (char *)ds->p_entry
-				- (char *)&dcd_v1->addr_data[0].type;
-		break;
-	default:
-		break;
-
+	/* Byte, halfword, word */
+	if ((val != 1) && (val != 2) && (val != 4)) {
+		fprintf(stderr, "Error: Invalid register size (%d)\n", val);
+		return -1;
 	}
+	*ds->p_entry++ = val;
+	*ds->p_entry++ = *data++;
+	*ds->p_entry++ = *data++;
+	dcd_v1->preamble.length = (char *)ds->p_entry - (char *)&dcd_v1->
+			addr_data[0].type;
+	return 0;
 }
 
-static void set_dcd_val_v2(struct data_src *ds, char *name, int lineno,
-					int fld, uint32_t value)
+static int set_dcd_val_v2(struct data_src *ds, uint32_t *data)
 {
 	uint32_t len;
 	dcd_v2_t *dcd_v2 = &ds->imxhdr->header.hdr_v2.dcd_table;
+	uint32_t val = *data++;
 
-	switch (fld) {
-	case CFG_REG_SIZE:
-		/* Byte, halfword, word */
-		if ((value != 1) && (value != 2) && (value != 4)) {
-			fprintf(stderr, "Error: %s[%d] - "
-				"Invalid register size " "(%d)\n",
-				name, lineno, value);
-			exit(EXIT_FAILURE);
-		}
-		if (ds->p_dcd && (ds->p_dcd->param == value))
-			break;
+	/* Byte, halfword, word */
+	if ((val != 1) && (val != 2) && (val != 4)) {
+		fprintf(stderr, "Error: Invalid register size (%d)\n", val);
+		return -1;
+	}
+	if (!(ds->p_dcd && (ds->p_dcd->param == val))) {
 		if (!ds->p_dcd) {
 			dcd_v2->header.tag = DCD_HEADER_TAG;
 			dcd_v2->header.version = DCD_VERSION;

@@ -166,24 +131,19 @@ static void set_dcd_val_v2(struct data_src *ds, char *name, int lineno,
 		} else {
 			ds->p_dcd = (write_dcd_command_t *)ds->p_entry;
 		}
-		ds->p_dcd->param = value;
+		ds->p_dcd->param = val;
 		ds->p_dcd->tag = DCD_COMMAND_TAG;
 		ds->p_entry = (uint32_t *)(ds->p_dcd + 1);
-		break;
-	case CFG_REG_ADDRESS:
-		*ds->p_entry++ = cpu_to_be32(value);
-		break;
-	case CFG_REG_VALUE:
-		*ds->p_entry++ = cpu_to_be32(value);
-		len = (char *)ds->p_entry - (char *)&dcd_v2->header;
-		dcd_v2->header.length = cpu_to_be16(len);
-		len = (char *)ds->p_entry - (char *)ds->p_dcd;
-		ds->p_dcd->length = cpu_to_be16(len);
-		break;
-	default:
-		break;
-
 	}
+	val = *data++;
+	*ds->p_entry++ = cpu_to_be32(val);
+	val = *data++;
+	*ds->p_entry++ = cpu_to_be32(val);
+	len = (char *)ds->p_entry - (char *)&dcd_v2->header;
+	dcd_v2->header.length = cpu_to_be16(len);
+	len = (char *)ds->p_entry - (char *)ds->p_dcd;
+	ds->p_dcd->length = cpu_to_be16(len);
+	return 0;
 }
 
 static int set_imx_hdr_v1(struct data_src *ds,

@@ -323,95 +283,71 @@ static void print_hdr_v2(struct imx_header *imx_hdr)
 	printf("Entry Point:  %08x\n", (uint32_t)fhdr_v2->entry);
 }
 
-static void parse_cfg_cmd(struct data_src *ds, int32_t cmd, char *token,
-				char *name, int lineno, int fld)
+static int parse_cmd_data(struct data_src *ds)
+{
+	uint32_t data[3];
+	int ret = ph_get_array(&ds->ph, data, 3);
+
+	if (ret < 0)
+		return ret;
+	ret = (*ds->set_dcd_val)(ds, data);
+	if (ret)
+		return ret;
+	if (ds->p_entry > ds->p_max_dcd) {
+		uint32_t size = (char *)ds->p_max_dcd - (char *)ds->imxhdr;
+		fprintf(stderr, "Error: header exceeds maximum size(%d)\n",
+				size);
+		return -1;
+	}
+	return 0;
+}
+
+static int parse_image_version(struct data_src *ds)
 {
-	int value;
-	static int cmd_ver_first = ~0;
+	int ret;
 	uint32_t imximage_version;
 
-	switch (cmd) {
-	case CMD_IMAGE_VERSION:
-		imximage_version = get_cfg_value(token, name, lineno);
-		if (cmd_ver_first == 0) {
-			fprintf(stderr, "Error: %s[%d] - IMAGE_VERSION "
-				"command need be the first before other "
-				"valid command in the file\n", name, lineno);
-			exit(EXIT_FAILURE);
-		}
-		cmd_ver_first = 1;
-		set_hdr_func(ds, imximage_version);
-		break;
-	case CMD_BOOT_FROM:
-		g_flash_offset = get_table_entry_id(imximage_bootops,
-					"imximage boot option", token);
-		if (g_flash_offset == -1) {
-			fprintf(stderr, "Error: %s[%d] -Invalid boot device"
-				"(%s)\n", name, lineno, token);
-			exit(EXIT_FAILURE);
-		}
-		if (unlikely(cmd_ver_first != 1))
-			cmd_ver_first = 0;
-		break;
-	case CMD_DATA:
-		value = get_cfg_value(token, name, lineno);
-		(*ds->set_dcd_val)(ds, name, lineno, fld, value);
-		if (unlikely(cmd_ver_first != 1))
-			cmd_ver_first = 0;
-		break;
+	ret = ph_get_value(&ds->ph, &imximage_version);
+	if (ret)
+		return ret;
+	if (ds->cmd_cnt) {
+		fprintf(stderr, "Error: IMAGE_VERSION command needs be "
+				"before other valid commands in the file\n");
+		return -1;
 	}
+	set_hdr_func(ds, imximage_version);
+	return 0;
 }
 
-static void parse_cfg_fld(struct data_src *ds, int32_t *cmd,
-		char *token, char *name, int lineno, int fld)
+static int parse_boot_from(struct data_src *ds)
 {
-	int value;
-
-	switch (fld) {
-	case CFG_COMMAND:
-		*cmd = get_table_entry_id(imximage_cmds,
-			"imximage commands", token);
-		if (*cmd < 0) {
-			fprintf(stderr, "Error: %s[%d] - Invalid command"
-			"(%s)\n", name, lineno, token);
-			exit(EXIT_FAILURE);
-		}
-		break;
-	case CFG_REG_SIZE:
-		parse_cfg_cmd(ds, *cmd, token, name, lineno, fld);
-		break;
-	case CFG_REG_ADDRESS:
-	case CFG_REG_VALUE:
-		if (*cmd != CMD_DATA)
-			return;
-
-		value = get_cfg_value(token, name, lineno);
-		(*ds->set_dcd_val)(ds, name, lineno, fld, value);
-		if (ds->p_entry > ds->p_max_dcd) {
-			uint32_t size = (char *)ds->p_max_dcd -
-					(char *)ds->imxhdr;
-			fprintf(stderr, "Error: %s[%d] -"
-					"header exceeds maximum size(%d)\n",
-					name, lineno, size);
-			exit(EXIT_FAILURE);
-		}
-		break;
-	default:
-		break;
+	g_flash_offset = ph_get_table_entry_id(&ds->ph, imximage_bootops,
+			"imximage boot option");
+	if (g_flash_offset == -1) {
+		fprintf(stderr, "Error: Invalid boot device\n");
+		return -1;
 	}
+	return 0;
+}
+
+static const parse_fld_t cmd_table[] = {
+	parse_image_version, parse_boot_from, parse_cmd_data
+};
+
+static int parse_command(struct data_src *ds)
+{
+	int cmd = ph_get_table_entry_id(&ds->ph, imximage_cmds,
+			"imximage commands");
+	if (cmd < 0)
+		return cmd;
+	return cmd_table[cmd](ds);
 }
 
 static int parse_cfg_file(struct imx_header *imxhdr, char *name,
 		uint32_t entry_point)
 {
 	struct data_src ds;
-	FILE *fd = NULL;
-	char *line = NULL;
-	char *token, *saveptr1, *saveptr2;
-	int lineno = 0;
-	int fld;
-	size_t len;
-	int32_t cmd;
+	struct parse_helper *ph = &ds.ph;
 
 	/* Be able to detect if the cfg file has no BOOT_FROM tag */
 	g_flash_offset = FLASH_OFFSET_UNDEFINED;

@@ -423,8 +359,7 @@ static int parse_cfg_file(struct imx_header *imxhdr, char *name,
 	 * set up function ptr group to V1 by default.
 	 */
 	set_hdr_func(&ds, IMXIMAGE_V1);
-	fd = fopen(name, "r");
-	if (fd == 0) {
+	if (ph_open(ph, name)) {
 		fprintf(stderr, "Error: %s - Can't open DCD file\n", name);
 		exit(EXIT_FAILURE);
 	}

@@ -432,31 +367,19 @@ static int parse_cfg_file(struct imx_header *imxhdr, char *name,
 	/* Very simple parsing, line starting with # are comments
 	 * and are dropped
 	 */
-	while ((getline(&line, &len, fd)) > 0) {
-		lineno++;
-
-		token = strtok_r(line, "\r\n", &saveptr1);
-		if (token == NULL)
-			continue;
-
-		/* Check inside the single line */
-		for (fld = CFG_COMMAND, cmd = CMD_INVALID,
-				line = token; ; line = NULL, fld++) {
-			token = strtok_r(line, " \t", &saveptr2);
-			if (token == NULL)
-				break;
-
-			/* Drop all text starting with '#' as comments */
-			if (token[0] == '#')
-				break;
-
-			parse_cfg_fld(&ds, &cmd, token, name,
-					lineno, fld);
+	for (;;) {
+		ph->cmd_started = 0;
+		if (ph_skip_separators(ph))
+			break;
+		ph->cmd_started = 1;
+		if (parse_command(&ds)) {
+			fprintf(stderr, "Error: invalid token %s[%d](%s)\n",
+					name, ph->lineno, ph->p);
+			exit(EXIT_FAILURE);
 		}
-
+		ds.cmd_cnt++;
 	}
-	fclose(fd);
-
+	ph_close(ph);
 	/* Exit if there is no BOOT_FROM field specifying the flash_offset */
 	if (g_flash_offset == FLASH_OFFSET_UNDEFINED) {
 		fprintf(stderr, "Error: No BOOT_FROM tag in %s\n", name);

@@ -546,12 +469,12 @@ static void imximage_set_header(void *ptr, struct stat *sbuf, int ifd,
 int imximage_check_params(struct mkimage_params *params)
 {
 	if (!params)
-		return CFG_INVALID;
+		return -1;
 	if (!strlen(params->imagename)) {
 		fprintf(stderr, "Error: %s - Configuration file not specified, "
 			"it is needed for imximage generation\n",
 			params->cmdname);
-		return CFG_INVALID;
+		return -1;
 	}
 	/*
 	 * Check parameters:

tools/imximage.h +6 ~~-11~~

index 196bb51..6bcd082 100644
@@ -23,6 +23,7 @@
 
 #ifndef _IMXIMAGE_H_
 #define _IMXIMAGE_H_
+#include "parse_helper.h"
 
 #define MAX_HW_CFG_SIZE_V2 121 /* Max number of registers imx can set for v2 */
 #define MAX_HW_CFG_SIZE_V1 60  /* Max number of registers imx can set for v1 */

@@ -49,20 +50,11 @@
 #define DCD_VERSION 0x40
 
 enum imximage_cmd {
-	CMD_INVALID,
 	CMD_IMAGE_VERSION,
 	CMD_BOOT_FROM,
 	CMD_DATA
 };
 
-enum imximage_fld_types {
-	CFG_INVALID = -1,
-	CFG_COMMAND,
-	CFG_REG_SIZE,
-	CFG_REG_ADDRESS,
-	CFG_REG_VALUE
-};
-
 enum imximage_version {
 	IMXIMAGE_VER_INVALID = -1,
 	IMXIMAGE_V1 = 1,

@@ -159,14 +151,17 @@ struct imx_header {
 };
 
 struct data_src;
-typedef void (*set_dcd_val_t)(struct data_src *ds, char *name,
-		int lineno, int fld, uint32_t value);
+typedef int (*parse_fld_t)(struct data_src *ds);
+
+typedef int (*set_dcd_val_t)(struct data_src *ds, uint32_t *data);
 
 typedef int (*set_imx_hdr_t)(struct data_src *ds, uint32_t entry_point,
 		uint32_t flash_offset);
 
 struct data_src {
+	struct parse_helper ph;
 	struct imx_header *imxhdr;
+	int cmd_cnt;
 	set_imx_hdr_t set_imx_hdr;
 	set_dcd_val_t set_dcd_val;
 	uint32_t *p_max_dcd;

Signature · 1 line

1.7.9.5

Liu Hui-R64343

2012-11-28 10:48 UTC #131 lore raw

PATCH v4 10/11 imximage: use parse_helper functions

Quoted 8 lines

-----Original Message-----
From: Troy Kisky [mailto:troy.kisky at boundarydevices.com]
Sent: Wednesday, November 28, 2012 9:32 AM
To: sbabic at denx.de
Cc: dirk.behme at googlemail.com; u-boot at lists.denx.de; Liu Hui-R64343; festevam at gmail.com; Troy Kisky
Subject: [PATCH V4 10/11] imximage: use parse_helper functions

Quoted 4 lines

Use parse_helper functions to pulling tokens instead of pushing them. Remove need for switch statements to process commands.
Signed-off-by Troy Kisky <[email protected]>

Acked-by Jason Liu <[email protected]>

Quoted 419 lines

---
v2: uses file parse_helper added in previous patch changed patch subject, was cleanup parsing
---
tools/imximage.c | 267 +++++++++++++++++++-----------------------------------
tools/imximage.h | 17 ++--

2 files changed, 101 insertions(+), 183 deletions(-)

tools/imximage.c index 2f5ee14..5147989 renamed from tools/imximage.c +0 -0

100644

tools/imximage.c +0 -1

@@ -25,9 +25,6 @@
 * MA 02111-1307 USA
 */
 
-/* Required to obtain the getline prototype from stdio.h */ -#define

_GNU_SOURCE
-
#include "mkimage.h"
#include <image.h>
#include "imximage.h"

tools/imximage.c +1 ~~-14~~

@@ -70,21 +67,6 @@ static uint32_t g_flash_offset;
 
 static struct image_type_params imximage_params;
 
-static uint32_t get_cfg_value(char *token, char *name,  int linenr) -{
-	char *endptr;
-	uint32_t value;
-
-	errno = 0;
-	value = strtoul(token, &endptr, 16);
-	if (errno || (token == endptr)) {
-		fprintf(stderr, "Error: %s[%d] - Invalid hex data(%s)\n",
-			name,  linenr, token);
-		exit(EXIT_FAILURE);
-	}
-	return value;
-}
-
 static uint32_t detect_imximage_version(struct imx_header *imx_hdr)  {
 	imx_header_v1_t *hdr_v1 = &imx_hdr->header.hdr_v1; @@ -112,53
+94,36 @@ static void err_imximage_version(int version)

	exit(EXIT_FAILURE);
}

tools/imximage.c +1 -2

-static void set_dcd_val_v1(struct data_src *ds, char *name, int lineno,
-					int fld, uint32_t value)
+static int set_dcd_val_v1(struct data_src *ds, uint32_t *data)

{
	dcd_v1_t *dcd_v1 = &ds->imxhdr->header.hdr_v1.dcd_table;

tools/imximage.c +5 ~~-22~~

+	uint32_t val = *data++;
 
-	switch (fld) {
-	case CFG_REG_SIZE:
-		/* Byte, halfword, word */
-		if ((value != 1) && (value != 2) && (value != 4)) {
-			fprintf(stderr, "Error: %s[%d] - "
-				"Invalid register size " "(%d)\n",
-				name, lineno, value);
-			exit(EXIT_FAILURE);
-		}
-		*ds->p_entry++ = value;
-		break;
-	case CFG_REG_ADDRESS:
-		*ds->p_entry++ = value;
-		break;
-	case CFG_REG_VALUE:
-		*ds->p_entry++ = value;
-		dcd_v1->preamble.length = (char *)ds->p_entry
-				- (char *)&dcd_v1->addr_data[0].type;
-		break;
-	default:
-		break;
-
+	/* Byte, halfword, word */
+	if ((val != 1) && (val != 2) && (val != 4)) {
+		fprintf(stderr, "Error: Invalid register size (%d)\n", val);
+		return -1;

tools/imximage.c +6 -0

+	*ds->p_entry++ = val;
+	*ds->p_entry++ = *data++;
+	*ds->p_entry++ = *data++;
+	dcd_v1->preamble.length = (char *)ds->p_entry - (char *)&dcd_v1->
+			addr_data[0].type;
+	return 0;

}

tools/imximage.c +1 -2

-static void set_dcd_val_v2(struct data_src *ds, char *name, int lineno,
-					int fld, uint32_t value)
+static int set_dcd_val_v2(struct data_src *ds, uint32_t *data)

{
	uint32_t len;
	dcd_v2_t *dcd_v2 = &ds->imxhdr->header.hdr_v2.dcd_table;

tools/imximage.c +7 ~~-11~~

+	uint32_t val = *data++;
 
-	switch (fld) {
-	case CFG_REG_SIZE:
-		/* Byte, halfword, word */
-		if ((value != 1) && (value != 2) && (value != 4)) {
-			fprintf(stderr, "Error: %s[%d] - "
-				"Invalid register size " "(%d)\n",
-				name, lineno, value);
-			exit(EXIT_FAILURE);
-		}
-		if (ds->p_dcd && (ds->p_dcd->param == value))
-			break;
+	/* Byte, halfword, word */
+	if ((val != 1) && (val != 2) && (val != 4)) {
+		fprintf(stderr, "Error: Invalid register size (%d)\n", val);
+		return -1;
+	}
+	if (!(ds->p_dcd && (ds->p_dcd->param == val))) {

		if (!ds->p_dcd) {
			dcd_v2->header.tag = DCD_HEADER_TAG;
			dcd_v2->header.version = DCD_VERSION; @@ -166,24
+131,19 @@ static void set_dcd_val_v2(struct data_src *ds, char *name, int
lineno,
		} else {
			ds->p_dcd = (write_dcd_command_t *)ds->p_entry;
		}

tools/imximage.c +1 -1

-		ds->p_dcd->param = value;
+		ds->p_dcd->param = val;

		ds->p_dcd->tag = DCD_COMMAND_TAG;
		ds->p_entry = (uint32_t *)(ds->p_dcd + 1);

tools/imximage.c +0 ~~-14~~

-		break;
-	case CFG_REG_ADDRESS:
-		*ds->p_entry++ = cpu_to_be32(value);
-		break;
-	case CFG_REG_VALUE:
-		*ds->p_entry++ = cpu_to_be32(value);
-		len = (char *)ds->p_entry - (char *)&dcd_v2->header;
-		dcd_v2->header.length = cpu_to_be16(len);
-		len = (char *)ds->p_entry - (char *)ds->p_dcd;
-		ds->p_dcd->length = cpu_to_be16(len);
-		break;
-	default:
-		break;
-

tools/imximage.c +9 -0

+	val = *data++;
+	*ds->p_entry++ = cpu_to_be32(val);
+	val = *data++;
+	*ds->p_entry++ = cpu_to_be32(val);
+	len = (char *)ds->p_entry - (char *)&dcd_v2->header;
+	dcd_v2->header.length = cpu_to_be16(len);
+	len = (char *)ds->p_entry - (char *)ds->p_dcd;
+	ds->p_dcd->length = cpu_to_be16(len);
+	return 0;

}

static int set_imx_hdr_v1(struct data_src *ds, @@ -323,95 +283,71 @@ static void print_hdr_v2(struct imx_header *imx_hdr)

	printf("Entry Point:  %08x\n", (uint32_t)fhdr_v2->entry);  }

tools/imximage.c +19 -2

-static void parse_cfg_cmd(struct data_src *ds, int32_t cmd, char *token,
-				char *name, int lineno, int fld)
+static int parse_cmd_data(struct data_src *ds) {
+	uint32_t data[3];
+	int ret = ph_get_array(&ds->ph, data, 3);
+
+	if (ret < 0)
+		return ret;
+	ret = (*ds->set_dcd_val)(ds, data);
+	if (ret)
+		return ret;
+	if (ds->p_entry > ds->p_max_dcd) {
+		uint32_t size = (char *)ds->p_max_dcd - (char *)ds->imxhdr;
+		fprintf(stderr, "Error: header exceeds maximum size(%d)\n",
+				size);
+		return -1;
+	}
+	return 0;
+}
+
+static int parse_image_version(struct data_src *ds)

{

tools/imximage.c +1 -2

-	int value;
-	static int cmd_ver_first = ~0;
+	int ret;

	uint32_t imximage_version;

tools/imximage.c +7 ~~-29~~

-	switch (cmd) {
-	case CMD_IMAGE_VERSION:
-		imximage_version = get_cfg_value(token, name, lineno);
-		if (cmd_ver_first == 0) {
-			fprintf(stderr, "Error: %s[%d] - IMAGE_VERSION "
-				"command need be the first before other "
-				"valid command in the file\n", name, lineno);
-			exit(EXIT_FAILURE);
-		}
-		cmd_ver_first = 1;
-		set_hdr_func(ds, imximage_version);
-		break;
-	case CMD_BOOT_FROM:
-		g_flash_offset = get_table_entry_id(imximage_bootops,
-					"imximage boot option", token);
-		if (g_flash_offset == -1) {
-			fprintf(stderr, "Error: %s[%d] -Invalid boot device"
-				"(%s)\n", name, lineno, token);
-			exit(EXIT_FAILURE);
-		}
-		if (unlikely(cmd_ver_first != 1))
-			cmd_ver_first = 0;
-		break;
-	case CMD_DATA:
-		value = get_cfg_value(token, name, lineno);
-		(*ds->set_dcd_val)(ds, name, lineno, fld, value);
-		if (unlikely(cmd_ver_first != 1))
-			cmd_ver_first = 0;
-		break;
+	ret = ph_get_value(&ds->ph, &imximage_version);
+	if (ret)
+		return ret;
+	if (ds->cmd_cnt) {
+		fprintf(stderr, "Error: IMAGE_VERSION command needs be "
+				"before other valid commands in the file\n");
+		return -1;

tools/imximage.c +2 -0

+	set_hdr_func(ds, imximage_version);
+	return 0;

}

tools/imximage.c +1 -2

-static void parse_cfg_fld(struct data_src *ds, int32_t *cmd,
-		char *token, char *name, int lineno, int fld)
+static int parse_boot_from(struct data_src *ds)

{

tools/imximage.c +5 ~~-33~~

-	int value;
-
-	switch (fld) {
-	case CFG_COMMAND:
-		*cmd = get_table_entry_id(imximage_cmds,
-			"imximage commands", token);
-		if (*cmd < 0) {
-			fprintf(stderr, "Error: %s[%d] - Invalid command"
-			"(%s)\n", name, lineno, token);
-			exit(EXIT_FAILURE);
-		}
-		break;
-	case CFG_REG_SIZE:
-		parse_cfg_cmd(ds, *cmd, token, name, lineno, fld);
-		break;
-	case CFG_REG_ADDRESS:
-	case CFG_REG_VALUE:
-		if (*cmd != CMD_DATA)
-			return;
-
-		value = get_cfg_value(token, name, lineno);
-		(*ds->set_dcd_val)(ds, name, lineno, fld, value);
-		if (ds->p_entry > ds->p_max_dcd) {
-			uint32_t size = (char *)ds->p_max_dcd -
-					(char *)ds->imxhdr;
-			fprintf(stderr, "Error: %s[%d] -"
-					"header exceeds maximum size(%d)\n",
-					name, lineno, size);
-			exit(EXIT_FAILURE);
-		}
-		break;
-	default:
-		break;
+	g_flash_offset = ph_get_table_entry_id(&ds->ph, imximage_bootops,
+			"imximage boot option");
+	if (g_flash_offset == -1) {
+		fprintf(stderr, "Error: Invalid boot device\n");
+		return -1;

tools/imximage.c +12 -0

+	return 0;
+}
+
+static const parse_fld_t cmd_table[] = {
+	parse_image_version, parse_boot_from, parse_cmd_data };
+
+static int parse_command(struct data_src *ds) {
+	int cmd = ph_get_table_entry_id(&ds->ph, imximage_cmds,
+			"imximage commands");
+	if (cmd < 0)
+		return cmd;
+	return cmd_table[cmd](ds);

}

static int parse_cfg_file(struct imx_header *imxhdr, char *name,
uint32_t entry_point)

{
	struct data_src ds;

tools/imximage.c +1 -7

-	FILE *fd = NULL;
-	char *line = NULL;
-	char *token, *saveptr1, *saveptr2;
-	int lineno = 0;
-	int fld;
-	size_t len;
-	int32_t cmd;
+	struct parse_helper *ph = &ds.ph;

	/* Be able to detect if the cfg file has no BOOT_FROM tag */
	g_flash_offset = FLASH_OFFSET_UNDEFINED; @@ -423,8 +359,7 @@
static int parse_cfg_file(struct imx_header *imxhdr, char *name,
	 * set up function ptr group to V1 by default.
	 */
	set_hdr_func(&ds, IMXIMAGE_V1);

tools/imximage.c +1 -2

-	fd = fopen(name, "r");
-	if (fd == 0) {
+	if (ph_open(ph, name)) {

		fprintf(stderr, "Error: %s - Can't open DCD file\n", name);
		exit(EXIT_FAILURE);
	}

tools/imximage.c +11 ~~-23~~

@@ -432,31 +367,19 @@ static int parse_cfg_file(struct imx_header *imxhdr,
 char *name,
 	/* Very simple parsing, line starting with # are comments
 	 * and are dropped
 	 */
-	while ((getline(&line, &len, fd)) > 0) {
-		lineno++;
-
-		token = strtok_r(line, "\r\n", &saveptr1);
-		if (token == NULL)
-			continue;
-
-		/* Check inside the single line */
-		for (fld = CFG_COMMAND, cmd = CMD_INVALID,
-				line = token; ; line = NULL, fld++) {
-			token = strtok_r(line, " \t", &saveptr2);
-			if (token == NULL)
-				break;
-
-			/* Drop all text starting with '#' as comments */
-			if (token[0] == '#')
-				break;
-
-			parse_cfg_fld(&ds, &cmd, token, name,
-					lineno, fld);
+	for (;;) {
+		ph->cmd_started = 0;
+		if (ph_skip_separators(ph))
+			break;
+		ph->cmd_started = 1;
+		if (parse_command(&ds)) {
+			fprintf(stderr, "Error: invalid token %s[%d](%s)\n",
+					name, ph->lineno, ph->p);
+			exit(EXIT_FAILURE);
 		}
-
+		ds.cmd_cnt++;
 	}
-	fclose(fd);
-
+	ph_close(ph);
 	/* Exit if there is no BOOT_FROM field specifying the flash_offset */
 	if (g_flash_offset == FLASH_OFFSET_UNDEFINED) {

fprintf(stderr, "Error: No BOOT_FROM tag in %s\n", name); @@
-546,12 +469,12 @@ static void imximage_set_header(void *ptr, struct stat *sbuf, int ifd, int imximage_check_params(struct mkimage_params *params) {
if (!params)

tools/imximage.c +1 -1

-		return CFG_INVALID;
+		return -1;

	if (!strlen(params->imagename)) {
		fprintf(stderr, "Error: %s - Configuration file not specified, "
			"it is needed for imximage generation\n",
			params->cmdname);

tools/imximage.c +1 -1

-		return CFG_INVALID;
+		return -1;

	}
	/*
	 * Check parameters:

tools/imximage.h index 196bb51..6bcd082 renamed from tools/imximage.h +0 -0

100644

tools/imximage.h +1 -0

@@ -23,6 +23,7 @@
 
 #ifndef _IMXIMAGE_H_
 #define _IMXIMAGE_H_
+#include "parse_helper.h"
 
 #define MAX_HW_CFG_SIZE_V2 121 /* Max number of registers imx can set

for v2 */ #define MAX_HW_CFG_SIZE_V1 60 /* Max number of registers imx can set for v1 */ @@ -49,20 +50,11 @@ #define DCD_VERSION 0x40

enum imximage_cmd {

tools/imximage.h +0 -1

-	CMD_INVALID,

CMD_IMAGE_VERSION,
CMD_BOOT_FROM,
CMD_DATA
};

tools/imximage.h +0 -8

-enum imximage_fld_types {
-	CFG_INVALID = -1,
-	CFG_COMMAND,
-	CFG_REG_SIZE,
-	CFG_REG_ADDRESS,
-	CFG_REG_VALUE
-};
-

enum imximage_version {
	IMXIMAGE_VER_INVALID = -1,
	IMXIMAGE_V1 = 1,

tools/imximage.h +5 -3

@@ -159,14 +151,17 @@ struct imx_header {  };
 
 struct data_src;
-typedef void (*set_dcd_val_t)(struct data_src *ds, char *name,
-		int lineno, int fld, uint32_t value);
+typedef int (*parse_fld_t)(struct data_src *ds);
+
+typedef int (*set_dcd_val_t)(struct data_src *ds, uint32_t *data);
 
 typedef int (*set_imx_hdr_t)(struct data_src *ds, uint32_t entry_point,
 		uint32_t flash_offset);
 
 struct data_src {
+	struct parse_helper ph;
 	struct imx_header *imxhdr;
+	int cmd_cnt;
 	set_imx_hdr_t set_imx_hdr;
 	set_dcd_val_t set_dcd_val;
 	uint32_t *p_max_dcd;
--

1.7.9.5

Troy Kisky

author

2012-11-28 01:31 UTC #132 lore raw

PATCH v4 11/11 parse_helper: add expression evaluation

In reply to Troy Kisky

Basic expressions with order precedence is
now supported.
ie. (----3 + ((1+2*3)/--2 + --5 *(8/4))) is 16.

Signed-off-by Troy Kisky <[email protected]>

---
 tools/parse_helper.c |  172 +++++++++++++++++++++++++++++++++++++++++++++++---
 1 file changed, 162 insertions(+), 10 deletions(-)

tools/parse_helper.c +162 ~~-10~~

index 0a5c5f6..50be832 100644
@@ -97,20 +97,172 @@ int ph_skip_comma(struct parse_helper *ph)
 	}
 }
 
+static const char precedence[] = {
+	/* (  +  -  *  /  &  ^  |  ) */
+	   0, 2, 2, 1, 1, 3, 4, 5, 6
+};
+static const char unary_operations[]  = "(+-";
+static const char binary_operations[] = " +-*/&^|)";
+
+static uint32_t do_func(uint32_t val1, uint32_t val2, int op)
+{
+	switch (op) {
+	case 1:
+		return val1 + val2;
+	case 2:
+		return val1 - val2;
+	case 3:
+		return val1 * val2;
+	case 4:
+		return val1 / val2;
+	case 5:
+		return val1 & val2;
+	case 6:
+		return val1 ^ val2;
+	case 7:
+		return val1 | val2;
+	}
+	fprintf(stderr, "Error: in func %s: val1=%d val2=%d op = %d\n",
+			__func__, val1, val2, op);
+	exit(EXIT_FAILURE);
+}
+
+static int find_op(char c, const char *p)
+{
+	int i;
+	for (i = 0; ; i++) {
+		if (c == p[i])
+			return i;
+		if (!p[i])
+			break;
+	}
+	return -1;
+}
+
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
 int ph_get_value(struct parse_helper *ph, uint32_t *pval)
 {
 	char *endptr;
-	uint32_t value;
+	int op_i = 0;
+	int val_i = 0;
+	unsigned char op[16];
+	uint32_t val[16];
+	int unary = 1;
+	char *p;
 
-	if (ph_skip_separators(ph))
-		return -1;
-	errno = 0;
-	value = strtoul(ph->p, &endptr, 16);
-	if (errno || (ph->p == endptr))
-		return -1;
-	*pval = value;
-	ph->p = endptr;
-	return 0;
+	p = ph->p;
+	for (;;) {
+		char c;
+		int i, j;
+		const char *ops = unary ? unary_operations : binary_operations;
+
+		if (unary) {
+			ph->p = p;
+			if (ph_skip_separators(ph))
+				return -1;
+			p = ph->p;
+			c = *p;
+		} else {
+			for (;;) {
+				c = *p;
+				if ((c != ' ') && (c != '\t'))
+					break;
+				p++;
+			}
+		}
+		i = find_op(c, ops);
+		debug("%d,%c,%d:%s\n", i, c, unary, p);
+		if ((i < 0) && unary) {
+			if (val_i >= ARRAY_SIZE(val))
+				return -1;
+			errno = 0;
+			val[val_i++] = strtoul(p, &endptr, 16);
+			if (errno || (p == endptr)) {
+				ph->p = p;
+				return -1;
+			}
+			p = endptr;
+			unary = 0;
+			debug("val[%d]=%x,%d,%d\n", val_i - 1, val[val_i - 1],
+					op_i, val_i);
+do_unary:
+			while (op_i) {
+				j = op[op_i - 1];
+				if (!(j & 0x80))
+					break;
+				op_i--;
+				val[val_i - 1] = do_func(0,
+						val[val_i - 1], j & 0x7f);
+				debug("un:%d,%x,%d,%d\n", val[val_i - 1], j,
+						op_i, val_i);
+			}
+			continue;
+		}
+		if (i < 0) {
+			c = 0;
+			i = 8;
+		} else {
+			p++;
+		}
+		if (c == '(') {
+			if (op_i >= ARRAY_SIZE(op))
+				return -1;
+			op[op_i++] = i;
+			debug("op[%d]=%x,%d,%d\n", op_i - 1, op[op_i - 1],
+					op_i, val_i);
+			unary = 1;
+			continue;
+		}
+		for (;;) {
+			if (!op_i || unary)
+				break;
+			j = op[op_i - 1];
+			if (j == 0) {
+				if (c == ')') {
+					op_i--;
+					goto do_unary;
+				}
+				break;
+			}
+			if ((j & 0x80)) {
+				op_i--;
+				val[val_i - 1] = do_func(0,
+						val[val_i - 1], j & 0x7f);
+				debug("unary:%d,%x\n", val[val_i - 1], j);
+				continue;
+			}
+			if (precedence[i] < precedence[j])
+				break;
+			if (val_i < 2)
+				return -1;
+			op_i--;
+			val[val_i - 2] = do_func(val[val_i - 2],
+					val[val_i - 1], j);
+			val_i--;
+			debug("binary:%d,%x,%d,%d\n", val[val_i - 1], j,
+					op_i, val_i);
+		}
+		if (c == ')') {
+			fprintf(stderr, "Error: unmatched parenthesis\n");
+			return -1;
+		}
+		if (i == 8) {
+			if ((op_i != 0) || (val_i != 1)) {
+				fprintf(stderr, "Error: syntax %d %d\n",
+						op_i, val_i);
+				return -1;
+			}
+			ph->p = p;
+			*pval = val[0];
+			return 0;
+		}
+		if (op_i >= ARRAY_SIZE(op))
+			return -1;
+		op[op_i++] = i | (unary << 7);
+		debug("op[%d]=%x,%d,%d\n", op_i - 1, op[op_i - 1], op_i, val_i);
+		unary = 1;
+	}
 }
 
 /*

Signature · 1 line

1.7.9.5

Liu Hui-R64343

2012-11-28 10:49 UTC #133 lore raw

PATCH v4 11/11 parse_helper: add expression evaluation

Quoted 8 lines

-----Original Message-----
From: Troy Kisky [mailto:troy.kisky at boundarydevices.com]
Sent: Wednesday, November 28, 2012 9:32 AM
To: sbabic at denx.de
Cc: dirk.behme at googlemail.com; u-boot at lists.denx.de; Liu Hui-R64343; festevam at gmail.com; Troy Kisky
Subject: [PATCH V4 11/11] parse_helper: add expression evaluation

Quoted 4 lines

Basic expressions with order precedence is now supported. ie. (----3 + ((1+2*3)/--2 + --5 *(8/4))) is 16.
Signed-off-by Troy Kisky <[email protected]>

Acked-by Jason Liu <[email protected]>

Quoted 193 lines

---
tools/parse_helper.c | 172
+++++++++++++++++++++++++++++++++++++++++++++++---

1 file changed, 162 insertions(+), 10 deletions(-)

tools/parse_helper.c index renamed from tools/parse_helper.c +0 -0

0a5c5f6..50be832 100644

tools/parse_helper.c +160 ~~-11~~

@@ -97,20 +97,172 @@ int ph_skip_comma(struct parse_helper *ph)
 	}
 }
 
+static const char precedence[] = {
+	/* (  +  -  *  /  &  ^  |  ) */
+	   0, 2, 2, 1, 1, 3, 4, 5, 6
+};
+static const char unary_operations[]  = "(+-"; static const char
+binary_operations[] = " +-*/&^|)";
+
+static uint32_t do_func(uint32_t val1, uint32_t val2, int op) {
+	switch (op) {
+	case 1:
+		return val1 + val2;
+	case 2:
+		return val1 - val2;
+	case 3:
+		return val1 * val2;
+	case 4:
+		return val1 / val2;
+	case 5:
+		return val1 & val2;
+	case 6:
+		return val1 ^ val2;
+	case 7:
+		return val1 | val2;
+	}
+	fprintf(stderr, "Error: in func %s: val1=%d val2=%d op = %d\n",
+			__func__, val1, val2, op);
+	exit(EXIT_FAILURE);
+}
+
+static int find_op(char c, const char *p) {
+	int i;
+	for (i = 0; ; i++) {
+		if (c == p[i])
+			return i;
+		if (!p[i])
+			break;
+	}
+	return -1;
+}
+
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
 int ph_get_value(struct parse_helper *ph, uint32_t *pval)  {
 	char *endptr;
-	uint32_t value;
+	int op_i = 0;
+	int val_i = 0;
+	unsigned char op[16];
+	uint32_t val[16];
+	int unary = 1;
+	char *p;
 
-	if (ph_skip_separators(ph))
-		return -1;
-	errno = 0;
-	value = strtoul(ph->p, &endptr, 16);
-	if (errno || (ph->p == endptr))
-		return -1;
-	*pval = value;
-	ph->p = endptr;
-	return 0;
+	p = ph->p;
+	for (;;) {
+		char c;
+		int i, j;
+		const char *ops = unary ? unary_operations :
 binary_operations;
+
+		if (unary) {
+			ph->p = p;
+			if (ph_skip_separators(ph))
+				return -1;
+			p = ph->p;
+			c = *p;
+		} else {
+			for (;;) {
+				c = *p;
+				if ((c != ' ') && (c != '\t'))
+					break;
+				p++;
+			}
+		}
+		i = find_op(c, ops);
+		debug("%d,%c,%d:%s\n", i, c, unary, p);
+		if ((i < 0) && unary) {
+			if (val_i >= ARRAY_SIZE(val))
+				return -1;
+			errno = 0;
+			val[val_i++] = strtoul(p, &endptr, 16);
+			if (errno || (p == endptr)) {
+				ph->p = p;
+				return -1;
+			}
+			p = endptr;
+			unary = 0;
+			debug("val[%d]=%x,%d,%d\n", val_i - 1, val[val_i - 1],
+					op_i, val_i);
+do_unary:
+			while (op_i) {
+				j = op[op_i - 1];
+				if (!(j & 0x80))
+					break;
+				op_i--;
+				val[val_i - 1] = do_func(0,
+						val[val_i - 1], j & 0x7f);
+				debug("un:%d,%x,%d,%d\n", val[val_i - 1], j,
+						op_i, val_i);
+			}
+			continue;
+		}
+		if (i < 0) {
+			c = 0;
+			i = 8;
+		} else {
+			p++;
+		}
+		if (c == '(') {
+			if (op_i >= ARRAY_SIZE(op))
+				return -1;
+			op[op_i++] = i;
+			debug("op[%d]=%x,%d,%d\n", op_i - 1, op[op_i - 1],
+					op_i, val_i);
+			unary = 1;
+			continue;
+		}
+		for (;;) {
+			if (!op_i || unary)
+				break;
+			j = op[op_i - 1];
+			if (j == 0) {
+				if (c == ')') {
+					op_i--;
+					goto do_unary;
+				}
+				break;
+			}
+			if ((j & 0x80)) {
+				op_i--;
+				val[val_i - 1] = do_func(0,
+						val[val_i - 1], j & 0x7f);
+				debug("unary:%d,%x\n", val[val_i - 1], j);
+				continue;
+			}
+			if (precedence[i] < precedence[j])
+				break;
+			if (val_i < 2)
+				return -1;
+			op_i--;
+			val[val_i - 2] = do_func(val[val_i - 2],
+					val[val_i - 1], j);
+			val_i--;
+			debug("binary:%d,%x,%d,%d\n", val[val_i - 1], j,
+					op_i, val_i);
+		}
+		if (c == ')') {
+			fprintf(stderr, "Error: unmatched parenthesis\n");
+			return -1;
+		}
+		if (i == 8) {
+			if ((op_i != 0) || (val_i != 1)) {
+				fprintf(stderr, "Error: syntax %d %d\n",
+						op_i, val_i);
+				return -1;
+			}
+			ph->p = p;
+			*pval = val[0];
+			return 0;
+		}
+		if (op_i >= ARRAY_SIZE(op))
+			return -1;
+		op[op_i++] = i | (unary << 7);
+		debug("op[%d]=%x,%d,%d\n", op_i - 1, op[op_i - 1], op_i, val_i);
+		unary = 1;
+	}
 }
 
 /*
--

1.7.9.5

Wolfgang Denk

2012-11-28 09:30 UTC #134 lore raw

v4 cover imximage series

In reply to Troy Kisky

Dear Troy Kisky,

Quoted 8 lines · In message <[email protected]>…

This series make the file imximage.c easier to read, as well as produces a slightly smaller file.
Only the 1st two patches are different from version 3. The 1st is a new patch which addresses an mx53 ROM bug. The 2nd is slight changes due to rebase on 1st.

Would it make sense to use this opportunity to integrate this tool into mkimage ?

Best regards,

Wolfgang Denk

Signature · 6 lines

DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
You see things; and you say ``Why?'' But I dream  things  that  never
were; and I say ``Why not?''
       - George Bernard Shaw _Back to Methuselah_ (1921) pt. 1, act 1

Troy Kisky

author

2012-11-28 18:29 UTC #135 lore raw

v4 cover imximage series

Quoted 10 lines · Wolfgang Denk

Dear Troy Kisky,
Quoted 7 lines · In message <[email protected]>…
This series make the file imximage.c easier to read, as well as produces a slightly smaller file.
Only the 1st two patches are different from version 3. The 1st is a new patch which addresses an mx53 ROM bug. The 2nd is slight changes due to rebase on 1st.

Quoted 7 lines

Would it make sense to use this opportunity to integrate this tool into mkimage ?
Best regards,
Wolfgang Denk

I did not mean to imply that it wasn't already in mkimage, but I can see that interpretation. It is part of mkimage.

Troy

Troy Kisky

author

2012-10-04 01:47 UTC #136 lore raw

PATCH v3 9/32 imximage: remove static imximage_version

In reply to Troy Kisky

This variable does not need to have file scope.

Signed-off-by Troy Kisky <[email protected]>

---
 tools/imximage.c |   21 +++++++++------------
 1 file changed, 9 insertions(+), 12 deletions(-)

tools/imximage.c +9 ~~-12~~

index 1365b1e..10ccfa9 100644
@@ -65,8 +65,6 @@ static table_entry_t imximage_versions[] = {
 	{-1,            "",     " (Invalid)",                 },
 };
 
-static uint32_t imximage_version;
-
 static set_dcd_val_t set_dcd_val;
 static set_dcd_rst_t set_dcd_rst;
 static set_imx_hdr_t set_imx_hdr;

@@ -254,7 +252,7 @@ static int set_imx_hdr_v2(struct imx_header *imxhdr, uint32_t dcd_len,
 	return header_length;
 }
 
-static void set_hdr_func(struct imx_header *imxhdr)
+static void set_hdr_func(struct imx_header *imxhdr, uint32_t imximage_version)
 {
 	switch (imximage_version) {
 	case IMXIMAGE_V1:

@@ -335,6 +333,7 @@ static void parse_cfg_cmd(struct imx_header *imxhdr, int32_t cmd, char *token,
 {
 	int value;
 	static int cmd_ver_first = ~0;
+	uint32_t imximage_version;
 
 	switch (cmd) {
 	case CMD_IMAGE_VERSION:

@@ -346,7 +345,7 @@ static void parse_cfg_cmd(struct imx_header *imxhdr, int32_t cmd, char *token,
 			exit(EXIT_FAILURE);
 		}
 		cmd_ver_first = 1;
-		set_hdr_func(imxhdr);
+		set_hdr_func(imxhdr, imximage_version);
 		break;
 	case CMD_BOOT_FROM:
 		g_flash_offset = get_table_entry_id(imximage_bootops,

@@ -419,6 +418,12 @@ static uint32_t parse_cfg_file(struct imx_header *imxhdr, char *name)
 	int dcd_len = 0;
 	int32_t cmd;
 
+	/*
+	 * In order to not change the old imx cfg file
+	 * by adding VERSION command into it, here need
+	 * set up function ptr group to V1 by default.
+	 */
+	set_hdr_func(imxhdr, IMXIMAGE_V1);
 	fd = fopen(name, "r");
 	if (fd == 0) {
 		fprintf(stderr, "Error: %s - Can't open DCD file\n", name);

@@ -512,16 +517,8 @@ int imximage_vrec_header(struct mkimage_params *params,
 		fprintf(stderr, "Error: out of memory\n");
 		exit(EXIT_FAILURE);
 	}
-	/*
-	 * In order to not change the old imx cfg file
-	 * by adding VERSION command into it, here need
-	 * set up function ptr group to V1 by default.
-	 */
-	imximage_version = IMXIMAGE_V1;
 	/* Be able to detect if the cfg file has no BOOT_FROM tag */
 	g_flash_offset = FLASH_OFFSET_UNDEFINED;
-	set_hdr_func(imxhdr);
-
 	/* Parse dcd configuration file */
 	dcd_len = parse_cfg_file(imxhdr, params->imagename);

Signature · 1 line

1.7.9.5

Troy Kisky

author

2012-10-04 01:47 UTC #137 lore raw

PATCH v3 10/32 imximage: prepare to move static variables to struct data_src

In reply to Troy Kisky

Need to move accesses to the static variables to
a function where struct data_src is used.

Signed-off-by Troy Kisky <[email protected]>

---
v3: new patch

---
 tools/imximage.c |   24 +++++++++++++-----------
 tools/imximage.h |    3 +++
 2 files changed, 16 insertions(+), 11 deletions(-)

tools/imximage.c +13 ~~-11~~

index 10ccfa9..a2460d6 100644
@@ -407,8 +407,11 @@ static void parse_cfg_fld(struct imx_header *imxhdr, int32_t *cmd,
 		break;
 	}
 }
-static uint32_t parse_cfg_file(struct imx_header *imxhdr, char *name)
+
+static int parse_cfg_file(struct imx_header *imxhdr, char *name,
+		uint32_t entry_point)
 {
+	struct data_src ds;
 	FILE *fd = NULL;
 	char *line = NULL;
 	char *token, *saveptr1, *saveptr2;

@@ -418,6 +421,10 @@ static uint32_t parse_cfg_file(struct imx_header *imxhdr, char *name)
 	int dcd_len = 0;
 	int32_t cmd;
 
+	/* Be able to detect if the cfg file has no BOOT_FROM tag */
+	g_flash_offset = FLASH_OFFSET_UNDEFINED;
+	memset(&ds, 0, sizeof(struct data_src));
+	ds.imxhdr = imxhdr;
 	/*
 	 * In order to not change the old imx cfg file
 	 * by adding VERSION command into it, here need

@@ -465,10 +472,10 @@ static uint32_t parse_cfg_file(struct imx_header *imxhdr, char *name)
 		fprintf(stderr, "Error: No BOOT_FROM tag in %s\n", name);
 		exit(EXIT_FAILURE);
 	}
-	return dcd_len;
+	/* Set the imx header */
+	return (*set_imx_hdr)(imxhdr, dcd_len, entry_point, g_flash_offset);
 }
 
-
 static int imximage_check_image_types(uint8_t type)
 {
 	if (type == IH_TYPE_IMXIMAGE)

@@ -510,21 +517,16 @@ int imximage_vrec_header(struct mkimage_params *params,
 		struct image_type_params *tparams)
 {
 	struct imx_header *imxhdr;
-	uint32_t dcd_len;
 
 	imxhdr = calloc(1, MAX_HEADER_SIZE);
 	if (!imxhdr) {
 		fprintf(stderr, "Error: out of memory\n");
 		exit(EXIT_FAILURE);
 	}
-	/* Be able to detect if the cfg file has no BOOT_FROM tag */
-	g_flash_offset = FLASH_OFFSET_UNDEFINED;
-	/* Parse dcd configuration file */
-	dcd_len = parse_cfg_file(imxhdr, params->imagename);
 
-	/* Set the imx header */
-	imximage_params.header_size = (*set_imx_hdr)(imxhdr, dcd_len,
-			params->ep, g_flash_offset);
+	/* Parse dcd configuration file */
+	imximage_params.header_size = parse_cfg_file(imxhdr, params->imagename,
+			params->ep);
 	imximage_params.hdr = imxhdr;
 	return 0;
 }

tools/imximage.h +3 -0

index 0f39447..2895378 100644
@@ -171,4 +171,7 @@ typedef void (*set_dcd_rst_t)(struct imx_header *imxhdr,
 typedef int (*set_imx_hdr_t)(struct imx_header *imxhdr, uint32_t dcd_len,
 		uint32_t entry_point, uint32_t flash_offset);
 
+struct data_src {
+	struct imx_header *imxhdr;
+};
 #endif /* _IMXIMAGE_H_ */

Signature · 1 line

1.7.9.5

Troy Kisky

author

2012-10-04 01:47 UTC #138 lore raw

PATCH v3 11/32 imximage: change parameters for set_dcd_val/set_imx_hdr

In reply to Troy Kisky

Change 1st argument of set_imx_hdr/set_dcd_val
to struct data_src.

Signed-off-by Troy Kisky <[email protected]>

---
 tools/imximage.c |   41 +++++++++++++++++++++--------------------
 tools/imximage.h |    5 +++--
 2 files changed, 24 insertions(+), 22 deletions(-)

tools/imximage.c +21 ~~-20~~

index a2460d6..85d3753 100644
@@ -116,10 +116,10 @@ static void err_imximage_version(int version)
 	exit(EXIT_FAILURE);
 }
 
-static void set_dcd_val_v1(struct imx_header *imxhdr, char *name, int lineno,
+static void set_dcd_val_v1(struct data_src *ds, char *name, int lineno,
 					int fld, uint32_t value, uint32_t off)
 {
-	dcd_v1_t *dcd_v1 = &imxhdr->header.hdr_v1.dcd_table;
+	dcd_v1_t *dcd_v1 = &ds->imxhdr->header.hdr_v1.dcd_table;
 
 	switch (fld) {
 	case CFG_REG_SIZE:

@@ -144,10 +144,10 @@ static void set_dcd_val_v1(struct imx_header *imxhdr, char *name, int lineno,
 	}
 }
 
-static void set_dcd_val_v2(struct imx_header *imxhdr, char *name, int lineno,
+static void set_dcd_val_v2(struct data_src *ds, char *name, int lineno,
 					int fld, uint32_t value, uint32_t off)
 {
-	dcd_v2_t *dcd_v2 = &imxhdr->header.hdr_v2.dcd_table;
+	dcd_v2_t *dcd_v2 = &ds->imxhdr->header.hdr_v2.dcd_table;
 
 	switch (fld) {
 	case CFG_REG_ADDRESS:

@@ -194,15 +194,15 @@ static void set_dcd_rst_v2(struct imx_header *imxhdr, uint32_t dcd_len,
 	dcd_v2->write_dcd_command.param = DCD_COMMAND_PARAM;
 }
 
-static int set_imx_hdr_v1(struct imx_header *imxhdr, uint32_t dcd_len,
+static int set_imx_hdr_v1(struct data_src *ds, uint32_t dcd_len,
 		uint32_t entry_point, uint32_t flash_offset)
 {
-	imx_header_v1_t *hdr_v1 = &imxhdr->header.hdr_v1;
+	imx_header_v1_t *hdr_v1 = &ds->imxhdr->header.hdr_v1;
 	flash_header_v1_t *fhdr_v1 = &hdr_v1->fhdr;
 	dcd_v1_t *dcd_v1 = &hdr_v1->dcd_table;
 	uint32_t hdr_base;
 	uint32_t header_length = (((char *)&dcd_v1->addr_data[dcd_len].addr)
-			- ((char *)imxhdr));
+			- ((char *)ds->imxhdr));
 
 	/* Set magic number */
 	fhdr_v1->app_code_barker = APP_CODE_BARKER;

@@ -217,19 +217,20 @@ static int set_imx_hdr_v1(struct imx_header *imxhdr, uint32_t dcd_len,
 	/* Security feature are not supported */
 	fhdr_v1->app_code_csf = 0;
 	fhdr_v1->super_root_key = 0;
-	header_size_ptr = (uint32_t *)(((char *)imxhdr) + header_length - 4);
+	header_size_ptr = (uint32_t *)(((char *)ds->imxhdr) +
+			header_length - 4);
 	return header_length;
 }
 
-static int set_imx_hdr_v2(struct imx_header *imxhdr, uint32_t dcd_len,
+static int set_imx_hdr_v2(struct data_src *ds, uint32_t dcd_len,
 		uint32_t entry_point, uint32_t flash_offset)
 {
-	imx_header_v2_t *hdr_v2 = &imxhdr->header.hdr_v2;
+	imx_header_v2_t *hdr_v2 = &ds->imxhdr->header.hdr_v2;
 	flash_header_v2_t *fhdr_v2 = &hdr_v2->fhdr;
 	uint32_t hdr_base;
 	uint32_t header_length = (dcd_len) ?
-		(char *)&hdr_v2->dcd_table.addr_data[dcd_len] - ((char*)imxhdr)
-		: offsetof(imx_header_v2_t, dcd_table);
+		(char *)&hdr_v2->dcd_table.addr_data[dcd_len] -
+		((char *)ds->imxhdr) : offsetof(imx_header_v2_t, dcd_table);
 
 	/* Set magic number */
 	fhdr_v2->header.tag = IVT_HEADER_TAG; /* 0xD1 */

@@ -328,7 +329,7 @@ static void print_hdr_v2(struct imx_header *imx_hdr)
 	printf("Entry Point:  %08x\n", (uint32_t)fhdr_v2->entry);
 }
 
-static void parse_cfg_cmd(struct imx_header *imxhdr, int32_t cmd, char *token,
+static void parse_cfg_cmd(struct data_src *ds, int32_t cmd, char *token,
 				char *name, int lineno, int fld, int dcd_len)
 {
 	int value;

@@ -345,7 +346,7 @@ static void parse_cfg_cmd(struct imx_header *imxhdr, int32_t cmd, char *token,
 			exit(EXIT_FAILURE);
 		}
 		cmd_ver_first = 1;
-		set_hdr_func(imxhdr, imximage_version);
+		set_hdr_func(ds->imxhdr, imximage_version);
 		break;
 	case CMD_BOOT_FROM:
 		g_flash_offset = get_table_entry_id(imximage_bootops,

@@ -360,14 +361,14 @@ static void parse_cfg_cmd(struct imx_header *imxhdr, int32_t cmd, char *token,
 		break;
 	case CMD_DATA:
 		value = get_cfg_value(token, name, lineno);
-		(*set_dcd_val)(imxhdr, name, lineno, fld, value, dcd_len);
+		(*set_dcd_val)(ds, name, lineno, fld, value, dcd_len);
 		if (unlikely(cmd_ver_first != 1))
 			cmd_ver_first = 0;
 		break;
 	}
 }
 
-static void parse_cfg_fld(struct imx_header *imxhdr, int32_t *cmd,
+static void parse_cfg_fld(struct data_src *ds, int32_t *cmd,
 		char *token, char *name, int lineno, int fld, int *dcd_len)
 {
 	int value;

@@ -383,7 +384,7 @@ static void parse_cfg_fld(struct imx_header *imxhdr, int32_t *cmd,
 		}
 		break;
 	case CFG_REG_SIZE:
-		parse_cfg_cmd(imxhdr, *cmd, token, name, lineno, fld, *dcd_len);
+		parse_cfg_cmd(ds, *cmd, token, name, lineno, fld, *dcd_len);
 		break;
 	case CFG_REG_ADDRESS:
 	case CFG_REG_VALUE:

@@ -391,7 +392,7 @@ static void parse_cfg_fld(struct imx_header *imxhdr, int32_t *cmd,
 			return;
 
 		value = get_cfg_value(token, name, lineno);
-		(*set_dcd_val)(imxhdr, name, lineno, fld, value, *dcd_len);
+		(*set_dcd_val)(ds, name, lineno, fld, value, *dcd_len);
 
 		if (fld == CFG_REG_VALUE) {
 			(*dcd_len)++;

@@ -458,7 +459,7 @@ static int parse_cfg_file(struct imx_header *imxhdr, char *name,
 			if (token[0] == '#')
 				break;
 
-			parse_cfg_fld(imxhdr, &cmd, token, name,
+			parse_cfg_fld(&ds, &cmd, token, name,
 					lineno, fld, &dcd_len);
 		}

@@ -473,7 +474,7 @@ static int parse_cfg_file(struct imx_header *imxhdr, char *name,
 		exit(EXIT_FAILURE);
 	}
 	/* Set the imx header */
-	return (*set_imx_hdr)(imxhdr, dcd_len, entry_point, g_flash_offset);
+	return (*set_imx_hdr)(&ds, dcd_len, entry_point, g_flash_offset);
 }
 
 static int imximage_check_image_types(uint8_t type)

tools/imximage.h +3 -2

index 2895378..3054d55 100644
@@ -159,7 +159,8 @@ struct imx_header {
 	} header;
 };
 
-typedef void (*set_dcd_val_t)(struct imx_header *imxhdr,
+struct data_src;
+typedef void (*set_dcd_val_t)(struct data_src *ds,
 					char *name, int lineno,
 					int fld, uint32_t value,
 					uint32_t off);

@@ -168,7 +169,7 @@ typedef void (*set_dcd_rst_t)(struct imx_header *imxhdr,
 					uint32_t dcd_len,
 					char *name, int lineno);
 
-typedef int (*set_imx_hdr_t)(struct imx_header *imxhdr, uint32_t dcd_len,
+typedef int (*set_imx_hdr_t)(struct data_src *ds, uint32_t dcd_len,
 		uint32_t entry_point, uint32_t flash_offset);
 
 struct data_src {

Signature · 1 line

1.7.9.5

Troy Kisky

author

2012-10-04 01:47 UTC #139 lore raw

PATCH v3 12/32 imximage: move set_imx_hdr to struct data_src

In reply to Troy Kisky

Signed-off-by Troy Kisky <[email protected]>

---
v3: new patch

---
 tools/imximage.c |   13 ++++++-------
 tools/imximage.h |    1 +
 2 files changed, 7 insertions(+), 7 deletions(-)

tools/imximage.c +6 -7

index 85d3753..eb1ab62 100644
@@ -67,7 +67,6 @@ static table_entry_t imximage_versions[] = {
 
 static set_dcd_val_t set_dcd_val;
 static set_dcd_rst_t set_dcd_rst;
-static set_imx_hdr_t set_imx_hdr;
 static uint32_t max_dcd_entries;
 static uint32_t *header_size_ptr;
 static uint32_t g_flash_offset;

@@ -253,19 +252,19 @@ static int set_imx_hdr_v2(struct data_src *ds, uint32_t dcd_len,
 	return header_length;
 }
 
-static void set_hdr_func(struct imx_header *imxhdr, uint32_t imximage_version)
+static void set_hdr_func(struct data_src *ds, uint32_t imximage_version)
 {
 	switch (imximage_version) {
 	case IMXIMAGE_V1:
 		set_dcd_val = set_dcd_val_v1;
 		set_dcd_rst = set_dcd_rst_v1;
-		set_imx_hdr = set_imx_hdr_v1;
+		ds->set_imx_hdr = set_imx_hdr_v1;
 		max_dcd_entries = MAX_HW_CFG_SIZE_V1;
 		break;
 	case IMXIMAGE_V2:
 		set_dcd_val = set_dcd_val_v2;
 		set_dcd_rst = set_dcd_rst_v2;
-		set_imx_hdr = set_imx_hdr_v2;
+		ds->set_imx_hdr = set_imx_hdr_v2;
 		max_dcd_entries = MAX_HW_CFG_SIZE_V2;
 		break;
 	default:

@@ -346,7 +345,7 @@ static void parse_cfg_cmd(struct data_src *ds, int32_t cmd, char *token,
 			exit(EXIT_FAILURE);
 		}
 		cmd_ver_first = 1;
-		set_hdr_func(ds->imxhdr, imximage_version);
+		set_hdr_func(ds, imximage_version);
 		break;
 	case CMD_BOOT_FROM:
 		g_flash_offset = get_table_entry_id(imximage_bootops,

@@ -431,7 +430,7 @@ static int parse_cfg_file(struct imx_header *imxhdr, char *name,
 	 * by adding VERSION command into it, here need
 	 * set up function ptr group to V1 by default.
 	 */
-	set_hdr_func(imxhdr, IMXIMAGE_V1);
+	set_hdr_func(&ds, IMXIMAGE_V1);
 	fd = fopen(name, "r");
 	if (fd == 0) {
 		fprintf(stderr, "Error: %s - Can't open DCD file\n", name);

@@ -474,7 +473,7 @@ static int parse_cfg_file(struct imx_header *imxhdr, char *name,
 		exit(EXIT_FAILURE);
 	}
 	/* Set the imx header */
-	return (*set_imx_hdr)(&ds, dcd_len, entry_point, g_flash_offset);
+	return (*ds.set_imx_hdr)(&ds, dcd_len, entry_point, g_flash_offset);
 }
 
 static int imximage_check_image_types(uint8_t type)

tools/imximage.h +1 -0

index 3054d55..f27a2ef 100644
@@ -174,5 +174,6 @@ typedef int (*set_imx_hdr_t)(struct data_src *ds, uint32_t dcd_len,
 
 struct data_src {
 	struct imx_header *imxhdr;
+	set_imx_hdr_t set_imx_hdr;
 };
 #endif /* _IMXIMAGE_H_ */

Signature · 1 line

1.7.9.5

Troy Kisky

author

2012-10-04 01:47 UTC #140 lore raw

PATCH v3 13/32 imximage: move set_dcd_val to struct data_src

In reply to Troy Kisky

Signed-off-by Troy Kisky <[email protected]>

---
v3: new patch

---
 tools/imximage.c |    9 ++++-----
 tools/imximage.h |    1 +
 2 files changed, 5 insertions(+), 5 deletions(-)

tools/imximage.c +4 -5

index eb1ab62..6fcb6ee 100644
@@ -65,7 +65,6 @@ static table_entry_t imximage_versions[] = {
 	{-1,            "",     " (Invalid)",                 },
 };
 
-static set_dcd_val_t set_dcd_val;
 static set_dcd_rst_t set_dcd_rst;
 static uint32_t max_dcd_entries;
 static uint32_t *header_size_ptr;

@@ -256,13 +255,13 @@ static void set_hdr_func(struct data_src *ds, uint32_t imximage_version)
 {
 	switch (imximage_version) {
 	case IMXIMAGE_V1:
-		set_dcd_val = set_dcd_val_v1;
+		ds->set_dcd_val = set_dcd_val_v1;
 		set_dcd_rst = set_dcd_rst_v1;
 		ds->set_imx_hdr = set_imx_hdr_v1;
 		max_dcd_entries = MAX_HW_CFG_SIZE_V1;
 		break;
 	case IMXIMAGE_V2:
-		set_dcd_val = set_dcd_val_v2;
+		ds->set_dcd_val = set_dcd_val_v2;
 		set_dcd_rst = set_dcd_rst_v2;
 		ds->set_imx_hdr = set_imx_hdr_v2;
 		max_dcd_entries = MAX_HW_CFG_SIZE_V2;

@@ -360,7 +359,7 @@ static void parse_cfg_cmd(struct data_src *ds, int32_t cmd, char *token,
 		break;
 	case CMD_DATA:
 		value = get_cfg_value(token, name, lineno);
-		(*set_dcd_val)(ds, name, lineno, fld, value, dcd_len);
+		(*ds->set_dcd_val)(ds, name, lineno, fld, value, dcd_len);
 		if (unlikely(cmd_ver_first != 1))
 			cmd_ver_first = 0;
 		break;

@@ -391,7 +390,7 @@ static void parse_cfg_fld(struct data_src *ds, int32_t *cmd,
 			return;
 
 		value = get_cfg_value(token, name, lineno);
-		(*set_dcd_val)(ds, name, lineno, fld, value, *dcd_len);
+		(*ds->set_dcd_val)(ds, name, lineno, fld, value, *dcd_len);
 
 		if (fld == CFG_REG_VALUE) {
 			(*dcd_len)++;

tools/imximage.h +1 -0

index f27a2ef..444ddce 100644
@@ -175,5 +175,6 @@ typedef int (*set_imx_hdr_t)(struct data_src *ds, uint32_t dcd_len,
 struct data_src {
 	struct imx_header *imxhdr;
 	set_imx_hdr_t set_imx_hdr;
+	set_dcd_val_t set_dcd_val;
 };
 #endif /* _IMXIMAGE_H_ */

Signature · 1 line

1.7.9.5

Troy Kisky

author

2012-10-04 01:47 UTC #141 lore raw

PATCH v3 14/32 imximage: enable word writes for version2 header

In reply to Troy Kisky

Before, only 1 write_dcd_command table was built.
Now, a new table is built when the size changes.

Signed-off-by Troy Kisky <[email protected]>

---
v3: moved static variables together

---
 tools/imximage.c |  143 ++++++++++++++++++++++++++----------------------------
 tools/imximage.h |   18 +++----
 2 files changed, 76 insertions(+), 85 deletions(-)

tools/imximage.c +69 ~~-74~~

index 6fcb6ee..29a12bc 100644
@@ -65,8 +65,6 @@ static table_entry_t imximage_versions[] = {
 	{-1,            "",     " (Invalid)",                 },
 };
 
-static set_dcd_rst_t set_dcd_rst;
-static uint32_t max_dcd_entries;
 static uint32_t *header_size_ptr;
 static uint32_t g_flash_offset;

@@ -115,7 +113,7 @@ static void err_imximage_version(int version)
 }
 
 static void set_dcd_val_v1(struct data_src *ds, char *name, int lineno,
-					int fld, uint32_t value, uint32_t off)
+					int fld, uint32_t value)
 {
 	dcd_v1_t *dcd_v1 = &ds->imxhdr->header.hdr_v1.dcd_table;

@@ -128,13 +126,15 @@ static void set_dcd_val_v1(struct data_src *ds, char *name, int lineno,
 				name, lineno, value);
 			exit(EXIT_FAILURE);
 		}
-		dcd_v1->addr_data[off].type = value;
+		*ds->p_entry++ = value;
 		break;
 	case CFG_REG_ADDRESS:
-		dcd_v1->addr_data[off].addr = value;
+		*ds->p_entry++ = value;
 		break;
 	case CFG_REG_VALUE:
-		dcd_v1->addr_data[off].value = value;
+		*ds->p_entry++ = value;
+		dcd_v1->preamble.length = (char *)ds->p_entry
+				- (char *)&dcd_v1->addr_data[0].type;
 		break;
 	default:
 		break;

@@ -143,16 +143,42 @@ static void set_dcd_val_v1(struct data_src *ds, char *name, int lineno,
 }
 
 static void set_dcd_val_v2(struct data_src *ds, char *name, int lineno,
-					int fld, uint32_t value, uint32_t off)
+					int fld, uint32_t value)
 {
+	uint32_t len;
 	dcd_v2_t *dcd_v2 = &ds->imxhdr->header.hdr_v2.dcd_table;
 
 	switch (fld) {
+	case CFG_REG_SIZE:
+		/* Byte, halfword, word */
+		if ((value != 1) && (value != 2) && (value != 4)) {
+			fprintf(stderr, "Error: %s[%d] - "
+				"Invalid register size " "(%d)\n",
+				name, lineno, value);
+			exit(EXIT_FAILURE);
+		}
+		if (ds->p_dcd && (ds->p_dcd->param == value))
+			break;
+		if (!ds->p_dcd) {
+			dcd_v2->header.tag = DCD_HEADER_TAG;
+			dcd_v2->header.version = DCD_VERSION;
+			ds->p_dcd = &dcd_v2->write_dcd_command;
+		} else {
+			ds->p_dcd = (write_dcd_command_t *)ds->p_entry;
+		}
+		ds->p_dcd->param = value;
+		ds->p_dcd->tag = DCD_COMMAND_TAG;
+		ds->p_entry = (uint32_t *)(ds->p_dcd + 1);
+		break;
 	case CFG_REG_ADDRESS:
-		dcd_v2->addr_data[off].addr = cpu_to_be32(value);
+		*ds->p_entry++ = cpu_to_be32(value);
 		break;
 	case CFG_REG_VALUE:
-		dcd_v2->addr_data[off].value = cpu_to_be32(value);
+		*ds->p_entry++ = cpu_to_be32(value);
+		len = (char *)ds->p_entry - (char *)&dcd_v2->header;
+		dcd_v2->header.length = cpu_to_be16(len);
+		len = (char *)ds->p_entry - (char *)ds->p_dcd;
+		ds->p_dcd->length = cpu_to_be16(len);
 		break;
 	default:
 		break;

@@ -160,47 +186,14 @@ static void set_dcd_val_v2(struct data_src *ds, char *name, int lineno,
 	}
 }
 
-/*
- * Complete setting up the rest field of DCD of V1
- * such as barker code and DCD data length.
- */
-static void set_dcd_rst_v1(struct imx_header *imxhdr, uint32_t dcd_len,
-						char *name, int lineno)
-{
-	dcd_v1_t *dcd_v1 = &imxhdr->header.hdr_v1.dcd_table;
-
-	dcd_v1->preamble.barker = DCD_BARKER;
-	dcd_v1->preamble.length = dcd_len * sizeof(dcd_type_addr_data_t);
-}
-
-/*
- * Complete setting up the reset field of DCD of V2
- * such as DCD tag, version, length, etc.
- */
-static void set_dcd_rst_v2(struct imx_header *imxhdr, uint32_t dcd_len,
-						char *name, int lineno)
-{
-	dcd_v2_t *dcd_v2 = &imxhdr->header.hdr_v2.dcd_table;
-
-	dcd_v2->header.tag = DCD_HEADER_TAG;
-	dcd_v2->header.length = cpu_to_be16(
-			dcd_len * sizeof(dcd_addr_data_t) + 8);
-	dcd_v2->header.version = DCD_VERSION;
-	dcd_v2->write_dcd_command.tag = DCD_COMMAND_TAG;
-	dcd_v2->write_dcd_command.length = cpu_to_be16(
-			dcd_len * sizeof(dcd_addr_data_t) + 4);
-	dcd_v2->write_dcd_command.param = DCD_COMMAND_PARAM;
-}
-
-static int set_imx_hdr_v1(struct data_src *ds, uint32_t dcd_len,
+static int set_imx_hdr_v1(struct data_src *ds,
 		uint32_t entry_point, uint32_t flash_offset)
 {
 	imx_header_v1_t *hdr_v1 = &ds->imxhdr->header.hdr_v1;
 	flash_header_v1_t *fhdr_v1 = &hdr_v1->fhdr;
-	dcd_v1_t *dcd_v1 = &hdr_v1->dcd_table;
 	uint32_t hdr_base;
-	uint32_t header_length = (((char *)&dcd_v1->addr_data[dcd_len].addr)
-			- ((char *)ds->imxhdr));
+	uint32_t header_length = ((char *)ds->p_entry) + 4
+			- ((char *)ds->imxhdr);
 
 	/* Set magic number */
 	fhdr_v1->app_code_barker = APP_CODE_BARKER;

@@ -220,15 +213,13 @@ static int set_imx_hdr_v1(struct data_src *ds, uint32_t dcd_len,
 	return header_length;
 }
 
-static int set_imx_hdr_v2(struct data_src *ds, uint32_t dcd_len,
+static int set_imx_hdr_v2(struct data_src *ds,
 		uint32_t entry_point, uint32_t flash_offset)
 {
 	imx_header_v2_t *hdr_v2 = &ds->imxhdr->header.hdr_v2;
 	flash_header_v2_t *fhdr_v2 = &hdr_v2->fhdr;
 	uint32_t hdr_base;
-	uint32_t header_length = (dcd_len) ?
-		(char *)&hdr_v2->dcd_table.addr_data[dcd_len] -
-		((char *)ds->imxhdr) : offsetof(imx_header_v2_t, dcd_table);
+	uint32_t header_length = ((char *)ds->p_entry) - ((char *)ds->imxhdr);
 
 	/* Set magic number */
 	fhdr_v2->header.tag = IVT_HEADER_TAG; /* 0xD1 */

@@ -239,7 +230,7 @@ static int set_imx_hdr_v2(struct data_src *ds, uint32_t dcd_len,
 	fhdr_v2->reserved1 = fhdr_v2->reserved2 = 0;
 	fhdr_v2->self = hdr_base = entry_point - header_length;
 
-	fhdr_v2->dcd_ptr = (dcd_len) ? hdr_base
+	fhdr_v2->dcd_ptr = (ds->p_dcd) ? hdr_base
 			+ offsetof(imx_header_v2_t, dcd_table) : 0;
 	fhdr_v2->boot_data_ptr = hdr_base
 			+ offsetof(imx_header_v2_t, boot_data);

@@ -256,15 +247,20 @@ static void set_hdr_func(struct data_src *ds, uint32_t imximage_version)
 	switch (imximage_version) {
 	case IMXIMAGE_V1:
 		ds->set_dcd_val = set_dcd_val_v1;
-		set_dcd_rst = set_dcd_rst_v1;
 		ds->set_imx_hdr = set_imx_hdr_v1;
-		max_dcd_entries = MAX_HW_CFG_SIZE_V1;
+		ds->p_entry = &ds->imxhdr->header.hdr_v1.dcd_table
+				.addr_data[0].type;
+		ds->p_max_dcd = &ds->imxhdr->header.hdr_v1.dcd_table
+				.addr_data[MAX_HW_CFG_SIZE_V1].type;
+		ds->imxhdr->header.hdr_v1.dcd_table.preamble.barker =
+				DCD_BARKER;
 		break;
 	case IMXIMAGE_V2:
 		ds->set_dcd_val = set_dcd_val_v2;
-		set_dcd_rst = set_dcd_rst_v2;
 		ds->set_imx_hdr = set_imx_hdr_v2;
-		max_dcd_entries = MAX_HW_CFG_SIZE_V2;
+		ds->p_entry = (uint32_t *)&ds->imxhdr->header.hdr_v2.dcd_table;
+		ds->p_max_dcd = (uint32_t *)
+				((char *)ds->imxhdr + MAX_HEADER_SIZE);
 		break;
 	default:
 		err_imximage_version(imximage_version);

@@ -328,7 +324,7 @@ static void print_hdr_v2(struct imx_header *imx_hdr)
 }
 
 static void parse_cfg_cmd(struct data_src *ds, int32_t cmd, char *token,
-				char *name, int lineno, int fld, int dcd_len)
+				char *name, int lineno, int fld)
 {
 	int value;
 	static int cmd_ver_first = ~0;

@@ -359,7 +355,7 @@ static void parse_cfg_cmd(struct data_src *ds, int32_t cmd, char *token,
 		break;
 	case CMD_DATA:
 		value = get_cfg_value(token, name, lineno);
-		(*ds->set_dcd_val)(ds, name, lineno, fld, value, dcd_len);
+		(*ds->set_dcd_val)(ds, name, lineno, fld, value);
 		if (unlikely(cmd_ver_first != 1))
 			cmd_ver_first = 0;
 		break;

@@ -367,7 +363,7 @@ static void parse_cfg_cmd(struct data_src *ds, int32_t cmd, char *token,
 }
 
 static void parse_cfg_fld(struct data_src *ds, int32_t *cmd,
-		char *token, char *name, int lineno, int fld, int *dcd_len)
+		char *token, char *name, int lineno, int fld)
 {
 	int value;

@@ -382,7 +378,7 @@ static void parse_cfg_fld(struct data_src *ds, int32_t *cmd,
 		}
 		break;
 	case CFG_REG_SIZE:
-		parse_cfg_cmd(ds, *cmd, token, name, lineno, fld, *dcd_len);
+		parse_cfg_cmd(ds, *cmd, token, name, lineno, fld);
 		break;
 	case CFG_REG_ADDRESS:
 	case CFG_REG_VALUE:

@@ -390,16 +386,14 @@ static void parse_cfg_fld(struct data_src *ds, int32_t *cmd,
 			return;
 
 		value = get_cfg_value(token, name, lineno);
-		(*ds->set_dcd_val)(ds, name, lineno, fld, value, *dcd_len);
-
-		if (fld == CFG_REG_VALUE) {
-			(*dcd_len)++;
-			if (*dcd_len > max_dcd_entries) {
-				fprintf(stderr, "Error: %s[%d] -"
-					"DCD table exceeds maximum size(%d)\n",
-					name, lineno, max_dcd_entries);
-				exit(EXIT_FAILURE);
-			}
+		(*ds->set_dcd_val)(ds, name, lineno, fld, value);
+		if (ds->p_entry > ds->p_max_dcd) {
+			uint32_t size = (char *)ds->p_max_dcd -
+					(char *)ds->imxhdr;
+			fprintf(stderr, "Error: %s[%d] -"
+					"header exceeds maximum size(%d)\n",
+					name, lineno, size);
+			exit(EXIT_FAILURE);
 		}
 		break;
 	default:

@@ -417,7 +411,6 @@ static int parse_cfg_file(struct imx_header *imxhdr, char *name,
 	int lineno = 0;
 	int fld;
 	size_t len;
-	int dcd_len = 0;
 	int32_t cmd;
 
 	/* Be able to detect if the cfg file has no BOOT_FROM tag */

@@ -458,12 +451,10 @@ static int parse_cfg_file(struct imx_header *imxhdr, char *name,
 				break;
 
 			parse_cfg_fld(&ds, &cmd, token, name,
-					lineno, fld, &dcd_len);
+					lineno, fld);
 		}
 
 	}
-
-	(*set_dcd_rst)(imxhdr, dcd_len, name, lineno);
 	fclose(fd);
 
 	/* Exit if there is no BOOT_FROM field specifying the flash_offset */

@@ -472,7 +463,7 @@ static int parse_cfg_file(struct imx_header *imxhdr, char *name,
 		exit(EXIT_FAILURE);
 	}
 	/* Set the imx header */
-	return (*ds.set_imx_hdr)(&ds, dcd_len, entry_point, g_flash_offset);
+	return (*ds.set_imx_hdr)(&ds, entry_point, g_flash_offset);
 }
 
 static int imximage_check_image_types(uint8_t type)

@@ -517,7 +508,11 @@ int imximage_vrec_header(struct mkimage_params *params,
 {
 	struct imx_header *imxhdr;
 
-	imxhdr = calloc(1, MAX_HEADER_SIZE);
+	/*
+	 * A little extra space to avoid access violation on dcd table overflow.
+	 * Overflow is checked after entry is added.
+	 */
+	imxhdr = calloc(1, MAX_HEADER_SIZE + 32);
 	if (!imxhdr) {
 		fprintf(stderr, "Error: out of memory\n");
 		exit(EXIT_FAILURE);

tools/imximage.h +7 ~~-11~~

index 444ddce..196bb51 100644
@@ -47,7 +47,6 @@
 #define DCD_HEADER_TAG 0xD2
 #define DCD_COMMAND_TAG 0xCC
 #define DCD_VERSION 0x40
-#define DCD_COMMAND_PARAM 0x4
 
 enum imximage_cmd {
 	CMD_INVALID,

@@ -160,21 +159,18 @@ struct imx_header {
 };
 
 struct data_src;
-typedef void (*set_dcd_val_t)(struct data_src *ds,
-					char *name, int lineno,
-					int fld, uint32_t value,
-					uint32_t off);
+typedef void (*set_dcd_val_t)(struct data_src *ds, char *name,
+		int lineno, int fld, uint32_t value);
 
-typedef void (*set_dcd_rst_t)(struct imx_header *imxhdr,
-					uint32_t dcd_len,
-					char *name, int lineno);
-
-typedef int (*set_imx_hdr_t)(struct data_src *ds, uint32_t dcd_len,
-		uint32_t entry_point, uint32_t flash_offset);
+typedef int (*set_imx_hdr_t)(struct data_src *ds, uint32_t entry_point,
+		uint32_t flash_offset);
 
 struct data_src {
 	struct imx_header *imxhdr;
 	set_imx_hdr_t set_imx_hdr;
 	set_dcd_val_t set_dcd_val;
+	uint32_t *p_max_dcd;
+	uint32_t *p_entry;
+	write_dcd_command_t *p_dcd;
 };
 #endif /* _IMXIMAGE_H_ */

Signature · 1 line

1.7.9.5

Troy Kisky

author

2012-10-04 01:47 UTC #142 lore raw

PATCH v3 15/32 tools: add parse_helper file

In reply to Troy Kisky

This file can help you parse
configuration files.

Signed-off-by Troy Kisky <[email protected]>

---
 tools/Makefile       |    2 +
 tools/parse_helper.c |  173 ++++++++++++++++++++++++++++++++++++++++++++++++++
 tools/parse_helper.h |   28 ++++++++
 3 files changed, 203 insertions(+)
 create mode 100644 tools/parse_helper.c
 create mode 100644 tools/parse_helper.h

tools/Makefile +2 -0

index c31437e..a540274 100644
@@ -94,6 +94,7 @@ NOPED_OBJ_FILES-y += aisimage.o
 NOPED_OBJ_FILES-y += kwbimage.o
 NOPED_OBJ_FILES-y += pblimage.o
 NOPED_OBJ_FILES-y += imximage.o
+NOPED_OBJ_FILES-y += parse_helper.o
 NOPED_OBJ_FILES-y += omapimage.o
 NOPED_OBJ_FILES-y += mkenvimage.o
 NOPED_OBJ_FILES-y += mkimage.o

@@ -208,6 +209,7 @@ $(obj)mkimage$(SFX):	$(obj)aisimage.o \
 			$(obj)fit_image.o \
 			$(obj)image.o \
 			$(obj)imximage.o \
+			$(obj)parse_helper.o \
 			$(obj)kwbimage.o \
 			$(obj)pblimage.o \
 			$(obj)md5.o \

tools/parse_helper.c new file +173 -0

173 lines not on this page · raw message

tools/parse_helper.h new file +28 -0

new file mode 100644
index 0000000..1ff98a3
@@ -0,0 +1,28 @@
+/*
+ * (C) Copyright 20012  Boundary Devices Inc, troy.kisky at boundarydevices.com
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#ifndef _PARSE_HELPER_H_
+#define _PARSE_HELPER_H_
+
+struct parse_helper {
+	char *line;
+	size_t len;
+	FILE *fd;
+	int lineno;
+	char cmd_started;
+	char *filename;
+	char *p;
+};
+
+int ph_open(struct parse_helper *ph, char *filename);
+void ph_close(struct parse_helper *ph);
+int ph_skip_separators(struct parse_helper *ph);
+int ph_skip_comma(struct parse_helper *ph);
+int ph_get_value(struct parse_helper *ph, uint32_t *pval);
+int ph_get_array(struct parse_helper *ph, uint32_t *data, int cnt);
+int ph_get_table_entry_id(struct parse_helper *ph,
+		const table_entry_t *table, const char *table_name);
+#endif

Signature · 1 line

1.7.9.5

Troy Kisky

author

2012-10-04 01:47 UTC #143 lore raw

PATCH v3 16/32 imximage: use parse_helper functions

In reply to Troy Kisky

Use parse_helper functions to pulling tokens instead of pushing them.
Remove need for switch statements to process commands.

Signed-off-by Troy Kisky <[email protected]>

---
v2: uses file parse_helper added in previous patch changed patch subject, was cleanup parsing

---
 tools/imximage.c |  267 +++++++++++++++++++-----------------------------------
 tools/imximage.h |   17 ++--
 2 files changed, 101 insertions(+), 183 deletions(-)

tools/imximage.c +95 ~~-172~~

index 29a12bc..c13fee1 100644
@@ -25,9 +25,6 @@
  * MA 02111-1307 USA
  */
 
-/* Required to obtain the getline prototype from stdio.h */
-#define _GNU_SOURCE
-
 #include "mkimage.h"
 #include <image.h>
 #include "imximage.h"

@@ -70,21 +67,6 @@ static uint32_t g_flash_offset;
 
 static struct image_type_params imximage_params;
 
-static uint32_t get_cfg_value(char *token, char *name,  int linenr)
-{
-	char *endptr;
-	uint32_t value;
-
-	errno = 0;
-	value = strtoul(token, &endptr, 16);
-	if (errno || (token == endptr)) {
-		fprintf(stderr, "Error: %s[%d] - Invalid hex data(%s)\n",
-			name,  linenr, token);
-		exit(EXIT_FAILURE);
-	}
-	return value;
-}
-
 static uint32_t detect_imximage_version(struct imx_header *imx_hdr)
 {
 	imx_header_v1_t *hdr_v1 = &imx_hdr->header.hdr_v1;

@@ -112,53 +94,36 @@ static void err_imximage_version(int version)
 	exit(EXIT_FAILURE);
 }
 
-static void set_dcd_val_v1(struct data_src *ds, char *name, int lineno,
-					int fld, uint32_t value)
+static int set_dcd_val_v1(struct data_src *ds, uint32_t *data)
 {
 	dcd_v1_t *dcd_v1 = &ds->imxhdr->header.hdr_v1.dcd_table;
+	uint32_t val = *data++;
 
-	switch (fld) {
-	case CFG_REG_SIZE:
-		/* Byte, halfword, word */
-		if ((value != 1) && (value != 2) && (value != 4)) {
-			fprintf(stderr, "Error: %s[%d] - "
-				"Invalid register size " "(%d)\n",
-				name, lineno, value);
-			exit(EXIT_FAILURE);
-		}
-		*ds->p_entry++ = value;
-		break;
-	case CFG_REG_ADDRESS:
-		*ds->p_entry++ = value;
-		break;
-	case CFG_REG_VALUE:
-		*ds->p_entry++ = value;
-		dcd_v1->preamble.length = (char *)ds->p_entry
-				- (char *)&dcd_v1->addr_data[0].type;
-		break;
-	default:
-		break;
-
+	/* Byte, halfword, word */
+	if ((val != 1) && (val != 2) && (val != 4)) {
+		fprintf(stderr, "Error: Invalid register size (%d)\n", val);
+		return -1;
 	}
+	*ds->p_entry++ = val;
+	*ds->p_entry++ = *data++;
+	*ds->p_entry++ = *data++;
+	dcd_v1->preamble.length = (char *)ds->p_entry - (char *)&dcd_v1->
+			addr_data[0].type;
+	return 0;
 }
 
-static void set_dcd_val_v2(struct data_src *ds, char *name, int lineno,
-					int fld, uint32_t value)
+static int set_dcd_val_v2(struct data_src *ds, uint32_t *data)
 {
 	uint32_t len;
 	dcd_v2_t *dcd_v2 = &ds->imxhdr->header.hdr_v2.dcd_table;
+	uint32_t val = *data++;
 
-	switch (fld) {
-	case CFG_REG_SIZE:
-		/* Byte, halfword, word */
-		if ((value != 1) && (value != 2) && (value != 4)) {
-			fprintf(stderr, "Error: %s[%d] - "
-				"Invalid register size " "(%d)\n",
-				name, lineno, value);
-			exit(EXIT_FAILURE);
-		}
-		if (ds->p_dcd && (ds->p_dcd->param == value))
-			break;
+	/* Byte, halfword, word */
+	if ((val != 1) && (val != 2) && (val != 4)) {
+		fprintf(stderr, "Error: Invalid register size (%d)\n", val);
+		return -1;
+	}
+	if (!(ds->p_dcd && (ds->p_dcd->param == val))) {
 		if (!ds->p_dcd) {
 			dcd_v2->header.tag = DCD_HEADER_TAG;
 			dcd_v2->header.version = DCD_VERSION;

@@ -166,24 +131,19 @@ static void set_dcd_val_v2(struct data_src *ds, char *name, int lineno,
 		} else {
 			ds->p_dcd = (write_dcd_command_t *)ds->p_entry;
 		}
-		ds->p_dcd->param = value;
+		ds->p_dcd->param = val;
 		ds->p_dcd->tag = DCD_COMMAND_TAG;
 		ds->p_entry = (uint32_t *)(ds->p_dcd + 1);
-		break;
-	case CFG_REG_ADDRESS:
-		*ds->p_entry++ = cpu_to_be32(value);
-		break;
-	case CFG_REG_VALUE:
-		*ds->p_entry++ = cpu_to_be32(value);
-		len = (char *)ds->p_entry - (char *)&dcd_v2->header;
-		dcd_v2->header.length = cpu_to_be16(len);
-		len = (char *)ds->p_entry - (char *)ds->p_dcd;
-		ds->p_dcd->length = cpu_to_be16(len);
-		break;
-	default:
-		break;
-
 	}
+	val = *data++;
+	*ds->p_entry++ = cpu_to_be32(val);
+	val = *data++;
+	*ds->p_entry++ = cpu_to_be32(val);
+	len = (char *)ds->p_entry - (char *)&dcd_v2->header;
+	dcd_v2->header.length = cpu_to_be16(len);
+	len = (char *)ds->p_entry - (char *)ds->p_dcd;
+	ds->p_dcd->length = cpu_to_be16(len);
+	return 0;
 }
 
 static int set_imx_hdr_v1(struct data_src *ds,

@@ -323,95 +283,71 @@ static void print_hdr_v2(struct imx_header *imx_hdr)
 	printf("Entry Point:  %08x\n", (uint32_t)fhdr_v2->entry);
 }
 
-static void parse_cfg_cmd(struct data_src *ds, int32_t cmd, char *token,
-				char *name, int lineno, int fld)
+static int parse_cmd_data(struct data_src *ds)
+{
+	uint32_t data[3];
+	int ret = ph_get_array(&ds->ph, data, 3);
+
+	if (ret < 0)
+		return ret;
+	ret = (*ds->set_dcd_val)(ds, data);
+	if (ret)
+		return ret;
+	if (ds->p_entry > ds->p_max_dcd) {
+		uint32_t size = (char *)ds->p_max_dcd - (char *)ds->imxhdr;
+		fprintf(stderr, "Error: header exceeds maximum size(%d)\n",
+				size);
+		return -1;
+	}
+	return 0;
+}
+
+static int parse_image_version(struct data_src *ds)
 {
-	int value;
-	static int cmd_ver_first = ~0;
+	int ret;
 	uint32_t imximage_version;
 
-	switch (cmd) {
-	case CMD_IMAGE_VERSION:
-		imximage_version = get_cfg_value(token, name, lineno);
-		if (cmd_ver_first == 0) {
-			fprintf(stderr, "Error: %s[%d] - IMAGE_VERSION "
-				"command need be the first before other "
-				"valid command in the file\n", name, lineno);
-			exit(EXIT_FAILURE);
-		}
-		cmd_ver_first = 1;
-		set_hdr_func(ds, imximage_version);
-		break;
-	case CMD_BOOT_FROM:
-		g_flash_offset = get_table_entry_id(imximage_bootops,
-					"imximage boot option", token);
-		if (g_flash_offset == -1) {
-			fprintf(stderr, "Error: %s[%d] -Invalid boot device"
-				"(%s)\n", name, lineno, token);
-			exit(EXIT_FAILURE);
-		}
-		if (unlikely(cmd_ver_first != 1))
-			cmd_ver_first = 0;
-		break;
-	case CMD_DATA:
-		value = get_cfg_value(token, name, lineno);
-		(*ds->set_dcd_val)(ds, name, lineno, fld, value);
-		if (unlikely(cmd_ver_first != 1))
-			cmd_ver_first = 0;
-		break;
+	ret = ph_get_value(&ds->ph, &imximage_version);
+	if (ret)
+		return ret;
+	if (ds->cmd_cnt) {
+		fprintf(stderr, "Error: IMAGE_VERSION command needs be "
+				"before other valid commands in the file\n");
+		return -1;
 	}
+	set_hdr_func(ds, imximage_version);
+	return 0;
 }
 
-static void parse_cfg_fld(struct data_src *ds, int32_t *cmd,
-		char *token, char *name, int lineno, int fld)
+static int parse_boot_from(struct data_src *ds)
 {
-	int value;
-
-	switch (fld) {
-	case CFG_COMMAND:
-		*cmd = get_table_entry_id(imximage_cmds,
-			"imximage commands", token);
-		if (*cmd < 0) {
-			fprintf(stderr, "Error: %s[%d] - Invalid command"
-			"(%s)\n", name, lineno, token);
-			exit(EXIT_FAILURE);
-		}
-		break;
-	case CFG_REG_SIZE:
-		parse_cfg_cmd(ds, *cmd, token, name, lineno, fld);
-		break;
-	case CFG_REG_ADDRESS:
-	case CFG_REG_VALUE:
-		if (*cmd != CMD_DATA)
-			return;
-
-		value = get_cfg_value(token, name, lineno);
-		(*ds->set_dcd_val)(ds, name, lineno, fld, value);
-		if (ds->p_entry > ds->p_max_dcd) {
-			uint32_t size = (char *)ds->p_max_dcd -
-					(char *)ds->imxhdr;
-			fprintf(stderr, "Error: %s[%d] -"
-					"header exceeds maximum size(%d)\n",
-					name, lineno, size);
-			exit(EXIT_FAILURE);
-		}
-		break;
-	default:
-		break;
+	g_flash_offset = ph_get_table_entry_id(&ds->ph, imximage_bootops,
+			"imximage boot option");
+	if (g_flash_offset == -1) {
+		fprintf(stderr, "Error: Invalid boot device\n");
+		return -1;
 	}
+	return 0;
+}
+
+static const parse_fld_t cmd_table[] = {
+	parse_image_version, parse_boot_from, parse_cmd_data
+};
+
+static int parse_command(struct data_src *ds)
+{
+	int cmd = ph_get_table_entry_id(&ds->ph, imximage_cmds,
+			"imximage commands");
+	if (cmd < 0)
+		return cmd;
+	return cmd_table[cmd](ds);
 }
 
 static int parse_cfg_file(struct imx_header *imxhdr, char *name,
 		uint32_t entry_point)
 {
 	struct data_src ds;
-	FILE *fd = NULL;
-	char *line = NULL;
-	char *token, *saveptr1, *saveptr2;
-	int lineno = 0;
-	int fld;
-	size_t len;
-	int32_t cmd;
+	struct parse_helper *ph = &ds.ph;
 
 	/* Be able to detect if the cfg file has no BOOT_FROM tag */
 	g_flash_offset = FLASH_OFFSET_UNDEFINED;

@@ -423,8 +359,7 @@ static int parse_cfg_file(struct imx_header *imxhdr, char *name,
 	 * set up function ptr group to V1 by default.
 	 */
 	set_hdr_func(&ds, IMXIMAGE_V1);
-	fd = fopen(name, "r");
-	if (fd == 0) {
+	if (ph_open(ph, name)) {
 		fprintf(stderr, "Error: %s - Can't open DCD file\n", name);
 		exit(EXIT_FAILURE);
 	}

@@ -432,31 +367,19 @@ static int parse_cfg_file(struct imx_header *imxhdr, char *name,
 	/* Very simple parsing, line starting with # are comments
 	 * and are dropped
 	 */
-	while ((getline(&line, &len, fd)) > 0) {
-		lineno++;
-
-		token = strtok_r(line, "\r\n", &saveptr1);
-		if (token == NULL)
-			continue;
-
-		/* Check inside the single line */
-		for (fld = CFG_COMMAND, cmd = CMD_INVALID,
-				line = token; ; line = NULL, fld++) {
-			token = strtok_r(line, " \t", &saveptr2);
-			if (token == NULL)
-				break;
-
-			/* Drop all text starting with '#' as comments */
-			if (token[0] == '#')
-				break;
-
-			parse_cfg_fld(&ds, &cmd, token, name,
-					lineno, fld);
+	for (;;) {
+		ph->cmd_started = 0;
+		if (ph_skip_separators(ph))
+			break;
+		ph->cmd_started = 1;
+		if (parse_command(&ds)) {
+			fprintf(stderr, "Error: invalid token %s[%d](%s)\n",
+					name, ph->lineno, ph->p);
+			exit(EXIT_FAILURE);
 		}
-
+		ds.cmd_cnt++;
 	}
-	fclose(fd);
-
+	ph_close(ph);
 	/* Exit if there is no BOOT_FROM field specifying the flash_offset */
 	if (g_flash_offset == FLASH_OFFSET_UNDEFINED) {
 		fprintf(stderr, "Error: No BOOT_FROM tag in %s\n", name);

@@ -538,12 +461,12 @@ static void imximage_set_header(void *ptr, struct stat *sbuf, int ifd,
 int imximage_check_params(struct mkimage_params *params)
 {
 	if (!params)
-		return CFG_INVALID;
+		return -1;
 	if (!strlen(params->imagename)) {
 		fprintf(stderr, "Error: %s - Configuration file not specified, "
 			"it is needed for imximage generation\n",
 			params->cmdname);
-		return CFG_INVALID;
+		return -1;
 	}
 	/*
 	 * Check parameters:

tools/imximage.h +6 ~~-11~~

index 196bb51..6bcd082 100644
@@ -23,6 +23,7 @@
 
 #ifndef _IMXIMAGE_H_
 #define _IMXIMAGE_H_
+#include "parse_helper.h"
 
 #define MAX_HW_CFG_SIZE_V2 121 /* Max number of registers imx can set for v2 */
 #define MAX_HW_CFG_SIZE_V1 60  /* Max number of registers imx can set for v1 */

@@ -49,20 +50,11 @@
 #define DCD_VERSION 0x40
 
 enum imximage_cmd {
-	CMD_INVALID,
 	CMD_IMAGE_VERSION,
 	CMD_BOOT_FROM,
 	CMD_DATA
 };
 
-enum imximage_fld_types {
-	CFG_INVALID = -1,
-	CFG_COMMAND,
-	CFG_REG_SIZE,
-	CFG_REG_ADDRESS,
-	CFG_REG_VALUE
-};
-
 enum imximage_version {
 	IMXIMAGE_VER_INVALID = -1,
 	IMXIMAGE_V1 = 1,

@@ -159,14 +151,17 @@ struct imx_header {
 };
 
 struct data_src;
-typedef void (*set_dcd_val_t)(struct data_src *ds, char *name,
-		int lineno, int fld, uint32_t value);
+typedef int (*parse_fld_t)(struct data_src *ds);
+
+typedef int (*set_dcd_val_t)(struct data_src *ds, uint32_t *data);
 
 typedef int (*set_imx_hdr_t)(struct data_src *ds, uint32_t entry_point,
 		uint32_t flash_offset);
 
 struct data_src {
+	struct parse_helper ph;
 	struct imx_header *imxhdr;
+	int cmd_cnt;
 	set_imx_hdr_t set_imx_hdr;
 	set_dcd_val_t set_dcd_val;
 	uint32_t *p_max_dcd;

Signature · 1 line

1.7.9.5

Troy Kisky

author

2012-10-04 01:47 UTC #144 lore raw

PATCH v3 17/32 imximage.cfg: run files through C preprocessor

In reply to Troy Kisky

The '#' used as comments in the files cause the preprocessor trouble, so change to /* */.

Signed-off-by Troy Kisky <[email protected]>

---
 Makefile                                     |    3 +-
 board/esg/ima3-mx53/imximage.cfg             |  120 ++++++-----
 board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg |   90 ++++----
 board/freescale/mx25pdk/imximage.cfg         |   77 +++----
 board/freescale/mx51evk/imximage.cfg         |  114 +++++-----
 board/freescale/mx53ard/imximage_dd3.cfg     |   83 ++++----
 board/freescale/mx53evk/imximage.cfg         |   86 ++++----
 board/freescale/mx53loco/imximage.cfg        |   83 ++++----
 board/freescale/mx53smd/imximage.cfg         |   83 ++++----
 board/freescale/mx6qarm2/imximage.cfg        |   88 ++++----
 board/genesi/mx51_efikamx/imximage_mx.cfg    |  132 ++++++------
 board/genesi/mx51_efikamx/imximage_sb.cfg    |  126 +++++------
 board/ttcontrol/vision2/imximage_hynix.cfg   |  295 ++++++++++++++------------
 13 files changed, 727 insertions(+), 653 deletions(-)

Makefile +2 -1

index a40d4cc..64ff1b8 100644
@@ -431,7 +431,8 @@ $(obj)u-boot.img:	$(obj)u-boot.bin
 		-d $< $@
 
 $(obj)u-boot.imx:       $(obj)u-boot.bin
-		$(obj)tools/mkimage -n  $(CONFIG_IMX_CONFIG) -T imximage \
+		$(CC) -E -x c $(CONFIG_IMX_CONFIG) -I./include -o $(obj)imxcfg.imx
+		$(obj)tools/mkimage -n  $(obj)imxcfg.imx -T imximage \
 		-e $(CONFIG_SYS_TEXT_BASE) -d $< $@
 
 $(obj)u-boot.kwb:       $(obj)u-boot.bin

board/esg/ima3-mx53/imximage.cfg +66 ~~-54~~

153 lines not on this page · raw message

board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg +47 ~~-43~~

109 lines not on this page · raw message

board/freescale/mx25pdk/imximage.cfg +40 ~~-37~~

93 lines not on this page · raw message

board/freescale/mx51evk/imximage.cfg +60 ~~-54~~

147 lines not on this page · raw message

board/freescale/mx53ard/imximage_dd3.cfg +43 ~~-40~~

91 lines not on this page · raw message

board/freescale/mx53evk/imximage.cfg +44 ~~-42~~

94 lines not on this page · raw message

board/freescale/mx53loco/imximage.cfg +43 ~~-40~~

91 lines not on this page · raw message

board/freescale/mx53smd/imximage.cfg +43 ~~-40~~

91 lines not on this page · raw message

board/freescale/mx6qarm2/imximage.cfg +46 ~~-42~~

101 lines not on this page · raw message

board/genesi/mx51_efikamx/imximage_mx.cfg +70 ~~-62~~

170 lines not on this page · raw message

board/genesi/mx51_efikamx/imximage_sb.cfg +66 ~~-60~~

158 lines not on this page · raw message

board/ttcontrol/vision2/imximage_hynix.cfg +157 ~~-138~~

366 lines not on this page · raw message

Signature · 1 line

1.7.9.5

Eric Nelson

2012-10-07 18:19 UTC #145 lore raw

PATCH v3 17/32 imximage.cfg: run files through C preprocessor

Hi Troy,

Quoted 25 lines · Troy Kisky

The '#' used as comments in the files cause the preprocessor trouble, so change to /* */.

Signed-off-by Troy Kisky<[email protected]>

---
  Makefile                                     |    3 +-
  board/esg/ima3-mx53/imximage.cfg             |  120 ++++++-----
  board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg |   90 ++++----
  board/freescale/mx25pdk/imximage.cfg         |   77 +++----
  board/freescale/mx51evk/imximage.cfg         |  114 +++++-----
  board/freescale/mx53ard/imximage_dd3.cfg     |   83 ++++----
  board/freescale/mx53evk/imximage.cfg         |   86 ++++----
  board/freescale/mx53loco/imximage.cfg        |   83 ++++----
  board/freescale/mx53smd/imximage.cfg         |   83 ++++----
  board/freescale/mx6qarm2/imximage.cfg        |   88 ++++----
  board/genesi/mx51_efikamx/imximage_mx.cfg    |  132 ++++++------
  board/genesi/mx51_efikamx/imximage_sb.cfg    |  126 +++++------
  board/ttcontrol/vision2/imximage_hynix.cfg   |  295 ++++++++++++++------------
  13 files changed, 727 insertions(+), 653 deletions(-)

Makefile +0 -0

index a40d4cc..64ff1b8 100644

Makefile $(obj)u-boot.img: $(obj)u-boot.bin · line 436

Quoted 7 lines

Makefile +2 -1

@@ -431,7 +431,8 @@ $(obj)u-boot.img:	$(obj)u-boot.bin
  		-d $<  $@
 
  $(obj)u-boot.imx:       $(obj)u-boot.bin
-		$(obj)tools/mkimage -n  $(CONFIG_IMX_CONFIG) -T imximage \
+		$(CC) -E -x c $(CONFIG_IMX_CONFIG) -I./include -o $(obj)imxcfg.imx
+		$(obj)tools/mkimage -n  $(obj)imxcfg.imx -T imximage \
  		-e $(CONFIG_SYS_TEXT_BASE) -d $<  $@

This bit creates imxcfg.imx.

If built in-tree, the file will be reported as a new file in 'git status'. Is there a reason it can't be deleted after the build?

Troy Kisky

author

2012-10-08 19:11 UTC #146 lore raw

PATCH v3 17/32 imximage.cfg: run files through C preprocessor

Quoted 40 lines · Eric Nelson

Hi Troy,

Quoted 32 lines · Troy Kisky

The '#' used as comments in the files cause the preprocessor trouble, so change to /* */.

Signed-off-by Troy Kisky<[email protected]>

---
  Makefile                                     |    3 +-
  board/esg/ima3-mx53/imximage.cfg             |  120 ++++++-----
  board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg |   90 ++++----
  board/freescale/mx25pdk/imximage.cfg         |   77 +++----
  board/freescale/mx51evk/imximage.cfg         |  114 +++++-----
  board/freescale/mx53ard/imximage_dd3.cfg     |   83 ++++----
  board/freescale/mx53evk/imximage.cfg         |   86 ++++----
  board/freescale/mx53loco/imximage.cfg        |   83 ++++----
  board/freescale/mx53smd/imximage.cfg         |   83 ++++----
  board/freescale/mx6qarm2/imximage.cfg        |   88 ++++----
  board/genesi/mx51_efikamx/imximage_mx.cfg    |  132 ++++++------
  board/genesi/mx51_efikamx/imximage_sb.cfg    |  126 +++++------
  board/ttcontrol/vision2/imximage_hynix.cfg   |  295 
++++++++++++++------------
  13 files changed, 727 insertions(+), 653 deletions(-)

Makefile +1 -1

index a40d4cc..64ff1b8 100644
@@ -431,7 +431,8 @@ $(obj)u-boot.img:    $(obj)u-boot.bin
          -d $<  $@
 
  $(obj)u-boot.imx:       $(obj)u-boot.bin
-        $(obj)tools/mkimage -n  $(CONFIG_IMX_CONFIG) -T imximage \
+        $(CC) -E -x c $(CONFIG_IMX_CONFIG) -I./include -o

$(obj)imxcfg.imx

Quoted 2 lines

+        $(obj)tools/mkimage -n  $(obj)imxcfg.imx -T imximage \
          -e $(CONFIG_SYS_TEXT_BASE) -d $<  $@

This bit creates imxcfg.imx.

Quoted 4 lines

If built in-tree, the file will be reported as a new file in 'git status'.
Is there a reason it can't be deleted after the build?

Just being able to look at it to see that the output makes sense. I should make sure that make clean, deletes it, but I kinda like being able to look at it after a make all.
Is an entry in gitignore ok?

Is everyone OK was the file name imxcfg.imx, or should some other extension be used?

Stefano Babic

2012-10-08 13:38 UTC #147 lore raw

PATCH v3 17/32 imximage.cfg: run files through C preprocessor

In reply to Troy Kisky

Quoted 5 lines · Troy Kisky

The '#' used as comments in the files cause the preprocessor trouble, so change to /* */.
Signed-off-by Troy Kisky <[email protected]>
---

Hi Troy,

Quoted 6 lines

 Makefile                                     |    3 +-
 board/esg/ima3-mx53/imximage.cfg             |  120 ++++++-----
 board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg |   90 ++++----
 board/freescale/mx25pdk/imximage.cfg         |   77 +++----
 board/freescale/mx51evk/imximage.cfg         |  114 +++++-----
 board/freescale/mx53ard/imximage_dd3.cfg     |   83 ++++----

Quoted 9 lines

 board/freescale/mx53evk/imximage.cfg         |   86 ++++----
 board/freescale/mx53loco/imximage.cfg        |   83 ++++----
 board/freescale/mx53smd/imximage.cfg         |   83 ++++----
 board/freescale/mx6qarm2/imximage.cfg        |   88 ++++----
 board/genesi/mx51_efikamx/imximage_mx.cfg    |  132 ++++++------
 board/genesi/mx51_efikamx/imximage_sb.cfg    |  126 +++++------
 board/ttcontrol/vision2/imximage_hynix.cfg   |  295 ++++++++++++++------------
 13 files changed, 727 insertions(+), 653 deletions(-)

I see the C preprocessor as an optional feature, instead of a rule everybody must follow.

Makefile $(obj)u-boot.img: $(obj)u-boot.bin · line 436

Quoted 12 lines

Makefile +2 -1

index a40d4cc..64ff1b8 100644
@@ -431,7 +431,8 @@ $(obj)u-boot.img:	$(obj)u-boot.bin
 		-d $< $@
 
 $(obj)u-boot.imx:       $(obj)u-boot.bin
-		$(obj)tools/mkimage -n  $(CONFIG_IMX_CONFIG) -T imximage \
+		$(CC) -E -x c $(CONFIG_IMX_CONFIG) -I./include -o $(obj)imxcfg.imx
+		$(obj)tools/mkimage -n  $(obj)imxcfg.imx -T imximage \
 		-e $(CONFIG_SYS_TEXT_BASE) -d $< $@

In fact, adding this rule here requires that each board configuration must be changed. And for all of them, running the preprocessor is unnnecessary.

What about to add this rule only to the Makefile of the boards that require preprocessing ?

Best regards,
Stefano Babic

Signature · 5 lines

=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: [email protected]
=====================================================================

Troy Kisky

author

2012-10-08 21:48 UTC #148 lore raw

PATCH v3 17/32 imximage.cfg: run files through C preprocessor

Quoted 42 lines · Stefano Babic

Quoted 5 lines · Troy Kisky

The '#' used as comments in the files cause the preprocessor trouble, so change to /* */.
Signed-off-by Troy Kisky <[email protected]>
---

Hi Troy,

Quoted 6 lines

  Makefile                                     |    3 +-
  board/esg/ima3-mx53/imximage.cfg             |  120 ++++++-----
  board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg |   90 ++++----
  board/freescale/mx25pdk/imximage.cfg         |   77 +++----
  board/freescale/mx51evk/imximage.cfg         |  114 +++++-----
  board/freescale/mx53ard/imximage_dd3.cfg     |   83 ++++----

Quoted 9 lines

  board/freescale/mx53evk/imximage.cfg         |   86 ++++----
  board/freescale/mx53loco/imximage.cfg        |   83 ++++----
  board/freescale/mx53smd/imximage.cfg         |   83 ++++----
  board/freescale/mx6qarm2/imximage.cfg        |   88 ++++----
  board/genesi/mx51_efikamx/imximage_mx.cfg    |  132 ++++++------
  board/genesi/mx51_efikamx/imximage_sb.cfg    |  126 +++++------
  board/ttcontrol/vision2/imximage_hynix.cfg   |  295 ++++++++++++++------------
  13 files changed, 727 insertions(+), 653 deletions(-)

I see the C preprocessor as an optional feature, instead of a rule everybody must follow.

Makefile $(obj)u-boot.img: $(obj)u-boot.bin · line 436

Quoted 12 lines

Makefile +2 -1

index a40d4cc..64ff1b8 100644
@@ -431,7 +431,8 @@ $(obj)u-boot.img:	$(obj)u-boot.bin
  		-d $< $@
 
  $(obj)u-boot.imx:       $(obj)u-boot.bin
-		$(obj)tools/mkimage -n  $(CONFIG_IMX_CONFIG) -T imximage \
+		$(CC) -E -x c $(CONFIG_IMX_CONFIG) -I./include -o $(obj)imxcfg.imx
+		$(obj)tools/mkimage -n  $(obj)imxcfg.imx -T imximage \
  		-e $(CONFIG_SYS_TEXT_BASE) -d $< $@

In fact, adding this rule here requires that each board configuration must be changed. And for all of them, running the preprocessor is unnnecessary.

Quoted 6 lines

What about to add this rule only to the Makefile of the boards that require preprocessing ?
Best regards,
Stefano Babic

That would be great. But I don't know how to accomplish that. Can you point to similar magic that
I can try to understand?

Thanks
Troy

Troy Kisky

author

2012-10-10 02:03 UTC #149 lore raw

PATCH v3 17/32 imximage.cfg: run files through C preprocessor

In reply to Stefano Babic

Quoted 42 lines · Stefano Babic

Quoted 5 lines · Troy Kisky

The '#' used as comments in the files cause the preprocessor trouble, so change to /* */.
Signed-off-by Troy Kisky <[email protected]>
---

Hi Troy,

Quoted 6 lines

  Makefile                                     |    3 +-
  board/esg/ima3-mx53/imximage.cfg             |  120 ++++++-----
  board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg |   90 ++++----
  board/freescale/mx25pdk/imximage.cfg         |   77 +++----
  board/freescale/mx51evk/imximage.cfg         |  114 +++++-----
  board/freescale/mx53ard/imximage_dd3.cfg     |   83 ++++----

Quoted 9 lines

  board/freescale/mx53evk/imximage.cfg         |   86 ++++----
  board/freescale/mx53loco/imximage.cfg        |   83 ++++----
  board/freescale/mx53smd/imximage.cfg         |   83 ++++----
  board/freescale/mx6qarm2/imximage.cfg        |   88 ++++----
  board/genesi/mx51_efikamx/imximage_mx.cfg    |  132 ++++++------
  board/genesi/mx51_efikamx/imximage_sb.cfg    |  126 +++++------
  board/ttcontrol/vision2/imximage_hynix.cfg   |  295 ++++++++++++++------------
  13 files changed, 727 insertions(+), 653 deletions(-)

I see the C preprocessor as an optional feature, instead of a rule everybody must follow.

Makefile $(obj)u-boot.img: $(obj)u-boot.bin · line 436

Quoted 12 lines

Makefile +2 -1

index a40d4cc..64ff1b8 100644
@@ -431,7 +431,8 @@ $(obj)u-boot.img:	$(obj)u-boot.bin
  		-d $< $@
 
  $(obj)u-boot.imx:       $(obj)u-boot.bin
-		$(obj)tools/mkimage -n  $(CONFIG_IMX_CONFIG) -T imximage \
+		$(CC) -E -x c $(CONFIG_IMX_CONFIG) -I./include -o $(obj)imxcfg.imx
+		$(obj)tools/mkimage -n  $(obj)imxcfg.imx -T imximage \
  		-e $(CONFIG_SYS_TEXT_BASE) -d $< $@

In fact, adding this rule here requires that each board configuration must be changed. And for all of them, running the preprocessor is unnnecessary.

Quoted 6 lines

What about to add this rule only to the Makefile of the boards that require preprocessing ?
Best regards,
Stefano Babic

How about this to do the job....

Subject: [PATCH 17/32] boards.cfg: run mx6q_4x_mt41j128.pcfg through C
preprocessor

The '#' used as comments in the cfg file cause the preprocessor trouble, so change to /* */. Also, rename mx6q_4x_mt41j128.cfg to mx6q_4x_mt41j128.pcfg.

Files with extension of .pcfg are run through the preprocessor before being given to mkimage.

Signed-off-by Troy Kisky <[email protected]>

---
v4: Don't run every file through preprocessor, only .pcfg files

---
  .gitignore                                         |    1 +
  Makefile                                           |   16 +++-
  ...{mx6q_4x_mt41j128.cfg => mx6q_4x_mt41j128.pcfg} |   90 
++++++++++----------
  boards.cfg                                         |    4 +-
  4 files changed, 63 insertions(+), 48 deletions(-)

rename board/freescale/imx/ddr/{mx6q_4x_mt41j128.cfg =>
mx6q_4x_mt41j128.pcfg} (65%)

.gitignore +1 -0

index d91e91b..e5273bd 100644
@@ -15,6 +15,7 @@
  *.swp
  *.patch
  *.bin
+*.pcfgtmp
 
  # Build tree
  /build-*

Makefile +5 -2

index a40d4cc..99666b9 100644
@@ -430,8 +430,17 @@ $(obj)u-boot.img:  $(obj)u-boot.bin
                         sed -e 's/"[     ]*$$/ for $(BOARD) board"/') \
                 -d $< $@
 
-$(obj)u-boot.imx:       $(obj)u-boot.bin
-               $(obj)tools/mkimage -n  $(CONFIG_IMX_CONFIG) -T imximage \
+ifeq ($(suffix $(patsubst "%",%,$(CONFIG_IMX_CONFIG))),.pcfg)
+$(obj)$(patsubst "%",%,$(CONFIG_IMX_CONFIG))tmp: %.pcfgtmp : %.pcfg
+               $(CC) -E -x c $< -I./include -o $@
+
+$(obj)u-boot.imx: %.imx : %.bin $(obj)$(patsubst

"%",%,$(CONFIG_IMX_CONFIG))tmp
+else
+$(obj)u-boot.imx: %.imx : %.bin $(patsubst "%",%,$(CONFIG_IMX_CONFIG)) +endif
+
+$(obj)u-boot.imx:

+               $(obj)tools/mkimage -n  $(filter-out %.bin,$^) -T imximage \
                 -e $(CONFIG_SYS_TEXT_BASE) -d $< $@

$(obj)u-boot.kwb: $(obj)u-boot.bin
@@ -794,7 +803,8 @@ clean:

         @rm -f $(TIMESTAMP_FILE) $(VERSION_FILE)
         @find $(OBJTREE) -type f \
                 \( -name 'core' -o -name '*.bak' -o -name '*~' -o -name 
'*.su' \
-               -o -name '*.o'  -o -name '*.a' -o -name '*.exe' \) -print \
+               -o -name '*.o'  -o -name '*.a' -o -name '*.exe' \
+               -o -name '*.pcfgtmp' \) -print \

| xargs rm -f

# Removes everything not needed for testing u-boot

(quoted diff) +0 -0

b/board/freescale/imx/ddr/mx6q_4x_mt41j128.pcfg similarity index 65%
rename from board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg rename to board/freescale/imx/ddr/mx6q_4x_mt41j128.pcfg

boards.cfg +0 -0

index e9e073e..677beac 100644
@@ -232,8 +232,8 @@ ima3-mx53                    arm armv7

ima3-mx53 esg
vision2 arm armv7 vision2
ttcontrol mx5 vision2:IMX_CONFIG=board/ttcontrol/vision2/imx
image_hynix.cfg
mx6qarm2 arm armv7 mx6qarm2
freescale mx6 mx6qarm2:IMX_CONFIG=board/freescale/mx6qarm2/i
mximage.cfg
mx6qsabreauto arm armv7 mx6qsabreauto
freescale mx6 mx6qsabreauto:IMX_CONFIG=board/freescale/mx6qs
abreauto/imximage.cfg
-mx6qsabrelite arm armv7 mx6qsabrelite
freescale mx6 mx6qsabrelite:IMX_CONFIG=board/freescale/imx/d
dr/mx6q_4x_mt41j128.cfg
-mx6qsabresd arm armv7 mx6qsabresd
freescale mx6 mx6qsabresd:IMX_CONFIG=board/freescale/imx/ddr
/mx6q_4x_mt41j128.cfg
+mx6qsabrelite arm armv7 mx6qsabrelite
freescale mx6 mx6qsabrelite:IMX_CONFIG=board/freescale/imx/d
dr/mx6q_4x_mt41j128.pcfg
+mx6qsabresd arm armv7 mx6qsabresd
freescale mx6 mx6qsabresd:IMX_CONFIG=board/freescale/imx/ddr
/mx6q_4x_mt41j128.pcfg
cm_t35 arm armv7 cm_t35
- omap3
omap3_overo arm armv7 overo
- omap3
omap3_pandora arm armv7 pandora
- omap3
--
1.7.9.5

Stefano Babic

2012-10-11 11:11 UTC #150 lore raw

PATCH v3 17/32 imximage.cfg: run files through C preprocessor

Am 10/10/2012 04:03, schrieb Troy Kisky:

Quoted 114 lines · Stefano Babic

Quoted 43 lines · Troy Kisky
Quoted 5 lines
The '#' used as comments in the files cause the preprocessor trouble, so change to /* */.
Signed-off-by Troy Kisky <[email protected]>
---
Hi Troy,
Quoted 7 lines
  Makefile                                     |    3 +-
  board/esg/ima3-mx53/imximage.cfg             |  120 ++++++-----
  board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg |   90 ++++----
  board/freescale/mx25pdk/imximage.cfg         |   77 +++----
  board/freescale/mx51evk/imximage.cfg         |  114 +++++-----
  board/freescale/mx53ard/imximage_dd3.cfg     |   83 ++++----
  board/freescale/mx53evk/imximage.cfg         |   86 ++++----
Quoted 9 lines
  board/freescale/mx53loco/imximage.cfg        |   83 ++++----
  board/freescale/mx53smd/imximage.cfg         |   83 ++++----
  board/freescale/mx6qarm2/imximage.cfg        |   88 ++++----
  board/genesi/mx51_efikamx/imximage_mx.cfg    |  132 ++++++------
  board/genesi/mx51_efikamx/imximage_sb.cfg    |  126 +++++------
  board/ttcontrol/vision2/imximage_hynix.cfg   |  295
++++++++++++++------------
  13 files changed, 727 insertions(+), 653 deletions(-)
I see the C preprocessor as an optional feature, instead of a rule everybody must follow.
Quoted 10 lines
Makefile +1 -1
index a40d4cc..64ff1b8 100644
@@ -431,7 +431,8 @@ $(obj)u-boot.img:    $(obj)u-boot.bin
          -d $< $@
    $(obj)u-boot.imx:       $(obj)u-boot.bin
-        $(obj)tools/mkimage -n  $(CONFIG_IMX_CONFIG) -T imximage \
+        $(CC) -E -x c $(CONFIG_IMX_CONFIG) -I./include -o
$(obj)imxcfg.imx
Quoted 2 lines
+        $(obj)tools/mkimage -n  $(obj)imxcfg.imx -T imximage \
          -e $(CONFIG_SYS_TEXT_BASE) -d $< $@
In fact, adding this rule here requires that each board configuration must be changed. And for all of them, running the preprocessor is unnnecessary.
Quoted 6 lines
What about to add this rule only to the Makefile of the boards that require preprocessing ?
Best regards,
Stefano Babic
How about this to do the job....
Subject: [PATCH 17/32] boards.cfg: run mx6q_4x_mt41j128.pcfg through C
preprocessor
The '#' used as comments in the cfg file cause the preprocessor trouble, so change to /* */. Also, rename mx6q_4x_mt41j128.cfg to mx6q_4x_mt41j128.pcfg.
Files with extension of .pcfg are run through the preprocessor before being given to mkimage.
Signed-off-by Troy Kisky <[email protected]>
---
v4: Don't run every file through preprocessor, only .pcfg files
---
 .gitignore                                         |    1 +
 Makefile                                           |   16 +++-
 ...{mx6q_4x_mt41j128.cfg => mx6q_4x_mt41j128.pcfg} |   90
++++++++++----------
 boards.cfg                                         |    4 +-
 4 files changed, 63 insertions(+), 48 deletions(-)
 rename board/freescale/imx/ddr/{mx6q_4x_mt41j128.cfg =>
mx6q_4x_mt41j128.pcfg} (65%)
.gitignore +1 -0
index d91e91b..e5273bd 100644
@@ -15,6 +15,7 @@
 *.swp
 *.patch
 *.bin
+*.pcfgtmp
 
 # Build tree
 /build-*
Makefile +5 -2
index a40d4cc..99666b9 100644
@@ -430,8 +430,17 @@ $(obj)u-boot.img:  $(obj)u-boot.bin
                        sed -e 's/"[     ]*$$/ for $(BOARD) board"/') \
                -d $< $@
 
-$(obj)u-boot.imx:       $(obj)u-boot.bin
-               $(obj)tools/mkimage -n  $(CONFIG_IMX_CONFIG) -T imximage \
+ifeq ($(suffix $(patsubst "%",%,$(CONFIG_IMX_CONFIG))),.pcfg)
+$(obj)$(patsubst "%",%,$(CONFIG_IMX_CONFIG))tmp: %.pcfgtmp : %.pcfg
+               $(CC) -E -x c $< -I./include -o $@
+
+$(obj)u-boot.imx: %.imx : %.bin $(obj)$(patsubst
"%",%,$(CONFIG_IMX_CONFIG))tmp
Makefile +6 -0
+else
+$(obj)u-boot.imx: %.imx : %.bin $(patsubst "%",%,$(CONFIG_IMX_CONFIG))
+endif
+
+$(obj)u-boot.imx:
+               $(obj)tools/mkimage -n  $(filter-out %.bin,$^) -T

Quoted 3 lines

imximage \
                -e $(CONFIG_SYS_TEXT_BASE) -d $< $@

Does it work something more direct (I have not tested, really...) ?

In board Makefile, for example board/freescale/mx6qsabrelite, a rule for the imximage file:

$(CONFIG_IMX_CONFIG): <your base file, mx6q_4x_mt41j128.cfg maybe>

	$(CC) -E -x c $< -I./include -o $@

And let unchanged in the main Makefile. So CONFIG_IMX_CONFIG is produced and you do not need to change logic in the main Makefile.

Regards,
Stefano

Signature · 5 lines

=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: [email protected]
=====================================================================

Troy Kisky

author

2012-10-11 20:33 UTC #151 lore raw

PATCH v3 17/32 imximage.cfg: run files through C preprocessor

Quoted 5 lines · Stefano Babic

Does it work something more direct (I have not tested, really...) ?
In board Makefile, for example board/freescale/mx6qsabrelite, a rule for the imximage file:

Quoted 9 lines

$(CONFIG_IMX_CONFIG): <your base file, mx6q_4x_mt41j128.cfg maybe>
	$(CC) -E -x c $< -I./include -o $@
And let unchanged in the main Makefile. So CONFIG_IMX_CONFIG is produced and you do not need to change logic in the main Makefile.
Regards,
Stefano

The advantages I see of changing the main Makefile are
1. Easy for other boards to use the preprocessor. You merely need to change the file extension to pcfg.

2. Easy to clean the temporary generated file. The main Makefile deletes files with .pcfgtmp extension.

3. The file referred to by boards.cfg actually exists before the build starts.

4. The temporary file can be placed in an out-of-tree directory for make -O builds

Using the file extension to determine whether to use the preprocessor is also
what gcc uses to preprocess ".S" files while skipping this for ".s" files.

I believe that at least other mx6 boards will quickly change to using the preprocessor
as well to add support for solo/duallite, so total line count should eventually be
less with changes to the main makefile.

Having said that, I really have no problem going your route, I just don't prefer it.
Let me know.

Thanks
Troy

stefano babic

2012-10-11 22:27 UTC #152 lore raw

PATCH v3 17/32 imximage.cfg: run files through C preprocessor

Am 11/10/2012 22:33, schrieb Troy Kisky:

Quoted 12 lines · Stefano Babic

Quoted 11 lines
Does it work something more direct (I have not tested, really...) ?
In board Makefile, for example board/freescale/mx6qsabrelite, a rule for the imximage file:
$(CONFIG_IMX_CONFIG): <your base file, mx6q_4x_mt41j128.cfg maybe>
    $(CC) -E -x c $< -I./include -o $@
And let unchanged in the main Makefile. So CONFIG_IMX_CONFIG is produced and you do not need to change logic in the main Makefile.

Quoted 7 lines

Quoted 3 lines
Regards,
Stefano
The advantages I see of changing the main Makefile are
1. Easy for other boards to use the preprocessor. You merely need to change the file extension to pcfg.

I set Tom in CC, because changing the main Makefile is more related to the whole project, and not only for the i.MX.

One reason to move into the board directory is that there was a decision to move rules related to only one arch or SOC where they belong to, that is in the corresponding arch/ or board/ directory.

Quoted 6 lines

2. Easy to clean the temporary generated file. The main Makefile deletes files with .pcfgtmp extension.
3. The file referred to by boards.cfg actually exists before the build starts.

This is true, but I do not understand which is the advantage. A lot of files are generated, also .c or .S files. If it exists or not, it does not matter.

Quoted 8 lines

4. The temporary file can be placed in an out-of-tree directory for make -O builds
Using the file extension to determine whether to use the preprocessor is also
what gcc uses to preprocess ".S" files while skipping this for ".s" files.

Quoted 5 lines

I believe that at least other mx6 boards will quickly change to using the preprocessor
as well to add support for solo/duallite, so total line count should eventually be
less with changes to the main makefile.

Ok, but if this true, the rule should be moved to the mx6 directory, and should not be valid for other i.MX that do not need it.

Quoted 3 lines

Having said that, I really have no problem going your route, I just don't prefer it.
Let me know.

Let's wait to know Tom's opinion.

Regards,
Stefano

Signature · 5 lines

=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: office at denx.de
=====================================================================

Tom Rini

2012-10-11 23:15 UTC #153 lore raw

PATCH v3 17/32 imximage.cfg: run files through C preprocessor

On Fri, Oct 12, 2012 at 12:27:09AM +0200, stefano babic wrote:

[snip]

Quoted 3 lines

One reason to move into the board directory is that there was a decision to move rules related to only one arch or SOC where they belong to, that is in the corresponding arch/ or board/ directory.

I'll admit that maybe my make-fu is off, but that idea doesn't work, at least for SPL. So I'd really like someone to make that work first.

Quoted 18 lines

Quoted 5 lines
2. Easy to clean the temporary generated file. The main Makefile deletes files with .pcfgtmp extension.
3. The file referred to by boards.cfg actually exists before the build starts.
This is true, but I do not understand which is the advantage. A lot of files are generated, also .c or .S files. If it exists or not, it does not matter.
Quoted 8 lines
4. The temporary file can be placed in an out-of-tree directory for make -O builds
Using the file extension to determine whether to use the preprocessor is also
what gcc uses to preprocess ".S" files while skipping this for ".s" files.

Quoted 8 lines

Quoted 5 lines
I believe that at least other mx6 boards will quickly change to using the preprocessor
as well to add support for solo/duallite, so total line count should eventually be
less with changes to the main makefile.
Ok, but if this true, the rule should be moved to the mx6 directory, and should not be valid for other i.MX that do not need it.

Introducing slight differences to the image generation rules per family generation when we could just have one rule that works fine for all generations is one worry I have about the notion of moving things out of a top level Makefile and putting them elsewhere.

Quoted 5 lines

Quoted 3 lines
Having said that, I really have no problem going your route, I just don't prefer it.
Let me know.
Let's wait to know Tom's opinion.

How about this, if we convert the existing cfg files to '@' comments and use the LDSCRIPT style preprocessor rule instead of another one? I assume there's improvements that could be done to the mx5 ones if we preprocessed them. Or no? I'm looking for opinions here myself still..

Signature · 8 lines

Tom
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Albert ARIBAUD

2012-10-13 10:11 UTC #154 lore raw

[U-Boot] File placement in Soc / board dirs and make issues (was: [PATCH V3 17/32] imximage.cfg: run files through C preprocessor)

Hi Tom,

Quoted 9 lines · Tom Rini

On Fri, Oct 12, 2012 at 12:27:09AM +0200, stefano babic wrote:
[snip]
Quoted 3 lines
One reason to move into the board directory is that there was a decision to move rules related to only one arch or SOC where they belong to, that is in the corresponding arch/ or board/ directory.
I'll admit that maybe my make-fu is off, but that idea doesn't work, at least for SPL. So I'd really like someone to make that work first.

Tom, can you be more specific than 'it doesn't work'? :)

Seriously, though, I'm interested in understand what the make issue is there, because I am indeed a proponent of putting files where they belong to, so if help is needed there, I would try to.

Amicalement,

Signature · 1 line

Albert.

Tom Rini

2012-10-13 15:17 UTC #155 lore raw

[U-Boot] File placement in Soc / board dirs and make issues (was: [PATCH V3 17/32] imximage.cfg: run files through C preprocessor)

Quoted 11 lines · Albert ARIBAUD

Hi Tom,
Quoted 7 lines · Tom Rini
On Fri, Oct 12, 2012 at 12:27:09AM +0200, stefano babic wrote:
[snip]
Quoted 3 lines
One reason to move into the board directory is that there was a decision to move rules related to only one arch or SOC where they belong to, that is in the corresponding arch/ or board/ directory.

Quoted 8 lines

Quoted 2 lines
I'll admit that maybe my make-fu is off, but that idea doesn't work, at least for SPL. So I'd really like someone to make that work first.
Tom, can you be more specific than 'it doesn't work'? :)
Seriously, though, I'm interested in understand what the make issue is there, because I am indeed a proponent of putting files where they belong to, so if help is needed there, I would try to.

I have had no luck moving things like the 'MLO' rule from spl/Makefile to anywhere else. Same with the 'checkthumb' rule in the top-level Makefile.

Signature · 1 line

Tom

Albert ARIBAUD

2012-10-14 08:37 UTC #156 lore raw

[U-Boot] File placement in Soc / board dirs and make issues

Hi Tom,

(seems like gmail does not honor the rule that replies should drop the "(was: xxxxx)" part in an e-mail subject; but hey, neither does Claws apparently. Sigh.)

Quoted 18 lines · Tom Rini

Quoted 16 lines · Albert ARIBAUD
Hi Tom,
Quoted 9 lines · Tom Rini
On Fri, Oct 12, 2012 at 12:27:09AM +0200, stefano babic wrote:
[snip]
Quoted 3 lines
One reason to move into the board directory is that there was a decision to move rules related to only one arch or SOC where they belong to, that is in the corresponding arch/ or board/ directory.
I'll admit that maybe my make-fu is off, but that idea doesn't work, at least for SPL. So I'd really like someone to make that work first.
Tom, can you be more specific than 'it doesn't work'? :)

Quoted 7 lines

Quoted 3 lines
Seriously, though, I'm interested in understand what the make issue is there, because I am indeed a proponent of putting files where they belong to, so if help is needed there, I would try to.
I have had no luck moving things like the 'MLO' rule from spl/Makefile to anywhere else. Same with the 'checkthumb' rule in the top-level Makefile.

Ok, now it is more precise :) but still not enough for me to efficiently try and analyze the issue.

Let's take the checkthumb rule. Where did you try to move it?

Amicalement,

Signature · 1 line

Albert.

Tom Rini

2012-10-15 01:24 UTC #157 lore raw

[U-Boot] File placement in Soc / board dirs and make issues

Quoted 30 lines · Albert ARIBAUD

Hi Tom,
(seems like gmail does not honor the rule that replies should drop the "(was: xxxxx)" part in an e-mail subject; but hey, neither does Claws apparently. Sigh.)
Quoted 22 lines · Tom Rini
Quoted 19 lines · Albert ARIBAUD
Hi Tom,
Quoted 9 lines · Tom Rini
On Fri, Oct 12, 2012 at 12:27:09AM +0200, stefano babic wrote:
[snip]
Quoted 3 lines
One reason to move into the board directory is that there was a decision to move rules related to only one arch or SOC where they belong to, that is in the corresponding arch/ or board/ directory.
I'll admit that maybe my make-fu is off, but that idea doesn't work, at least for SPL. So I'd really like someone to make that work first.
Tom, can you be more specific than 'it doesn't work'? :)
Seriously, though, I'm interested in understand what the make issue is there, because I am indeed a proponent of putting files where they belong to, so if help is needed there, I would try to.

Quoted 8 lines

Quoted 3 lines
I have had no luck moving things like the 'MLO' rule from spl/Makefile to anywhere else. Same with the 'checkthumb' rule in the top-level Makefile.
Ok, now it is more precise :) but still not enough for me to efficiently try and analyze the issue.
Let's take the checkthumb rule. Where did you try to move it?

I tried both arch/arm/config.mk arch/arm/Makefile and couldn't make either work.

Signature · 1 line

Tom

Albert ARIBAUD

2012-10-23 06:30 UTC #158 lore raw

[U-Boot] File placement in Soc / board dirs and make issues

Hi Tom,

Quoted 36 lines · Tom Rini

Quoted 34 lines · Albert ARIBAUD
Hi Tom,
(seems like gmail does not honor the rule that replies should drop the "(was: xxxxx)" part in an e-mail subject; but hey, neither does Claws apparently. Sigh.)
Quoted 25 lines · Tom Rini
Quoted 11 lines · Albert ARIBAUD
Hi Tom,
Quoted 7 lines · Tom Rini
On Fri, Oct 12, 2012 at 12:27:09AM +0200, stefano babic wrote:
[snip]
Quoted 3 lines
One reason to move into the board directory is that there was a decision to move rules related to only one arch or SOC where they belong to, that is in the corresponding arch/ or board/ directory.
Quoted 8 lines
Quoted 2 lines
I'll admit that maybe my make-fu is off, but that idea doesn't work, at least for SPL. So I'd really like someone to make that work first.
Tom, can you be more specific than 'it doesn't work'? :)
Seriously, though, I'm interested in understand what the make issue is there, because I am indeed a proponent of putting files where they belong to, so if help is needed there, I would try to.
I have had no luck moving things like the 'MLO' rule from spl/Makefile to anywhere else. Same with the 'checkthumb' rule in the top-level Makefile.

Quoted 6 lines

Quoted 4 lines
Ok, now it is more precise :) but still not enough for me to efficiently try and analyze the issue.
Let's take the checkthumb rule. Where did you try to move it?
I tried both arch/arm/config.mk arch/arm/Makefile and couldn't make either work.

Thanks. I'm adding this to my todo list, although not as an immediate priority.

Amicalement,

Signature · 1 line

Albert.

Troy Kisky

author

2012-10-17 20:32 UTC #159 lore raw

PATCH v3 17/32 imximage.cfg: run files through C preprocessor

In reply to Tom Rini

Quoted 17 lines · Tom Rini

On Fri, Oct 12, 2012 at 12:27:09AM +0200, stefano babic wrote:
[snip]
Quoted 3 lines
One reason to move into the board directory is that there was a decision to move rules related to only one arch or SOC where they belong to, that is in the corresponding arch/ or board/ directory.
I'll admit that maybe my make-fu is off, but that idea doesn't work, at least for SPL. So I'd really like someone to make that work first.
Quoted 8 lines
Quoted 5 lines
2. Easy to clean the temporary generated file. The main Makefile deletes files with .pcfgtmp extension.
3. The file referred to by boards.cfg actually exists before the build starts.
This is true, but I do not understand which is the advantage. A lot of files are generated, also .c or .S files. If it exists or not, it does not matter.

Consistency was my point here. Every other file in boards.cfg exists prior to build.

Quoted 19 lines

Quoted 7 lines
Quoted 7 lines
4. The temporary file can be placed in an out-of-tree directory for make -O builds
Using the file extension to determine whether to use the preprocessor is also
what gcc uses to preprocess ".S" files while skipping this for ".s" files.
Quoted 7 lines
Quoted 5 lines
I believe that at least other mx6 boards will quickly change to using the preprocessor
as well to add support for solo/duallite, so total line count should eventually be
less with changes to the main makefile.
Ok, but if this true, the rule should be moved to the mx6 directory, and should not be valid for other i.MX that do not need it.
Introducing slight differences to the image generation rules per family generation when we could just have one rule that works fine for all generations is one worry I have about the notion of moving things out of a top level Makefile and putting them elsewhere.

Quoted 9 lines

Quoted 4 lines
Quoted 3 lines
Having said that, I really have no problem going your route, I just don't prefer it.
Let me know.
Let's wait to know Tom's opinion.
How about this, if we convert the existing cfg files to '@' comments and use the LDSCRIPT style preprocessor rule instead of another one? I assume there's improvements that could be done to the mx5 ones if we preprocessed them. Or no? I'm looking for opinions here myself still..

I had previously converted all existing cfg files to /* */ comments. That style of
comment seems common for LDSCRIPTs as well. '@''s actually give me an error.

arm-eabi-ld:u-boot.lds:1: ignoring invalid character `@' in expression

I do believe mx5 files can benefit from preprocessing. I can see the advantage of
converting everything now. I also like flexibility of not forcing every cfg file to
change now. So, I am setting on the fence. If I have to take a position, I'd fall on the side of the smaller patch set of a gradual conversion, just because I
like smaller patches.

Troy

Tom Rini

2012-10-17 21:05 UTC #160 lore raw

PATCH v3 17/32 imximage.cfg: run files through C preprocessor

-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1

Quoted 54 lines · Troy Kisky

Quoted 19 lines · Tom Rini
On Fri, Oct 12, 2012 at 12:27:09AM +0200, stefano babic wrote:
[snip]
Quoted 4 lines
One reason to move into the board directory is that there was a decision to move rules related to only one arch or SOC where they belong to, that is in the corresponding arch/ or board/ directory.
I'll admit that maybe my make-fu is off, but that idea doesn't work, at least for SPL. So I'd really like someone to make that work first.
Quoted 8 lines
Quoted 5 lines
2. Easy to clean the temporary generated file. The main Makefile deletes files with .pcfgtmp extension.
3. The file referred to by boards.cfg actually exists before the build starts.
This is true, but I do not understand which is the advantage. A lot of files are generated, also .c or .S files. If it exists or not, it does not matter.
Consistency was my point here. Every other file in boards.cfg exists prior to build.
Quoted 20 lines
Quoted 7 lines
Quoted 7 lines
4. The temporary file can be placed in an out-of-tree directory for make -O builds
Using the file extension to determine whether to use the preprocessor is also what gcc uses to preprocess ".S" files while skipping this for ".s" files.
Quoted 7 lines
Quoted 4 lines
I believe that at least other mx6 boards will quickly change to using the preprocessor as well to add support for solo/duallite, so total line count should eventually be less with changes to the main makefile.
Ok, but if this true, the rule should be moved to the mx6 directory, and should not be valid for other i.MX that do not need it.
Introducing slight differences to the image generation rules per family generation when we could just have one rule that works fine for all generations is one worry I have about the notion of moving things out of a top level Makefile and putting them elsewhere.
Quoted 9 lines
Quoted 3 lines
Quoted 2 lines
Having said that, I really have no problem going your route, I just don't prefer it. Let me know.
Let's wait to know Tom's opinion.
How about this, if we convert the existing cfg files to '@' comments and use the LDSCRIPT style preprocessor rule instead of another one? I assume there's improvements that could be done to the mx5 ones if we preprocessed them. Or no? I'm looking for opinions here myself still..

Quoted 6 lines

I had previously converted all existing cfg files to /* */ comments. That style of comment seems common for LDSCRIPTs as well. '@''s actually give me an error.
arm-eabi-ld:u-boot.lds:1: ignoring invalid character `@' in expression

Right, but in u-boot.lds.S it gets preprocessed away, at least I swear I changed and tested that. My thinking being it was a smaller diff delta. But my final point being I don't think we should start introducing artificial differences here just because older boards may not use it. That doing that leads to bit rot.

Quoted 6 lines

I do believe mx5 files can benefit from preprocessing. I can see the advantage of converting everything now. I also like flexibility of not forcing every cfg file to change now. So, I am setting on the fence. If I have to take a position, I'd fall on the side of the smaller patch set of a gradual conversion, just because I like smaller patches.

I'm on the other side only because "later" sometimes never happens. Doing it as a series of smaller patches, now might be fine too...

- --
Tom
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Troy Kisky

author

2012-10-17 21:38 UTC #161 lore raw

PATCH v3 17/32 imximage.cfg: run files through C preprocessor

Quoted 60 lines · Tom Rini

-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1
Quoted 56 lines · Troy Kisky
Quoted 19 lines · Tom Rini
On Fri, Oct 12, 2012 at 12:27:09AM +0200, stefano babic wrote:
[snip]
Quoted 4 lines
One reason to move into the board directory is that there was a decision to move rules related to only one arch or SOC where they belong to, that is in the corresponding arch/ or board/ directory.
I'll admit that maybe my make-fu is off, but that idea doesn't work, at least for SPL. So I'd really like someone to make that work first.
Quoted 8 lines
Quoted 5 lines
2. Easy to clean the temporary generated file. The main Makefile deletes files with .pcfgtmp extension.
3. The file referred to by boards.cfg actually exists before the build starts.
This is true, but I do not understand which is the advantage. A lot of files are generated, also .c or .S files. If it exists or not, it does not matter.
Consistency was my point here. Every other file in boards.cfg exists prior to build.
Quoted 20 lines
Quoted 7 lines
Quoted 7 lines
4. The temporary file can be placed in an out-of-tree directory for make -O builds
Using the file extension to determine whether to use the preprocessor is also what gcc uses to preprocess ".S" files while skipping this for ".s" files.
Quoted 7 lines
Quoted 4 lines
I believe that at least other mx6 boards will quickly change to using the preprocessor as well to add support for solo/duallite, so total line count should eventually be less with changes to the main makefile.
Ok, but if this true, the rule should be moved to the mx6 directory, and should not be valid for other i.MX that do not need it.
Introducing slight differences to the image generation rules per family generation when we could just have one rule that works fine for all generations is one worry I have about the notion of moving things out of a top level Makefile and putting them elsewhere.
Quoted 9 lines
Quoted 3 lines
Quoted 2 lines
Having said that, I really have no problem going your route, I just don't prefer it. Let me know.
Let's wait to know Tom's opinion.
How about this, if we convert the existing cfg files to '@' comments and use the LDSCRIPT style preprocessor rule instead of another one? I assume there's improvements that could be done to the mx5 ones if we preprocessed them. Or no? I'm looking for opinions here myself still..
I had previously converted all existing cfg files to /* */ comments. That style of comment seems common for LDSCRIPTs as well. '@''s actually give me an error.

Quoted 5 lines

Quoted 2 lines
arm-eabi-ld:u-boot.lds:1: ignoring invalid character `@' in expression
Right, but in u-boot.lds.S it gets preprocessed away, at least I swear I changed and tested that. My thinking being it was a smaller diff delta.

Good point. Is there some magic parameter to pass to gcc to strip @. My current
command line is expanded to

arm-eabi-gcc -E -x c board/freescale/imx/ddr/mx6q_4x_mt41j128.pcfg -g -Os
-fno-common -ffixed-r8 -msoft-float -D__KERNEL__
-DCONFIG_SYS_TEXT_BASE=0x17800000
-I/home/tkisky/u-boot-imx6/include -fno-builtin -ffreestanding -nostdinc
-isystem
/home/tkisky/myandroid/prebuilt/linux-x86/toolchain/arm-eabi-4.4.3/bin/../lib/gcc/arm-eabi/4.4.3/include -pipe
-DCONFIG_ARM -D__ARM__ -marm -mno-thumb-interwork -mabi=aapcs-linux
-march=armv7-a
-o board/freescale/imx/ddr/mx6q_4x_mt41j128.pcfgtmp

Alternatively, I could send a small patch to mkimage to ignore @ lines along with the currently
ignored # lines.

I grepped all lds files in u-boot, but could not find one that used @ as a comment indicator.
I don't know what/where u-boot.lds.S is.

Quoted 16 lines

But my final point being I don't think we should start
introducing artificial differences here just because older boards may not use it. That doing that leads to bit rot.
Quoted 6 lines
I do believe mx5 files can benefit from preprocessing. I can see the advantage of converting everything now. I also like flexibility of not forcing every cfg file to change now. So, I am setting on the fence. If I have to take a position, I'd fall on the side of the smaller patch set of a gradual conversion, just because I like smaller patches.
I'm on the other side only because "later" sometimes never happens. Doing it as a series of smaller patches, now might be fine too...
- --
Tom

Tom Rini

2012-10-17 22:29 UTC #162 lore raw

PATCH v3 17/32 imximage.cfg: run files through C preprocessor

Quoted 61 lines · Troy Kisky

Quoted 60 lines · Tom Rini
-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1
Quoted 56 lines · Troy Kisky
Quoted 19 lines · Tom Rini
On Fri, Oct 12, 2012 at 12:27:09AM +0200, stefano babic wrote:
[snip]
Quoted 4 lines
One reason to move into the board directory is that there was a decision to move rules related to only one arch or SOC where they belong to, that is in the corresponding arch/ or board/ directory.
I'll admit that maybe my make-fu is off, but that idea doesn't work, at least for SPL. So I'd really like someone to make that work first.
Quoted 8 lines
Quoted 5 lines
2. Easy to clean the temporary generated file. The main Makefile deletes files with .pcfgtmp extension.
3. The file referred to by boards.cfg actually exists before the build starts.
This is true, but I do not understand which is the advantage. A lot of files are generated, also .c or .S files. If it exists or not, it does not matter.
Consistency was my point here. Every other file in boards.cfg exists prior to build.
Quoted 20 lines
Quoted 7 lines
Quoted 7 lines
4. The temporary file can be placed in an out-of-tree directory for make -O builds
Using the file extension to determine whether to use the preprocessor is also what gcc uses to preprocess ".S" files while skipping this for ".s" files.
Quoted 7 lines
Quoted 4 lines
I believe that at least other mx6 boards will quickly change to using the preprocessor as well to add support for solo/duallite, so total line count should eventually be less with changes to the main makefile.
Ok, but if this true, the rule should be moved to the mx6 directory, and should not be valid for other i.MX that do not need it.
Introducing slight differences to the image generation rules per family generation when we could just have one rule that works fine for all generations is one worry I have about the notion of moving things out of a top level Makefile and putting them elsewhere.
Quoted 9 lines
Quoted 3 lines
Quoted 2 lines
Having said that, I really have no problem going your route, I just don't prefer it. Let me know.
Let's wait to know Tom's opinion.
How about this, if we convert the existing cfg files to '@' comments and use the LDSCRIPT style preprocessor rule instead of another one? I assume there's improvements that could be done to the mx5 ones if we preprocessed them. Or no? I'm looking for opinions here myself still..
I had previously converted all existing cfg files to /* */ comments. That style of comment seems common for LDSCRIPTs as well. '@''s actually give me an error.

Quoted 7 lines

Quoted 5 lines
Quoted 2 lines
arm-eabi-ld:u-boot.lds:1: ignoring invalid character `@' in expression
Right, but in u-boot.lds.S it gets preprocessed away, at least I swear I changed and tested that. My thinking being it was a smaller diff delta.
Good point. Is there some magic parameter to pass to gcc to strip @.

Lets just go with /* */ comments, everyone understands that.

Signature · 8 lines

Tom
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Troy Kisky

author

2012-10-04 01:47 UTC #163 lore raw

PATCH v3 18/32 mx6q_4x_mt41j128.cfg: use symbols instead of hardcoded constants

In reply to Troy Kisky

This allows us to generate DCD table data appropriate for MX6Q, MX6DL, or MX6Solo simply by defining CONFIG_MX6Q, CONFIG_MX6DL, or CONFIG_MX6S

Signed-off-by Troy Kisky <[email protected]>

---
 arch/arm/include/asm/arch-mx6/imx-mkimage.h  |  156 ++++++++++++++++
 board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg |  245 +++++++++++++-------------
 2 files changed, 280 insertions(+), 121 deletions(-)
 create mode 100644 arch/arm/include/asm/arch-mx6/imx-mkimage.h

arch/arm/include/asm/arch-mx6/imx-mkimage.h new file +156 -0

new file mode 100644
index 0000000..4abd3f1
@@ -0,0 +1,156 @@
+/*
+ * Copyright (C) 2012 Boundary Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+#ifndef __ASM_ARCH_IMX_MKIMAGE_H__
+#define __ASM_ARCH_IMX_MKIMAGE_H__
+
+#define IOMUXC_GPR4		0x020e0010
+#define IOMUXC_GPR6		0x020e0018
+#define IOMUXC_GPR7		0x020e001c
+
+/* mx6 duallite and solo have same offsets */
+
+#define IOM_DRAM_DQM0		MA(0x020e05ac, 0x020e0470, 0x0)
+#define IOM_DRAM_DQM1		MA(0x020e05b4, 0x020e0474, 0x0)
+#define IOM_DRAM_DQM2		MA(0x020e0528, 0x020e0478, 0x0)
+#define IOM_DRAM_DQM3		MA(0x020e0520, 0x020e047c, 0x0)
+#define IOM_DRAM_DQM4		MA(0x020e0514, 0x020e0480, 0x0)
+#define IOM_DRAM_DQM5		MA(0x020e0510, 0x020e0484, 0x0)
+#define IOM_DRAM_DQM6		MA(0x020e05bc, 0x020e0488, 0x0)
+#define IOM_DRAM_DQM7		MA(0x020e05c4, 0x020e048c, 0x0)
+
+#define IOM_DRAM_CAS		MA(0x020e056c, 0x020e0464, 0x0)
+#define IOM_DRAM_RAS		MA(0x020e0578, 0x020e0490, 0x0)
+#define IOM_DRAM_RESET		MA(0x020e057c, 0x020e0494, 0x0)
+#define IOM_DRAM_SDCLK_0	MA(0x020e0588, 0x020e04ac, 0x0)
+#define IOM_DRAM_SDCLK_1	MA(0x020e0594, 0x020e04b0, 0x0)
+#define IOM_DRAM_SDBA2		MA(0x020e058c, 0x020e04a0, 0x0)
+#define IOM_DRAM_SDCKE0		MA(0x020e0590, 0x020e04a4, 0x0)
+#define IOM_DRAM_SDCKE1		MA(0x020e0598, 0x020e04a8, 0x0)
+#define IOM_DRAM_SDODT0		MA(0x020e059c, 0x020e04b4, 0x0)
+#define IOM_DRAM_SDODT1		MA(0x020e05a0, 0x020e04b8, 0x0)
+
+#define IOM_DRAM_SDQS0		MA(0x020e05a8, 0x020e04bc, 0x0)
+#define IOM_DRAM_SDQS1		MA(0x020e05b0, 0x020e04c0, 0x0)
+#define IOM_DRAM_SDQS2		MA(0x020e0524, 0x020e04c4, 0x0)
+#define IOM_DRAM_SDQS3		MA(0x020e051c, 0x020e04c8, 0x0)
+#define IOM_DRAM_SDQS4		MA(0x020e0518, 0x020e04cc, 0x0)
+#define IOM_DRAM_SDQS5		MA(0x020e050c, 0x020e04d0, 0x0)
+#define IOM_DRAM_SDQS6		MA(0x020e05b8, 0x020e04d4, 0x0)
+#define IOM_DRAM_SDQS7		MA(0x020e05c0, 0x020e04d8, 0x0)
+
+#define IOM_GRP_B0DS		MA(0x020e0784, 0x020e0764, 0x0)
+#define IOM_GRP_B1DS		MA(0x020e0788, 0x020e0770, 0x0)
+#define IOM_GRP_B2DS		MA(0x020e0794, 0x020e0778, 0x0)
+#define IOM_GRP_B3DS		MA(0x020e079c, 0x020e077c, 0x0)
+#define IOM_GRP_B4DS		MA(0x020e07a0, 0x020e0780, 0x0)
+#define IOM_GRP_B5DS		MA(0x020e07a4, 0x020e0784, 0x0)
+#define IOM_GRP_B6DS		MA(0x020e07a8, 0x020e078c, 0x0)
+#define IOM_GRP_B7DS		MA(0x020e0748, 0x020e0748, 0x0)
+#define IOM_GRP_ADDDS		MA(0x020e074c, 0x020e074c, 0x0)
+#define IOM_DDRMODE_CTL		MA(0x020e0750, 0x020e0750, 0x0)
+#define IOM_GRP_DDRPKE		MA(0x020e0758, 0x020e0754, 0x0)
+#define IOM_GRP_DDRMODE		MA(0x020e0774, 0x020e0760, 0x0)
+#define IOM_GRP_CTLDS		MA(0x020e078c, 0x020e076c, 0x0)
+#define IOM_GRP_DDR_TYPE	MA(0x020e0798, 0x020e0774, 0x0)
+
+#define IRAM_FREE_START		0x00907000
+
+#define MMDC_P0_MDCTL		0x021b0000
+#define MMDC_P0_MDPDC		0x021b0004
+#define MMDC_P0_MDOTC		0x021b0008
+#define MMDC_P0_MDCFG0		0x021b000c
+#define MMDC_P0_MDCFG1		0x021b0010
+#define MMDC_P0_MDCFG2		0x021b0014
+#define MMDC_P0_MDMISC		0x021b0018
+#define MMDC_P0_MDSCR		0x021b001c
+#define MMDC_P0_MDREF		0x021b0020
+#define MMDC_P0_MDRWD		0x021b002c
+#define MMDC_P0_MDOR		0x021b0030
+#define MMDC_P0_MDASP		0x021b0040
+#define MMDC_P0_MAPSR		0x021b0404
+#define MMDC_P0_MPZQHWCTRL	0x021b0800
+#define MMDC_P0_MPWLDECTRL0	0x021b080c
+#define MMDC_P0_MPWLDECTRL1	0x021b0810
+#define MMDC_P0_MPODTCTRL	0x021b0818
+#define MMDC_P0_MPRDDQBY0DL	0x021b081c
+#define MMDC_P0_MPRDDQBY1DL	0x021b0820
+#define MMDC_P0_MPRDDQBY2DL	0x021b0824
+#define MMDC_P0_MPRDDQBY3DL	0x021b0828
+#define MMDC_P0_MPDGCTRL0	0x021b083c
+#define MMDC_P0_MPDGCTRL1	0x021b0840
+#define MMDC_P0_MPRDDLCTL	0x021b0848
+#define MMDC_P0_MPWRDLCTL	0x021b0850
+#define MMDC_P0_MPMUR0		0x021b08b8
+
+#define MMDC_P1_MDCTL		0x021b4000
+#define MMDC_P1_MDPDC		0x021b4004
+#define MMDC_P1_MDOTC		0x021b4008
+#define MMDC_P1_MDCFG0		0x021b400c
+#define MMDC_P1_MDCFG1		0x021b4010
+#define MMDC_P1_MDCFG2		0x021b4014
+#define MMDC_P1_MDMISC		0x021b4018
+#define MMDC_P1_MDSCR		0x021b401c
+#define MMDC_P1_MDREF		0x021b4020
+#define MMDC_P1_MDRWD		0x021b402c
+#define MMDC_P1_MDOR		0x021b4030
+#define MMDC_P1_MDASP		0x021b4040
+#define MMDC_P1_MAPSR		0x021b4404
+#define MMDC_P1_MPZQHWCTRL	0x021b4800
+#define MMDC_P1_MPWLDECTRL0	0x021b480c
+#define MMDC_P1_MPWLDECTRL1	0x021b4810
+#define MMDC_P1_MPODTCTRL	0x021b4818
+#define MMDC_P1_MPRDDQBY0DL	0x021b481c
+#define MMDC_P1_MPRDDQBY1DL	0x021b4820
+#define MMDC_P1_MPRDDQBY2DL	0x021b4824
+#define MMDC_P1_MPRDDQBY3DL	0x021b4828
+#define MMDC_P1_MPDGCTRL0	0x021b483c
+#define MMDC_P1_MPDGCTRL1	0x021b4840
+#define MMDC_P1_MPRDDLCTL	0x021b4848
+#define MMDC_P1_MPWRDLCTL	0x021b4850
+#define MMDC_P1_MPMUR0		0x021b48b8
+
+#define CCM_CCGR0		0x020C4068
+#define CCM_CCGR1		0x020C406c
+#define CCM_CCGR2		0x020C4070
+#define CCM_CCGR3		0x020C4074
+#define CCM_CCGR4		0x020C4078
+#define CCM_CCGR5		0x020C407c
+#define CCM_CCGR6		0x020C4080
+
+
+#define WRITE_ENTRY1(addr, q)		DATA 4, addr, q
+#ifdef CONFIG_MX6Q
+#define MA(mx6q, mx6dl_solo, mx6sololite)	mx6q
+#define WRITE_ENTRY2(addr, q, dl)		WRITE_ENTRY1(addr, q)
+#define WRITE_ENTRY3(addr, q, dl, solo)		WRITE_ENTRY1(addr, q)
+#define WRITE_ENTRY4(addr, q, dl, solo, sl)	WRITE_ENTRY1(addr, q)
+#else
+
+#define WRITE_ENTRY2(addr, q, dl)		WRITE_ENTRY1(addr, dl)
+#ifdef CONFIG_MX6DL
+#define MA(mx6q, mx6dl_solo, mx6sololite)	mx6dl_solo
+#define WRITE_ENTRY3(addr, q, dl, solo)		WRITE_ENTRY1(addr, dl)
+#define WRITE_ENTRY4(addr, q, dl, solo, sl)	WRITE_ENTRY1(addr, dl)
+#else
+
+#define WRITE_ENTRY3(addr, q, dl, solo)		WRITE_ENTRY1(addr, solo)
+#ifdef CONFIG_MX6S
+#define MA(mx6q, mx6dl_solo, mx6sololite)	mx6dl_solo
+#define WRITE_ENTRY4(addr, q, dl, solo, sl)	WRITE_ENTRY1(addr, solo)
+#else
+
+#define WRITE_ENTRY4(addr, q, dl, solo, sl)	WRITE_ENTRY1(addr, sl)
+#ifdef CONFIG_MX6SL
+#define MA(mx6q, mx6dl_solo, mx6sololite)	mx6sololite
+#else
+
+#error "Please select cpu"
+#endif	/* CONFIG_MX6SL */
+#endif	/* CONFIG_MX6S */
+#endif	/* CONFIG_MX6DL */
+#endif	/* CONFIG_MX6Q */
+
+#endif	/*__ASM_ARCH_IMX_MKIMAGE_H__ */

board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg +124 ~~-121~~

259 lines not on this page · raw message

Signature · 1 line

1.7.9.5

Troy Kisky

author

2012-10-04 01:47 UTC #164 lore raw

PATCH v3 19/32 mx6q_4x_mt41j128.cfg: add comments

In reply to Troy Kisky

Signed-off-by Troy Kisky <[email protected]>

---
 board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg |   55 ++++++++++++++++++++++----
 1 file changed, 47 insertions(+), 8 deletions(-)

board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg +47 -8

index 84823f8..b859e2f 100644
@@ -53,7 +53,6 @@ WRITE_ENTRY1(IOM_DRAM_SDQS0, 0x00000030)
 WRITE_ENTRY1(IOM_DRAM_SDQS1, 0x00000030)
 WRITE_ENTRY1(IOM_DRAM_SDQS2, 0x00000030)
 WRITE_ENTRY1(IOM_DRAM_SDQS3, 0x00000030)
-
 WRITE_ENTRY1(IOM_DRAM_SDQS4, 0x00000030)
 WRITE_ENTRY1(IOM_DRAM_SDQS5, 0x00000030)
 WRITE_ENTRY1(IOM_DRAM_SDQS6, 0x00000030)

@@ -63,7 +62,6 @@ WRITE_ENTRY1(IOM_DRAM_DQM0, 0x00020030)
 WRITE_ENTRY1(IOM_DRAM_DQM1, 0x00020030)
 WRITE_ENTRY1(IOM_DRAM_DQM2, 0x00020030)
 WRITE_ENTRY1(IOM_DRAM_DQM3, 0x00020030)
-
 WRITE_ENTRY1(IOM_DRAM_DQM4, 0x00020030)
 WRITE_ENTRY1(IOM_DRAM_DQM5, 0x00020030)
 WRITE_ENTRY1(IOM_DRAM_DQM6, 0x00020030)

@@ -81,65 +79,105 @@ WRITE_ENTRY1(IOM_DRAM_SDBA2, 0x00000000)
 
 WRITE_ENTRY1(IOM_DRAM_SDODT0, 0x00003030)
 WRITE_ENTRY1(IOM_DRAM_SDODT1, 0x00003030)
+
 WRITE_ENTRY1(IOM_GRP_B0DS, 0x00000030)
 WRITE_ENTRY1(IOM_GRP_B1DS, 0x00000030)
-
 WRITE_ENTRY1(IOM_GRP_B2DS, 0x00000030)
 WRITE_ENTRY1(IOM_GRP_B3DS, 0x00000030)
 WRITE_ENTRY1(IOM_GRP_B4DS, 0x00000030)
 WRITE_ENTRY1(IOM_GRP_B5DS, 0x00000030)
-
 WRITE_ENTRY1(IOM_GRP_B6DS, 0x00000030)
 WRITE_ENTRY1(IOM_GRP_B7DS, 0x00000030)
+
 WRITE_ENTRY1(IOM_GRP_ADDDS, 0x00000030)
+/* (differential input) */
 WRITE_ENTRY1(IOM_DDRMODE_CTL, 0x00020000)
-
+/* disable ddr pullups */
 WRITE_ENTRY1(IOM_GRP_DDRPKE, 0x00000000)
+/* (differential input) */
 WRITE_ENTRY1(IOM_GRP_DDRMODE, 0x00020000)
+/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
 WRITE_ENTRY1(IOM_GRP_CTLDS, 0x00000030)
 WRITE_ENTRY1(IOM_GRP_DDR_TYPE, 0x000C0000)
 
+/* Read data DQ Byte0-3 delay */
 WRITE_ENTRY1(MMDC_P0_MPRDDQBY0DL, 0x33333333)
 WRITE_ENTRY1(MMDC_P0_MPRDDQBY1DL, 0x33333333)
 WRITE_ENTRY1(MMDC_P0_MPRDDQBY2DL, 0x33333333)
 WRITE_ENTRY1(MMDC_P0_MPRDDQBY3DL, 0x33333333)
-
 WRITE_ENTRY1(MMDC_P1_MPRDDQBY0DL, 0x33333333)
 WRITE_ENTRY1(MMDC_P1_MPRDDQBY1DL, 0x33333333)
 WRITE_ENTRY1(MMDC_P1_MPRDDQBY2DL, 0x33333333)
 WRITE_ENTRY1(MMDC_P1_MPRDDQBY3DL, 0x33333333)
 
+/*
+ * MDMISC, mirroring, interleaved (row/bank/col)
+ */
 WRITE_ENTRY1(MMDC_P0_MDMISC, 0x00081740)
 
+/*
+ * MDSCR, con_req
+ */
 WRITE_ENTRY1(MMDC_P0_MDSCR, 0x00008000)
+/*
+ * MDCFG0, tRFC=0x56 clocks, tXS=0x5b clocks
+ * tXP=4 clocks, tXPDLL=13 clocks
+ * tFAW=24 clocks, cas=8 cycles
+ */
 WRITE_ENTRY1(MMDC_P0_MDCFG0, 0x555A7975)
+/*
+ * MDCFG1, tRDC=8, tRP=8, tRC=27,tRAS=20,tRPA=tRP+1,tWR=8
+ * tMRD=4, tCWL=6
+ */
 WRITE_ENTRY1(MMDC_P0_MDCFG1, 0xFF538E64)
+/*
+ * MDCFG2,tDLLK=512,tRTP=4,tWTR=4,tRRD=4
+ */
 WRITE_ENTRY1(MMDC_P0_MDCFG2, 0x01FF00DB)
 WRITE_ENTRY1(MMDC_P0_MDRWD, 0x000026D2)
 
 WRITE_ENTRY1(MMDC_P0_MDOR, 0x005B0E21)
 WRITE_ENTRY1(MMDC_P0_MDOTC, 0x09444040)
 WRITE_ENTRY1(MMDC_P0_MDPDC, 0x00025576)
+
+/*
+ * Mx6Q - 64 bit wide ddr
+ * last address is  (1<<28 (base) + 1<<30  - 1)  / (1<<25) =
+ * 	1<<3 + 1<<5 - 1 = 8 + 0x20 -1 = 0x27
+ */
+/* MDASP, CS0_END */
 WRITE_ENTRY1(MMDC_P0_MDASP, 0x00000027)
+/*
+ * MDCTL, CS0 enable, CS1 disabled, row=14, col=10, burst=8, width=64/32bit
+ * mx6q   : row+col+bank+width=14+10+3+3=30 = 1G
+ */
 WRITE_ENTRY1(MMDC_P0_MDCTL, 0x831A0000)
 
+/* MDSCR, con_req, LOAD MR2, CS0, A3,A10 set (CAS Write=6), RZQ/2 */
 WRITE_ENTRY1(MMDC_P0_MDSCR, 0x04088032)
 WRITE_ENTRY1(MMDC_P0_MDSCR, 0x0408803A)
+/* LOAD MR3, CS0 */
 WRITE_ENTRY1(MMDC_P0_MDSCR, 0x00008033)
 WRITE_ENTRY1(MMDC_P0_MDSCR, 0x0000803B)
+/* LOAD MR1, CS0, A1,A6 set Rtt=RZQ/2, ODI=RZQ/7 */
 WRITE_ENTRY1(MMDC_P0_MDSCR, 0x00428031)
 WRITE_ENTRY1(MMDC_P0_MDSCR, 0x00428039)
+/* LOAD MR0, CS0, A6,A8,A11 set CAS=8, WR=8, DLL reset */
 WRITE_ENTRY1(MMDC_P0_MDSCR, 0x09408030)
 WRITE_ENTRY1(MMDC_P0_MDSCR, 0x09408038)
 
+/* ZQ calibrate, CS0 */
 WRITE_ENTRY1(MMDC_P0_MDSCR, 0x04008040)
 WRITE_ENTRY1(MMDC_P0_MDSCR, 0x04008048)
 WRITE_ENTRY1(MMDC_P0_MPZQHWCTRL, 0xA1380003)
 WRITE_ENTRY1(MMDC_P1_MPZQHWCTRL, 0xA1380003)
+
+/* MDREF,  32KHz refresh, 4 refeshes each */
 WRITE_ENTRY1(MMDC_P0_MDREF, 0x00005800)
 WRITE_ENTRY1(MMDC_P0_MPODTCTRL, 0x00022227)
 WRITE_ENTRY1(MMDC_P1_MPODTCTRL, 0x00022227)
 
+/* MPDGCTRL0/1 DQS GATE*/
 WRITE_ENTRY1(MMDC_P0_MPDGCTRL0, 0x434B0350)
 WRITE_ENTRY1(MMDC_P0_MPDGCTRL1, 0x034C0359)
 WRITE_ENTRY1(MMDC_P1_MPDGCTRL0, 0x434B0350)

@@ -148,17 +186,18 @@ WRITE_ENTRY1(MMDC_P0_MPRDDLCTL, 0x4436383B)
 WRITE_ENTRY1(MMDC_P1_MPRDDLCTL, 0x39393341)
 WRITE_ENTRY1(MMDC_P0_MPWRDLCTL, 0x35373933)
 WRITE_ENTRY1(MMDC_P1_MPWRDLCTL, 0x48254A36)
-
 WRITE_ENTRY1(MMDC_P0_MPWLDECTRL0, 0x001F001F)
 WRITE_ENTRY1(MMDC_P0_MPWLDECTRL1, 0x001F001F)
-
 WRITE_ENTRY1(MMDC_P1_MPWLDECTRL0, 0x00440044)
 WRITE_ENTRY1(MMDC_P1_MPWLDECTRL1, 0x00440044)
 
+/* MPMUR0 - Complete calibration by forced measurement */
 WRITE_ENTRY1(MMDC_P0_MPMUR0, 0x00000800)
 WRITE_ENTRY1(MMDC_P1_MPMUR0, 0x00000800)
 
+/* MDSCR, enable ddr */
 WRITE_ENTRY1(MMDC_P0_MDSCR, 0x00000000)
+/* MAPSR, 1024 cycles idle before self-refresh */
 WRITE_ENTRY1(MMDC_P0_MAPSR, 0x00011006)
 
 /* set the default clock gate to save power */

Signature · 1 line

1.7.9.5

Troy Kisky

author

2012-10-04 01:47 UTC #165 lore raw

PATCH v3 20/32 mx6q_4x_mt41j128.cfg: use ddr3 mode for reset

In reply to Troy Kisky

Bits 19-18 of IOMUXC_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET should be 3 for DDR3 mode. The current value of 0 is reserved in TRM.

Signed-off-by Troy Kisky <[email protected]>

---
 board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg +1 -1

index b859e2f..9c622c8 100644
@@ -72,7 +72,7 @@ WRITE_ENTRY1(IOM_DRAM_RAS, 0x00020030)
 WRITE_ENTRY1(IOM_DRAM_SDCLK_0, 0x00020030)
 WRITE_ENTRY1(IOM_DRAM_SDCLK_1, 0x00020030)
 
-WRITE_ENTRY1(IOM_DRAM_RESET, 0x00020030)
+WRITE_ENTRY1(IOM_DRAM_RESET, 0x000e0030)
 WRITE_ENTRY1(IOM_DRAM_SDCKE0, 0x00003000)
 WRITE_ENTRY1(IOM_DRAM_SDCKE1, 0x00003000)
 WRITE_ENTRY1(IOM_DRAM_SDBA2, 0x00000000)

Signature · 1 line

1.7.9.5

Troy Kisky

author

2012-10-04 01:47 UTC #166 lore raw

PATCH v3 21/32 mx6q_4x_mt41j128.cfg: skip initiailizing non-existent memory

In reply to Troy Kisky

Sabrelite does not have memory associated with CS1

Signed-off-by Troy Kisky <[email protected]>

---
 board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg |    5 -----
 1 file changed, 5 deletions(-)

board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg +0 -5

index 9c622c8..2d03ff7 100644
@@ -155,20 +155,15 @@ WRITE_ENTRY1(MMDC_P0_MDCTL, 0x831A0000)
 
 /* MDSCR, con_req, LOAD MR2, CS0, A3,A10 set (CAS Write=6), RZQ/2 */
 WRITE_ENTRY1(MMDC_P0_MDSCR, 0x04088032)
-WRITE_ENTRY1(MMDC_P0_MDSCR, 0x0408803A)
 /* LOAD MR3, CS0 */
 WRITE_ENTRY1(MMDC_P0_MDSCR, 0x00008033)
-WRITE_ENTRY1(MMDC_P0_MDSCR, 0x0000803B)
 /* LOAD MR1, CS0, A1,A6 set Rtt=RZQ/2, ODI=RZQ/7 */
 WRITE_ENTRY1(MMDC_P0_MDSCR, 0x00428031)
-WRITE_ENTRY1(MMDC_P0_MDSCR, 0x00428039)
 /* LOAD MR0, CS0, A6,A8,A11 set CAS=8, WR=8, DLL reset */
 WRITE_ENTRY1(MMDC_P0_MDSCR, 0x09408030)
-WRITE_ENTRY1(MMDC_P0_MDSCR, 0x09408038)
 
 /* ZQ calibrate, CS0 */
 WRITE_ENTRY1(MMDC_P0_MDSCR, 0x04008040)
-WRITE_ENTRY1(MMDC_P0_MDSCR, 0x04008048)
 WRITE_ENTRY1(MMDC_P0_MPZQHWCTRL, 0xA1380003)
 WRITE_ENTRY1(MMDC_P1_MPZQHWCTRL, 0xA1380003)

Signature · 1 line

1.7.9.5

Eric Nelson

2012-10-07 21:01 UTC #167 lore raw

PATCH v3 21/32 mx6q_4x_mt41j128.cfg: skip initiailizing non-existent memory

Hi Troy,

Quoted 22 lines · Troy Kisky

Sabrelite does not have memory associated with CS1

Signed-off-by Troy Kisky<[email protected]>

---
  board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg |    5 -----
  1 file changed, 5 deletions(-)

board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg +0 -3

index 9c622c8..2d03ff7 100644
@@ -155,20 +155,15 @@ WRITE_ENTRY1(MMDC_P0_MDCTL, 0x831A0000)
 
  /* MDSCR, con_req, LOAD MR2, CS0, A3,A10 set (CAS Write=6), RZQ/2 */
  WRITE_ENTRY1(MMDC_P0_MDSCR, 0x04088032)
-WRITE_ENTRY1(MMDC_P0_MDSCR, 0x0408803A)
  /* LOAD MR3, CS0 */
  WRITE_ENTRY1(MMDC_P0_MDSCR, 0x00008033)
-WRITE_ENTRY1(MMDC_P0_MDSCR, 0x0000803B)
  /* LOAD MR1, CS0, A1,A6 set Rtt=RZQ/2, ODI=RZQ/7 */
  WRITE_ENTRY1(MMDC_P0_MDSCR, 0x00428031)
-WRITE_ENTRY1(MMDC_P0_MDSCR, 0x00428039)

board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg WRITE_ENTRY1(MMDC_P0_MDCTL, 0x831A0000) · line 169

Quoted 10 lines

board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg +0 -2

  /* LOAD MR0, CS0, A6,A8,A11 set CAS=8, WR=8, DLL reset */
  WRITE_ENTRY1(MMDC_P0_MDSCR, 0x09408030)
-WRITE_ENTRY1(MMDC_P0_MDSCR, 0x09408038)
 
  /* ZQ calibrate, CS0 */
  WRITE_ENTRY1(MMDC_P0_MDSCR, 0x04008040)
-WRITE_ENTRY1(MMDC_P0_MDSCR, 0x04008048)
  WRITE_ENTRY1(MMDC_P0_MPZQHWCTRL, 0xA1380003)
  WRITE_ENTRY1(MMDC_P1_MPZQHWCTRL, 0xA1380003)

Note that mx6qsabreauto and mx6qsabresd also use this config file. That said, none of these boards have pad DRAM_CS1 connected.

Troy Kisky

author

2012-10-04 01:47 UTC #168 lore raw

PATCH v3 22/32 mx6q_4x_mt41j128.cfg: force ZQ calibration

In reply to Troy Kisky

Signed-off-by Troy Kisky <[email protected]>

---
 board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg |    4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg +2 -2

index 2d03ff7..9e20db0 100644
@@ -164,8 +164,8 @@ WRITE_ENTRY1(MMDC_P0_MDSCR, 0x09408030)
 
 /* ZQ calibrate, CS0 */
 WRITE_ENTRY1(MMDC_P0_MDSCR, 0x04008040)
-WRITE_ENTRY1(MMDC_P0_MPZQHWCTRL, 0xA1380003)
-WRITE_ENTRY1(MMDC_P1_MPZQHWCTRL, 0xA1380003)
+WRITE_ENTRY1(MMDC_P0_MPZQHWCTRL, 0xA1390003)
+WRITE_ENTRY1(MMDC_P1_MPZQHWCTRL, 0xA1390003)
 
 /* MDREF,  32KHz refresh, 4 refeshes each */
 WRITE_ENTRY1(MMDC_P0_MDREF, 0x00005800)

Signature · 1 line

1.7.9.5

Troy Kisky

author

2012-10-04 01:47 UTC #169 lore raw

PATCH v3 23/32 mx6: soc: update get_cpu_rev and get_imx_type for mx6solo/sololite

In reply to Troy Kisky

Previously, the same value was returned for both mx6dl and mx6solo. Check number of processors to differeniate.
Also, a freescale patch says that sololite has its cpu/rev stored at 0x280 instead of 0x260.
I don't have a sololite to verify.

Signed-off-by Troy Kisky <[email protected]>

---

Changed in V3.
V2 had created in new function get_cpu_type instead.

---
 arch/arm/cpu/armv7/mx6/soc.c              |   32 +++++++++++++++++++++--------
 arch/arm/imx-common/cpu.c                 |   16 ++++++++-------
 arch/arm/include/asm/arch-mx5/sys_proto.h |    9 +++++++-
 arch/arm/include/asm/arch-mx6/imx-regs.h  |    2 ++
 arch/arm/include/asm/arch-mx6/sys_proto.h |    9 +++++++-
 5 files changed, 51 insertions(+), 17 deletions(-)

arch/arm/cpu/armv7/mx6/soc.c +24 -8

index bc65767..a8aad5d 100644
@@ -31,17 +31,33 @@
 #include <asm/arch/sys_proto.h>
 #include <asm/imx-common/boot_mode.h>
 
+struct scu_regs {
+	u32	ctrl;
+	u32	config;
+	u32	status;
+	u32	invalidate;
+	u32	fpga_rev;
+};
+
 u32 get_cpu_rev(void)
 {
 	struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
-	int reg = readl(&anatop->digprog);
-
-	/* Read mx6 variant: quad, dual or solo */
-	int system_rev = (reg >> 4) & 0xFF000;
-	/* Read mx6 silicon revision */
-	system_rev |= (reg & 0xFF) + 0x10;
-
-	return system_rev;
+	u32 reg = readl(&anatop->digprog_sololite);
+	u32 type = ((reg >> 16) & 0xff);
+
+	if (type != MXC_CPU_MX6SL) {
+		reg = readl(&anatop->digprog);
+		type = ((reg >> 16) & 0xff);
+		if (type == MXC_CPU_MX6DL) {
+			struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
+			u32 cfg = readl(&scu->config) & 3;
+
+			if (!cfg)
+				type = MXC_CPU_MX6SOLO;
+		}
+	}
+	reg &= 0xff;		/* mx6 silicon revision */
+	return (type << 12) | (reg + 0x10);
 }
 
 void init_aips(void)

arch/arm/imx-common/cpu.c +9 -7

index a10d12d..102c254 100644
@@ -67,18 +67,20 @@ char *get_reset_cause(void)
 
 #if defined(CONFIG_DISPLAY_CPUINFO)
 
-static const char *get_imx_type(u32 imxtype)
+const char *get_imx_type(u32 imxtype)
 {
 	switch (imxtype) {
-	case 0x63:
+	case MXC_CPU_MX6Q:
 		return "6Q";	/* Quad-core version of the mx6 */
-	case 0x61:
-		return "6DS";	/* Dual/Solo version of the mx6 */
-	case 0x60:
+	case MXC_CPU_MX6DL:
+		return "6DL";	/* Dual Lite version of the mx6 */
+	case MXC_CPU_MX6SOLO:
+		return "6SOLO";	/* Solo version of the mx6 */
+	case MXC_CPU_MX6SL:
 		return "6SL";	/* Solo-Lite version of the mx6 */
-	case 0x51:
+	case MXC_CPU_MX51:
 		return "51";
-	case 0x53:
+	case MXC_CPU_MX53:
 		return "53";
 	default:
 		return "??";

arch/arm/include/asm/arch-mx5/sys_proto.h +8 -1

index 7b5246e..4435be1 100644
@@ -24,8 +24,15 @@
 #ifndef _SYS_PROTO_H_
 #define _SYS_PROTO_H_
 
-u32 get_cpu_rev(void);
+#define MXC_CPU_MX51		0x51
+#define MXC_CPU_MX53		0x53
+#define MXC_CPU_MX6SL		0x60
+#define MXC_CPU_MX6DL		0x61
+#define MXC_CPU_MX6SOLO		0x62
+#define MXC_CPU_MX6Q		0x63
+
 #define is_soc_rev(rev)	((get_cpu_rev() & 0xFF) - rev)
+u32 get_cpu_rev(void);
 void sdelay(unsigned long);
 void set_chipselect_size(int const);

arch/arm/include/asm/arch-mx6/imx-regs.h +2 -0

index dc737ba..b3a0d90 100644
@@ -558,6 +558,8 @@ struct anatop_regs {
 	u32	usb2_misc_clr;		/* 0x258 */
 	u32	usb2_misc_tog;		/* 0x25c */
 	u32	digprog;		/* 0x260 */
+	u32	reserved1[7];
+	u32	digprog_sololite;	/* 0x280 */
 };
 
 #define ANATOP_PFD_480_PFD0_FRAC_SHIFT		0

arch/arm/include/asm/arch-mx6/sys_proto.h +8 -1

index 711b30d..6627bbc 100644
@@ -24,9 +24,16 @@
 #ifndef _SYS_PROTO_H_
 #define _SYS_PROTO_H_
 
-#define is_soc_rev(rev)	((get_cpu_rev() & 0xFF) - rev)
+#define MXC_CPU_MX51		0x51
+#define MXC_CPU_MX53		0x53
+#define MXC_CPU_MX6SL		0x60
+#define MXC_CPU_MX6DL		0x61
+#define MXC_CPU_MX6SOLO		0x62
+#define MXC_CPU_MX6Q		0x63
 
+#define is_soc_rev(rev)	((get_cpu_rev() & 0xFF) - rev)
 u32 get_cpu_rev(void);
+const char *get_imx_type(u32 imxtype);
 
 void set_vddsoc(u32 mv);

Signature · 1 line

1.7.9.5

Troy Kisky

author

2012-10-04 01:47 UTC #170 lore raw

PATCH v3 24/32 mx6: use CONFIG_MX6 instead of CONFIG_MX6Q

In reply to Troy Kisky

Use CONFIG_MX6 when the particular processor
variant isn't important.

Reserve the use of CONFIG_MX6Q to
specifically test for quad cores variant.

Signed-off-by Troy Kisky <[email protected]>

---
 drivers/gpio/mxc_gpio.c            |    6 +++---
 drivers/video/ipu_regs.h           |    2 +-
 include/configs/mx6qarm2.h         |    1 +
 include/configs/mx6qsabre_common.h |    1 +
 include/configs/mx6qsabrelite.h    |    1 +
 5 files changed, 7 insertions(+), 4 deletions(-)

drivers/gpio/mxc_gpio.c +3 -3

index 2c79bff..a388064 100644
@@ -42,14 +42,14 @@ static unsigned long gpio_ports[] = {
 	[1] = GPIO2_BASE_ADDR,
 	[2] = GPIO3_BASE_ADDR,
 #if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX51) || \
-		defined(CONFIG_MX53) || defined(CONFIG_MX6Q)
+		defined(CONFIG_MX53) || defined(CONFIG_MX6)
 	[3] = GPIO4_BASE_ADDR,
 #endif
-#if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6Q)
+#if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6)
 	[4] = GPIO5_BASE_ADDR,
 	[5] = GPIO6_BASE_ADDR,
 #endif
-#if defined(CONFIG_MX53) || defined(CONFIG_MX6Q)
+#if defined(CONFIG_MX53) || defined(CONFIG_MX6)
 	[6] = GPIO7_BASE_ADDR,
 #endif
 };

drivers/video/ipu_regs.h +1 -1

index a43aa03..982e252 100644
@@ -55,7 +55,7 @@
 #define IPU_TPM_REG_BASE	0x01060000
 #define IPU_DC_TMPL_REG_BASE	0x01080000
 #define IPU_ISP_TBPR_REG_BASE	0x010C0000
-#elif defined(CONFIG_MX6Q)
+#elif defined(CONFIG_MX6)
 #define IPU_CPMEM_REG_BASE	0x00100000
 #define IPU_LUT_REG_BASE	0x00120000
 #define IPU_SRM_REG_BASE	0x00140000

include/configs/mx6qarm2.h +1 -0

index 965bea3..8e5b81e 100644
@@ -22,6 +22,7 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
+#define CONFIG_MX6
 #define CONFIG_MX6Q
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO

include/configs/mx6qsabre_common.h +1 -0

index 247e8d6..5a940da 100644
@@ -17,6 +17,7 @@
 #ifndef __MX6QSABRE_COMMON_CONFIG_H
 #define __MX6QSABRE_COMMON_CONFIG_H
 
+#define CONFIG_MX6
 #define CONFIG_MX6Q
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO

include/configs/mx6qsabrelite.h +1 -0

index e7bf658..6a10232 100644
@@ -22,6 +22,7 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
+#define CONFIG_MX6
 #define CONFIG_MX6Q
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO

Signature · 1 line

1.7.9.5

Stefano Babic

2012-10-08 13:41 UTC #171 lore raw

PATCH v3 24/32 mx6: use CONFIG_MX6 instead of CONFIG_MX6Q

Quoted 80 lines · Troy Kisky

Use CONFIG_MX6 when the particular processor
variant isn't important.

Reserve the use of CONFIG_MX6Q to
specifically test for quad cores variant.

Signed-off-by Troy Kisky <[email protected]>

---
 drivers/gpio/mxc_gpio.c            |    6 +++---
 drivers/video/ipu_regs.h           |    2 +-
 include/configs/mx6qarm2.h         |    1 +
 include/configs/mx6qsabre_common.h |    1 +
 include/configs/mx6qsabrelite.h    |    1 +
 5 files changed, 7 insertions(+), 4 deletions(-)

drivers/gpio/mxc_gpio.c +3 -3

index 2c79bff..a388064 100644
@@ -42,14 +42,14 @@ static unsigned long gpio_ports[] = {
 	[1] = GPIO2_BASE_ADDR,
 	[2] = GPIO3_BASE_ADDR,
 #if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX51) || \
-		defined(CONFIG_MX53) || defined(CONFIG_MX6Q)
+		defined(CONFIG_MX53) || defined(CONFIG_MX6)
 	[3] = GPIO4_BASE_ADDR,
 #endif
-#if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6Q)
+#if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6)
 	[4] = GPIO5_BASE_ADDR,
 	[5] = GPIO6_BASE_ADDR,
 #endif
-#if defined(CONFIG_MX53) || defined(CONFIG_MX6Q)
+#if defined(CONFIG_MX53) || defined(CONFIG_MX6)
 	[6] = GPIO7_BASE_ADDR,
 #endif
 };

drivers/video/ipu_regs.h +1 -1

index a43aa03..982e252 100644
@@ -55,7 +55,7 @@
 #define IPU_TPM_REG_BASE	0x01060000
 #define IPU_DC_TMPL_REG_BASE	0x01080000
 #define IPU_ISP_TBPR_REG_BASE	0x010C0000
-#elif defined(CONFIG_MX6Q)
+#elif defined(CONFIG_MX6)
 #define IPU_CPMEM_REG_BASE	0x00100000
 #define IPU_LUT_REG_BASE	0x00120000
 #define IPU_SRM_REG_BASE	0x00140000

include/configs/mx6qarm2.h +1 -0

index 965bea3..8e5b81e 100644
@@ -22,6 +22,7 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
+#define CONFIG_MX6
 #define CONFIG_MX6Q
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO

include/configs/mx6qsabre_common.h +1 -0

index 247e8d6..5a940da 100644
@@ -17,6 +17,7 @@
 #ifndef __MX6QSABRE_COMMON_CONFIG_H
 #define __MX6QSABRE_COMMON_CONFIG_H
 
+#define CONFIG_MX6
 #define CONFIG_MX6Q
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO

include/configs/mx6qsabrelite.h +0 -0

index e7bf658..6a10232 100644

include/configs/mx6qsabrelite.h line 28

Quoted 7 lines

include/configs/mx6qsabrelite.h +1 -0

@@ -22,6 +22,7 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
+#define CONFIG_MX6
 #define CONFIG_MX6Q
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO

This changes affects also mx6qsabreauto and mx6qsabresd, that I have already merged.

Best regards,
Stefano Babic

Signature · 5 lines

=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

Troy Kisky

author

2012-10-08 21:49 UTC #172 lore raw

PATCH v3 24/32 mx6: use CONFIG_MX6 instead of CONFIG_MX6Q

Quoted 91 lines · Stefano Babic

Quoted 80 lines · Troy Kisky

Use CONFIG_MX6 when the particular processor
variant isn't important.

Reserve the use of CONFIG_MX6Q to
specifically test for quad cores variant.

Signed-off-by Troy Kisky <[email protected]>

---
  drivers/gpio/mxc_gpio.c            |    6 +++---
  drivers/video/ipu_regs.h           |    2 +-
  include/configs/mx6qarm2.h         |    1 +
  include/configs/mx6qsabre_common.h |    1 +
  include/configs/mx6qsabrelite.h    |    1 +
  5 files changed, 7 insertions(+), 4 deletions(-)

drivers/gpio/mxc_gpio.c +3 -3

index 2c79bff..a388064 100644
@@ -42,14 +42,14 @@ static unsigned long gpio_ports[] = {
  	[1] = GPIO2_BASE_ADDR,
  	[2] = GPIO3_BASE_ADDR,
  #if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX51) || \
-		defined(CONFIG_MX53) || defined(CONFIG_MX6Q)
+		defined(CONFIG_MX53) || defined(CONFIG_MX6)
  	[3] = GPIO4_BASE_ADDR,
  #endif
-#if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6Q)
+#if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6)
  	[4] = GPIO5_BASE_ADDR,
  	[5] = GPIO6_BASE_ADDR,
  #endif
-#if defined(CONFIG_MX53) || defined(CONFIG_MX6Q)
+#if defined(CONFIG_MX53) || defined(CONFIG_MX6)
  	[6] = GPIO7_BASE_ADDR,
  #endif
  };

drivers/video/ipu_regs.h +1 -1

index a43aa03..982e252 100644
@@ -55,7 +55,7 @@
  #define IPU_TPM_REG_BASE	0x01060000
  #define IPU_DC_TMPL_REG_BASE	0x01080000
  #define IPU_ISP_TBPR_REG_BASE	0x010C0000
-#elif defined(CONFIG_MX6Q)
+#elif defined(CONFIG_MX6)
  #define IPU_CPMEM_REG_BASE	0x00100000
  #define IPU_LUT_REG_BASE	0x00120000
  #define IPU_SRM_REG_BASE	0x00140000

include/configs/mx6qarm2.h +1 -0

index 965bea3..8e5b81e 100644
@@ -22,6 +22,7 @@
  #ifndef __CONFIG_H
  #define __CONFIG_H
 
+#define CONFIG_MX6
  #define CONFIG_MX6Q
  #define CONFIG_DISPLAY_CPUINFO
  #define CONFIG_DISPLAY_BOARDINFO

include/configs/mx6qsabre_common.h +1 -0

index 247e8d6..5a940da 100644
@@ -17,6 +17,7 @@
  #ifndef __MX6QSABRE_COMMON_CONFIG_H
  #define __MX6QSABRE_COMMON_CONFIG_H
 
+#define CONFIG_MX6
  #define CONFIG_MX6Q
  #define CONFIG_DISPLAY_CPUINFO
  #define CONFIG_DISPLAY_BOARDINFO

include/configs/mx6qsabrelite.h +0 -0

index e7bf658..6a10232 100644

include/configs/mx6qsabrelite.h line 28

Quoted 7 lines

include/configs/mx6qsabrelite.h +1 -0

@@ -22,6 +22,7 @@
  #ifndef __CONFIG_H
  #define __CONFIG_H
 
+#define CONFIG_MX6
  #define CONFIG_MX6Q
  #define CONFIG_DISPLAY_CPUINFO
  #define CONFIG_DISPLAY_BOARDINFO

This changes affects also mx6qsabreauto and mx6qsabresd, that I have already merged.

Quoted 2 lines

Best regards,
Stefano Babic

They should be covered by
#include "mx6qsabre_common.h"

Troy Kisky

author

2012-10-04 01:47 UTC #173 lore raw

PATCH v3 25/32 imx-common: cpu: add imx_ddr_size

In reply to Troy Kisky

Read memory setup registers to determine size of available ram. This routine works for mx53/mx6x

I need this because when mx6solo called get_ram_size with a too large maximum size, the system hanged.

Signed-off-by Troy Kisky <[email protected]>

---
New patch with V3. V2 had code in mx6qsabrelite.c

---
 arch/arm/imx-common/cpu.c                 |   50 +++++++++++++++++++++++++++++
 arch/arm/include/asm/arch-mx5/sys_proto.h |    1 +
 arch/arm/include/asm/arch-mx6/sys_proto.h |    1 +
 3 files changed, 52 insertions(+)

arch/arm/imx-common/cpu.c +50 -0

index 102c254..5081908 100644
@@ -65,6 +65,56 @@ char *get_reset_cause(void)
 	}
 }
 
+#if defined(CONFIG_MX53) || defined(CONFIG_MX6)
+#if defined(CONFIG_MX53)
+#define MEMCTL_BASE	ESDCTL_BASE_ADDR;
+#else
+#define MEMCTL_BASE	MMDC_P0_BASE_ADDR;
+#endif
+static const unsigned char col_lookup[] = {9, 10, 11, 8, 12, 9, 9, 9};
+static const unsigned char bank_lookup[] = {3, 2};
+
+struct esd_mmdc_regs {
+	uint32_t	ctl;
+	uint32_t	pdc;
+	uint32_t	otc;
+	uint32_t	cfg0;
+	uint32_t	cfg1;
+	uint32_t	cfg2;
+	uint32_t	misc;
+	uint32_t	scr;
+	uint32_t	ref;
+	uint32_t	rsvd1;
+	uint32_t	rsvd2;
+	uint32_t	rwd;
+	uint32_t	or;
+	uint32_t	mrr;
+	uint32_t	cfg3lp;
+	uint32_t	mr4;
+};
+
+#define ESD_MMDC_CTL_GET_ROW(mdctl)	((ctl >> 24) & 7)
+#define ESD_MMDC_CTL_GET_COLUMN(mdctl)	((ctl >> 20) & 7)
+#define ESD_MMDC_CTL_GET_WIDTH(mdctl)	((ctl >> 16) & 3)
+#define ESD_MMDC_CTL_GET_CS1(mdctl)	((ctl >> 30) & 1)
+#define ESD_MMDC_MISC_GET_BANK(mdmisc)	((misc >> 5) & 1)
+
+unsigned imx_ddr_size(void)
+{
+	struct esd_mmdc_regs *mem = (struct esd_mmdc_regs *)MEMCTL_BASE;
+	unsigned ctl = readl(&mem->ctl);
+	unsigned misc = readl(&mem->misc);
+	int bits = 11 + 0 + 0 + 1;      /* row + col + bank + width */
+
+	bits += ESD_MMDC_CTL_GET_ROW(ctl);
+	bits += col_lookup[ESD_MMDC_CTL_GET_COLUMN(ctl)];
+	bits += bank_lookup[ESD_MMDC_MISC_GET_BANK(misc)];
+	bits += ESD_MMDC_CTL_GET_WIDTH(ctl);
+	bits += ESD_MMDC_CTL_GET_CS1(ctl);
+	return 1 << bits;
+}
+#endif
+
 #if defined(CONFIG_DISPLAY_CPUINFO)
 
 const char *get_imx_type(u32 imxtype)

arch/arm/include/asm/arch-mx5/sys_proto.h +1 -0

index 4435be1..93ad1c6 100644
@@ -33,6 +33,7 @@
 
 #define is_soc_rev(rev)	((get_cpu_rev() & 0xFF) - rev)
 u32 get_cpu_rev(void);
+unsigned imx_ddr_size(void);
 void sdelay(unsigned long);
 void set_chipselect_size(int const);

arch/arm/include/asm/arch-mx6/sys_proto.h +1 -0

index 6627bbc..3193297 100644
@@ -34,6 +34,7 @@
 #define is_soc_rev(rev)	((get_cpu_rev() & 0xFF) - rev)
 u32 get_cpu_rev(void);
 const char *get_imx_type(u32 imxtype);
+unsigned imx_ddr_size(void);
 
 void set_vddsoc(u32 mv);

Signature · 1 line

1.7.9.5

Stefano Babic

2012-10-08 13:06 UTC #174 lore raw

PATCH v3 25/32 imx-common: cpu: add imx_ddr_size

Quoted 8 lines · Troy Kisky

Read memory setup registers to determine size of available ram. This routine works for mx53/mx6x
I need this because when mx6solo called get_ram_size with a too large maximum size, the system hanged.
Signed-off-by Troy Kisky <[email protected]>

Hi Troy,

I am interested to better understand why get_ram_size() does not work. It seems to me you discovered a bug in this function, and you circumvent it decoding the DRAM controller setup to get the RAM size.

Because the max size is added to the start address in get_ram_size(), I have the feeling that this overwlow the long value, and maybe can be fixed swithcing to a "long long". With which parameters to get_ram_size() does your board hang ?

Quoted 86 lines

---
New patch with V3. V2 had code in mx6qsabrelite.c

---
 arch/arm/imx-common/cpu.c                 |   50 +++++++++++++++++++++++++++++
 arch/arm/include/asm/arch-mx5/sys_proto.h |    1 +
 arch/arm/include/asm/arch-mx6/sys_proto.h |    1 +
 3 files changed, 52 insertions(+)

arch/arm/imx-common/cpu.c +50 -0

index 102c254..5081908 100644
@@ -65,6 +65,56 @@ char *get_reset_cause(void)
 	}
 }
 
+#if defined(CONFIG_MX53) || defined(CONFIG_MX6)
+#if defined(CONFIG_MX53)
+#define MEMCTL_BASE	ESDCTL_BASE_ADDR;
+#else
+#define MEMCTL_BASE	MMDC_P0_BASE_ADDR;
+#endif
+static const unsigned char col_lookup[] = {9, 10, 11, 8, 12, 9, 9, 9};
+static const unsigned char bank_lookup[] = {3, 2};
+
+struct esd_mmdc_regs {
+	uint32_t	ctl;
+	uint32_t	pdc;
+	uint32_t	otc;
+	uint32_t	cfg0;
+	uint32_t	cfg1;
+	uint32_t	cfg2;
+	uint32_t	misc;
+	uint32_t	scr;
+	uint32_t	ref;
+	uint32_t	rsvd1;
+	uint32_t	rsvd2;
+	uint32_t	rwd;
+	uint32_t	or;
+	uint32_t	mrr;
+	uint32_t	cfg3lp;
+	uint32_t	mr4;
+};
+
+#define ESD_MMDC_CTL_GET_ROW(mdctl)	((ctl >> 24) & 7)
+#define ESD_MMDC_CTL_GET_COLUMN(mdctl)	((ctl >> 20) & 7)
+#define ESD_MMDC_CTL_GET_WIDTH(mdctl)	((ctl >> 16) & 3)
+#define ESD_MMDC_CTL_GET_CS1(mdctl)	((ctl >> 30) & 1)
+#define ESD_MMDC_MISC_GET_BANK(mdmisc)	((misc >> 5) & 1)
+
+unsigned imx_ddr_size(void)
+{
+	struct esd_mmdc_regs *mem = (struct esd_mmdc_regs *)MEMCTL_BASE;
+	unsigned ctl = readl(&mem->ctl);
+	unsigned misc = readl(&mem->misc);
+	int bits = 11 + 0 + 0 + 1;      /* row + col + bank + width */
+
+	bits += ESD_MMDC_CTL_GET_ROW(ctl);
+	bits += col_lookup[ESD_MMDC_CTL_GET_COLUMN(ctl)];
+	bits += bank_lookup[ESD_MMDC_MISC_GET_BANK(misc)];
+	bits += ESD_MMDC_CTL_GET_WIDTH(ctl);
+	bits += ESD_MMDC_CTL_GET_CS1(ctl);
+	return 1 << bits;
+}
+#endif
+
 #if defined(CONFIG_DISPLAY_CPUINFO)
 
 const char *get_imx_type(u32 imxtype)

arch/arm/include/asm/arch-mx5/sys_proto.h +1 -0

index 4435be1..93ad1c6 100644
@@ -33,6 +33,7 @@
 
 #define is_soc_rev(rev)	((get_cpu_rev() & 0xFF) - rev)
 u32 get_cpu_rev(void);
+unsigned imx_ddr_size(void);
 void sdelay(unsigned long);
 void set_chipselect_size(int const);

arch/arm/include/asm/arch-mx6/sys_proto.h +0 -0

index 6627bbc..3193297 100644

arch/arm/include/asm/arch-mx6/sys_proto.h line 38

Quoted 5 lines

arch/arm/include/asm/arch-mx6/sys_proto.h +1 -0

@@ -34,6 +34,7 @@
 #define is_soc_rev(rev)	((get_cpu_rev() & 0xFF) - rev)
 u32 get_cpu_rev(void);
 const char *get_imx_type(u32 imxtype);
+unsigned imx_ddr_size(void);

Best regards,
Stefano Babic

Signature · 5 lines

=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

Troy Kisky

author

2012-10-08 21:35 UTC #175 lore raw

PATCH v3 25/32 imx-common: cpu: add imx_ddr_size

Quoted 11 lines · Stefano Babic

Quoted 8 lines · Troy Kisky
Read memory setup registers to determine size of available ram. This routine works for mx53/mx6x
I need this because when mx6solo called get_ram_size with a too large maximum size, the system hanged.
Signed-off-by Troy Kisky <[email protected]>
Hi Troy,

Quoted 10 lines

I am interested to better understand why get_ram_size() does not work. It seems to me you discovered a bug in this function, and you circumvent it decoding the DRAM controller setup to get the RAM size.
Because the max size is added to the start address in get_ram_size(), I have the feeling that this overwlow the long value, and maybe can be fixed swithcing to a "long long". With which parameters to get_ram_size() does your board hang ?

#define MMDC0_ARB_BASE_ADDR 0x10000000
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)

get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);

So, base + size = 0x50000000

Troy Kisky

author

2012-10-04 01:47 UTC #176 lore raw

PATCH v3 26/32 arch-mx6: add mx6dl_pins.h

In reply to Troy Kisky

Only the values used in the sabrelite board are added currently. Add more as other boards use them.

Signed-off-by Troy Kisky <[email protected]>

---
 arch/arm/include/asm/arch-mx6/mx6dl_pins.h |  118 ++++++++++++++++++++++++++++
 1 file changed, 118 insertions(+)
 create mode 100644 arch/arm/include/asm/arch-mx6/mx6dl_pins.h

arch/arm/include/asm/arch-mx6/mx6dl_pins.h new file +118 -0

new file mode 100644
index 0000000..5848013
@@ -0,0 +1,118 @@
+/*
+ * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ */
+
+#ifndef __ASM_ARCH_MX6_MX6DL_PINS_H__
+#define __ASM_ARCH_MX6_MX6DL_PINS_H__
+
+#include <asm/imx-common/iomux-v3.h>
+
+/* Use to set PAD control */
+#define PAD_CTL_HYS		(1 << 16)
+#define PAD_CTL_PUS_100K_DOWN	(0 << 14)
+#define PAD_CTL_PUS_47K_UP	(1 << 14)
+#define PAD_CTL_PUS_100K_UP	(2 << 14)
+#define PAD_CTL_PUS_22K_UP	(3 << 14)
+
+#define PAD_CTL_PUE		(1 << 13)
+#define PAD_CTL_PKE		(1 << 12)
+#define PAD_CTL_ODE		(1 << 11)
+#define PAD_CTL_SPEED_LOW	(1 << 6)
+#define PAD_CTL_SPEED_MED	(2 << 6)
+#define PAD_CTL_SPEED_HIGH	(3 << 6)
+#define PAD_CTL_DSE_DISABLE	(0 << 3)
+#define PAD_CTL_DSE_240ohm	(1 << 3)
+#define PAD_CTL_DSE_120ohm	(2 << 3)
+#define PAD_CTL_DSE_80ohm	(3 << 3)
+#define PAD_CTL_DSE_60ohm	(4 << 3)
+#define PAD_CTL_DSE_48ohm	(5 << 3)
+#define PAD_CTL_DSE_40ohm	(6 << 3)
+#define PAD_CTL_DSE_34ohm	(7 << 3)
+#define PAD_CTL_SRE_FAST	(1 << 0)
+#define PAD_CTL_SRE_SLOW	(0 << 0)
+
+#define IOMUX_CONFIG_SION 0x10
+#define NO_MUX_I                0
+#define NO_PAD_I                0
+enum {
+	MX6DL_PAD_EIM_D16__ECSPI1_SCLK		= IOMUX_PAD(0x0514, 0x0144, 1, 0x07D8, 2, 0),
+	MX6DL_PAD_EIM_D17__ECSPI1_MISO		= IOMUX_PAD(0x0518, 0x0148, 1, 0x07DC, 2, 0),
+	MX6DL_PAD_EIM_D18__ECSPI1_MOSI		= IOMUX_PAD(0x051C, 0x014C, 1, 0x07E0, 2, 0),
+	MX6DL_PAD_EIM_D19__GPIO_3_19		= IOMUX_PAD(0x0520, 0x0150, 5, 0x0000, 0, 0),
+	MX6DL_PAD_EIM_D21__GPIO_3_21		= IOMUX_PAD(0x0528, 0x0158, 5, 0x0000, 0, 0),
+	MX6DL_PAD_EIM_D21__I2C1_SCL		= IOMUX_PAD(0x0528, 0x0158, 6 | IOMUX_CONFIG_SION, 0x0868, 1, 0),
+	MX6DL_PAD_EIM_D23__GPIO_3_23		= IOMUX_PAD(0x0530, 0x0160, 5, 0x0000, 0, 0),
+	MX6DL_PAD_EIM_D26__UART2_TXD		= IOMUX_PAD(0x053C, 0x016C, 4, 0x0000, 0, 0),
+	MX6DL_PAD_EIM_D27__UART2_RXD		= IOMUX_PAD(0x0540, 0x0170, 4, 0x0904, 1, 0),
+	MX6DL_PAD_EIM_D28__I2C1_SDA		= IOMUX_PAD(0x0544, 0x0174, 1 | IOMUX_CONFIG_SION, 0x086C, 1, 0),
+	MX6DL_PAD_EIM_D28__GPIO_3_28		= IOMUX_PAD(0x0544, 0x0174, 5, 0x0000, 0, 0),
+	MX6DL_PAD_ENET_MDC__ENET_MDC		= IOMUX_PAD(0x05B8, 0x01E8, 1, 0x0000, 0,  0),
+	MX6DL_PAD_ENET_MDIO__ENET_MDIO		= IOMUX_PAD(0x05BC, 0x01EC, 1, 0x0810, 0, 0),
+	MX6DL_PAD_ENET_REF_CLK__ENET_TX_CLK	= IOMUX_PAD(0x05C0, 0x01F0, 1, 0x0000, 0, 0),
+	MX6DL_PAD_ENET_RXD0__GPIO_1_27		= IOMUX_PAD(0x05C8, 0x01F8, 5, 0x0000, 0, 0),
+	MX6DL_PAD_GPIO_16__GPIO_7_11		= IOMUX_PAD(0x05E4, 0x0214, 5, 0x0000, 0, 0),
+	MX6DL_PAD_GPIO_16__I2C3_SDA		= IOMUX_PAD(0x05E4, 0x0214, 6 | IOMUX_CONFIG_SION, 0x087C, 1, 0),
+	MX6DL_PAD_GPIO_17__GPIO_7_12		= IOMUX_PAD(0x05E8, 0x0218, 5, 0x0000, 0, 0),
+	MX6DL_PAD_GPIO_18__GPIO_7_13		= IOMUX_PAD(0x05EC, 0x021C, 5, 0x0000, 0, 0),
+	MX6DL_PAD_GPIO_19__GPIO_4_5		= IOMUX_PAD(0x05F0, 0x0220, 5, 0x0000, 0, 0),
+	MX6DL_PAD_GPIO_5__GPIO_1_5		= IOMUX_PAD(0x0600, 0x0230, 5, 0x0000, 0, 0),
+	MX6DL_PAD_GPIO_5__I2C3_SCL		= IOMUX_PAD(0x0600, 0x0230, 6 | IOMUX_CONFIG_SION, 0x0878, 2, 0),
+	MX6DL_PAD_KEY_COL3__I2C2_SCL		= IOMUX_PAD(0x0638, 0x0250, 4 | IOMUX_CONFIG_SION, 0x0870, 1, 0),
+	MX6DL_PAD_KEY_COL3__GPIO_4_12		= IOMUX_PAD(0x0638, 0x0250, 5, 0x0000, 0, 0),
+	MX6DL_PAD_KEY_ROW3__I2C2_SDA		= IOMUX_PAD(0x064C, 0x0264, 4 | IOMUX_CONFIG_SION, 0x0874, 1, 0),
+	MX6DL_PAD_KEY_ROW3__GPIO_4_13		= IOMUX_PAD(0x064C, 0x0264, 5, 0x0000, 0, 0),
+	MX6DL_PAD_NANDF_D1__GPIO_2_1		= IOMUX_PAD(0x0670, 0x0288, 5, 0x0000, 0, 0),
+	MX6DL_PAD_NANDF_D2__GPIO_2_2		= IOMUX_PAD(0x0674, 0x028C, 5, 0x0000, 0, 0),
+	MX6DL_PAD_NANDF_D3__GPIO_2_3		= IOMUX_PAD(0x0678, 0x0290, 5, 0x0000, 0, 0),
+	MX6DL_PAD_NANDF_D4__GPIO_2_4		= IOMUX_PAD(0x067C, 0x0294, 5, 0x0000, 0, 0),
+	MX6DL_PAD_NANDF_D6__GPIO_2_6		= IOMUX_PAD(0x0684, 0x029C, 5, 0x0000, 0, 0),
+	MX6DL_PAD_RGMII_RD0__ENET_RGMII_RD0     = IOMUX_PAD(0x0694, 0x02AC, 1, 0x0818, 1, 0),
+	MX6DL_PAD_RGMII_RD0__GPIO_6_25		= IOMUX_PAD(0x0694, 0x02AC, 5, 0x0000, 0, 0),
+	MX6DL_PAD_RGMII_RD1__ENET_RGMII_RD1	= IOMUX_PAD(0x0698, 0x02B0, 1, 0x081C, 1, 0),
+	MX6DL_PAD_RGMII_RD1__GPIO_6_27		= IOMUX_PAD(0x0698, 0x02B0, 5, 0x0000, 0, 0),
+	MX6DL_PAD_RGMII_RD2__ENET_RGMII_RD2	= IOMUX_PAD(0x069C, 0x02B4, 1, 0x0820, 1, 0),
+	MX6DL_PAD_RGMII_RD2__GPIO_6_28		= IOMUX_PAD(0x069C, 0x02B4, 5, 0x0000, 0, 0),
+	MX6DL_PAD_RGMII_RD3__ENET_RGMII_RD3	= IOMUX_PAD(0x06A0, 0x02B8, 1, 0x0824, 1, 0),
+	MX6DL_PAD_RGMII_RD3__GPIO_6_29		= IOMUX_PAD(0x06A0, 0x02B8, 5, 0x0000, 0, 0),
+	MX6DL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	= IOMUX_PAD(0x06A4, 0x02BC, 1, 0x0828, 1, 0),
+	MX6DL_PAD_RGMII_RX_CTL__GPIO_6_24	= IOMUX_PAD(0x06A4, 0x02BC, 5, 0x0000, 0, 0),
+	MX6DL_PAD_RGMII_RXC__ENET_RGMII_RXC	= IOMUX_PAD(0x06A8, 0x02C0, 1, 0x0814, 1, 0),
+	MX6DL_PAD_RGMII_RXC__GPIO_6_30		= IOMUX_PAD(0x06A8, 0x02C0, 5, 0x0000, 0, 0),
+	MX6DL_PAD_RGMII_TD0__ENET_RGMII_TD0	= IOMUX_PAD(0x06AC, 0x02C4, 1, 0x0000, 0, 0),
+	MX6DL_PAD_RGMII_TD1__ENET_RGMII_TD1	= IOMUX_PAD(0x06B0, 0x02C8, 1, 0x0000, 0, 0),
+	MX6DL_PAD_RGMII_TD2__ENET_RGMII_TD2	= IOMUX_PAD(0x06B4, 0x02CC, 1, 0x0000, 0, 0),
+	MX6DL_PAD_RGMII_TD3__ENET_RGMII_TD3	= IOMUX_PAD(0x06B8, 0x02D0, 1, 0x0000, 0, 0),
+	MX6DL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	= IOMUX_PAD(0x06BC, 0x02D4, 1, 0x0000, 0, 0),
+	MX6DL_PAD_RGMII_TXC__ENET_RGMII_TXC	= IOMUX_PAD(0x06C0, 0x02D8, 1, 0x0000, 0, 0),
+	MX6DL_PAD_SD3_CLK__USDHC3_CLK		= IOMUX_PAD(0x06F4, 0x030C, 0, 0x0934, 1, 0),
+	MX6DL_PAD_SD3_CMD__USDHC3_CMD		= IOMUX_PAD(0x06F8, 0x0310, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0),
+	MX6DL_PAD_SD3_DAT0__USDHC3_DAT0		= IOMUX_PAD(0x06FC, 0x0314, 0, 0x0000, 0, 0),
+	MX6DL_PAD_SD3_DAT1__USDHC3_DAT1		= IOMUX_PAD(0x0700, 0x0318, 0, 0x0000, 0, 0),
+	MX6DL_PAD_SD3_DAT2__USDHC3_DAT2		= IOMUX_PAD(0x0704, 0x031C, 0, 0x0000, 0, 0),
+	MX6DL_PAD_SD3_DAT3__USDHC3_DAT3		= IOMUX_PAD(0x0708, 0x0320, 0, 0x0000, 0, 0),
+	MX6DL_PAD_SD3_DAT5__GPIO_7_0		= IOMUX_PAD(0x0710, 0x0328, 5, 0x0000, 0, 0),
+	MX6DL_PAD_SD3_DAT6__UART1_RXD		= IOMUX_PAD(0x0714, 0x032C, 1, 0x08FC, 2, 0),
+	MX6DL_PAD_SD3_DAT7__UART1_TXD		= IOMUX_PAD(0x0718, 0x0330, 1, 0x0000, 0, 0),
+	MX6DL_PAD_SD4_CLK__USDHC4_CLK		= IOMUX_PAD(0x0720, 0x0338, 0, 0x0938, 1, 0),
+	MX6DL_PAD_SD4_CMD__USDHC4_CMD		= IOMUX_PAD(0x0724, 0x033C, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0),
+	MX6DL_PAD_SD4_DAT0__USDHC4_DAT0		= IOMUX_PAD(0x0728, 0x0340, 1, 0x0000, 0, 0),
+	MX6DL_PAD_SD4_DAT1__USDHC4_DAT1		= IOMUX_PAD(0x072C, 0x0344, 1, 0x0000, 0, 0),
+	MX6DL_PAD_SD4_DAT2__USDHC4_DAT2		= IOMUX_PAD(0x0730, 0x0348, 1, 0x0000, 0, 0),
+	MX6DL_PAD_SD4_DAT3__USDHC4_DAT3		= IOMUX_PAD(0x0734, 0x034C, 1, 0x0000, 0, 0),
+};
+#endif	/* __ASM_ARCH_MX6_MX6DL_PINS_H__ */

Signature · 1 line

1.7.9.5

Troy Kisky

author

2012-10-04 01:47 UTC #177 lore raw

PATCH v3 27/32 mx6qsabrelite: add support for mx6 solo/duallite

In reply to Troy Kisky

Signed-off-by Troy Kisky <[email protected]>

---
 board/freescale/mx6qsabrelite/mx6qsabrelite.c |  235 ++++++-------------------
 board/freescale/mx6qsabrelite/pads.h          |  172 ++++++++++++++++++
 2 files changed, 229 insertions(+), 178 deletions(-)
 create mode 100644 board/freescale/mx6qsabrelite/pads.h

board/freescale/mx6qsabrelite/mx6qsabrelite.c +57 ~~-178~~

index 4b4e89b..454972c 100644
@@ -26,6 +26,8 @@
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/iomux.h>
 #include <asm/arch/mx6x_pins.h>
+#include <asm/arch/mx6dl_pins.h>
+#include <asm/arch/sys_proto.h>
 #include <asm/errno.h>
 #include <asm/gpio.h>
 #include <asm/imx-common/iomux-v3.h>

@@ -38,162 +40,52 @@
 #include <netdev.h>
 DECLARE_GLOBAL_DATA_PTR;
 
-#define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |	       \
-       PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |	       \
-       PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
-
-#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |	       \
-       PAD_CTL_PUS_47K_UP  | PAD_CTL_SPEED_LOW |	       \
-       PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
-
-#define ENET_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |		\
-	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED	  |		\
-	PAD_CTL_DSE_40ohm   | PAD_CTL_HYS)
-
-#define SPI_PAD_CTRL (PAD_CTL_HYS |				\
-	PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED |		\
-	PAD_CTL_DSE_40ohm     | PAD_CTL_SRE_FAST)
-
-#define BUTTON_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |		\
-	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED   |		\
-	PAD_CTL_DSE_40ohm   | PAD_CTL_HYS)
-
-#define I2C_PAD_CTRL	(PAD_CTL_PKE | PAD_CTL_PUE |		\
-	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |		\
-	PAD_CTL_DSE_40ohm | PAD_CTL_HYS |			\
-	PAD_CTL_ODE | PAD_CTL_SRE_FAST)
+#ifdef CONFIG_MX6Q
+#include "pads.h"
+#endif
+#if defined(CONFIG_MX6DL) || defined(CONFIG_MX6S)
+#define FOR_DL_SOLO
+#include "pads.h"
+#endif
 
-int dram_init(void)
+int cpu_is_mx6q(void)
 {
-       gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
-
-       return 0;
+	return (get_cpu_rev() >> 12) == MXC_CPU_MX6Q;
 }
 
-iomux_v3_cfg_t uart1_pads[] = {
-	MX6Q_PAD_SD3_DAT6__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
-	MX6Q_PAD_SD3_DAT7__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
-};
-
-iomux_v3_cfg_t uart2_pads[] = {
-       MX6Q_PAD_EIM_D26__UART2_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
-       MX6Q_PAD_EIM_D27__UART2_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
-};
-
-#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
-
-/* I2C1, SGTL5000 */
-struct i2c_pads_info i2c_pad_info0 = {
-	.scl = {
-		.i2c_mode = MX6Q_PAD_EIM_D21__I2C1_SCL | PC,
-		.gpio_mode = MX6Q_PAD_EIM_D21__GPIO_3_21 | PC,
-		.gp = IMX_GPIO_NR(3, 21)
-	},
-	.sda = {
-		.i2c_mode = MX6Q_PAD_EIM_D28__I2C1_SDA | PC,
-		.gpio_mode = MX6Q_PAD_EIM_D28__GPIO_3_28 | PC,
-		.gp = IMX_GPIO_NR(3, 28)
-	}
-};
-
-/* I2C2 Camera, MIPI */
-struct i2c_pads_info i2c_pad_info1 = {
-	.scl = {
-		.i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL | PC,
-		.gpio_mode = MX6Q_PAD_KEY_COL3__GPIO_4_12 | PC,
-		.gp = IMX_GPIO_NR(4, 12)
-	},
-	.sda = {
-		.i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA | PC,
-		.gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO_4_13 | PC,
-		.gp = IMX_GPIO_NR(4, 13)
-	}
-};
-
-/* I2C3, J15 - RGB connector */
-struct i2c_pads_info i2c_pad_info2 = {
-	.scl = {
-		.i2c_mode = MX6Q_PAD_GPIO_5__I2C3_SCL | PC,
-		.gpio_mode = MX6Q_PAD_GPIO_5__GPIO_1_5 | PC,
-		.gp = IMX_GPIO_NR(1, 5)
-	},
-	.sda = {
-		.i2c_mode = MX6Q_PAD_GPIO_16__I2C3_SDA | PC,
-		.gpio_mode = MX6Q_PAD_GPIO_16__GPIO_7_11 | PC,
-		.gp = IMX_GPIO_NR(7, 11)
-	}
-};
+#if defined(CONFIG_MX6DL) || defined(CONFIG_MX6S)
+#ifdef CONFIG_MX6Q
+#define GET_MX6_REF(ref) (cpu_is_mx6q() ? mx6q_##ref : mx6dl_solo_##ref)
+#define IOMUX_SETUP(list)  iomux_setup(mx6q_##list, ARRAY_SIZE(mx6q_##list), \
+		mx6dl_solo_##list, ARRAY_SIZE(mx6dl_solo_##list))
 
-iomux_v3_cfg_t usdhc3_pads[] = {
-       MX6Q_PAD_SD3_CLK__USDHC3_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-       MX6Q_PAD_SD3_CMD__USDHC3_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-       MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-       MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-       MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-       MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-       MX6Q_PAD_SD3_DAT5__GPIO_7_0    | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
-};
+int iomux_setup(iomux_v3_cfg_t *mx6q_pad_list, int mx6q_pad_cnt,
+		iomux_v3_cfg_t *mx6dl_solo_pad_list, int mx6dl_solo_pad_cnt)
+{
+	int mx6q = cpu_is_mx6q();
+	iomux_v3_cfg_t *p =  mx6q ? mx6q_pad_list : mx6dl_solo_pad_list;
+	int cnt = mx6q ? mx6q_pad_cnt : mx6dl_solo_pad_cnt;
 
-iomux_v3_cfg_t usdhc4_pads[] = {
-       MX6Q_PAD_SD4_CLK__USDHC4_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-       MX6Q_PAD_SD4_CMD__USDHC4_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-       MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-       MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-       MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-       MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-       MX6Q_PAD_NANDF_D6__GPIO_2_6    | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
-};
+	return imx_iomux_v3_setup_multiple_pads(p, cnt);
+}
 
-iomux_v3_cfg_t enet_pads1[] = {
-	MX6Q_PAD_ENET_MDIO__ENET_MDIO		| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6Q_PAD_ENET_MDC__ENET_MDC		| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	/* pin 35 - 1 (PHY_AD2) on reset */
-	MX6Q_PAD_RGMII_RXC__GPIO_6_30		| MUX_PAD_CTRL(NO_PAD_CTRL),
-	/* pin 32 - 1 - (MODE0) all */
-	MX6Q_PAD_RGMII_RD0__GPIO_6_25		| MUX_PAD_CTRL(NO_PAD_CTRL),
-	/* pin 31 - 1 - (MODE1) all */
-	MX6Q_PAD_RGMII_RD1__GPIO_6_27		| MUX_PAD_CTRL(NO_PAD_CTRL),
-	/* pin 28 - 1 - (MODE2) all */
-	MX6Q_PAD_RGMII_RD2__GPIO_6_28		| MUX_PAD_CTRL(NO_PAD_CTRL),
-	/* pin 27 - 1 - (MODE3) all */
-	MX6Q_PAD_RGMII_RD3__GPIO_6_29		| MUX_PAD_CTRL(NO_PAD_CTRL),
-	/* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */
-	MX6Q_PAD_RGMII_RX_CTL__GPIO_6_24	| MUX_PAD_CTRL(NO_PAD_CTRL),
-	/* pin 42 PHY nRST */
-	MX6Q_PAD_EIM_D23__GPIO_3_23		| MUX_PAD_CTRL(NO_PAD_CTRL),
-};
+#else
+#define GET_MX6_REF(ref) (mx6dl_solo_##ref)
+#define IOMUX_SETUP(list)  imx_iomux_v3_setup_multiple_pads(	\
+		mx6dl_solo_##list, ARRAY_SIZE(mx6dl_solo_##list))
+#endif
+#else
 
-iomux_v3_cfg_t enet_pads2[] = {
-	MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-};
+#define GET_MX6_REF(ref) (mx6q_##ref)
+#define IOMUX_SETUP(list)  imx_iomux_v3_setup_multiple_pads(	\
+		mx6q_##list, ARRAY_SIZE(mx6q_##list))
+#endif
 
-/* Button assignments for J14 */
-static iomux_v3_cfg_t button_pads[] = {
-	/* Menu */
-	MX6Q_PAD_NANDF_D1__GPIO_2_1	| MUX_PAD_CTRL(BUTTON_PAD_CTRL),
-	/* Back */
-	MX6Q_PAD_NANDF_D2__GPIO_2_2	| MUX_PAD_CTRL(BUTTON_PAD_CTRL),
-	/* Labelled Search (mapped to Power under Android) */
-	MX6Q_PAD_NANDF_D3__GPIO_2_3	| MUX_PAD_CTRL(BUTTON_PAD_CTRL),
-	/* Home */
-	MX6Q_PAD_NANDF_D4__GPIO_2_4	| MUX_PAD_CTRL(BUTTON_PAD_CTRL),
-	/* Volume Down */
-	MX6Q_PAD_GPIO_19__GPIO_4_5	| MUX_PAD_CTRL(BUTTON_PAD_CTRL),
-	/* Volume Up */
-	MX6Q_PAD_GPIO_18__GPIO_7_13	| MUX_PAD_CTRL(BUTTON_PAD_CTRL),
-};
+int dram_init(void)
+{
+	gd->ram_size = imx_ddr_size();
+	return 0;
+}
 
 static void setup_iomux_enet(void)
 {

@@ -203,30 +95,26 @@ static void setup_iomux_enet(void)
 	gpio_direction_output(IMX_GPIO_NR(6, 27), 1);
 	gpio_direction_output(IMX_GPIO_NR(6, 28), 1);
 	gpio_direction_output(IMX_GPIO_NR(6, 29), 1);
-	imx_iomux_v3_setup_multiple_pads(enet_pads1, ARRAY_SIZE(enet_pads1));
+	IOMUX_SETUP(enet_pads1);
 	gpio_direction_output(IMX_GPIO_NR(6, 24), 1);
 
 	/* Need delay 10ms according to KSZ9021 spec */
 	udelay(1000 * 10);
 	gpio_set_value(IMX_GPIO_NR(3, 23), 1);
 
-	imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2));
+	IOMUX_SETUP(enet_pads2);
 }
 
-iomux_v3_cfg_t usb_pads[] = {
-	MX6Q_PAD_GPIO_17__GPIO_7_12 | MUX_PAD_CTRL(NO_PAD_CTRL),
-};
-
 static void setup_iomux_uart(void)
 {
-	imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
-       imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
+	IOMUX_SETUP(uart1_pads);
+	IOMUX_SETUP(uart2_pads);
 }
 
 #ifdef CONFIG_USB_EHCI_MX6
 int board_ehci_hcd_init(int port)
 {
-	imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads));
+	IOMUX_SETUP(usb_pads);
 
 	/* Reset USB hub */
 	gpio_direction_output(IMX_GPIO_NR(7, 12), 0);

@@ -267,12 +155,10 @@ int board_mmc_init(bd_t *bis)
        for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
 	       switch (index) {
 	       case 0:
-		       imx_iomux_v3_setup_multiple_pads(
-			       usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
+		       IOMUX_SETUP(usdhc3_pads);
 		       break;
 	       case 1:
-		       imx_iomux_v3_setup_multiple_pads(
-			       usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
+		       IOMUX_SETUP(usdhc4_pads);
 		       break;
 	       default:
 		       printf("Warning: you configured more USDHC controllers"

@@ -294,19 +180,10 @@ u32 get_board_rev(void)
 }
 
 #ifdef CONFIG_MXC_SPI
-iomux_v3_cfg_t ecspi1_pads[] = {
-	/* SS1 */
-	MX6Q_PAD_EIM_D19__GPIO_3_19   | MUX_PAD_CTRL(SPI_PAD_CTRL),
-	MX6Q_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
-	MX6Q_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
-	MX6Q_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
-};
-
 void setup_spi(void)
 {
 	gpio_direction_output(CONFIG_SF_DEFAULT_CS, 1);
-	imx_iomux_v3_setup_multiple_pads(ecspi1_pads,
-					 ARRAY_SIZE(ecspi1_pads));
+	IOMUX_SETUP(ecspi1_pads);
 }
 #endif

@@ -342,8 +219,7 @@ int board_eth_init(bd_t *bis)
 
 static void setup_buttons(void)
 {
-	imx_iomux_v3_setup_multiple_pads(button_pads,
-					 ARRAY_SIZE(button_pads));
+	IOMUX_SETUP(button_pads);
 }
 
 #ifdef CONFIG_CMD_SATA

@@ -382,15 +258,17 @@ int board_early_init_f(void)
 
 int board_init(void)
 {
+	struct i2c_pads_info *p = GET_MX6_REF(i2c_pad_info);
+
        /* address of boot parameters */
        gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 
 #ifdef CONFIG_MXC_SPI
 	setup_spi();
 #endif
-	setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0);
-	setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
-	setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
+	setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &p[0]);
+	setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &p[1]);
+	setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &p[2]);
 
 #ifdef CONFIG_CMD_SATA
 	setup_sata();

@@ -401,9 +279,10 @@ int board_init(void)
 
 int checkboard(void)
 {
-       puts("Board: MX6Q-Sabre Lite\n");
-
-       return 0;
+	puts("Board: MX");
+	puts(get_imx_type(get_cpu_rev() >> 12));
+	puts("-Sabre Lite\n");
+	return 0;
 }
 
 struct button_key {

board/freescale/mx6qsabrelite/pads.h new file +172 -0

172 lines not on this page · raw message

Signature · 1 line

1.7.9.5

Otavio Salvador

2012-10-04 03:23 UTC #178 lore raw

PATCH v3 27/32 mx6qsabrelite: add support for mx6 solo/duallite

Quoted 4 lines · Troy Kisky

Signed-off-by Troy Kisky <[email protected]>

---
 board/freescale/mx6qsabrelite/mx6qsabrelite.c |  235 ++++++-------------------
 board/freescale/mx6qsabrelite/pads.h          |  172 ++++++++++++++++++

I'd say mx6qsabrelite could be renamed to mx6sabrelite so it is not confusing.

Signature · 3 lines

Otavio Salvador                             O.S. Systems
E-mail: otavio at ossystems.com.br  http://www.ossystems.com.br
Mobile: +55 53 9981-7854              http://projetos.ossystems.com.br

Troy Kisky

author

2012-10-04 23:34 UTC #179 lore raw

PATCH v3 27/32 mx6qsabrelite: add support for mx6 solo/duallite

Quoted 8 lines · Otavio Salvador

Quoted 4 lines · Troy Kisky
Signed-off-by Troy Kisky <[email protected]>
---
  board/freescale/mx6qsabrelite/mx6qsabrelite.c |  235 ++++++-------------------
  board/freescale/mx6qsabrelite/pads.h          |  172 ++++++++++++++++++
I'd say mx6qsabrelite could be renamed to mx6sabrelite so it is not confusing.

Both mx6qsabrelite.c and mx6qsabrelite.h should be renamed to drop the q. Also, the directory could be renamed ?
I think a follow on patch later to reduced conflicts with others work would be
appropriate.

Troy

Stefano Babic

2012-10-08 13:47 UTC #180 lore raw

PATCH v3 27/32 mx6qsabrelite: add support for mx6 solo/duallite

Quoted 9 lines · Troy Kisky

Quoted 8 lines · Otavio Salvador
Quoted 6 lines · Troy Kisky
Signed-off-by Troy Kisky <[email protected]>
---
  board/freescale/mx6qsabrelite/mx6qsabrelite.c |  235
++++++-------------------
  board/freescale/mx6qsabrelite/pads.h          |  172
++++++++++++++++++

Quoted 5 lines

Quoted 3 lines
I'd say mx6qsabrelite could be renamed to mx6sabrelite so it is not confusing.
Both mx6qsabrelite.c and mx6qsabrelite.h should be renamed to drop the q. Also, the directory could be renamed ?

Yes, it can, but add board's maintainer (Fabio) to the discussion.

Regards,
Stefano

Signature · 5 lines

=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

Troy Kisky

author

2012-10-04 01:47 UTC #181 lore raw

PATCH v3 28/32 mx6q_4x_mt41j128.cfg: add mx6 solo/duallite support

In reply to Troy Kisky

Signed-off-by Troy Kisky <[email protected]>

---
 board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg |  120 +++++++++++++++++++-------
 1 file changed, 87 insertions(+), 33 deletions(-)

board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg +87 ~~-33~~

index 9e20db0..f45f93e 100644
@@ -49,6 +49,15 @@ BOOT_FROM      sd
  *      Address   absolute address of the register
  *      value     value to be stored in the register
  */
+/*
+ * DDR3 settings
+ * MX6Q    ddr is limited to 1066 Mhz, currently 1056 MHz(528 MHz clock),
+ *	   memory bus width: 64 bits, x16/x32/x64
+ * MX6DL   ddr is limited to 800 MHz(400 MHz clock)
+ *	   memory bus width: 64 bits, x16/x32/x64
+ * MX6SOLO ddr is limited to 800 MHz(400 MHz clock)
+ *	   memory bus width: 32 bits, x16/x32
+ */
 WRITE_ENTRY1(IOM_DRAM_SDQS0, 0x00000030)
 WRITE_ENTRY1(IOM_DRAM_SDQS1, 0x00000030)
 WRITE_ENTRY1(IOM_DRAM_SDQS2, 0x00000030)

@@ -90,6 +99,7 @@ WRITE_ENTRY1(IOM_GRP_B6DS, 0x00000030)
 WRITE_ENTRY1(IOM_GRP_B7DS, 0x00000030)
 
 WRITE_ENTRY1(IOM_GRP_ADDDS, 0x00000030)
+
 /* (differential input) */
 WRITE_ENTRY1(IOM_DDRMODE_CTL, 0x00020000)
 /* disable ddr pullups */

@@ -119,48 +129,92 @@ WRITE_ENTRY1(MMDC_P0_MDMISC, 0x00081740)
  * MDSCR, con_req
  */
 WRITE_ENTRY1(MMDC_P0_MDSCR, 0x00008000)
+
 /*
- * MDCFG0, tRFC=0x56 clocks, tXS=0x5b clocks
- * tXP=4 clocks, tXPDLL=13 clocks
- * tFAW=24 clocks, cas=8 cycles
+ * MDCFG0,
+ * MX6Q:
+ *	tRFC=0x56 clocks, tXS=0x5b clocks, tXP=4 clocks, tXPDLL=13 clocks
+ *	tFAW=24 clocks, cas=8 cycles
+ * MX6DL/SOLO:
+ *	tRFC=0x6a clocks, tXS=0x6e clocks, tXP=3 clocks, tXPDLL=10 clocks
+ *	 tFAW=19 clocks, cas=6 cycles
  */
-WRITE_ENTRY1(MMDC_P0_MDCFG0, 0x555A7975)
+WRITE_ENTRY2(MMDC_P0_MDCFG0, 0x555A7975, 0x696D5323)
+
 /*
- * MDCFG1, tRDC=8, tRP=8, tRC=27,tRAS=20,tRPA=tRP+1,tWR=8
- * tMRD=4, tCWL=6
+ * MDCFG1,
+ * MX6Q:
+ *	tRDC=8, tRP=8, tRC=27, tRAS=20, tRPA=tRP+1, tWR=8, tMRD=4, tCWL=6
+ * MX6DL/SOLO:
+ *	tRDC=6, tRP=6, tRC=20, tRAS=15, tRPA=tRP+1, tWR=7, tMRD=4, tCWL=5
  */
-WRITE_ENTRY1(MMDC_P0_MDCFG1, 0xFF538E64)
+WRITE_ENTRY2(MMDC_P0_MDCFG1, 0xFF538E64, 0xB66E8C63)
+
 /*
  * MDCFG2,tDLLK=512,tRTP=4,tWTR=4,tRRD=4
  */
 WRITE_ENTRY1(MMDC_P0_MDCFG2, 0x01FF00DB)
 WRITE_ENTRY1(MMDC_P0_MDRWD, 0x000026D2)
-
 WRITE_ENTRY1(MMDC_P0_MDOR, 0x005B0E21)
-WRITE_ENTRY1(MMDC_P0_MDOTC, 0x09444040)
-WRITE_ENTRY1(MMDC_P0_MDPDC, 0x00025576)
 
 /*
- * Mx6Q - 64 bit wide ddr
+ * MMDC_MDOTC,
+ * MX6Q:
+ *	tAOFPD=2 cycles, tAONPD=2, tANPD=5, tAXPD=5, tODTLon=5, tODT_idle_off=5
+ * MX6DL/SOLO:
+ *	tAOFPD=1 cycles, tAONPD=1, tANPD=4, tAXPD=4, tODTLon=4, tODT_idle_off=4
+ */
+WRITE_ENTRY2(MMDC_P0_MDOTC, 0x09444040, 0x00333030)
+
+/*
+ * MDPDC - [17:16](2) => CKE pulse width = 3 cycles.
+ * [15:12](5) => PWDT_1 = 256 cycles
+ * [11:8](5) =>PWDR_0 = 256 cycles
+ * MX6Q:       [2:0](6) => CKSRE = 6 cycles, [5:3](6) => CKSRX = 6 cycles
+ * MX6DL/SOLO: [2:0](5) => CKSRE = 5 cycles, [5:3](5) => CKSRX = 5 cycles
+ */
+WRITE_ENTRY2(MMDC_P0_MDPDC, 0x00025576, 0x0002556D)
+
+/*
+ * MX6Q/DL - 64 bit wide ddr
  * last address is  (1<<28 (base) + 1<<30  - 1)  / (1<<25) =
  * 	1<<3 + 1<<5 - 1 = 8 + 0x20 -1 = 0x27
  */
+/*
+ * MX6SOLO - 32 bit wide ddr
+ * last address is  (1<<28 (base) + 1<<29  - 1)  / (1<<25) =
+ *	1<<3 + 1<<4 - 1 = 8 + 0x10 -1 = 0x17
+ */
 /* MDASP, CS0_END */
-WRITE_ENTRY1(MMDC_P0_MDASP, 0x00000027)
+WRITE_ENTRY3(MMDC_P0_MDASP, 0x00000027, 0x00000027, 0x00000017)
 /*
- * MDCTL, CS0 enable, CS1 disabled, row=14, col=10, burst=8, width=64/32bit
- * mx6q   : row+col+bank+width=14+10+3+3=30 = 1G
+ * MDCTL, CS0 enable, CS1 disabled, row=14, col=10, burst=8
+ * MX6Q/DL: width=64bit row+col+bank+width=14+10+3+3=30 = 1G
+ * MX6SOLO: width=32bit row+col+bank+width=14+10+3+2=29 = 512M
  */
-WRITE_ENTRY1(MMDC_P0_MDCTL, 0x831A0000)
+WRITE_ENTRY3(MMDC_P0_MDCTL, 0x831A0000, 0x831A0000, 0x83190000)
 
-/* MDSCR, con_req, LOAD MR2, CS0, A3,A10 set (CAS Write=6), RZQ/2 */
-WRITE_ENTRY1(MMDC_P0_MDSCR, 0x04088032)
+/*
+ * LOAD MR2: MDSCR, con_req,  CS0, A10 set - RZQ/2
+ * MX6Q:    A3 set(CAS Write=6)
+ * MX6DL/SOLO: (CAS Write=5)
+ */
+WRITE_ENTRY2(MMDC_P0_MDSCR, 0x04088032, 0x04008032)
 /* LOAD MR3, CS0 */
 WRITE_ENTRY1(MMDC_P0_MDSCR, 0x00008033)
-/* LOAD MR1, CS0, A1,A6 set Rtt=RZQ/2, ODI=RZQ/7 */
-WRITE_ENTRY1(MMDC_P0_MDSCR, 0x00428031)
-/* LOAD MR0, CS0, A6,A8,A11 set CAS=8, WR=8, DLL reset */
-WRITE_ENTRY1(MMDC_P0_MDSCR, 0x09408030)
+
+/*
+ * LOAD MR1, CS0
+ * MX6Q: A6 set: Rtt=RZQ/2, A1 set: ODI=RZQ/7
+ * MX6DL/SOLO: A2 set: Rtt=RZQ/4, ODI=RZQ/6
+ */
+WRITE_ENTRY2(MMDC_P0_MDSCR, 0x00428031, 0x00048031)
+
+/* LOAD MR0, CS0 A8 set: DLL Reset
+ * MX6Q: A6 set: CAS=8 A11 set: WR=8
+ * MX6DL/SOLO: A4 set: CAS=5, A9,A10 set: WR=7
+ */
+WRITE_ENTRY2(MMDC_P0_MDSCR, 0x09408030, 0x07208030)
 
 /* ZQ calibrate, CS0 */
 WRITE_ENTRY1(MMDC_P0_MDSCR, 0x04008040)

@@ -173,18 +227,18 @@ WRITE_ENTRY1(MMDC_P0_MPODTCTRL, 0x00022227)
 WRITE_ENTRY1(MMDC_P1_MPODTCTRL, 0x00022227)
 
 /* MPDGCTRL0/1 DQS GATE*/
-WRITE_ENTRY1(MMDC_P0_MPDGCTRL0, 0x434B0350)
-WRITE_ENTRY1(MMDC_P0_MPDGCTRL1, 0x034C0359)
-WRITE_ENTRY1(MMDC_P1_MPDGCTRL0, 0x434B0350)
-WRITE_ENTRY1(MMDC_P1_MPDGCTRL1, 0x03650348)
-WRITE_ENTRY1(MMDC_P0_MPRDDLCTL, 0x4436383B)
-WRITE_ENTRY1(MMDC_P1_MPRDDLCTL, 0x39393341)
-WRITE_ENTRY1(MMDC_P0_MPWRDLCTL, 0x35373933)
-WRITE_ENTRY1(MMDC_P1_MPWRDLCTL, 0x48254A36)
-WRITE_ENTRY1(MMDC_P0_MPWLDECTRL0, 0x001F001F)
-WRITE_ENTRY1(MMDC_P0_MPWLDECTRL1, 0x001F001F)
-WRITE_ENTRY1(MMDC_P1_MPWLDECTRL0, 0x00440044)
-WRITE_ENTRY1(MMDC_P1_MPWLDECTRL1, 0x00440044)
+WRITE_ENTRY2(MMDC_P0_MPDGCTRL0, 0x434B0350, 0x42350231)
+WRITE_ENTRY2(MMDC_P0_MPDGCTRL1, 0x034C0359, 0x021A0218)
+WRITE_ENTRY2(MMDC_P1_MPDGCTRL0, 0x434B0350, 0x42350231)
+WRITE_ENTRY2(MMDC_P1_MPDGCTRL1, 0x03650348, 0x021A0218)
+WRITE_ENTRY2(MMDC_P0_MPRDDLCTL, 0x4436383B, 0x4B4B4E49)
+WRITE_ENTRY2(MMDC_P1_MPRDDLCTL, 0x39393341, 0x4B4B4E49)
+WRITE_ENTRY2(MMDC_P0_MPWRDLCTL, 0x35373933, 0x3F3F3035)
+WRITE_ENTRY2(MMDC_P1_MPWRDLCTL, 0x48254A36, 0x3F3F3035)
+WRITE_ENTRY2(MMDC_P0_MPWLDECTRL0, 0x001F001F, 0x0040003C)
+WRITE_ENTRY2(MMDC_P0_MPWLDECTRL1, 0x001F001F, 0x0032003E)
+WRITE_ENTRY2(MMDC_P1_MPWLDECTRL0, 0x00440044, 0x0040003C)
+WRITE_ENTRY2(MMDC_P1_MPWLDECTRL1, 0x00440044, 0x0032003E)
 
 /* MPMUR0 - Complete calibration by forced measurement */
 WRITE_ENTRY1(MMDC_P0_MPMUR0, 0x00000800)

Signature · 1 line

1.7.9.5

Eric Nelson

2012-10-08 18:46 UTC #182 lore raw

PATCH v3 28/32 mx6q_4x_mt41j128.cfg: add mx6 solo/duallite support

Hi Troy,

This seems to be the patch where the rubber meets the road in much of this series.

Quoted 12 lines · Troy Kisky

Signed-off-by Troy Kisky<[email protected]>

---
  board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg |  120 +++++++++++++++++++-------
  1 file changed, 87 insertions(+), 33 deletions(-)

board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg +0 -0

index 9e20db0..f45f93e 100644
@@ -49,6 +49,15 @@ BOOT_FROM      sd
   *      Address   absolute address of the register
   *      value     value to be stored in the register

board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg BOOT_FROM sd · line 60

Quoted 10 lines

board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg +9 -0

   */
+/*
+ * DDR3 settings
+ * MX6Q    ddr is limited to 1066 Mhz, currently 1056 MHz(528 MHz clock),
+ *	   memory bus width: 64 bits, x16/x32/x64
+ * MX6DL   ddr is limited to 800 MHz(400 MHz clock)
+ *	   memory bus width: 64 bits, x16/x32/x64
+ * MX6SOLO ddr is limited to 800 MHz(400 MHz clock)
+ *	   memory bus width: 32 bits, x16/x32
+ */

This comment seems to be critical to understanding some of what's below, since now three **different** memory configurations are represented in this file.

At a minimum, the file name should be changed to get rid of '6q' and '4x' since those don't necessarily apply.

Quoted 21 lines

board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg +3 -3

  WRITE_ENTRY1(IOM_DRAM_SDQS0, 0x00000030)
  WRITE_ENTRY1(IOM_DRAM_SDQS1, 0x00000030)
  WRITE_ENTRY1(IOM_DRAM_SDQS2, 0x00000030)

@@ -90,6 +99,7 @@ WRITE_ENTRY1(IOM_GRP_B6DS, 0x00000030)
  WRITE_ENTRY1(IOM_GRP_B7DS, 0x00000030)
 
  WRITE_ENTRY1(IOM_GRP_ADDDS, 0x00000030)
+
  /* (differential input) */
  WRITE_ENTRY1(IOM_DDRMODE_CTL, 0x00020000)
  /* disable ddr pullups */

@@ -119,48 +129,92 @@ WRITE_ENTRY1(MMDC_P0_MDMISC, 0x00081740)
   * MDSCR, con_req
   */
  WRITE_ENTRY1(MMDC_P0_MDSCR, 0x00008000)
+
  /*
- * MDCFG0, tRFC=0x56 clocks, tXS=0x5b clocks
- * tXP=4 clocks, tXPDLL=13 clocks
- * tFAW=24 clocks, cas=8 cycles
+ * MDCFG0,

board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg WRITE_ENTRY1(MMDC_P0_MDMISC, 0x00081740) · line 143

Quoted 10 lines

board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg +8 -1

+ * MX6Q:
+ *	tRFC=0x56 clocks, tXS=0x5b clocks, tXP=4 clocks, tXPDLL=13 clocks
+ *	tFAW=24 clocks, cas=8 cycles
+ * MX6DL/SOLO:
+ *	tRFC=0x6a clocks, tXS=0x6e clocks, tXP=3 clocks, tXPDLL=10 clocks
+ *	 tFAW=19 clocks, cas=6 cycles
   */
-WRITE_ENTRY1(MMDC_P0_MDCFG0, 0x555A7975)
+WRITE_ENTRY2(MMDC_P0_MDCFG0, 0x555A7975, 0x696D5323)
+

Here's where I start to get lost in the macro-fu.

The WRITE_ENTRY1 macros make some sense to me in that they always write a single value to an offset whose address changes based on the processor type.

In order to understand WRITE_ENTRY2, you really have to know that the dual, solo, and sololite share many characteristics.

It's kinda hard to infer that knowledge from the code and I wonder if this structure will hold up under future revisions.

Quoted 44 lines

board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg +26 -7

  /*
- * MDCFG1, tRDC=8, tRP=8, tRC=27,tRAS=20,tRPA=tRP+1,tWR=8
- * tMRD=4, tCWL=6
+ * MDCFG1,
+ * MX6Q:
+ *	tRDC=8, tRP=8, tRC=27, tRAS=20, tRPA=tRP+1, tWR=8, tMRD=4, tCWL=6
+ * MX6DL/SOLO:
+ *	tRDC=6, tRP=6, tRC=20, tRAS=15, tRPA=tRP+1, tWR=7, tMRD=4, tCWL=5
   */
-WRITE_ENTRY1(MMDC_P0_MDCFG1, 0xFF538E64)
+WRITE_ENTRY2(MMDC_P0_MDCFG1, 0xFF538E64, 0xB66E8C63)
+
  /*
   * MDCFG2,tDLLK=512,tRTP=4,tWTR=4,tRRD=4
   */
  WRITE_ENTRY1(MMDC_P0_MDCFG2, 0x01FF00DB)
  WRITE_ENTRY1(MMDC_P0_MDRWD, 0x000026D2)
-
  WRITE_ENTRY1(MMDC_P0_MDOR, 0x005B0E21)
-WRITE_ENTRY1(MMDC_P0_MDOTC, 0x09444040)
-WRITE_ENTRY1(MMDC_P0_MDPDC, 0x00025576)
 
  /*
- * Mx6Q - 64 bit wide ddr
+ * MMDC_MDOTC,
+ * MX6Q:
+ *	tAOFPD=2 cycles, tAONPD=2, tANPD=5, tAXPD=5, tODTLon=5, tODT_idle_off=5
+ * MX6DL/SOLO:
+ *	tAOFPD=1 cycles, tAONPD=1, tANPD=4, tAXPD=4, tODTLon=4, tODT_idle_off=4
+ */
+WRITE_ENTRY2(MMDC_P0_MDOTC, 0x09444040, 0x00333030)
+
+/*
+ * MDPDC - [17:16](2) =>  CKE pulse width = 3 cycles.
+ * [15:12](5) =>  PWDT_1 = 256 cycles
+ * [11:8](5) =>PWDR_0 = 256 cycles
+ * MX6Q:       [2:0](6) =>  CKSRE = 6 cycles, [5:3](6) =>  CKSRX = 6 cycles
+ * MX6DL/SOLO: [2:0](5) =>  CKSRE = 5 cycles, [5:3](5) =>  CKSRX = 5 cycles
+ */
+WRITE_ENTRY2(MMDC_P0_MDPDC, 0x00025576, 0x0002556D)
+
+/*
+ * MX6Q/DL - 64 bit wide ddr
   * last address is  (1<<28 (base) + 1<<30  - 1)  / (1<<25) =

board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg WRITE_ENTRY1(MMDC_P0_MDMISC, 0x00081740) · line 189

Quoted 10 lines

board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg +6 -1

   * 	1<<3 + 1<<5 - 1 = 8 + 0x20 -1 = 0x27
   */
+/*
+ * MX6SOLO - 32 bit wide ddr
+ * last address is  (1<<28 (base) + 1<<29  - 1)  / (1<<25) =
+ *	1<<3 + 1<<4 - 1 = 8 + 0x10 -1 = 0x17
+ */
  /* MDASP, CS0_END */
-WRITE_ENTRY1(MMDC_P0_MDASP, 0x00000027)
+WRITE_ENTRY3(MMDC_P0_MDASP, 0x00000027, 0x00000027, 0x00000017)

Is it unreasonable to think there's a use case for 32-bit wide memory on a dual or quad?

What happens when we populate 256Mx16 DDR chips?

Sabre Auto is already doing this.

Quoted 61 lines

board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg +28 ~~-21~~

  /*
- * MDCTL, CS0 enable, CS1 disabled, row=14, col=10, burst=8, width=64/32bit
- * mx6q   : row+col+bank+width=14+10+3+3=30 = 1G
+ * MDCTL, CS0 enable, CS1 disabled, row=14, col=10, burst=8
+ * MX6Q/DL: width=64bit row+col+bank+width=14+10+3+3=30 = 1G
+ * MX6SOLO: width=32bit row+col+bank+width=14+10+3+2=29 = 512M
   */
-WRITE_ENTRY1(MMDC_P0_MDCTL, 0x831A0000)
+WRITE_ENTRY3(MMDC_P0_MDCTL, 0x831A0000, 0x831A0000, 0x83190000)
 
-/* MDSCR, con_req, LOAD MR2, CS0, A3,A10 set (CAS Write=6), RZQ/2 */
-WRITE_ENTRY1(MMDC_P0_MDSCR, 0x04088032)
+/*
+ * LOAD MR2: MDSCR, con_req,  CS0, A10 set - RZQ/2
+ * MX6Q:    A3 set(CAS Write=6)
+ * MX6DL/SOLO: (CAS Write=5)
+ */
+WRITE_ENTRY2(MMDC_P0_MDSCR, 0x04088032, 0x04008032)
  /* LOAD MR3, CS0 */
  WRITE_ENTRY1(MMDC_P0_MDSCR, 0x00008033)
-/* LOAD MR1, CS0, A1,A6 set Rtt=RZQ/2, ODI=RZQ/7 */
-WRITE_ENTRY1(MMDC_P0_MDSCR, 0x00428031)
-/* LOAD MR0, CS0, A6,A8,A11 set CAS=8, WR=8, DLL reset */
-WRITE_ENTRY1(MMDC_P0_MDSCR, 0x09408030)
+
+/*
+ * LOAD MR1, CS0
+ * MX6Q: A6 set: Rtt=RZQ/2, A1 set: ODI=RZQ/7
+ * MX6DL/SOLO: A2 set: Rtt=RZQ/4, ODI=RZQ/6
+ */
+WRITE_ENTRY2(MMDC_P0_MDSCR, 0x00428031, 0x00048031)
+
+/* LOAD MR0, CS0 A8 set: DLL Reset
+ * MX6Q: A6 set: CAS=8 A11 set: WR=8
+ * MX6DL/SOLO: A4 set: CAS=5, A9,A10 set: WR=7
+ */
+WRITE_ENTRY2(MMDC_P0_MDSCR, 0x09408030, 0x07208030)
 
  /* ZQ calibrate, CS0 */
  WRITE_ENTRY1(MMDC_P0_MDSCR, 0x04008040)

@@ -173,18 +227,18 @@ WRITE_ENTRY1(MMDC_P0_MPODTCTRL, 0x00022227)
  WRITE_ENTRY1(MMDC_P1_MPODTCTRL, 0x00022227)
 
  /* MPDGCTRL0/1 DQS GATE*/
-WRITE_ENTRY1(MMDC_P0_MPDGCTRL0, 0x434B0350)
-WRITE_ENTRY1(MMDC_P0_MPDGCTRL1, 0x034C0359)
-WRITE_ENTRY1(MMDC_P1_MPDGCTRL0, 0x434B0350)
-WRITE_ENTRY1(MMDC_P1_MPDGCTRL1, 0x03650348)
-WRITE_ENTRY1(MMDC_P0_MPRDDLCTL, 0x4436383B)
-WRITE_ENTRY1(MMDC_P1_MPRDDLCTL, 0x39393341)
-WRITE_ENTRY1(MMDC_P0_MPWRDLCTL, 0x35373933)
-WRITE_ENTRY1(MMDC_P1_MPWRDLCTL, 0x48254A36)
-WRITE_ENTRY1(MMDC_P0_MPWLDECTRL0, 0x001F001F)
-WRITE_ENTRY1(MMDC_P0_MPWLDECTRL1, 0x001F001F)
-WRITE_ENTRY1(MMDC_P1_MPWLDECTRL0, 0x00440044)
-WRITE_ENTRY1(MMDC_P1_MPWLDECTRL1, 0x00440044)
+WRITE_ENTRY2(MMDC_P0_MPDGCTRL0, 0x434B0350, 0x42350231)
+WRITE_ENTRY2(MMDC_P0_MPDGCTRL1, 0x034C0359, 0x021A0218)
+WRITE_ENTRY2(MMDC_P1_MPDGCTRL0, 0x434B0350, 0x42350231)
+WRITE_ENTRY2(MMDC_P1_MPDGCTRL1, 0x03650348, 0x021A0218)
+WRITE_ENTRY2(MMDC_P0_MPRDDLCTL, 0x4436383B, 0x4B4B4E49)

board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg WRITE_ENTRY1(MMDC_P0_MPODTCTRL, 0x00022227) · line 244

Quoted 10 lines

board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg +7 -0

+WRITE_ENTRY2(MMDC_P1_MPRDDLCTL, 0x39393341, 0x4B4B4E49)
+WRITE_ENTRY2(MMDC_P0_MPWRDLCTL, 0x35373933, 0x3F3F3035)
+WRITE_ENTRY2(MMDC_P1_MPWRDLCTL, 0x48254A36, 0x3F3F3035)
+WRITE_ENTRY2(MMDC_P0_MPWLDECTRL0, 0x001F001F, 0x0040003C)
+WRITE_ENTRY2(MMDC_P0_MPWLDECTRL1, 0x001F001F, 0x0032003E)
+WRITE_ENTRY2(MMDC_P1_MPWLDECTRL0, 0x00440044, 0x0040003C)
+WRITE_ENTRY2(MMDC_P1_MPWLDECTRL1, 0x00440044, 0x0032003E)
 
  /* MPMUR0 - Complete calibration by forced measurement */
  WRITE_ENTRY1(MMDC_P0_MPMUR0, 0x00000800)

It appears that only the memory configuration registers use WRITE_ENTRY2 or WRITE_ENTRY3 macros, and if so, I'd much rather see three separate files expressing the values, i.e.:

     mx6q_4x_mt41j128.cfg
     mx6dl_4x_mt41j128.cfg
     mx6s_2x_mt41j128.cfg

I'm not certain the processor part of the name is the right designator though. If I understand correctly, the differences in values between 6q and 6dl are mostly based on the memory speed.

Is that right?

It also seems valid that a board would want to use an i.mx6quad with a lower memory bus speed.

If the address differences are taken care of by the preprocessor, it seems that a set like this would be more appropriate (and processor independent):

     mx6_4x_mt41j128_1066.cfg
     mx6_4x_mt41j128_800.cfg
     mx6_2x_mt41j128_800.cfg

By splitting up the files, we can still check for differences between them using 'diff', and it will be easier to extend the set.

Note that meaningful diffs will require the use of symbolic names rather than varying addresses for registers.

It's also conceivable that calibration on a given layout will require per-board tweaks, but that's not clear at the moment.

You've clearly been through this in more detail than I have. Please let me know your thoughts.

Regards,

Eric

Troy Kisky

author

2012-10-08 21:08 UTC #183 lore raw

PATCH v3 28/32 mx6q_4x_mt41j128.cfg: add mx6 solo/duallite support

Quoted 36 lines · Eric Nelson

Hi Troy,
This seems to be the patch where the rubber meets the road in much of this series.
Quoted 15 lines · Troy Kisky
Signed-off-by Troy Kisky<[email protected]>
---
  board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg |  120 
+++++++++++++++++++-------
  1 file changed, 87 insertions(+), 33 deletions(-)
board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg +0 -0
index 9e20db0..f45f93e 100644
@@ -49,6 +49,15 @@ BOOT_FROM      sd
   *      Address   absolute address of the register
   *      value     value to be stored in the register
   */
board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg BOOT_FROM sd · line 61
Quoted 10 lines
board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg +9 -0
+/*
+ * DDR3 settings
+ * MX6Q    ddr is limited to 1066 Mhz, currently 1056 MHz(528 MHz 
 clock),
+ *       memory bus width: 64 bits, x16/x32/x64
+ * MX6DL   ddr is limited to 800 MHz(400 MHz clock)
+ *       memory bus width: 64 bits, x16/x32/x64
+ * MX6SOLO ddr is limited to 800 MHz(400 MHz clock)
+ *       memory bus width: 32 bits, x16/x32
+ */
This comment seems to be critical to understanding some of what's below, since now three **different** memory configurations are represented in this file.

Quoted 2 lines

At a minimum, the file name should be changed to get rid of '6q' and '4x' since those don't necessarily apply.

Right, my preference is to put at back in board/freescale/mx6qsabrelite/imximage.cfg
since MPDGCTRL0/1 DQS GATE registers and MMDC_MPRDDQBYnDL should be very board specific,
but that may be meet by objections from Fabio.

Quoted 35 lines

Quoted 22 lines

board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg +0 -0

  WRITE_ENTRY1(IOM_DRAM_SDQS0, 0x00000030)
  WRITE_ENTRY1(IOM_DRAM_SDQS1, 0x00000030)

WRITE_ENTRY1(IOM_DRAM_SDQS2, 0x00000030)

board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg +3 -3

@@ -90,6 +99,7 @@ WRITE_ENTRY1(IOM_GRP_B6DS, 0x00000030)
  WRITE_ENTRY1(IOM_GRP_B7DS, 0x00000030)
 
  WRITE_ENTRY1(IOM_GRP_ADDDS, 0x00000030)
+
  /* (differential input) */
  WRITE_ENTRY1(IOM_DDRMODE_CTL, 0x00020000)
  /* disable ddr pullups */

@@ -119,48 +129,92 @@ WRITE_ENTRY1(MMDC_P0_MDMISC, 0x00081740)
   * MDSCR, con_req
   */
  WRITE_ENTRY1(MMDC_P0_MDSCR, 0x00008000)
+
  /*
- * MDCFG0, tRFC=0x56 clocks, tXS=0x5b clocks
- * tXP=4 clocks, tXPDLL=13 clocks
- * tFAW=24 clocks, cas=8 cycles
+ * MDCFG0,

board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg WRITE_ENTRY1(MMDC_P0_MDMISC, 0x00081740) · line 143

Quoted 10 lines

board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg +8 -1

+ * MX6Q:
+ *    tRFC=0x56 clocks, tXS=0x5b clocks, tXP=4 clocks, tXPDLL=13 clocks
+ *    tFAW=24 clocks, cas=8 cycles
+ * MX6DL/SOLO:
+ *    tRFC=0x6a clocks, tXS=0x6e clocks, tXP=3 clocks, tXPDLL=10 clocks
+ *     tFAW=19 clocks, cas=6 cycles
   */
-WRITE_ENTRY1(MMDC_P0_MDCFG0, 0x555A7975)
+WRITE_ENTRY2(MMDC_P0_MDCFG0, 0x555A7975, 0x696D5323)
+

Here's where I start to get lost in the macro-fu.

Quoted 7 lines

The WRITE_ENTRY1 macros make some sense to me in that they always write a single value to an offset whose address changes based on the processor type.
In order to understand WRITE_ENTRY2, you really have to know that the dual, solo, and sololite share many characteristics.

RIght, ENTRY2 is used when there are differences between mx6q, and mx6dl/solo. In the case above, the value 0x555A7975 is written if a mx6quad, and the value 0x696D5323 is written if a mx6duallite or mx6solo.

Quoted 58 lines

It's kinda hard to infer that knowledge from the code and I wonder if this structure will hold up under future revisions.

Quoted 53 lines

board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg +10 -7

  /*
- * MDCFG1, tRDC=8, tRP=8, tRC=27,tRAS=20,tRPA=tRP+1,tWR=8
- * tMRD=4, tCWL=6
+ * MDCFG1,
+ * MX6Q:
+ *    tRDC=8, tRP=8, tRC=27, tRAS=20, tRPA=tRP+1, tWR=8, tMRD=4, tCWL=6
+ * MX6DL/SOLO:
+ *    tRDC=6, tRP=6, tRC=20, tRAS=15, tRPA=tRP+1, tWR=7, tMRD=4, tCWL=5
   */
-WRITE_ENTRY1(MMDC_P0_MDCFG1, 0xFF538E64)
+WRITE_ENTRY2(MMDC_P0_MDCFG1, 0xFF538E64, 0xB66E8C63)
+
  /*
   * MDCFG2,tDLLK=512,tRTP=4,tWTR=4,tRRD=4
   */
  WRITE_ENTRY1(MMDC_P0_MDCFG2, 0x01FF00DB)
  WRITE_ENTRY1(MMDC_P0_MDRWD, 0x000026D2)
-
  WRITE_ENTRY1(MMDC_P0_MDOR, 0x005B0E21)
-WRITE_ENTRY1(MMDC_P0_MDOTC, 0x09444040)
-WRITE_ENTRY1(MMDC_P0_MDPDC, 0x00025576)
 
  /*
- * Mx6Q - 64 bit wide ddr
+ * MMDC_MDOTC,
+ * MX6Q:
+ *    tAOFPD=2 cycles, tAONPD=2, tANPD=5, tAXPD=5, tODTLon=5,

tODT_idle_off=5
+ * MX6DL/SOLO:
+ * tAOFPD=1 cycles, tAONPD=1, tANPD=4, tAXPD=4, tODTLon=4,
tODT_idle_off=4
+ */

board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg +7 -0

+WRITE_ENTRY2(MMDC_P0_MDOTC, 0x09444040, 0x00333030)
+
+/*
+ * MDPDC - [17:16](2) =>  CKE pulse width = 3 cycles.
+ * [15:12](5) =>  PWDT_1 = 256 cycles
+ * [11:8](5) =>PWDR_0 = 256 cycles
+ * MX6Q:       [2:0](6) =>  CKSRE = 6 cycles, [5:3](6) =>  CKSRX = 6

cycles
+ * MX6DL/SOLO: [2:0](5) => CKSRE = 5 cycles, [5:3](5) => CKSRX = 5 cycles
+ */

board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg +7 -0

+WRITE_ENTRY2(MMDC_P0_MDPDC, 0x00025576, 0x0002556D)
+
+/*
+ * MX6Q/DL - 64 bit wide ddr
   * last address is  (1<<28 (base) + 1<<30  - 1)  / (1<<25) =
   *     1<<3 + 1<<5 - 1 = 8 + 0x20 -1 = 0x27
   */
+/*
+ * MX6SOLO - 32 bit wide ddr
+ * last address is  (1<<28 (base) + 1<<29  - 1)  / (1<<25) =

Quoted 8 lines

board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
Quoted 5 lines
+ * 1<<3 + 1<<4 - 1 = 8 + 0x10 -1 = 0x17
+ */
/* MDASP, CS0_END */
board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg +1 -1
-WRITE_ENTRY1(MMDC_P0_MDASP, 0x00000027)
+WRITE_ENTRY3(MMDC_P0_MDASP, 0x00000027, 0x00000027, 0x00000017)
Is it unreasonable to think there's a use case for 32-bit wide memory on a dual or quad?

Sure, they just would not use this file.

Quoted 4 lines

What happens when we populate 256Mx16 DDR chips?
Sabre Auto is already doing this.

Again, definitely a new file would be needed.

Quoted 78 lines

Quoted 63 lines

/*
- * MDCTL, CS0 enable, CS1 disabled, row=14, col=10, burst=8, width=64/32bit
- * mx6q : row+col+bank+width=14+10+3+3=30 = 1G
+ * MDCTL, CS0 enable, CS1 disabled, row=14, col=10, burst=8
+ * MX6Q/DL: width=64bit row+col+bank+width=14+10+3+3=30 = 1G
+ * MX6SOLO: width=32bit row+col+bank+width=14+10+3+2=29 = 512M */

board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg +25 ~~-19~~

-WRITE_ENTRY1(MMDC_P0_MDCTL, 0x831A0000)
+WRITE_ENTRY3(MMDC_P0_MDCTL, 0x831A0000, 0x831A0000, 0x83190000)
 
-/* MDSCR, con_req, LOAD MR2, CS0, A3,A10 set (CAS Write=6), RZQ/2 */
-WRITE_ENTRY1(MMDC_P0_MDSCR, 0x04088032)
+/*
+ * LOAD MR2: MDSCR, con_req,  CS0, A10 set - RZQ/2
+ * MX6Q:    A3 set(CAS Write=6)
+ * MX6DL/SOLO: (CAS Write=5)
+ */
+WRITE_ENTRY2(MMDC_P0_MDSCR, 0x04088032, 0x04008032)
  /* LOAD MR3, CS0 */
  WRITE_ENTRY1(MMDC_P0_MDSCR, 0x00008033)
-/* LOAD MR1, CS0, A1,A6 set Rtt=RZQ/2, ODI=RZQ/7 */
-WRITE_ENTRY1(MMDC_P0_MDSCR, 0x00428031)
-/* LOAD MR0, CS0, A6,A8,A11 set CAS=8, WR=8, DLL reset */
-WRITE_ENTRY1(MMDC_P0_MDSCR, 0x09408030)
+
+/*
+ * LOAD MR1, CS0
+ * MX6Q: A6 set: Rtt=RZQ/2, A1 set: ODI=RZQ/7
+ * MX6DL/SOLO: A2 set: Rtt=RZQ/4, ODI=RZQ/6
+ */
+WRITE_ENTRY2(MMDC_P0_MDSCR, 0x00428031, 0x00048031)
+
+/* LOAD MR0, CS0 A8 set: DLL Reset
+ * MX6Q: A6 set: CAS=8 A11 set: WR=8
+ * MX6DL/SOLO: A4 set: CAS=5, A9,A10 set: WR=7
+ */
+WRITE_ENTRY2(MMDC_P0_MDSCR, 0x09408030, 0x07208030)
 
  /* ZQ calibrate, CS0 */
  WRITE_ENTRY1(MMDC_P0_MDSCR, 0x04008040)

@@ -173,18 +227,18 @@ WRITE_ENTRY1(MMDC_P0_MPODTCTRL, 0x00022227)
  WRITE_ENTRY1(MMDC_P1_MPODTCTRL, 0x00022227)
 
  /* MPDGCTRL0/1 DQS GATE*/
-WRITE_ENTRY1(MMDC_P0_MPDGCTRL0, 0x434B0350)
-WRITE_ENTRY1(MMDC_P0_MPDGCTRL1, 0x034C0359)
-WRITE_ENTRY1(MMDC_P1_MPDGCTRL0, 0x434B0350)
-WRITE_ENTRY1(MMDC_P1_MPDGCTRL1, 0x03650348)
-WRITE_ENTRY1(MMDC_P0_MPRDDLCTL, 0x4436383B)
-WRITE_ENTRY1(MMDC_P1_MPRDDLCTL, 0x39393341)
-WRITE_ENTRY1(MMDC_P0_MPWRDLCTL, 0x35373933)
-WRITE_ENTRY1(MMDC_P1_MPWRDLCTL, 0x48254A36)
-WRITE_ENTRY1(MMDC_P0_MPWLDECTRL0, 0x001F001F)
-WRITE_ENTRY1(MMDC_P0_MPWLDECTRL1, 0x001F001F)
-WRITE_ENTRY1(MMDC_P1_MPWLDECTRL0, 0x00440044)
-WRITE_ENTRY1(MMDC_P1_MPWLDECTRL1, 0x00440044)
+WRITE_ENTRY2(MMDC_P0_MPDGCTRL0, 0x434B0350, 0x42350231)
+WRITE_ENTRY2(MMDC_P0_MPDGCTRL1, 0x034C0359, 0x021A0218)
+WRITE_ENTRY2(MMDC_P1_MPDGCTRL0, 0x434B0350, 0x42350231)
+WRITE_ENTRY2(MMDC_P1_MPDGCTRL1, 0x03650348, 0x021A0218)
+WRITE_ENTRY2(MMDC_P0_MPRDDLCTL, 0x4436383B, 0x4B4B4E49)

board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg WRITE_ENTRY1(MMDC_P0_MPODTCTRL, 0x00022227) · line 244

Quoted 10 lines

board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg +7 -0

+WRITE_ENTRY2(MMDC_P1_MPRDDLCTL, 0x39393341, 0x4B4B4E49)
+WRITE_ENTRY2(MMDC_P0_MPWRDLCTL, 0x35373933, 0x3F3F3035)
+WRITE_ENTRY2(MMDC_P1_MPWRDLCTL, 0x48254A36, 0x3F3F3035)
+WRITE_ENTRY2(MMDC_P0_MPWLDECTRL0, 0x001F001F, 0x0040003C)
+WRITE_ENTRY2(MMDC_P0_MPWLDECTRL1, 0x001F001F, 0x0032003E)
+WRITE_ENTRY2(MMDC_P1_MPWLDECTRL0, 0x00440044, 0x0040003C)
+WRITE_ENTRY2(MMDC_P1_MPWLDECTRL1, 0x00440044, 0x0032003E)
 
  /* MPMUR0 - Complete calibration by forced measurement */
  WRITE_ENTRY1(MMDC_P0_MPMUR0, 0x00000800)

It appears that only the memory configuration registers use WRITE_ENTRY2 or WRITE_ENTRY3 macros, and if so, I'd much rather see three separate files expressing the values, i.e.:

Quoted 3 lines

    mx6q_4x_mt41j128.cfg
    mx6dl_4x_mt41j128.cfg
    mx6s_2x_mt41j128.cfg

That is definitely a valid option. But you lose the common settings of the iomux registers. Cut-n-pasting the files isn't so bad I guess, but updates such as
mx6q_4x_mt41j128.cfg: use ddr3 mode for reset

Bits 19-18 of IOMUXC_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET should be 3 for DDR3 mode. The current value of 0 is reserved in TRM.

Signed-off-by Troy Kisky <[email protected]>

(quoted diff) +0 -0

b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
index b859e2f..9c622c8 100644

board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg +1 -1

@@ -72,7 +72,7 @@ WRITE_ENTRY1(IOM_DRAM_RAS, 0x00020030)
  WRITE_ENTRY1(IOM_DRAM_SDCLK_0, 0x00020030)
  WRITE_ENTRY1(IOM_DRAM_SDCLK_1, 0x00020030)
 
-WRITE_ENTRY1(IOM_DRAM_RESET, 0x00020030)
+WRITE_ENTRY1(IOM_DRAM_RESET, 0x000e0030)
  WRITE_ENTRY1(IOM_DRAM_SDCKE0, 0x00003000)
  WRITE_ENTRY1(IOM_DRAM_SDCKE1, 0x00003000)
  WRITE_ENTRY1(IOM_DRAM_SDBA2, 0x00000000)

Would then need to be applied to all three files.

Quoted 7 lines

I'm not certain the processor part of the name is the right designator though. If I understand correctly, the differences in values between 6q and 6dl are mostly based on the memory speed.
Is that right?

Correct...

Quoted 3 lines

It also seems valid that a board would want to use an i.mx6quad with a lower memory bus speed.

Especially if there is a layout problem.

Quoted 8 lines

If the address differences are taken care of by the preprocessor, it seems that a set like this would be more appropriate (and processor independent):
    mx6_4x_mt41j128_1066.cfg
    mx6_4x_mt41j128_800.cfg
    mx6_2x_mt41j128_800.cfg

Right, this is definitely a valid option. And if different boards calibrated their DDR to the same settings (DQS and byte delays) it would make more sense.

But I still see this file as board specific and not so much memory type specific.

Quoted 21 lines

By splitting up the files, we can still check for differences between them using 'diff', and it will be easier to extend the set.
Note that meaningful diffs will require the use of symbolic names rather than varying addresses for registers.
It's also conceivable that calibration on a given layout will require per-board tweaks, but that's not clear at the moment.
You've clearly been through this in more detail than I have. Please let me know your thoughts.
Regards,
Eric

Troy Kisky

author

2012-10-04 01:47 UTC #184 lore raw

PATCH v3 29/32 Add boards for sabrelite variants mx6s(solo) and mx6dl(duallite)

In reply to Troy Kisky

mx6dlsabrelite - for duallite
mx6ssabrelite - for solo

Signed-off-by Troy Kisky <[email protected]>

---
 boards.cfg                      |    4 +++-
 include/configs/mx6qsabrelite.h |    1 -
 2 files changed, 3 insertions(+), 2 deletions(-)

boards.cfg +3 -1

index e9e073e..abc95d4 100644
@@ -232,7 +232,9 @@ ima3-mx53                    arm         armv7       ima3-mx53           esg
 vision2                      arm         armv7       vision2             ttcontrol      mx5		vision2:IMX_CONFIG=board/ttcontrol/vision2/imximage_hynix.cfg
 mx6qarm2                     arm         armv7       mx6qarm2            freescale      mx6		mx6qarm2:IMX_CONFIG=board/freescale/mx6qarm2/imximage.cfg
 mx6qsabreauto                arm         armv7       mx6qsabreauto       freescale      mx6		mx6qsabreauto:IMX_CONFIG=board/freescale/mx6qsabreauto/imximage.cfg
-mx6qsabrelite                arm         armv7       mx6qsabrelite       freescale      mx6		mx6qsabrelite:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
+mx6dlsabrelite               arm         armv7       mx6qsabrelite       freescale      mx6		mx6qsabrelite:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg,MX6DL
+mx6qsabrelite                arm         armv7       mx6qsabrelite       freescale      mx6		mx6qsabrelite:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg,MX6Q
+mx6ssabrelite                arm         armv7       mx6qsabrelite       freescale      mx6		mx6qsabrelite:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg,MX6S
 mx6qsabresd                  arm         armv7       mx6qsabresd         freescale      mx6		mx6qsabresd:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
 cm_t35                       arm         armv7       cm_t35              -              omap3
 omap3_overo                  arm         armv7       overo               -              omap3

include/configs/mx6qsabrelite.h +0 -1

index 6a10232..8890e4c 100644
@@ -23,7 +23,6 @@
 #define __CONFIG_H
 
 #define CONFIG_MX6
-#define CONFIG_MX6Q
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO

Signature · 1 line

1.7.9.5

Troy Kisky

author

2012-10-04 01:47 UTC #185 lore raw

PATCH v3 30/32 mx6qsabrelite: change CONFIG_SYS_PROMPT

In reply to Troy Kisky

The prompt is not appropriate if not running on
a mx6q processor.

Signed-off-by Troy Kisky <[email protected]>

---
 include/configs/mx6qsabrelite.h |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

include/configs/mx6qsabrelite.h +1 -1

index 8890e4c..8fd35a6 100644
@@ -180,7 +180,7 @@
 /* Miscellaneous configurable options */
 #define CONFIG_SYS_LONGHELP
 #define CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_PROMPT	       "MX6QSABRELITE U-Boot > "
+#define CONFIG_SYS_PROMPT	       "U-Boot > "
 #define CONFIG_AUTO_COMPLETE
 #define CONFIG_SYS_CBSIZE	       256

Signature · 1 line

1.7.9.5

Otavio Salvador

2012-10-04 03:00 UTC #186 lore raw

PATCH v3 30/32 mx6qsabrelite: change CONFIG_SYS_PROMPT

Quoted 4 lines · Troy Kisky

The prompt is not appropriate if not running on
a mx6q processor.
Signed-off-by Troy Kisky <[email protected]>

But in this case the board name will change, no?

Signature · 3 lines

Otavio Salvador                             O.S. Systems
E-mail: otavio at ossystems.com.br  http://www.ossystems.com.br
Mobile: +55 53 9981-7854              http://projetos.ossystems.com.br

Troy Kisky

author

2012-10-04 23:28 UTC #187 lore raw

PATCH v3 30/32 mx6qsabrelite: change CONFIG_SYS_PROMPT

Quoted 8 lines · Otavio Salvador

Quoted 4 lines · Troy Kisky
The prompt is not appropriate if not running on
a mx6q processor.
Signed-off-by Troy Kisky <[email protected]>
But in this case the board name will change, no?

No, patch 29/32 sets the new boards to use the same config file (mx6qsabrelite.h) only adding ",MX6DL" or ",MX6S" or ",MX6Q" to the end of the line in boards.cfg

Troy

Stefano Babic

2012-10-08 13:54 UTC #188 lore raw

PATCH v3 30/32 mx6qsabrelite: change CONFIG_SYS_PROMPT

Quoted 6 lines · Troy Kisky

Quoted 5 lines · Otavio Salvador
Quoted 3 lines · Troy Kisky
The prompt is not appropriate if not running on
a mx6q processor.

Quoted 6 lines

Quoted 3 lines
Quoted 1 line
Signed-off-by Troy Kisky <[email protected]>
But in this case the board name will change, no?
No, patch 29/32 sets the new boards to use the same config file (mx6qsabrelite.h) only adding ",MX6DL" or ",MX6S" or ",MX6Q" to the end of the line in boards.cfg

This means that CONFIG_MX6Dx is set. You can use it to set appropriately the prompt or use a more generic name including the board name, as "MX6SABRELITE U-Boot > ". The board is always the same, what is different is the SOC. I can compare this with a motherboard for a PC that can mount a dual or quad core. The board is always the same, and how many core are running is read in a different way (cat /proc/cpuinfo under Linux or get_cpu_rev in U-Boot with the patch you sent).

Best regards,
Stefano

Signature · 5 lines

=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

Troy Kisky

author

2012-10-08 21:58 UTC #189 lore raw

PATCH v3 30/32 mx6qsabrelite: change CONFIG_SYS_PROMPT

Quoted 8 lines · Stefano Babic

Quoted 7 lines · Troy Kisky
Quoted 6 lines · Otavio Salvador
Quoted 4 lines · Troy Kisky
The prompt is not appropriate if not running on
a mx6q processor.
Signed-off-by Troy Kisky <[email protected]>

Quoted 8 lines

Quoted 5 lines
Quoted 2 lines
But in this case the board name will change, no?
No, patch 29/32 sets the new boards to use the same config file (mx6qsabrelite.h) only adding ",MX6DL" or ",MX6S" or ",MX6Q" to the end of the line in boards.cfg
This means that CONFIG_MX6Dx is set. You can use it to set appropriately the prompt or use a more generic name including the board name, as "MX6SABRELITE U-Boot > ". The board is always the same, what is

I can live with "MX6SABRELITE U-Boot" but I prefer a plain "U-Boot". The rest seems a waste of screen real estate. The long u-boot commands are more likely to wrap. Anyone else have an opinion???

Thanks
Troy

Fabio Estevam

reviewer

2012-10-08 22:05 UTC #190 lore raw

PATCH v3 30/32 mx6qsabrelite: change CONFIG_SYS_PROMPT

Quoted 3 lines · Troy Kisky

I can live with "MX6SABRELITE U-Boot" but I prefer a plain "U-Boot". The rest seems a waste of screen real estate. The long u-boot commands are more likely to wrap. Anyone else have an opinion???

Agreed.

stefano babic

2012-10-08 22:18 UTC #191 lore raw

PATCH v3 30/32 mx6qsabrelite: change CONFIG_SYS_PROMPT

In reply to Troy Kisky

Am 08/10/2012 23:58, schrieb Troy Kisky:

Quoted 14 lines · Stefano Babic

Quoted 13 lines · Troy Kisky
Quoted 12 lines · Otavio Salvador
Quoted 8 lines
Quoted 4 lines · Troy Kisky
The prompt is not appropriate if not running on
a mx6q processor.
Signed-off-by Troy Kisky <[email protected]>
But in this case the board name will change, no?
No, patch 29/32 sets the new boards to use the same config file (mx6qsabrelite.h) only adding ",MX6DL" or ",MX6S" or ",MX6Q" to the end of the line in boards.cfg

Quoted 7 lines

Quoted 3 lines
This means that CONFIG_MX6Dx is set. You can use it to set appropriately the prompt or use a more generic name including the board name, as "MX6SABRELITE U-Boot > ". The board is always the same, what is
I can live with "MX6SABRELITE U-Boot" but I prefer a plain "U-Boot". The rest seems a waste of screen real estate. The long u-boot commands are more likely to wrap.

Personally agree, shorter is better.

Regards,
Stefano

Signature · 5 lines

=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: office at denx.de
=====================================================================

Eric Nelson

2012-10-08 22:22 UTC #192 lore raw

PATCH v3 30/32 mx6qsabrelite: change CONFIG_SYS_PROMPT

Quoted 19 lines · stefano babic

Am 08/10/2012 23:58, schrieb Troy Kisky:
Quoted 18 lines · Stefano Babic
Quoted 16 lines · Troy Kisky
Quoted 6 lines · Otavio Salvador
Quoted 5 lines
Quoted 3 lines · Troy Kisky
The prompt is not appropriate if not running on
a mx6q processor.
Quoted 6 lines
Quoted 3 lines
Quoted 1 line
Signed-off-by Troy Kisky<[email protected]>
But in this case the board name will change, no?
No, patch 29/32 sets the new boards to use the same config file (mx6qsabrelite.h) only adding ",MX6DL" or ",MX6S" or ",MX6Q" to the end of the line in boards.cfg
This means that CONFIG_MX6Dx is set. You can use it to set appropriately the prompt or use a more generic name including the board name, as "MX6SABRELITE U-Boot> ". The board is always the same, what is

Quoted 6 lines

Quoted 3 lines
I can live with "MX6SABRELITE U-Boot" but I prefer a plain "U-Boot". The rest seems a waste of screen real estate. The long u-boot commands are more likely to wrap.
Personally agree, shorter is better.

Shh! Nobody tell the marketing folks!

Eric Nelson

2012-10-08 22:21 UTC #193 lore raw

PATCH v3 30/32 mx6qsabrelite: change CONFIG_SYS_PROMPT

In reply to Troy Kisky

Quoted 14 lines · Troy Kisky

Quoted 13 lines · Stefano Babic
Quoted 12 lines · Troy Kisky
Quoted 8 lines · Otavio Salvador
Quoted 4 lines · Troy Kisky
The prompt is not appropriate if not running on
a mx6q processor.
Signed-off-by Troy Kisky <[email protected]>
But in this case the board name will change, no?
No, patch 29/32 sets the new boards to use the same config file (mx6qsabrelite.h) only adding ",MX6DL" or ",MX6S" or ",MX6Q" to the end of the line in boards.cfg

Quoted 8 lines

Quoted 3 lines
This means that CONFIG_MX6Dx is set. You can use it to set appropriately the prompt or use a more generic name including the board name, as "MX6SABRELITE U-Boot > ". The board is always the same, what is
I can live with "MX6SABRELITE U-Boot" but I prefer a plain "U-Boot". The rest seems a waste of screen real estate. The long u-boot commands are more likely to wrap. Anyone else have an opinion???

I'm with you, for selfish reasons.

When I write up instructions like these, things tend to wrap with the longer prompt (so I usually hand-edit them):

http://boundarydevices.com/configuring-i-mx6-machines-different-screens-nitrogen6x-sabre-lite/#timesys

The marketing value of MX6SABRELITE is pretty small when someone as one on their desk.

Regards,

Eric

Troy Kisky

author

2012-10-04 01:47 UTC #194 lore raw

PATCH v3 31/32 parse_helper: add expression evaluation

In reply to Troy Kisky

Basic expressions with order precedence is
now supported.
ie. (----3 + ((1+2*3)/--2 + --5 *(8/4))) is 16.

Signed-off-by Troy Kisky <[email protected]>

---
 tools/parse_helper.c |  172 +++++++++++++++++++++++++++++++++++++++++++++++---
 1 file changed, 162 insertions(+), 10 deletions(-)

tools/parse_helper.c +162 ~~-10~~

index 0a5c5f6..50be832 100644
@@ -97,20 +97,172 @@ int ph_skip_comma(struct parse_helper *ph)
 	}
 }
 
+static const char precedence[] = {
+	/* (  +  -  *  /  &  ^  |  ) */
+	   0, 2, 2, 1, 1, 3, 4, 5, 6
+};
+static const char unary_operations[]  = "(+-";
+static const char binary_operations[] = " +-*/&^|)";
+
+static uint32_t do_func(uint32_t val1, uint32_t val2, int op)
+{
+	switch (op) {
+	case 1:
+		return val1 + val2;
+	case 2:
+		return val1 - val2;
+	case 3:
+		return val1 * val2;
+	case 4:
+		return val1 / val2;
+	case 5:
+		return val1 & val2;
+	case 6:
+		return val1 ^ val2;
+	case 7:
+		return val1 | val2;
+	}
+	fprintf(stderr, "Error: in func %s: val1=%d val2=%d op = %d\n",
+			__func__, val1, val2, op);
+	exit(EXIT_FAILURE);
+}
+
+static int find_op(char c, const char *p)
+{
+	int i;
+	for (i = 0; ; i++) {
+		if (c == p[i])
+			return i;
+		if (!p[i])
+			break;
+	}
+	return -1;
+}
+
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
 int ph_get_value(struct parse_helper *ph, uint32_t *pval)
 {
 	char *endptr;
-	uint32_t value;
+	int op_i = 0;
+	int val_i = 0;
+	unsigned char op[16];
+	uint32_t val[16];
+	int unary = 1;
+	char *p;
 
-	if (ph_skip_separators(ph))
-		return -1;
-	errno = 0;
-	value = strtoul(ph->p, &endptr, 16);
-	if (errno || (ph->p == endptr))
-		return -1;
-	*pval = value;
-	ph->p = endptr;
-	return 0;
+	p = ph->p;
+	for (;;) {
+		char c;
+		int i, j;
+		const char *ops = unary ? unary_operations : binary_operations;
+
+		if (unary) {
+			ph->p = p;
+			if (ph_skip_separators(ph))
+				return -1;
+			p = ph->p;
+			c = *p;
+		} else {
+			for (;;) {
+				c = *p;
+				if ((c != ' ') && (c != '\t'))
+					break;
+				p++;
+			}
+		}
+		i = find_op(c, ops);
+		debug("%d,%c,%d:%s\n", i, c, unary, p);
+		if ((i < 0) && unary) {
+			if (val_i >= ARRAY_SIZE(val))
+				return -1;
+			errno = 0;
+			val[val_i++] = strtoul(p, &endptr, 16);
+			if (errno || (p == endptr)) {
+				ph->p = p;
+				return -1;
+			}
+			p = endptr;
+			unary = 0;
+			debug("val[%d]=%x,%d,%d\n", val_i - 1, val[val_i - 1],
+					op_i, val_i);
+do_unary:
+			while (op_i) {
+				j = op[op_i - 1];
+				if (!(j & 0x80))
+					break;
+				op_i--;
+				val[val_i - 1] = do_func(0,
+						val[val_i - 1], j & 0x7f);
+				debug("un:%d,%x,%d,%d\n", val[val_i - 1], j,
+						op_i, val_i);
+			}
+			continue;
+		}
+		if (i < 0) {
+			c = 0;
+			i = 8;
+		} else {
+			p++;
+		}
+		if (c == '(') {
+			if (op_i >= ARRAY_SIZE(op))
+				return -1;
+			op[op_i++] = i;
+			debug("op[%d]=%x,%d,%d\n", op_i - 1, op[op_i - 1],
+					op_i, val_i);
+			unary = 1;
+			continue;
+		}
+		for (;;) {
+			if (!op_i || unary)
+				break;
+			j = op[op_i - 1];
+			if (j == 0) {
+				if (c == ')') {
+					op_i--;
+					goto do_unary;
+				}
+				break;
+			}
+			if ((j & 0x80)) {
+				op_i--;
+				val[val_i - 1] = do_func(0,
+						val[val_i - 1], j & 0x7f);
+				debug("unary:%d,%x\n", val[val_i - 1], j);
+				continue;
+			}
+			if (precedence[i] < precedence[j])
+				break;
+			if (val_i < 2)
+				return -1;
+			op_i--;
+			val[val_i - 2] = do_func(val[val_i - 2],
+					val[val_i - 1], j);
+			val_i--;
+			debug("binary:%d,%x,%d,%d\n", val[val_i - 1], j,
+					op_i, val_i);
+		}
+		if (c == ')') {
+			fprintf(stderr, "Error: unmatched parenthesis\n");
+			return -1;
+		}
+		if (i == 8) {
+			if ((op_i != 0) || (val_i != 1)) {
+				fprintf(stderr, "Error: syntax %d %d\n",
+						op_i, val_i);
+				return -1;
+			}
+			ph->p = p;
+			*pval = val[0];
+			return 0;
+		}
+		if (op_i >= ARRAY_SIZE(op))
+			return -1;
+		op[op_i++] = i | (unary << 7);
+		debug("op[%d]=%x,%d,%d\n", op_i - 1, op[op_i - 1], op_i, val_i);
+		unary = 1;
+	}
 }
 
 /*

Signature · 1 line

1.7.9.5

Troy Kisky

author

2012-10-04 01:47 UTC #195 lore raw

PATCH v3 32/32 imx-mkimage.h: use base + offset syntax

In reply to Troy Kisky

Now that expression work, we can delete
the redundant MMC_P1_xxx defines and
just define MMC_P0 and MMC_P1 bases.

The other addresses are changed to a base
+ offset syntax as well.

Signed-off-by Troy Kisky <[email protected]>

---
 arch/arm/include/asm/arch-mx6/imx-mkimage.h  |  205 ++++++++++++--------------
 board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg |   90 +++++------
 2 files changed, 136 insertions(+), 159 deletions(-)

arch/arm/include/asm/arch-mx6/imx-mkimage.h +91 ~~-114~~

index 4abd3f1..dc9dadf 100644
@@ -6,124 +6,101 @@
 #ifndef __ASM_ARCH_IMX_MKIMAGE_H__
 #define __ASM_ARCH_IMX_MKIMAGE_H__
 
-#define IOMUXC_GPR4		0x020e0010
-#define IOMUXC_GPR6		0x020e0018
-#define IOMUXC_GPR7		0x020e001c
-
-/* mx6 duallite and solo have same offsets */
+#define IRAM_FREE_START		0x00907000
+#define MMDC_P0			0x021b0000
+#define MMDC_P1			0x021b4000
+#define IOMUXC_BASE		0x020e0000
+#define CCM_BASE		0x020c4000
 
-#define IOM_DRAM_DQM0		MA(0x020e05ac, 0x020e0470, 0x0)
-#define IOM_DRAM_DQM1		MA(0x020e05b4, 0x020e0474, 0x0)
-#define IOM_DRAM_DQM2		MA(0x020e0528, 0x020e0478, 0x0)
-#define IOM_DRAM_DQM3		MA(0x020e0520, 0x020e047c, 0x0)
-#define IOM_DRAM_DQM4		MA(0x020e0514, 0x020e0480, 0x0)
-#define IOM_DRAM_DQM5		MA(0x020e0510, 0x020e0484, 0x0)
-#define IOM_DRAM_DQM6		MA(0x020e05bc, 0x020e0488, 0x0)
-#define IOM_DRAM_DQM7		MA(0x020e05c4, 0x020e048c, 0x0)
-
-#define IOM_DRAM_CAS		MA(0x020e056c, 0x020e0464, 0x0)
-#define IOM_DRAM_RAS		MA(0x020e0578, 0x020e0490, 0x0)
-#define IOM_DRAM_RESET		MA(0x020e057c, 0x020e0494, 0x0)
-#define IOM_DRAM_SDCLK_0	MA(0x020e0588, 0x020e04ac, 0x0)
-#define IOM_DRAM_SDCLK_1	MA(0x020e0594, 0x020e04b0, 0x0)
-#define IOM_DRAM_SDBA2		MA(0x020e058c, 0x020e04a0, 0x0)
-#define IOM_DRAM_SDCKE0		MA(0x020e0590, 0x020e04a4, 0x0)
-#define IOM_DRAM_SDCKE1		MA(0x020e0598, 0x020e04a8, 0x0)
-#define IOM_DRAM_SDODT0		MA(0x020e059c, 0x020e04b4, 0x0)
-#define IOM_DRAM_SDODT1		MA(0x020e05a0, 0x020e04b8, 0x0)
-
-#define IOM_DRAM_SDQS0		MA(0x020e05a8, 0x020e04bc, 0x0)
-#define IOM_DRAM_SDQS1		MA(0x020e05b0, 0x020e04c0, 0x0)
-#define IOM_DRAM_SDQS2		MA(0x020e0524, 0x020e04c4, 0x0)
-#define IOM_DRAM_SDQS3		MA(0x020e051c, 0x020e04c8, 0x0)
-#define IOM_DRAM_SDQS4		MA(0x020e0518, 0x020e04cc, 0x0)
-#define IOM_DRAM_SDQS5		MA(0x020e050c, 0x020e04d0, 0x0)
-#define IOM_DRAM_SDQS6		MA(0x020e05b8, 0x020e04d4, 0x0)
-#define IOM_DRAM_SDQS7		MA(0x020e05c0, 0x020e04d8, 0x0)
-
-#define IOM_GRP_B0DS		MA(0x020e0784, 0x020e0764, 0x0)
-#define IOM_GRP_B1DS		MA(0x020e0788, 0x020e0770, 0x0)
-#define IOM_GRP_B2DS		MA(0x020e0794, 0x020e0778, 0x0)
-#define IOM_GRP_B3DS		MA(0x020e079c, 0x020e077c, 0x0)
-#define IOM_GRP_B4DS		MA(0x020e07a0, 0x020e0780, 0x0)
-#define IOM_GRP_B5DS		MA(0x020e07a4, 0x020e0784, 0x0)
-#define IOM_GRP_B6DS		MA(0x020e07a8, 0x020e078c, 0x0)
-#define IOM_GRP_B7DS		MA(0x020e0748, 0x020e0748, 0x0)
-#define IOM_GRP_ADDDS		MA(0x020e074c, 0x020e074c, 0x0)
-#define IOM_DDRMODE_CTL		MA(0x020e0750, 0x020e0750, 0x0)
-#define IOM_GRP_DDRPKE		MA(0x020e0758, 0x020e0754, 0x0)
-#define IOM_GRP_DDRMODE		MA(0x020e0774, 0x020e0760, 0x0)
-#define IOM_GRP_CTLDS		MA(0x020e078c, 0x020e076c, 0x0)
-#define IOM_GRP_DDR_TYPE	MA(0x020e0798, 0x020e0774, 0x0)
+#define IOMUXC_GPR4		(IOMUXC_BASE + 0x010)
+#define IOMUXC_GPR6		(IOMUXC_BASE + 0x018)
+#define IOMUXC_GPR7		(IOMUXC_BASE + 0x01c)
 
-#define IRAM_FREE_START		0x00907000
+/* mx6 duallite and solo have same offsets */
 
-#define MMDC_P0_MDCTL		0x021b0000
-#define MMDC_P0_MDPDC		0x021b0004
-#define MMDC_P0_MDOTC		0x021b0008
-#define MMDC_P0_MDCFG0		0x021b000c
-#define MMDC_P0_MDCFG1		0x021b0010
-#define MMDC_P0_MDCFG2		0x021b0014
-#define MMDC_P0_MDMISC		0x021b0018
-#define MMDC_P0_MDSCR		0x021b001c
-#define MMDC_P0_MDREF		0x021b0020
-#define MMDC_P0_MDRWD		0x021b002c
-#define MMDC_P0_MDOR		0x021b0030
-#define MMDC_P0_MDASP		0x021b0040
-#define MMDC_P0_MAPSR		0x021b0404
-#define MMDC_P0_MPZQHWCTRL	0x021b0800
-#define MMDC_P0_MPWLDECTRL0	0x021b080c
-#define MMDC_P0_MPWLDECTRL1	0x021b0810
-#define MMDC_P0_MPODTCTRL	0x021b0818
-#define MMDC_P0_MPRDDQBY0DL	0x021b081c
-#define MMDC_P0_MPRDDQBY1DL	0x021b0820
-#define MMDC_P0_MPRDDQBY2DL	0x021b0824
-#define MMDC_P0_MPRDDQBY3DL	0x021b0828
-#define MMDC_P0_MPDGCTRL0	0x021b083c
-#define MMDC_P0_MPDGCTRL1	0x021b0840
-#define MMDC_P0_MPRDDLCTL	0x021b0848
-#define MMDC_P0_MPWRDLCTL	0x021b0850
-#define MMDC_P0_MPMUR0		0x021b08b8
-
-#define MMDC_P1_MDCTL		0x021b4000
-#define MMDC_P1_MDPDC		0x021b4004
-#define MMDC_P1_MDOTC		0x021b4008
-#define MMDC_P1_MDCFG0		0x021b400c
-#define MMDC_P1_MDCFG1		0x021b4010
-#define MMDC_P1_MDCFG2		0x021b4014
-#define MMDC_P1_MDMISC		0x021b4018
-#define MMDC_P1_MDSCR		0x021b401c
-#define MMDC_P1_MDREF		0x021b4020
-#define MMDC_P1_MDRWD		0x021b402c
-#define MMDC_P1_MDOR		0x021b4030
-#define MMDC_P1_MDASP		0x021b4040
-#define MMDC_P1_MAPSR		0x021b4404
-#define MMDC_P1_MPZQHWCTRL	0x021b4800
-#define MMDC_P1_MPWLDECTRL0	0x021b480c
-#define MMDC_P1_MPWLDECTRL1	0x021b4810
-#define MMDC_P1_MPODTCTRL	0x021b4818
-#define MMDC_P1_MPRDDQBY0DL	0x021b481c
-#define MMDC_P1_MPRDDQBY1DL	0x021b4820
-#define MMDC_P1_MPRDDQBY2DL	0x021b4824
-#define MMDC_P1_MPRDDQBY3DL	0x021b4828
-#define MMDC_P1_MPDGCTRL0	0x021b483c
-#define MMDC_P1_MPDGCTRL1	0x021b4840
-#define MMDC_P1_MPRDDLCTL	0x021b4848
-#define MMDC_P1_MPWRDLCTL	0x021b4850
-#define MMDC_P1_MPMUR0		0x021b48b8
-
-#define CCM_CCGR0		0x020C4068
-#define CCM_CCGR1		0x020C406c
-#define CCM_CCGR2		0x020C4070
-#define CCM_CCGR3		0x020C4074
-#define CCM_CCGR4		0x020C4078
-#define CCM_CCGR5		0x020C407c
-#define CCM_CCGR6		0x020C4080
+#define IOM_DRAM_DQM0		MA(0x5ac, 0x470, 0x0)
+#define IOM_DRAM_DQM1		MA(0x5b4, 0x474, 0x0)
+#define IOM_DRAM_DQM2		MA(0x528, 0x478, 0x0)
+#define IOM_DRAM_DQM3		MA(0x520, 0x47c, 0x0)
+#define IOM_DRAM_DQM4		MA(0x514, 0x480, 0x0)
+#define IOM_DRAM_DQM5		MA(0x510, 0x484, 0x0)
+#define IOM_DRAM_DQM6		MA(0x5bc, 0x488, 0x0)
+#define IOM_DRAM_DQM7		MA(0x5c4, 0x48c, 0x0)
+
+#define IOM_DRAM_CAS		MA(0x56c, 0x464, 0x0)
+#define IOM_DRAM_RAS		MA(0x578, 0x490, 0x0)
+#define IOM_DRAM_RESET		MA(0x57c, 0x494, 0x0)
+#define IOM_DRAM_SDCLK_0	MA(0x588, 0x4ac, 0x0)
+#define IOM_DRAM_SDCLK_1	MA(0x594, 0x4b0, 0x0)
+#define IOM_DRAM_SDBA2		MA(0x58c, 0x4a0, 0x0)
+#define IOM_DRAM_SDCKE0		MA(0x590, 0x4a4, 0x0)
+#define IOM_DRAM_SDCKE1		MA(0x598, 0x4a8, 0x0)
+#define IOM_DRAM_SDODT0		MA(0x59c, 0x4b4, 0x0)
+#define IOM_DRAM_SDODT1		MA(0x5a0, 0x4b8, 0x0)
+
+#define IOM_DRAM_SDQS0		MA(0x5a8, 0x4bc, 0x0)
+#define IOM_DRAM_SDQS1		MA(0x5b0, 0x4c0, 0x0)
+#define IOM_DRAM_SDQS2		MA(0x524, 0x4c4, 0x0)
+#define IOM_DRAM_SDQS3		MA(0x51c, 0x4c8, 0x0)
+#define IOM_DRAM_SDQS4		MA(0x518, 0x4cc, 0x0)
+#define IOM_DRAM_SDQS5		MA(0x50c, 0x4d0, 0x0)
+#define IOM_DRAM_SDQS6		MA(0x5b8, 0x4d4, 0x0)
+#define IOM_DRAM_SDQS7		MA(0x5c0, 0x4d8, 0x0)
+
+#define IOM_GRP_B0DS		MA(0x784, 0x764, 0x0)
+#define IOM_GRP_B1DS		MA(0x788, 0x770, 0x0)
+#define IOM_GRP_B2DS		MA(0x794, 0x778, 0x0)
+#define IOM_GRP_B3DS		MA(0x79c, 0x77c, 0x0)
+#define IOM_GRP_B4DS		MA(0x7a0, 0x780, 0x0)
+#define IOM_GRP_B5DS		MA(0x7a4, 0x784, 0x0)
+#define IOM_GRP_B6DS		MA(0x7a8, 0x78c, 0x0)
+#define IOM_GRP_B7DS		MA(0x748, 0x748, 0x0)
+#define IOM_GRP_ADDDS		MA(0x74c, 0x74c, 0x0)
+#define IOM_DDRMODE_CTL		MA(0x750, 0x750, 0x0)
+#define IOM_GRP_DDRPKE		MA(0x758, 0x754, 0x0)
+#define IOM_GRP_DDRMODE		MA(0x774, 0x760, 0x0)
+#define IOM_GRP_CTLDS		MA(0x78c, 0x76c, 0x0)
+#define IOM_GRP_DDR_TYPE	MA(0x798, 0x774, 0x0)
+
+#define MMDC_MDCTL		0x000
+#define MMDC_MDPDC		0x004
+#define MMDC_MDOTC		0x008
+#define MMDC_MDCFG0		0x00c
+#define MMDC_MDCFG1		0x010
+#define MMDC_MDCFG2		0x014
+#define MMDC_MDMISC		0x018
+#define MMDC_MDSCR		0x01c
+#define MMDC_MDREF		0x020
+#define MMDC_MDRWD		0x02c
+#define MMDC_MDOR		0x030
+#define MMDC_MDASP		0x040
+#define MMDC_MAPSR		0x404
+#define MMDC_MPZQHWCTRL		0x800
+#define MMDC_MPWLDECTRL0	0x80c
+#define MMDC_MPWLDECTRL1	0x810
+#define MMDC_MPODTCTRL		0x818
+#define MMDC_MPRDDQBY0DL	0x81c
+#define MMDC_MPRDDQBY1DL	0x820
+#define MMDC_MPRDDQBY2DL	0x824
+#define MMDC_MPRDDQBY3DL	0x828
+#define MMDC_MPDGCTRL0		0x83c
+#define MMDC_MPDGCTRL1		0x840
+#define MMDC_MPRDDLCTL		0x848
+#define MMDC_MPWRDLCTL		0x850
+#define MMDC_MPMUR0		0x8b8
+
+#define CCM_CCGR0		(CCM_BASE + 0x068)
+#define CCM_CCGR1		(CCM_BASE + 0x06c)
+#define CCM_CCGR2		(CCM_BASE + 0x070)
+#define CCM_CCGR3		(CCM_BASE + 0x074)
+#define CCM_CCGR4		(CCM_BASE + 0x078)
+#define CCM_CCGR5		(CCM_BASE + 0x07c)
+#define CCM_CCGR6		(CCM_BASE + 0x080)
 
 
 #define WRITE_ENTRY1(addr, q)		DATA 4, addr, q
 #ifdef CONFIG_MX6Q
-#define MA(mx6q, mx6dl_solo, mx6sololite)	mx6q
+#define MA(mx6q, mx6dl_solo, mx6sololite)	(IOMUXC_BASE + mx6q)
 #define WRITE_ENTRY2(addr, q, dl)		WRITE_ENTRY1(addr, q)
 #define WRITE_ENTRY3(addr, q, dl, solo)		WRITE_ENTRY1(addr, q)
 #define WRITE_ENTRY4(addr, q, dl, solo, sl)	WRITE_ENTRY1(addr, q)

@@ -131,20 +108,20 @@
 
 #define WRITE_ENTRY2(addr, q, dl)		WRITE_ENTRY1(addr, dl)
 #ifdef CONFIG_MX6DL
-#define MA(mx6q, mx6dl_solo, mx6sololite)	mx6dl_solo
+#define MA(mx6q, mx6dl_solo, mx6sololite)	(IOMUXC_BASE + mx6dl_solo)
 #define WRITE_ENTRY3(addr, q, dl, solo)		WRITE_ENTRY1(addr, dl)
 #define WRITE_ENTRY4(addr, q, dl, solo, sl)	WRITE_ENTRY1(addr, dl)
 #else
 
 #define WRITE_ENTRY3(addr, q, dl, solo)		WRITE_ENTRY1(addr, solo)
 #ifdef CONFIG_MX6S
-#define MA(mx6q, mx6dl_solo, mx6sololite)	mx6dl_solo
+#define MA(mx6q, mx6dl_solo, mx6sololite)	(IOMUXC_BASE + mx6dl_solo)
 #define WRITE_ENTRY4(addr, q, dl, solo, sl)	WRITE_ENTRY1(addr, solo)
 #else
 
 #define WRITE_ENTRY4(addr, q, dl, solo, sl)	WRITE_ENTRY1(addr, sl)
 #ifdef CONFIG_MX6SL
-#define MA(mx6q, mx6dl_solo, mx6sololite)	mx6sololite
+#define MA(mx6q, mx6dl_solo, mx6sololite)	(IOMUXC_BASE + mx6sololite)
 #else
 
 #error "Please select cpu"

board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg +45 ~~-45~~

172 lines not on this page · raw message

Signature · 1 line

1.7.9.5

Albert ARIBAUD

2012-10-04 10:18 UTC #196 lore raw

v3 cover Add mx6solo/mx6duallite support

In reply to Troy Kisky

Hi Troy,

Quoted 3 lines · Troy Kisky

This series goal is to add support for mx6solo and mx6duallite variants of mx6qsabrelite board. The new targets are called mx6ssabrelite and mx6dlsabrelite.

If the boards are known as 'mx6solo' and 'mx6duallite', they should be named so rather than called yet another nickname.

Quoted 71 lines

The 1st 16 patches perform cleanup on imximage
The final 2 patches add support for expressions to mkimage. If found not to be worth the effort, they can be omitted.
Troy Kisky (32):
imximage: check dcd_len as entries added
imximage: remove redundant setting of app_dest_ptr
imximage: move flash_offset check to common location
imximage: fix size of image to load.
imximage: delay setting of image size
imximage: change parameters to set_imx_hdr
imximage: make set_imx_hdr_v1/v2 easier to read
imximage: make header variable length
imximage: remove static imximage_version
imximage: prepare to move static variables to struct data_src
imximage: change parameters for set_dcd_val/set_imx_hdr
imximage: move set_imx_hdr to struct data_src
imximage: move set_dcd_val to struct data_src
imximage: enable word writes for version2 header
tools: add parse_helper file
imximage: use parse_helper functions
imximage.cfg: run files through C preprocessor mx6q_4x_mt41j128.cfg: use symbols instead of hardcoded constants mx6q_4x_mt41j128.cfg: add comments mx6q_4x_mt41j128.cfg: use ddr3 mode for reset mx6q_4x_mt41j128.cfg: skip initiailizing non-existent memory mx6q_4x_mt41j128.cfg: force ZQ calibration
mx6: soc: update get_cpu_rev and get_imx_type for mx6solo/sololite
mx6: use CONFIG_MX6 instead of CONFIG_MX6Q
imx-common: cpu: add imx_ddr_size
arch-mx6: add mx6dl_pins.h
mx6qsabrelite: add support for mx6 solo/duallite mx6q_4x_mt41j128.cfg: add mx6 solo/duallite support
Add boards for sabrelite variants mx6s(solo) and mx6dl(duallite)
mx6qsabrelite: change CONFIG_SYS_PROMPT
parse_helper: add expression evaluation
imx-mkimage.h: use base + offset syntax
 Makefile                                      |    3 +-
 arch/arm/cpu/armv7/mx6/soc.c                  |   32 +-
 arch/arm/imx-common/cpu.c                     |   66 +++-
 arch/arm/include/asm/arch-mx5/sys_proto.h     |   10 +-
 arch/arm/include/asm/arch-mx6/imx-mkimage.h   |  133 +++++++
 arch/arm/include/asm/arch-mx6/imx-regs.h      |    2 +
 arch/arm/include/asm/arch-mx6/mx6dl_pins.h    |  118 ++++++
 arch/arm/include/asm/arch-mx6/sys_proto.h     |   10 +-
 board/esg/ima3-mx53/imximage.cfg              |  120 +++---
 board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg  |  425 ++++++++++++---------
 board/freescale/mx25pdk/imximage.cfg          |   77 ++--
 board/freescale/mx51evk/imximage.cfg          |  114 +++---
 board/freescale/mx53ard/imximage_dd3.cfg      |   83 +++--
 board/freescale/mx53evk/imximage.cfg          |   86 ++---
 board/freescale/mx53loco/imximage.cfg         |   83 +++--
 board/freescale/mx53smd/imximage.cfg          |   83 +++--
 board/freescale/mx6qarm2/imximage.cfg         |   88 ++---
 board/freescale/mx6qsabrelite/mx6qsabrelite.c |  235 +++---------
 board/freescale/mx6qsabrelite/pads.h          |  172 +++++++++
 board/genesi/mx51_efikamx/imximage_mx.cfg     |  132 +++----
 board/genesi/mx51_efikamx/imximage_sb.cfg     |  126 ++++---
 board/ttcontrol/vision2/imximage_hynix.cfg    |  295 ++++++++-------
 boards.cfg                                    |    4 +-
 drivers/gpio/mxc_gpio.c                       |    6 +-
 drivers/video/ipu_regs.h                      |    2 +-
 include/configs/mx6qarm2.h                    |    1 +
 include/configs/mx6qsabre_common.h            |    1 +
 include/configs/mx6qsabrelite.h               |    4 +-
 tools/Makefile                                |    2 +
 tools/imximage.c                              |  487 ++++++++++---------------
 tools/imximage.h                              |   39 +-

Quoted 9 lines

 tools/parse_helper.c                          |  325 +++++++++++++++++
 tools/parse_helper.h                          |   28 ++
 33 files changed, 2106 insertions(+), 1286 deletions(-)
 create mode 100644 arch/arm/include/asm/arch-mx6/imx-mkimage.h
 create mode 100644 arch/arm/include/asm/arch-mx6/mx6dl_pins.h
 create mode 100644 board/freescale/mx6qsabrelite/pads.h
 create mode 100644 tools/parse_helper.c
 create mode 100644 tools/parse_helper.h

Amicalement,

Signature · 1 line

Albert.

Eric Nelson

2012-10-04 14:36 UTC #197 lore raw

v3 cover Add mx6solo/mx6duallite support

Quoted 5 lines · Albert ARIBAUD

Hi Troy,
On Wed, 3 Oct 2012 18:47:02 -0700, Troy Kisky
<[email protected]> wrote:

Quoted 7 lines

Quoted 3 lines
This series goal is to add support for mx6solo and mx6duallite variants of mx6qsabrelite board. The new targets are called mx6ssabrelite and mx6dlsabrelite.
If the boards are known as 'mx6solo' and 'mx6duallite', they should be named so rather than called yet another nickname.

Hi Albert,

I'm not sure I understand your comment.

mx6solo and mx6duallite are the CPU names, not the board names.

mx6dlsabrelite is a version of the SABRE Lite board containing the mx6duallite CPU instead of the mx6quad.

We'll also be offering Nitrogen6X in mx6solo and mx6duallite variants.

Regards,

Eric

Albert ARIBAUD

2012-10-04 19:51 UTC #198 lore raw

v3 cover Add mx6solo/mx6duallite support

Hi Eric,

Quoted 14 lines · Eric Nelson

Quoted 5 lines · Albert ARIBAUD
Hi Troy,
On Wed, 3 Oct 2012 18:47:02 -0700, Troy Kisky
<[email protected]> wrote:
Quoted 7 lines
Quoted 3 lines
This series goal is to add support for mx6solo and mx6duallite variants of mx6qsabrelite board. The new targets are called mx6ssabrelite and mx6dlsabrelite.
If the boards are known as 'mx6solo' and 'mx6duallite', they should be named so rather than called yet another nickname.

Quoted 6 lines

Hi Albert,
I'm not sure I understand your comment.
mx6solo and mx6duallite are the CPU names, not the board names.

That's where the misunderstanding crept in: I thought these were board names, not CPU names.

Quoted 5 lines

mx6dlsabrelite is a version of the SABRE Lite board containing the mx6duallite CPU instead of the mx6quad.
We'll also be offering Nitrogen6X in mx6solo and mx6duallite variants.

Understood now -- and disregard my initial comment.

Quoted 4 lines

Regards,
Eric

Amicalement,

Signature · 1 line

Albert.

Eric Nelson

2012-10-04 14:52 UTC #199 lore raw

v3 cover Add mx6solo/mx6duallite support

In reply to Troy Kisky

Hi Troy,

Quoted 78 lines · Troy Kisky

This series goal is to add support for mx6solo and mx6duallite variants of mx6qsabrelite board. The new targets are called mx6ssabrelite and mx6dlsabrelite.
The 1st 16 patches perform cleanup on imximage
The final 2 patches add support for expressions to mkimage. If found not to be worth the effort, they can be omitted.
Troy Kisky (32):
imximage: check dcd_len as entries added
imximage: remove redundant setting of app_dest_ptr
imximage: move flash_offset check to common location
imximage: fix size of image to load.
imximage: delay setting of image size
imximage: change parameters to set_imx_hdr
imximage: make set_imx_hdr_v1/v2 easier to read
imximage: make header variable length
imximage: remove static imximage_version
imximage: prepare to move static variables to struct data_src
imximage: change parameters for set_dcd_val/set_imx_hdr
imximage: move set_imx_hdr to struct data_src
imximage: move set_dcd_val to struct data_src
imximage: enable word writes for version2 header
tools: add parse_helper file
imximage: use parse_helper functions
imximage.cfg: run files through C preprocessor mx6q_4x_mt41j128.cfg: use symbols instead of hardcoded constants mx6q_4x_mt41j128.cfg: add comments mx6q_4x_mt41j128.cfg: use ddr3 mode for reset mx6q_4x_mt41j128.cfg: skip initiailizing non-existent memory mx6q_4x_mt41j128.cfg: force ZQ calibration
mx6: soc: update get_cpu_rev and get_imx_type for mx6solo/sololite
mx6: use CONFIG_MX6 instead of CONFIG_MX6Q
imx-common: cpu: add imx_ddr_size
arch-mx6: add mx6dl_pins.h
mx6qsabrelite: add support for mx6 solo/duallite mx6q_4x_mt41j128.cfg: add mx6 solo/duallite support
Add boards for sabrelite variants mx6s(solo) and mx6dl(duallite)
mx6qsabrelite: change CONFIG_SYS_PROMPT
parse_helper: add expression evaluation
imx-mkimage.h: use base + offset syntax
  Makefile                                      |    3 +-
  arch/arm/cpu/armv7/mx6/soc.c                  |   32 +-
  arch/arm/imx-common/cpu.c                     |   66 +++-
  arch/arm/include/asm/arch-mx5/sys_proto.h     |   10 +-
  arch/arm/include/asm/arch-mx6/imx-mkimage.h   |  133 +++++++
  arch/arm/include/asm/arch-mx6/imx-regs.h      |    2 +
  arch/arm/include/asm/arch-mx6/mx6dl_pins.h    |  118 ++++++
  arch/arm/include/asm/arch-mx6/sys_proto.h     |   10 +-
  board/esg/ima3-mx53/imximage.cfg              |  120 +++---
  board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg  |  425 ++++++++++++---------
  board/freescale/mx25pdk/imximage.cfg          |   77 ++--
  board/freescale/mx51evk/imximage.cfg          |  114 +++---
  board/freescale/mx53ard/imximage_dd3.cfg      |   83 +++--
  board/freescale/mx53evk/imximage.cfg          |   86 ++---
  board/freescale/mx53loco/imximage.cfg         |   83 +++--
  board/freescale/mx53smd/imximage.cfg          |   83 +++--
  board/freescale/mx6qarm2/imximage.cfg         |   88 ++---
  board/freescale/mx6qsabrelite/mx6qsabrelite.c |  235 +++---------
  board/freescale/mx6qsabrelite/pads.h          |  172 +++++++++
  board/genesi/mx51_efikamx/imximage_mx.cfg     |  132 +++----
  board/genesi/mx51_efikamx/imximage_sb.cfg     |  126 ++++---
  board/ttcontrol/vision2/imximage_hynix.cfg    |  295 ++++++++-------
  boards.cfg                                    |    4 +-
  drivers/gpio/mxc_gpio.c                       |    6 +-
  drivers/video/ipu_regs.h                      |    2 +-
  include/configs/mx6qarm2.h                    |    1 +
  include/configs/mx6qsabre_common.h            |    1 +
  include/configs/mx6qsabrelite.h               |    4 +-
  tools/Makefile                                |    2 +
  tools/imximage.c                              |  487 ++++++++++---------------
  tools/imximage.h                              |   39 +-
  tools/parse_helper.c                          |  325 +++++++++++++++++
  tools/parse_helper.h                          |   28 ++
  33 files changed, 2106 insertions(+), 1286 deletions(-)

Quoted 6 lines

create mode 100644 arch/arm/include/asm/arch-mx6/imx-mkimage.h create mode 100644 arch/arm/include/asm/arch-mx6/mx6dl_pins.h create mode 100644 board/freescale/mx6qsabrelite/pads.h create mode 100644 tools/parse_helper.c
create mode 100644 tools/parse_helper.h

There's clearly a lot going on in this patch set. Does it make sense to split this into parts that can be reviewed and checked separately?

It seems that there are
- bug fixes to imximage
- enhancements to imximage
- enhancements to build for imximage.cfg (CPP)
- core i.MX6 changes (cpu types, etc)
- rework of imximage.cfg files to use CPP
...

And there's that simple one changing the prompt we can probably get a quick ack/nak on ;)

Stefano Babic

2012-10-08 13:15 UTC #200 lore raw

v3 cover Add mx6solo/mx6duallite support

In reply to Troy Kisky

Quoted 5 lines · Troy Kisky

This series goal is to add support for mx6solo and mx6duallite variants of mx6qsabrelite board. The new targets are called mx6ssabrelite and mx6dlsabrelite.
The 1st 16 patches perform cleanup on imximage

Hi Troy,

I have some difficulties to understand which are the dependencies of this patchset. IMHO there are very different topics here, and some patches can be applied independently from the other one. imximage patches. For example, why "add mx6dl_pins" belong to imximage patchset ? It is surely easier to split for each topic, so that each patcheset can be applied independently if on a different topic there is still an open issue.

I see at least:
- imximage fixes: they are really fix and can be applied soon.
- imximage new features
- mx6 patches

It is surely easier if you split your changes in separate patchset, as they covered different topics.

Best regards,
Stefano Babic

Signature · 5 lines

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HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
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Troy Kisky

author

2012-10-08 23:58 UTC #201 lore raw

v3 cover Add mx6solo/mx6duallite support

Quoted 22 lines · Stefano Babic

Quoted 5 lines · Troy Kisky
This series goal is to add support for mx6solo and mx6duallite variants of mx6qsabrelite board. The new targets are called mx6ssabrelite and mx6dlsabrelite.
The 1st 16 patches perform cleanup on imximage
Hi Troy,
I have some difficulties to understand which are the dependencies of this patchset. IMHO there are very different topics here, and some patches can be applied independently from the other one. imximage patches. For example, why "add mx6dl_pins" belong to imximage patchset ? It is surely easier to split for each topic, so that each patcheset can be applied independently if on a different topic there is still an open issue.
I see at least:
- imximage fixes: they are really fix and can be applied soon.
- imximage new features
- mx6 patches

Quoted 6 lines

It is surely easier if you split your changes in separate patchset, as they covered different topics.
Best regards,
Stefano Babic

Yes, Eric made the same comment. I'll split the next version up.

Thanks
Troy