mx5: Add workaround for ARM erratum ID 468414
Subsystems (2)
PATCH 1/1 mx5: Add workaround for ARM erratum ID 468414
From: Fabio Estevam <[email protected]>
Add the software workaround for ARM erratum ID 468414.
According to mx53/mx51 errata document:
"ENGcm11133 - ARM: NEON load data can be incorrectly forwarded to a subsequent request
Description:
Under very specific set of conditions, data from a Neon load request can be incorrectly forwarded to a subsequent, unrelated memory request.
The conditions are as follows:
??? Neon loads and stores must be in use
??? Neon L1 caching must be disabled
??? Trustzone must be configured and in use
??? The secure memory address space and the non-secure memory address space both use the same physical addresses, either as an alias or the same memory location or for separate memory locations
The issue is reported by ARM, erratum ID 468414, Category 2"
--- arch/arm/cpu/armv7/mx5/lowlevel_init.S | 9 +++++++++ 1 files changed, 9 insertions(+), 0 deletions(-)
arch/arm/cpu/armv7/mx5/lowlevel_init.S +9 -0
@@ -24,6 +24,13 @@ #include <generated/asm-offsets.h> #include <linux/linkage.h> +.macro init_arm_erratum + /* ARM erratum ID #468414 */ + mrc 15, 0, r1, c1, c0, 1 + orr r1, r1, #(1 << 5) /* enable L1NEON bit */ + mcr 15, 0, r1, c1, c0, 1 +.endm + /* * L2CC Cache setup/invalidation/disable */
@@ -338,6 +345,8 @@ ENTRY(lowlevel_init) str r1, [r0, #0x4] #endif + init_arm_erratum + init_l2cc init_aips
Signature · 1 line
1.7.1
PATCH 1/1 mx5: Add workaround for ARM erratum ID 468414
Quoted 46 lines · Fabio Estevam
From: Fabio Estevam <[email protected]>
Add the software workaround for ARM erratum ID 468414.
According to mx53/mx51 errata document:
"ENGcm11133 - ARM: NEON load data can be incorrectly forwarded to a subsequent request
Description:
Under very specific set of conditions, data from a Neon load request can be incorrectly forwarded to a subsequent, unrelated memory request.
The conditions are as follows:
??? Neon loads and stores must be in use
??? Neon L1 caching must be disabled
??? Trustzone must be configured and in use
??? The secure memory address space and the non-secure memory address space both use the same physical addresses, either as an alias or the same memory location or for separate memory locations
The issue is reported by ARM, erratum ID 468414, Category 2"Signed-off-by Fabio Estevam <[email protected]>--- arch/arm/cpu/armv7/mx5/lowlevel_init.S | 9 +++++++++ 1 files changed, 9 insertions(+), 0 deletions(-)arch/arm/cpu/armv7/mx5/lowlevel_init.S +7
-0@@ -24,6 +24,13 @@ #include <generated/asm-offsets.h> #include <linux/linkage.h> +.macro init_arm_erratum + /* ARM erratum ID #468414 */ + mrc 15, 0, r1, c1, c0, 1 + orr r1, r1, #(1 << 5) /* enable L1NEON bit */ + mcr 15, 0, r1, c1, c0, 1 +.endm + /* * L2CC Cache setup/invalidation/disable */
arch/arm/cpu/armv7/mx5/lowlevel_init.S ENTRY(lowlevel_init) · line 349
Quoted 5 lines
arch/arm/cpu/armv7/mx5/lowlevel_init.S +2
-0@@ -338,6 +345,8 @@ ENTRY(lowlevel_init) str r1, [r0, #0x4] #endif + init_arm_erratum +
I have only a small question. It is not for me to put this into MX5 stuff, but because it is ARM related should we not put it into arch/arm/cpu/armv7/start.S ?
Best regards,
Stefano Babic
Signature · 5 lines
===================================================================== DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de =====================================================================
PATCH 1/1 mx5: Add workaround for ARM erratum ID 468414
Am 09/05/2012 11:36, schrieb Stefano Babic:
Quoted 50 lines · Fabio Estevam
Quoted 49 lines
From: Fabio Estevam <[email protected]>
Add the software workaround for ARM erratum ID 468414.
According to mx53/mx51 errata document:
"ENGcm11133 - ARM: NEON load data can be incorrectly forwarded to a subsequent request
Description:
Under very specific set of conditions, data from a Neon load request can be incorrectly forwarded to a subsequent, unrelated memory request.
The conditions are as follows:
??? Neon loads and stores must be in use
??? Neon L1 caching must be disabled
??? Trustzone must be configured and in use
??? The secure memory address space and the non-secure memory address space both use the same physical addresses, either as an alias or the same memory location or for separate memory locations
The issue is reported by ARM, erratum ID 468414, Category 2"Signed-off-by Fabio Estevam <[email protected]>--- arch/arm/cpu/armv7/mx5/lowlevel_init.S | 9 +++++++++ 1 files changed, 9 insertions(+), 0 deletions(-)arch/arm/cpu/armv7/mx5/lowlevel_init.S +7
-0@@ -24,6 +24,13 @@ #include <generated/asm-offsets.h> #include <linux/linkage.h> +.macro init_arm_erratum + /* ARM erratum ID #468414 */ + mrc 15, 0, r1, c1, c0, 1 + orr r1, r1, #(1 << 5) /* enable L1NEON bit */ + mcr 15, 0, r1, c1, c0, 1 +.endm + /* * L2CC Cache setup/invalidation/disable */@@ -338,6 +345,8 @@ ENTRY(lowlevel_init) str r1, [r0, #0x4] #endif
Quoted 6 lines
arch/arm/cpu/armv7/mx5/lowlevel_init.S ENTRY(lowlevel_init) · line 349
Quoted 2 lines
arch/arm/cpu/armv7/mx5/lowlevel_init.S +2
-0+ init_arm_erratum +I have only a small question. It is not for me to put this into MX5 stuff, but because it is ARM related should we not put it into
arch/arm/cpu/armv7/start.S?
Checking again forgotten patches, I noted that the same issue is fixed separately in other SOCs directory (OMAP3). It is not bad to merge this, too, until we want to factorize it for all armv7 SOCs.
Applied to u-boot-imx, thanks.
Best regards,
Stefano Babic
Signature · 5 lines
===================================================================== DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de =====================================================================