ARM/dts: Update OMAP5 with address space and interrupts
cover ARM/dts: Update OMAP5 with address space and interrupts
Since kernel 3.7 the DTS data are not overwriten by hwmod data we can add the address space and interrupt line description inside dtsi file for OMAP5. This serie is updating the current OMAP5 IP with missing entry.
It has been tested on OMAP5 with 3.7-audio-display feature tree.
- MMC is probing and functional
- TWL6041 probing (GPIO/I2C)
- booting (UART)
Sebastien Guiriec (4):
ARM/dts: omap5: Update GPIO with address space and interrupt ARM/dts: omap5: Update I2C with address space and interrupts ARM/dts: omap5: Update UART with address space and interrupts ARM/dts: omap5: Update MMC with address space and interrupts
arch/arm/boot/dts/omap5.dtsi | 56 +++++++++++++++++++++++++++++++++++++++--- 1 file changed, 52 insertions(+), 4 deletions(-)
Signature · 1 line
1.7.10.4
PATCH 1/4 ARM/dts: omap5: Update GPIO with address space and interrupt
Add base address and interrupt line inside Device Tree data for OMAP5
--- arch/arm/boot/dts/omap5.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+)
arch/arm/boot/dts/omap5.dtsi +16 -0
@@ -104,6 +104,8 @@ gpio1: gpio at 4ae10000 { compatible = "ti,omap4-gpio"; + reg = <0x4ae10000 0x200>; + interrupts = <0 29 0x4>; ti,hwmods = "gpio1"; gpio-controller; #gpio-cells = <2>;
@@ -113,6 +115,8 @@ gpio2: gpio at 48055000 { compatible = "ti,omap4-gpio"; + reg = <0x48055000 0x200>; + interrupts = <0 30 0x4>; ti,hwmods = "gpio2"; gpio-controller; #gpio-cells = <2>;
@@ -122,6 +126,8 @@ gpio3: gpio at 48057000 { compatible = "ti,omap4-gpio"; + reg = <0x48057000 0x200>; + interrupts = <0 31 0x4>; ti,hwmods = "gpio3"; gpio-controller; #gpio-cells = <2>;
@@ -131,6 +137,8 @@ gpio4: gpio at 48059000 { compatible = "ti,omap4-gpio"; + reg = <0x48059000 0x200>; + interrupts = <0 32 0x4>; ti,hwmods = "gpio4"; gpio-controller; #gpio-cells = <2>;
@@ -140,6 +148,8 @@ gpio5: gpio at 4805b000 { compatible = "ti,omap4-gpio"; + reg = <0x4805b000 0x200>; + interrupts = <0 33 0x4>; ti,hwmods = "gpio5"; gpio-controller; #gpio-cells = <2>;
@@ -149,6 +159,8 @@ gpio6: gpio at 4805d000 { compatible = "ti,omap4-gpio"; + reg = <0x4805d000 0x200>; + interrupts = <0 34 0x4>; ti,hwmods = "gpio6"; gpio-controller; #gpio-cells = <2>;
@@ -158,6 +170,8 @@ gpio7: gpio at 48051000 { compatible = "ti,omap4-gpio"; + reg = <0x48051000 0x200>; + interrupts = <0 35 0x4>; ti,hwmods = "gpio7"; gpio-controller; #gpio-cells = <2>;
@@ -167,6 +181,8 @@ gpio8: gpio at 48053000 { compatible = "ti,omap4-gpio"; + reg = <0x48053000 0x200>; + interrupts = <0 121 0x4>; ti,hwmods = "gpio8"; gpio-controller; #gpio-cells = <2>;
Signature · 1 line
1.7.10.4
PATCH 2/4 ARM/dts: omap5: Update I2C with address space and interrupts
In reply to Sebastien GuiriecAdd base address and interrupt line inside Device Tree data for OMAP5
--- arch/arm/boot/dts/omap5.dtsi | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-)
arch/arm/boot/dts/omap5.dtsi +12 -2
@@ -192,6 +192,8 @@ i2c1: i2c at 48070000 { compatible = "ti,omap4-i2c"; + reg = <0x48070000 0x100>; + interrupts = <0 56 0x4>; #address-cells = <1>; #size-cells = <0>; ti,hwmods = "i2c1";
@@ -199,6 +201,8 @@ i2c2: i2c at 48072000 { compatible = "ti,omap4-i2c"; + reg = <0x48072000 0x100>; + interrupts = <0 57 0x4>; #address-cells = <1>; #size-cells = <0>; ti,hwmods = "i2c2";
@@ -206,20 +210,26 @@ i2c3: i2c at 48060000 { compatible = "ti,omap4-i2c"; + reg = <0x48060000 0x100>; + interrupts = <0 61 0x4>; #address-cells = <1>; #size-cells = <0>; ti,hwmods = "i2c3"; }; - i2c4: i2c at 4807A000 { + i2c4: i2c at 4807a000 { compatible = "ti,omap4-i2c"; + reg = <0x4807a000 0x100>; + interrupts = <0 62 0x4>; #address-cells = <1>; #size-cells = <0>; ti,hwmods = "i2c4"; }; - i2c5: i2c at 4807C000 { + i2c5: i2c at 4807c000 { compatible = "ti,omap4-i2c"; + reg = <0x4807c000 0x100>; + interrupts = <0 60 0x4>; #address-cells = <1>; #size-cells = <0>; ti,hwmods = "i2c5";
Signature · 1 line
1.7.10.4
PATCH 2/4 ARM/dts: omap5: Update I2C with address space and interrupts
Quoted 2 lines · Sebastien Guiriec
Add base address and interrupt line inside Device Tree data for OMAP5
Looks good to me.
Thanks ,
Quoted 64 lines
Signed-off-by Sebastien Guiriec <[email protected]>--- arch/arm/boot/dts/omap5.dtsi | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-)arch/arm/boot/dts/omap5.dtsi +12
-3@@ -192,6 +192,8 @@ i2c1: i2c at 48070000 { compatible = "ti,omap4-i2c"; + reg = <0x48070000 0x100>; + interrupts = <0 56 0x4>; #address-cells = <1>; #size-cells = <0>; ti,hwmods = "i2c1";@@ -199,6 +201,8 @@ i2c2: i2c at 48072000 { compatible = "ti,omap4-i2c"; + reg = <0x48072000 0x100>; + interrupts = <0 57 0x4>; #address-cells = <1>; #size-cells = <0>; ti,hwmods = "i2c2";@@ -206,20 +210,26 @@ i2c3: i2c at 48060000 { compatible = "ti,omap4-i2c"; + reg = <0x48060000 0x100>; + interrupts = <0 61 0x4>; #address-cells = <1>; #size-cells = <0>; ti,hwmods = "i2c3"; }; - i2c4: i2c at 4807A000 { + i2c4: i2c at 4807a000 { compatible = "ti,omap4-i2c"; + reg = <0x4807a000 0x100>; + interrupts = <0 62 0x4>; #address-cells = <1>; #size-cells = <0>; ti,hwmods = "i2c4"; }; - i2c5: i2c at 4807C000 { + i2c5: i2c at 4807c000 { compatible = "ti,omap4-i2c"; + reg = <0x4807c000 0x100>; + interrupts = <0 60 0x4>; #address-cells = <1>; #size-cells = <0>; ti,hwmods = "i2c5"; --1.7.10.4
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PATCH 3/4 ARM/dts: omap5: Update UART with address space and interrupts
In reply to Sebastien GuiriecAdd base address and interrupt line inside Device Tree data for
--- arch/arm/boot/dts/omap5.dtsi | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-)
arch/arm/boot/dts/omap5.dtsi +14 -2
@@ -237,36 +237,48 @@ uart1: serial at 4806a000 { compatible = "ti,omap4-uart"; + reg = <0x4806a000 0x100>; + interrupts = <0 72 0x4>; ti,hwmods = "uart1"; clock-frequency = <48000000>; }; uart2: serial at 4806c000 { compatible = "ti,omap4-uart"; + reg = <0x4806c000 0x100>; + interrupts = <0 73 0x4>; ti,hwmods = "uart2"; clock-frequency = <48000000>; }; uart3: serial at 48020000 { compatible = "ti,omap4-uart"; + reg = <0x48020000 0x100>; + interrupts = <0 74 0x4>; ti,hwmods = "uart3"; clock-frequency = <48000000>; }; uart4: serial at 4806e000 { compatible = "ti,omap4-uart"; + reg = <0x4806e000 0x100>; + interrupts = <0 70 0x4>; ti,hwmods = "uart4"; clock-frequency = <48000000>; }; uart5: serial at 48066000 { - compatible = "ti,omap5-uart"; + compatible = "ti,omap4-uart"; + reg = <0x48066000 0x100>; + interrupts = <0 105 0x4>; ti,hwmods = "uart5"; clock-frequency = <48000000>; }; uart6: serial at 48068000 { - compatible = "ti,omap6-uart"; + compatible = "ti,omap4-uart"; + reg = <0x48068000 0x100>; + interrupts = <0 106 0x4>; ti,hwmods = "uart6"; clock-frequency = <48000000>; };
Signature · 1 line
1.7.10.4
PATCH 3/4 ARM/dts: omap5: Update UART with address space and interrupts
Hi Sebastien,
Quoted 1 line · Sebastien Guiriec
Add base address and interrupt line inside Device Tree data for
Incomplete sentence!
Quoted 38 lines
Signed-off-by Sebastien Guiriec <[email protected]>--- arch/arm/boot/dts/omap5.dtsi | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-)arch/arm/boot/dts/omap5.dtsi +7
-0@@ -237,36 +237,48 @@ uart1: serial@4806a000 { compatible = "ti,omap4-uart"; + reg = <0x4806a000 0x100>; + interrupts = <0 72 0x4>; ti,hwmods = "uart1"; clock-frequency = <48000000>; }; uart2: serial@4806c000 { compatible = "ti,omap4-uart"; + reg = <0x4806c000 0x100>; + interrupts = <0 73 0x4>; ti,hwmods = "uart2"; clock-frequency = <48000000>; }; uart3: serial@48020000 { compatible = "ti,omap4-uart"; + reg = <0x48020000 0x100>; + interrupts = <0 74 0x4>; ti,hwmods = "uart3"; clock-frequency = <48000000>; }; uart4: serial@4806e000 { compatible = "ti,omap4-uart"; + reg = <0x4806e000 0x100>;
arch/arm/boot/dts/omap5.dtsi line 273
Quoted 10 lines
arch/arm/boot/dts/omap5.dtsi +4
-1+ interrupts = <0 70 0x4>; ti,hwmods = "uart4"; clock-frequency = <48000000>; }; uart5: serial@48066000 { - compatible = "ti,omap5-uart"; + compatible = "ti,omap4-uart"; + reg = <0x48066000 0x100>; + interrupts = <0 105 0x4>;
In Omap5 TRM, the interrupt number mentioned for uart5 is 138. How is 105 coming?
arch/arm/boot/dts/omap5.dtsi line 281
Quoted 9 lines
arch/arm/boot/dts/omap5.dtsi +3
-1ti,hwmods = "uart5"; clock-frequency = <48000000>; }; uart6: serial@48068000 { - compatible = "ti,omap6-uart"; + compatible = "ti,omap4-uart"; + reg = <0x48068000 0x100>; + interrupts = <0 106 0x4>;
Same here, TRM shows this number to be 139 ?
Quoted 3 lines
arch/arm/boot/dts/omap5.dtsi +0
-0ti,hwmods = "uart6"; clock-frequency = <48000000>; };
PATCH 3/4 ARM/dts: omap5: Update UART with address space and interrupts
Hi Sourav,
Quoted 41 lines · Sourav
Hi Sebastien,
Quoted 1 line · Sebastien Guiriec
Add base address and interrupt line inside Device Tree data for
Incomplete sentence!
Quoted 37 lines
Signed-off-by Sebastien Guiriec <[email protected]>--- arch/arm/boot/dts/omap5.dtsi | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-)arch/arm/boot/dts/omap5.dtsi +8
-0@@ -237,36 +237,48 @@ uart1: serial at 4806a000 { compatible = "ti,omap4-uart"; + reg = <0x4806a000 0x100>; + interrupts = <0 72 0x4>; ti,hwmods = "uart1"; clock-frequency = <48000000>; }; uart2: serial at 4806c000 { compatible = "ti,omap4-uart"; + reg = <0x4806c000 0x100>; + interrupts = <0 73 0x4>; ti,hwmods = "uart2"; clock-frequency = <48000000>; }; uart3: serial at 48020000 { compatible = "ti,omap4-uart"; + reg = <0x48020000 0x100>; + interrupts = <0 74 0x4>; ti,hwmods = "uart3"; clock-frequency = <48000000>; }; uart4: serial at 4806e000 { compatible = "ti,omap4-uart"; + reg = <0x4806e000 0x100>; + interrupts = <0 70 0x4>; ti,hwmods = "uart4"; clock-frequency = <48000000>;
Quoted 8 lines
arch/arm/boot/dts/omap5.dtsi line 273
Quoted 6 lines
arch/arm/boot/dts/omap5.dtsi +3
-1}; uart5: serial at 48066000 { - compatible = "ti,omap5-uart"; + compatible = "ti,omap4-uart"; + reg = <0x48066000 0x100>; + interrupts = <0 105 0x4>;In Omap5 TRM, the interrupt number mentioned for uart5 is 138. How is 105 coming?
It is from hwmod and thus from the HW spec. It looks like the TRM is wrong... or the HW spec :-)
Quoted 9 lines
arch/arm/boot/dts/omap5.dtsi line 281
Quoted 8 lines
arch/arm/boot/dts/omap5.dtsi +3
-1ti,hwmods = "uart5"; clock-frequency = <48000000>; }; uart6: serial at 48068000 { - compatible = "ti,omap6-uart"; + compatible = "ti,omap4-uart"; + reg = <0x48068000 0x100>; + interrupts = <0 106 0x4>;Same here, TRM shows this number to be 139 ?
Same source.
Regards,
Benoit
PATCH 3/4 ARM/dts: omap5: Update UART with address space and interrupts
Quoted 53 lines · Benoit Cousson
Hi Sourav,
Quoted 41 lines · Sourav
Hi Sebastien,
Quoted 1 line · Sebastien Guiriec
Add base address and interrupt line inside Device Tree data for
Incomplete sentence!
Quoted 37 lines
Signed-off-by Sebastien Guiriec <[email protected]>--- arch/arm/boot/dts/omap5.dtsi | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-)arch/arm/boot/dts/omap5.dtsi +8
-0@@ -237,36 +237,48 @@ uart1: serial at 4806a000 { compatible = "ti,omap4-uart"; + reg = <0x4806a000 0x100>; + interrupts = <0 72 0x4>; ti,hwmods = "uart1"; clock-frequency = <48000000>; }; uart2: serial at 4806c000 { compatible = "ti,omap4-uart"; + reg = <0x4806c000 0x100>; + interrupts = <0 73 0x4>; ti,hwmods = "uart2"; clock-frequency = <48000000>; }; uart3: serial at 48020000 { compatible = "ti,omap4-uart"; + reg = <0x48020000 0x100>; + interrupts = <0 74 0x4>; ti,hwmods = "uart3"; clock-frequency = <48000000>; }; uart4: serial at 4806e000 { compatible = "ti,omap4-uart"; + reg = <0x4806e000 0x100>; + interrupts = <0 70 0x4>; ti,hwmods = "uart4"; clock-frequency = <48000000>;Quoted 8 lines
arch/arm/boot/dts/omap5.dtsi line 273
Quoted 6 lines
arch/arm/boot/dts/omap5.dtsi +3
-1}; uart5: serial at 48066000 { - compatible = "ti,omap5-uart"; + compatible = "ti,omap4-uart"; + reg = <0x48066000 0x100>; + interrupts = <0 105 0x4>;In Omap5 TRM, the interrupt number mentioned for uart5 is 138. How is 105 coming?
Quoted 12 lines
It is from hwmod and thus from the HW spec. It looks like the TRM is wrong... or the HW spec :-)
Quoted 9 lines
arch/arm/boot/dts/omap5.dtsi line 281
Quoted 8 lines
arch/arm/boot/dts/omap5.dtsi +3
-1ti,hwmods = "uart5"; clock-frequency = <48000000>; }; uart6: serial at 48068000 { - compatible = "ti,omap6-uart"; + compatible = "ti,omap4-uart"; + reg = <0x48068000 0x100>; + interrupts = <0 106 0x4>;Same here, TRM shows this number to be 139 ?
In fact, even the TRM (ES1.0 NDA vM) is aligned with these data. Where did you see 138 and 139?
Regards,
Benoit
PATCH 3/4 ARM/dts: omap5: Update UART with address space and interrupts
Hi Benoit,
Quoted 64 lines · Benoit Cousson
Quoted 63 lines · Benoit Cousson
Hi Sourav,
Quoted 41 lines · Sourav
Hi Sebastien,
Quoted 1 line · Sebastien Guiriec
Add base address and interrupt line inside Device Tree data for
Incomplete sentence!
Quoted 37 lines
Signed-off-by Sebastien Guiriec <[email protected]>--- arch/arm/boot/dts/omap5.dtsi | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-)arch/arm/boot/dts/omap5.dtsi +8
-0@@ -237,36 +237,48 @@ uart1: serial@4806a000 { compatible = "ti,omap4-uart"; + reg = <0x4806a000 0x100>; + interrupts = <0 72 0x4>; ti,hwmods = "uart1"; clock-frequency = <48000000>; }; uart2: serial@4806c000 { compatible = "ti,omap4-uart"; + reg = <0x4806c000 0x100>; + interrupts = <0 73 0x4>; ti,hwmods = "uart2"; clock-frequency = <48000000>; }; uart3: serial@48020000 { compatible = "ti,omap4-uart"; + reg = <0x48020000 0x100>; + interrupts = <0 74 0x4>; ti,hwmods = "uart3"; clock-frequency = <48000000>; }; uart4: serial@4806e000 { compatible = "ti,omap4-uart"; + reg = <0x4806e000 0x100>; + interrupts = <0 70 0x4>; ti,hwmods = "uart4"; clock-frequency = <48000000>;Quoted 8 lines
arch/arm/boot/dts/omap5.dtsi line 273
Quoted 6 lines
arch/arm/boot/dts/omap5.dtsi +3
-1}; uart5: serial@48066000 { - compatible = "ti,omap5-uart"; + compatible = "ti,omap4-uart"; + reg = <0x48066000 0x100>; + interrupts = <0 105 0x4>;In Omap5 TRM, the interrupt number mentioned for uart5 is 138. How is 105 coming?
It is from hwmod and thus from the HW spec. It looks like the TRM is wrong... or the HW spec :-)
Quoted 8 lines
Quoted 8 lines
arch/arm/boot/dts/omap5.dtsi +3
-1ti,hwmods = "uart5"; clock-frequency = <48000000>; }; uart6: serial@48068000 { - compatible = "ti,omap6-uart"; + compatible = "ti,omap4-uart"; + reg = <0x48068000 0x100>; + interrupts = <0 106 0x4>;
Quoted 3 lines
Quoted 1 line
Quoted 1 line
Same here, TRM shows this number to be 139 ?
In fact, even the TRM (ES1.0 NDA vM) is aligned with these data. Where did you see 138 and 139?
I looked at Page 6300 of the above TRM, Figure 24-60. Is this place not correct to look up for these data?
Quoted 5 lines
Regards,
Benoit
PATCH 3/4 ARM/dts: omap5: Update UART with address space and interrupts
Quoted 66 lines · Sourav
Hi Benoit,
Quoted 64 lines · Benoit Cousson
Quoted 63 lines · Benoit Cousson
Hi Sourav,
Quoted 41 lines · Sourav
Hi Sebastien,
Quoted 1 line · Sebastien Guiriec
Add base address and interrupt line inside Device Tree data for
Incomplete sentence!
Quoted 37 lines
Signed-off-by Sebastien Guiriec <[email protected]>--- arch/arm/boot/dts/omap5.dtsi | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-)arch/arm/boot/dts/omap5.dtsi +8
-0@@ -237,36 +237,48 @@ uart1: serial at 4806a000 { compatible = "ti,omap4-uart"; + reg = <0x4806a000 0x100>; + interrupts = <0 72 0x4>; ti,hwmods = "uart1"; clock-frequency = <48000000>; }; uart2: serial at 4806c000 { compatible = "ti,omap4-uart"; + reg = <0x4806c000 0x100>; + interrupts = <0 73 0x4>; ti,hwmods = "uart2"; clock-frequency = <48000000>; }; uart3: serial at 48020000 { compatible = "ti,omap4-uart"; + reg = <0x48020000 0x100>; + interrupts = <0 74 0x4>; ti,hwmods = "uart3"; clock-frequency = <48000000>; }; uart4: serial at 4806e000 { compatible = "ti,omap4-uart"; + reg = <0x4806e000 0x100>; + interrupts = <0 70 0x4>; ti,hwmods = "uart4"; clock-frequency = <48000000>;Quoted 8 lines
arch/arm/boot/dts/omap5.dtsi line 273
Quoted 6 lines
arch/arm/boot/dts/omap5.dtsi +3
-1}; uart5: serial at 48066000 { - compatible = "ti,omap5-uart"; + compatible = "ti,omap4-uart"; + reg = <0x48066000 0x100>; + interrupts = <0 105 0x4>;In Omap5 TRM, the interrupt number mentioned for uart5 is 138. How is 105 coming?
It is from hwmod and thus from the HW spec. It looks like the TRM is wrong... or the HW spec :-)
Quoted 8 lines
Quoted 8 lines
arch/arm/boot/dts/omap5.dtsi +3
-1ti,hwmods = "uart5"; clock-frequency = <48000000>; }; uart6: serial at 48068000 { - compatible = "ti,omap6-uart"; + compatible = "ti,omap4-uart"; + reg = <0x48068000 0x100>; + interrupts = <0 106 0x4>;
Quoted 4 lines
Quoted 3 lines
Quoted 1 line
Quoted 1 line
Same here, TRM shows this number to be 139 ?
In fact, even the TRM (ES1.0 NDA vM) is aligned with these data. Where did you see 138 and 139?
I looked at Page 6300 of the above TRM, Figure 24-60. Is this place
correct page is 6366
Signature · 8 lines
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PATCH 3/4 ARM/dts: omap5: Update UART with address space and interrupts
In reply to SouravQuoted 67 lines · Sourav
Hi Benoit,
Quoted 65 lines · Benoit Cousson
Quoted 64 lines · Benoit Cousson
Hi Sourav,
Quoted 42 lines · Sourav
Hi Sebastien,
Quoted 1 line · Sebastien Guiriec
Add base address and interrupt line inside Device Tree data for
Incomplete sentence!
Quoted 38 lines
Signed-off-by Sebastien Guiriec <[email protected]>--- arch/arm/boot/dts/omap5.dtsi | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-)arch/arm/boot/dts/omap5.dtsi +8
-0@@ -237,36 +237,48 @@ uart1: serial at 4806a000 { compatible = "ti,omap4-uart"; + reg = <0x4806a000 0x100>; + interrupts = <0 72 0x4>; ti,hwmods = "uart1"; clock-frequency = <48000000>; }; uart2: serial at 4806c000 { compatible = "ti,omap4-uart"; + reg = <0x4806c000 0x100>; + interrupts = <0 73 0x4>; ti,hwmods = "uart2"; clock-frequency = <48000000>; }; uart3: serial at 48020000 { compatible = "ti,omap4-uart"; + reg = <0x48020000 0x100>; + interrupts = <0 74 0x4>; ti,hwmods = "uart3"; clock-frequency = <48000000>; }; uart4: serial at 4806e000 { compatible = "ti,omap4-uart"; + reg = <0x4806e000 0x100>; + interrupts = <0 70 0x4>; ti,hwmods = "uart4"; clock-frequency = <48000000>;Quoted 8 lines
arch/arm/boot/dts/omap5.dtsi line 273
Quoted 6 lines
arch/arm/boot/dts/omap5.dtsi +3
-1}; uart5: serial at 48066000 { - compatible = "ti,omap5-uart"; + compatible = "ti,omap4-uart"; + reg = <0x48066000 0x100>; + interrupts = <0 105 0x4>;In Omap5 TRM, the interrupt number mentioned for uart5 is 138. How is 105 coming?
It is from hwmod and thus from the HW spec. It looks like the TRM is wrong... or the HW spec :-)
Quoted 8 lines
Quoted 8 lines
arch/arm/boot/dts/omap5.dtsi +3
-1ti,hwmods = "uart5"; clock-frequency = <48000000>; }; uart6: serial at 48068000 { - compatible = "ti,omap6-uart"; + compatible = "ti,omap4-uart"; + reg = <0x48068000 0x100>; + interrupts = <0 106 0x4>;
Quoted 6 lines
Quoted 3 lines
Quoted 1 line
Quoted 1 line
Same here, TRM shows this number to be 139 ?
In fact, even the TRM (ES1.0 NDA vM) is aligned with these data. Where did you see 138 and 139?
I looked at Page 6300 of the above TRM, Figure 24-60. Is this place not correct to look
up for these data?
Nope. Well it should be accurate but since it is a diagram, it does not necessarily reflect the latest integration data like IRQ line.
You'd better use the table that list all the IRQ per CPU:
18.3.2 Interrupt Requests to INTC_MPU
Regards,
Benoit
PATCH 3/4 ARM/dts: omap5: Update UART with address space and interrupts
Quoted 74 lines · Benoit Cousson
Quoted 67 lines · Sourav
Hi Benoit,
Quoted 65 lines · Benoit Cousson
Quoted 64 lines · Benoit Cousson
Hi Sourav,
Quoted 42 lines · Sourav
Hi Sebastien,
Quoted 1 line · Sebastien Guiriec
Add base address and interrupt line inside Device Tree data for
Incomplete sentence!
Quoted 38 lines
Signed-off-by Sebastien Guiriec <[email protected]>--- arch/arm/boot/dts/omap5.dtsi | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-)arch/arm/boot/dts/omap5.dtsi +8
-0@@ -237,36 +237,48 @@ uart1: serial@4806a000 { compatible = "ti,omap4-uart"; + reg = <0x4806a000 0x100>; + interrupts = <0 72 0x4>; ti,hwmods = "uart1"; clock-frequency = <48000000>; }; uart2: serial@4806c000 { compatible = "ti,omap4-uart"; + reg = <0x4806c000 0x100>; + interrupts = <0 73 0x4>; ti,hwmods = "uart2"; clock-frequency = <48000000>; }; uart3: serial@48020000 { compatible = "ti,omap4-uart"; + reg = <0x48020000 0x100>; + interrupts = <0 74 0x4>; ti,hwmods = "uart3"; clock-frequency = <48000000>; }; uart4: serial@4806e000 { compatible = "ti,omap4-uart"; + reg = <0x4806e000 0x100>; + interrupts = <0 70 0x4>; ti,hwmods = "uart4"; clock-frequency = <48000000>;Quoted 8 lines
arch/arm/boot/dts/omap5.dtsi line 273
Quoted 6 lines
arch/arm/boot/dts/omap5.dtsi +3
-1}; uart5: serial@48066000 { - compatible = "ti,omap5-uart"; + compatible = "ti,omap4-uart"; + reg = <0x48066000 0x100>; + interrupts = <0 105 0x4>;In Omap5 TRM, the interrupt number mentioned for uart5 is 138. How is 105 coming?
It is from hwmod and thus from the HW spec. It looks like the TRM is wrong... or the HW spec :-)
Quoted 8 lines
Quoted 8 lines
arch/arm/boot/dts/omap5.dtsi +3
-1ti,hwmods = "uart5"; clock-frequency = <48000000>; }; uart6: serial@48068000 { - compatible = "ti,omap6-uart"; + compatible = "ti,omap4-uart"; + reg = <0x48068000 0x100>; + interrupts = <0 106 0x4>;Quoted 6 lines
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Same here, TRM shows this number to be 139 ?
In fact, even the TRM (ES1.0 NDA vM) is aligned with these data. Where did you see 138 and 139?
I looked at Page 6300 of the above TRM, Figure 24-60. Is this place not correct to look
up for these data?
Quoted 6 lines
Nope. Well it should be accurate but since it is a diagram, it does not necessarily reflect the latest integration data like IRQ line.
You'd better use the table that list all the IRQ per CPU:
18.3.2 Interrupt Requests to
INTC_MPU
Ahh. True. The table does show the numbers to be 105 and 106. Thanks for the pointer.
~Sourav
Quoted 3 lines
Regards,
Benoit
PATCH 3/4 ARM/dts: omap5: Update UART with address space and interrupts
Hi Sebestien,
Quoted 78 lines · Sourav
Quoted 77 lines · Benoit Cousson
Quoted 67 lines · Sourav
Hi Benoit,
Quoted 65 lines · Benoit Cousson
Quoted 64 lines · Benoit Cousson
Hi Sourav,
Quoted 42 lines · Sourav
Hi Sebastien,
Quoted 1 line · Sebastien Guiriec
Add base address and interrupt line inside Device Tree data for
Incomplete sentence!
Quoted 38 lines
Signed-off-by Sebastien Guiriec <[email protected]>--- arch/arm/boot/dts/omap5.dtsi | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-)arch/arm/boot/dts/omap5.dtsi +8
-0@@ -237,36 +237,48 @@ uart1: serial@4806a000 { compatible = "ti,omap4-uart"; + reg = <0x4806a000 0x100>; + interrupts = <0 72 0x4>; ti,hwmods = "uart1"; clock-frequency = <48000000>; }; uart2: serial@4806c000 { compatible = "ti,omap4-uart"; + reg = <0x4806c000 0x100>; + interrupts = <0 73 0x4>; ti,hwmods = "uart2"; clock-frequency = <48000000>; }; uart3: serial@48020000 { compatible = "ti,omap4-uart"; + reg = <0x48020000 0x100>; + interrupts = <0 74 0x4>; ti,hwmods = "uart3"; clock-frequency = <48000000>; }; uart4: serial@4806e000 { compatible = "ti,omap4-uart"; + reg = <0x4806e000 0x100>; + interrupts = <0 70 0x4>; ti,hwmods = "uart4"; clock-frequency = <48000000>;Quoted 8 lines
arch/arm/boot/dts/omap5.dtsi line 268
Quoted 6 lines
arch/arm/boot/dts/omap5.dtsi +3
-1}; uart5: serial@48066000 { - compatible = "ti,omap5-uart"; + compatible = "ti,omap4-uart"; + reg = <0x48066000 0x100>; + interrupts = <0 105 0x4>;In Omap5 TRM, the interrupt number mentioned for uart5 is 138. How is 105 coming?
It is from hwmod and thus from the HW spec. It looks like the TRM is wrong... or the HW spec :-)
Quoted 8 lines
Quoted 8 lines
arch/arm/boot/dts/omap5.dtsi +3
-1ti,hwmods = "uart5"; clock-frequency = <48000000>; }; uart6: serial@48068000 { - compatible = "ti,omap6-uart"; + compatible = "ti,omap4-uart"; + reg = <0x48068000 0x100>; + interrupts = <0 106 0x4>;Quoted 6 lines
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Same here, TRM shows this number to be 139 ?
In fact, even the TRM (ES1.0 NDA vM) is aligned with these data. Where did you see 138 and 139?
I looked at Page 6300 of the above TRM, Figure 24-60. Is this place not correct to look
up for these data?Nope. Well it should be accurate but since it is a diagram, it does not necessarily reflect the latest integration data like IRQ line.
Quoted 11 lines
Quoted 3 lines
You'd better use the table that list all the IRQ per CPU:
18.3.2 Interrupt Requests to
INTC_MPUAhh. True. The table does show the numbers to be 105 and 106. Thanks for the pointer.
~Sourav
Quoted 3 lines
Regards,
Benoit
After fixing the minor comment on the commit log, you can add
Quoted 5 lines
_______________________________________________
linux-arm-kernel mailing list
[email protected]
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
PATCH 4/4 ARM/dts: omap5: Update MMC with address space and interrupts
In reply to Sebastien GuiriecAdd base address and interrupt line inside Device Tree data for OMAP5.
--- arch/arm/boot/dts/omap5.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+)
arch/arm/boot/dts/omap5.dtsi +10 -0
@@ -285,6 +285,8 @@ mmc1: mmc at 4809c000 { compatible = "ti,omap4-hsmmc"; + reg = <0x4809c000 0x400>; + interrupts = <0 83 0x4>; ti,hwmods = "mmc1"; ti,dual-volt; ti,needs-special-reset;
@@ -292,24 +294,32 @@ mmc2: mmc at 480b4000 { compatible = "ti,omap4-hsmmc"; + reg = <0x480b4000 0x400>; + interrupts = <0 86 0x4>; ti,hwmods = "mmc2"; ti,needs-special-reset; }; mmc3: mmc at 480ad000 { compatible = "ti,omap4-hsmmc"; + reg = <0x480ad000 0x400>; + interrupts = <0 94 0x4>; ti,hwmods = "mmc3"; ti,needs-special-reset; }; mmc4: mmc at 480d1000 { compatible = "ti,omap4-hsmmc"; + reg = <0x480d1000 0x400>; + interrupts = <0 96 0x4>; ti,hwmods = "mmc4"; ti,needs-special-reset; }; mmc5: mmc at 480d5000 { compatible = "ti,omap4-hsmmc"; + reg = <0x480d5000 0x400>; + interrupts = <0 59 0x4>; ti,hwmods = "mmc5"; ti,needs-special-reset; };
Signature · 1 line
1.7.10.4
cover ARM/dts: Update OMAP5 with address space and interrupts
In reply to Sebastien GuiriecHi Seb,
Good work. Thanks for that series.
Just update it with all the acked-by you've got from the TI driver folks
+ the minor comment and I'll pull it in the for_3.8/dts branch.
That's a detail but you should update the subject with "ARM: dts: OMAP5:
XXX" prefix for consistency with the latest naming convention.
Please, Cc the DT list as well.
Regards,
Benoit
Quoted 18 lines · Sebastien Guiriec
Since kernel 3.7 the DTS data are not overwriten by hwmod data we can add the address space and interrupt line description inside dtsi file for OMAP5. This serie is updating the current OMAP5 IP with missing entry.
It has been tested on OMAP5 with 3.7-audio-display feature tree.
- MMC is probing and functional
- TWL6041 probing (GPIO/I2C)
- booting (UART)Sebastien Guiriec (4):
ARM/dts: omap5: Update GPIO with address space and interrupt ARM/dts: omap5: Update I2C with address space and interrupts ARM/dts: omap5: Update UART with address space and interrupts ARM/dts: omap5: Update MMC with address space and interruptsarch/arm/boot/dts/omap5.dtsi | 56 +++++++++++++++++++++++++++++++++++++++--- 1 file changed, 52 insertions(+), 4 deletions(-)
cover ARM/dts: Update OMAP5 with address space and interrupts
Hi Benoit,
Quoted 9 lines · Benoit Cousson
Hi Seb,
Good work. Thanks for that series.
Just update it with all the acked-by you've got from the TI driver folks
+ the minor comment and I'll pull it in the for_3.8/dts branch.That's a detail but you should update the subject with "ARM: dts: OMAP5:
XXX" prefix for consistency with the latest naming convention.
Thanks for the information I will update the series. I was thinking that it was the convention according to a past talk. I will update our full audio/display feature tree with this convention.
Quoted 26 lines
Please, Cc the DT list as well.
Regards,
BenoitQuoted 18 lines · Sebastien Guiriec
Since kernel 3.7 the DTS data are not overwriten by hwmod data we can add the address space and interrupt line description inside dtsi file for OMAP5. This serie is updating the current OMAP5 IP with missing entry.
It has been tested on OMAP5 with 3.7-audio-display feature tree.
- MMC is probing and functional
- TWL6041 probing (GPIO/I2C)
- booting (UART)Sebastien Guiriec (4):
ARM/dts: omap5: Update GPIO with address space and interrupt ARM/dts: omap5: Update I2C with address space and interrupts ARM/dts: omap5: Update UART with address space and interrupts ARM/dts: omap5: Update MMC with address space and interruptsarch/arm/boot/dts/omap5.dtsi | 56 +++++++++++++++++++++++++++++++++++++++--- 1 file changed, 52 insertions(+), 4 deletions(-)