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ARM: tegra: dt: add L2 cache controller

PATCH New Joseph Lo 2 participants 2 messages Oct 29, 2012

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Device tree bindings Tegra architecture support
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Joseph Lo

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#0 lore raw

PATCH v2 1/2 ARM: tegra: dt: add L2 cache controller

Add L2 cache controller binding into DT for Tegra.

Signed-off-by Joseph Lo <[email protected]>

---
V2:
* remove "L2" label for cache-controller DT binding

---
 arch/arm/boot/dts/tegra20.dtsi |    9 +++++++++
 arch/arm/boot/dts/tegra30.dtsi |    9 +++++++++
 2 files changed, 18 insertions(+), 0 deletions(-)
arch/arm/boot/dts/tegra20.dtsi +9 -0
index 6934bca..21ca861 100644
@@ -4,6 +4,15 @@
 	compatible = "nvidia,tegra20";
 	interrupt-parent = <&intc>;
 
+	cache-controller at 50043000 {
+		compatible = "arm,pl310-cache";
+		reg = <0x50043000 0x1000>;
+		arm,data-latency = <5 5 2>;
+		arm,tag-latency = <4 4 2>;
+		cache-unified;
+		cache-level = <2>;
+	};
+
 	timer at 50004600 {
 		compatible = "arm,cortex-a9-twd-timer";
 		reg = <0x50040600 0x20>;
arch/arm/boot/dts/tegra30.dtsi +9 -0
index 81f5df4..568f291 100644
@@ -4,6 +4,15 @@
 	compatible = "nvidia,tegra30";
 	interrupt-parent = <&intc>;
 
+	cache-controller at 50043000 {
+		compatible = "arm,pl310-cache";
+		reg = <0x50043000 0x1000>;
+		arm,data-latency = <6 6 2>;
+		arm,tag-latency = <5 5 2>;
+		cache-unified;
+		cache-level = <2>;
+	};
+
 	timer at 50004600 {
 		compatible = "arm,cortex-a9-twd-timer";
 		reg = <0x50040600 0x20>;
Signature · 1 line
1.7.0.4
#1 lore raw

PATCH v2 1/2 ARM: tegra: dt: add L2 cache controller

Quoted 1 line · Joseph Lo

Add L2 cache controller binding into DT for Tegra.

The series applied to Tegra's tree for 3.8. Thanks.