Convert p1_p2_rdb_pc to new spl

RFC PATCH New Scott Wood 8 participants 81 messages Sep 22, 2012 – Nov 26, 2012 1 message not in the archive

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PowerPC Kbuild Memory technology devices (MTD) Char and misc drivers +1 more subsystems

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Scott Wood

author

2012-09-22 00:01 UTC #0 lore raw

cover Convert p1_p2_rdb_pc to new spl

This is based on a merge of top-of-tree plus the 85xx tree and the spl framework branch (it doesn't use the SPL framework code because of size constraints, but I wanted to make sure there were no conflicts with it).

Tested on P2020RDB-PC_NAND and P1021RDB-PC_36BIT_NAND.

Jos? Miguel Gon?alves (1):
Add u-boot-pad.bin target to the Makefile

Scott Wood (16):
spl: rename u-boot-pad.bin to u-boot-with-spl.bin
powerpc: remove .fixup test
powerpc/mpc85xx: fix TLB alignment powerpc/mpc8xxx: move LAW code into arch/powerpc/cpu/mpc8xxx spl/mpc85xx: move udelay to cpu code
spl: include resetvec and lib8xxx
spl/powerpc: introduce CONFIG_SPL_INIT_MINIMAL spl/85xx: new SPL support
powerpc/p1_p2_rdb_pc: new SPL support
spl/nand: introduce CONFIG_SPL_NAND_MINIMAL spl/nand: config symbol documentation
spl/nand: Add minimal-spl driver for Freescale eLBC NAND
spl: introduce CONFIG_SPL_TARGET
p1_p2_rdb_pc: convert from nand_spl to new spl powerpc/mpc85xx/p2020rdb-pc: fix SPL DDR config
ns16550: wait for TENT before initializing

 Makefile                                           |   24 ++-
 README                                             |   32 +++-
 arch/powerpc/cpu/mpc85xx/Makefile                  |   39 +++--
 arch/powerpc/cpu/mpc85xx/cpu.c                     |    3 +-
 arch/powerpc/cpu/mpc85xx/cpu_init_nand.c           |   19 ++-
 arch/powerpc/cpu/mpc85xx/start.S                   |   58 ++++---
 arch/powerpc/cpu/mpc85xx/tlb.c                     |    4 +-
 arch/powerpc/cpu/mpc85xx/u-boot-spl.lds            |   81 ++++++++++
 arch/powerpc/cpu/mpc8xxx/Makefile                  |   17 ++
 .../fsl_law.c => arch/powerpc/cpu/mpc8xxx/law.c    |   11 +-
 arch/powerpc/lib/Makefile                          |   23 ++-
 board/freescale/p1_p2_rdb_pc/Makefile              |   16 ++
 board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c        |    2 +-
 .../freescale/p1_p2_rdb_pc/spl_minimal.c           |    3 +-
 board/freescale/p1_p2_rdb_pc/tlb.c                 |    7 +-
 doc/README.mpc85xx                                 |    2 +-
 drivers/misc/Makefile                              |    1 -
 drivers/mtd/nand/Makefile                          |   41 +++--
 drivers/mtd/nand/fsl_elbc_spl.c                    |  168 ++++++++++++++++++++
 drivers/serial/ns16550.c                           |    3 +
 include/configs/p1_p2_rdb_pc.h                     |   74 ++++-----
 nand_spl/board/freescale/common.c                  |   40 -----
 nand_spl/board/freescale/mpc8536ds/Makefile        |    2 +-
 nand_spl/board/freescale/mpc8569mds/Makefile       |    2 +-
 nand_spl/board/freescale/mpc8572ds/Makefile        |    2 +-
 nand_spl/board/freescale/p1010rdb/Makefile         |    8 +-
 nand_spl/board/freescale/p1023rds/Makefile         |    8 +-
 nand_spl/board/freescale/p1_p2_rdb/Makefile        |    2 +-
 nand_spl/board/freescale/p1_p2_rdb_pc/Makefile     |  141 ----------------
 spl/Makefile                                       |   21 +++
 30 files changed, 542 insertions(+), 312 deletions(-)
 create mode 100644 arch/powerpc/cpu/mpc85xx/u-boot-spl.lds
 rename drivers/misc/fsl_law.c => arch/powerpc/cpu/mpc8xxx/law.c (95%)
 rename nand_spl/board/freescale/p1_p2_rdb_pc/nand_boot.c => board/freescale/p1_p2_rdb_pc/spl_minimal.c (97%)
 create mode 100644 drivers/mtd/nand/fsl_elbc_spl.c
 delete mode 100644 nand_spl/board/freescale/common.c
 delete mode 100644 nand_spl/board/freescale/p1_p2_rdb_pc/Makefile

Signature · 1 line

1.7.9.5

Scott Wood

author

2012-09-22 00:01 UTC #1 lore raw

RFC PATCH 1/17 Add u-boot-pad.bin target to the Makefile

From: Jos? Miguel Gon?alves <[email protected]>

Samsung's S3C24XX SoCs need this in order to generate a binary image with a padded SPL concatenated with U-Boot.

Signed-off-by Jos? Miguel Gon?alves <[email protected]>

Signed-off-by Scott Wood <[email protected]>

---
 Makefile |   11 ++++++-----
 1 file changed, 6 insertions(+), 5 deletions(-)

Makefile +6 -5

index 23bd65a..025106e 100644
@@ -433,14 +433,15 @@ $(obj)u-boot.sha1:	$(obj)u-boot.bin
 $(obj)u-boot.dis:	$(obj)u-boot
 		$(OBJDUMP) -d $< > $@
 
-$(obj)u-boot.ubl:       $(obj)spl/u-boot-spl.bin $(obj)u-boot.bin
+$(obj)u-boot-pad.bin:       $(obj)spl/u-boot-spl.bin $(obj)u-boot.bin
 		$(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $(obj)spl/u-boot-spl $(obj)spl/u-boot-spl-pad.bin
-		cat $(obj)spl/u-boot-spl-pad.bin $(obj)u-boot.bin > $(obj)u-boot-ubl.bin
-		$(obj)tools/mkimage -n $(UBL_CONFIG) -T ublimage \
-		-e $(CONFIG_SYS_TEXT_BASE) -d $(obj)u-boot-ubl.bin $(obj)u-boot.ubl
-		rm $(obj)u-boot-ubl.bin
+		cat $(obj)spl/u-boot-spl-pad.bin $(obj)u-boot.bin > $(obj)u-boot-pad.bin
 		rm $(obj)spl/u-boot-spl-pad.bin
 
+$(obj)u-boot.ubl:       $(obj)spl/u-boot-pad.bin
+		$(obj)tools/mkimage -n $(UBL_CONFIG) -T ublimage \
+		-e $(CONFIG_SYS_TEXT_BASE) -d $(obj)u-boot-pad.bin $(obj)u-boot.ubl
+
 $(obj)u-boot.ais:       $(obj)spl/u-boot-spl.bin $(obj)u-boot.img
 		$(obj)tools/mkimage -s -n /dev/null -T aisimage \
 			-e $(CONFIG_SPL_TEXT_BASE) \

Signature · 1 line

1.7.9.5

Scott Wood

author

2012-09-22 00:01 UTC #2 lore raw

RFC PATCH 2/17 spl: rename u-boot-pad.bin to u-boot-with-spl.bin

In reply to Scott Wood

This is temporary until we settle on a naming scheme.

Signed-off-by Scott Wood <[email protected]>

---
 Makefile |    8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

Makefile +4 -4

index 025106e..dd879a5 100644
@@ -433,14 +433,14 @@ $(obj)u-boot.sha1:	$(obj)u-boot.bin
 $(obj)u-boot.dis:	$(obj)u-boot
 		$(OBJDUMP) -d $< > $@
 
-$(obj)u-boot-pad.bin:       $(obj)spl/u-boot-spl.bin $(obj)u-boot.bin
+$(obj)u-boot-with-spl.bin: $(obj)spl/u-boot-spl.bin $(obj)u-boot.bin
 		$(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $(obj)spl/u-boot-spl $(obj)spl/u-boot-spl-pad.bin
-		cat $(obj)spl/u-boot-spl-pad.bin $(obj)u-boot.bin > $(obj)u-boot-pad.bin
+		cat $(obj)spl/u-boot-spl-pad.bin $(obj)u-boot.bin > $@
 		rm $(obj)spl/u-boot-spl-pad.bin
 
-$(obj)u-boot.ubl:       $(obj)spl/u-boot-pad.bin
+$(obj)u-boot.ubl:       $(obj)spl/u-boot-with-spl.bin
 		$(obj)tools/mkimage -n $(UBL_CONFIG) -T ublimage \
-		-e $(CONFIG_SYS_TEXT_BASE) -d $(obj)u-boot-pad.bin $(obj)u-boot.ubl
+		-e $(CONFIG_SYS_TEXT_BASE) -d $< $(obj)u-boot.ubl
 
 $(obj)u-boot.ais:       $(obj)spl/u-boot-spl.bin $(obj)u-boot.img
 		$(obj)tools/mkimage -s -n /dev/null -T aisimage \

Signature · 1 line

1.7.9.5

Scott Wood

author

2012-09-22 00:01 UTC #3 lore raw

RFC PATCH 3/17 powerpc: remove .fixup test

In reply to Scott Wood

This was introduced by commit 244615197469dd6fe75ae082f38424b97c79aeaf, but it fails in a minimal SPL build where the only thing in arch/powerpc/lib is cache.c, which apparently doesn't generate any fixup records.

If this check is really still needed, it should be moved somewhere more appropriate, but given that it's been three years and no other architecture does a test like this, I think we can remove it. It would have been nice if the original commit said how old the problematic toolchains were.

Signed-off-by Scott Wood <[email protected]>

Cc Peter Tyser <[email protected]>

---
 arch/powerpc/lib/Makefile |    6 ------
 1 file changed, 6 deletions(-)

arch/powerpc/lib/Makefile +0 -6

index cdd62a2..6e92005 100644
@@ -75,12 +75,6 @@ TARGETS += $(LIB)
 all: $(TARGETS)
 
 $(LIB):	$(obj).depend $(OBJS)
-	@if ! $(CROSS_COMPILE)readelf -S $(OBJS) | grep -q '\.fixup.*PROGBITS';\
-	then \
-		echo "ERROR: Your compiler doesn't generate .fixup sections!";\
-		echo "       Upgrade to a recent toolchain."; \
-		exit 1; \
-	fi;
 	$(call cmd_link_o_target, $(OBJS))
 
 $(LIBGCC): $(obj).depend $(LGOBJS)

Signature · 1 line

1.7.9.5

Peter Tyser

2012-09-24 15:30 UTC #4 lore raw

RFC PATCH 3/17 powerpc: remove .fixup test

Hi Scott,

Quoted 9 lines · Scott Wood

This was introduced by commit 244615197469dd6fe75ae082f38424b97c79aeaf, but it fails in a minimal SPL build where the only thing in arch/powerpc/lib is cache.c, which apparently doesn't generate any fixup records.
If this check is really still needed, it should be moved somewhere more appropriate, but given that it's been three years and no other architecture does a test like this, I think we can remove it. It would have been nice if the original commit said how old the problematic toolchains were.

There was a discussion about it a long while back that has some version information:
http://www.mail-archive.com/u-boot at lists.denx.de/msg21415.html

Based on my testing I only could reproduce the issue with 3.x versions, which are 7+ years old.

Best,
Peter

Scott Wood

author

2012-09-24 18:47 UTC #5 lore raw

RFC PATCH 3/17 powerpc: remove .fixup test

Quoted 17 lines · Peter Tyser

Hi Scott,
Quoted 1 line · Scott Wood
This was introduced by commit
244615197469dd6fe75ae082f38424b97c79aeaf, but it
Quoted 1 line
fails in a minimal SPL build where the only thing in
arch/powerpc/lib is
Quoted 3 lines
cache.c, which apparently doesn't generate any fixup records.
If this check is really still needed, it should be moved somewhere
more
Quoted 2 lines
appropriate, but given that it's been three years and no other architecture does a test like this, I think we can remove it. It
would
Quoted 2 lines
have been nice if the original commit said how old the problematic toolchains were.

Quoted 8 lines

There was a discussion about it a long while back that has some version
information:
http://www.mail-archive.com/u-boot at lists.denx.de/msg21415.html
Based on my testing I only could reproduce the issue with 3.x versions,
which are 7+ years old.

So do you think we still need this check (moved to someplace we can be sure will generate fixups), or is it time to remove it?

-Scott

Tom Rini

2012-09-24 23:38 UTC #6 lore raw

RFC PATCH 3/17 powerpc: remove .fixup test

Quoted 23 lines · Scott Wood

Quoted 22 lines · Peter Tyser
Hi Scott,
Quoted 1 line · Scott Wood
This was introduced by commit
244615197469dd6fe75ae082f38424b97c79aeaf, but it
Quoted 1 line
fails in a minimal SPL build where the only thing in
arch/powerpc/lib is
Quoted 3 lines
cache.c, which apparently doesn't generate any fixup records.
If this check is really still needed, it should be moved
somewhere more
Quoted 2 lines
appropriate, but given that it's been three years and no other architecture does a test like this, I think we can remove it.
It would
Quoted 2 lines
have been nice if the original commit said how old the problematic toolchains were.
There was a discussion about it a long while back that has some version
information:
http://www.mail-archive.com/u-boot at lists.denx.de/msg21415.html

Quoted 6 lines

Quoted 3 lines
Based on my testing I only could reproduce the issue with 3.x versions,
which are 7+ years old.
So do you think we still need this check (moved to someplace we can be sure will generate fixups), or is it time to remove it?

On ARM, when we build in THUMB mode we make sure to have a new enough gcc to produce a working binary. Maybe given the age of the broken toolchains adding something like the checkthumb rule in Makefile and arch/arm/config.mk and failing on too old would be right?

Signature · 8 lines

Tom
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Scott Wood

author

2012-09-22 00:01 UTC #7 lore raw

RFC PATCH 4/17 powerpc/mpc85xx: fix TLB alignment

In reply to Scott Wood

In the RAMBOOT/SPL case we were creating a TLB entry starting at CONFIG_SYS_MONITOR_BASE, and just hoping that the base was properly aligned for the TLB entry size. This turned out to not be the case with NAND SPL because the main U-Boot starts at an offset into the image in order to skip the SPL itself.

Fix the TLB entry to always start at a proper alignment. We still assume that CONFIG_SYS_MONITOR_BASE doesn't start immediately before a large-page boundary thus requiring multiple TLB entries.

Signed-off-by Scott Wood <[email protected]>

Cc Andy Fleming <[email protected]>

---
 arch/powerpc/cpu/mpc85xx/start.S |   21 +++++++++++++--------
 1 file changed, 13 insertions(+), 8 deletions(-)

arch/powerpc/cpu/mpc85xx/start.S +13 -8

index 9e04257..958ed6f 100644
@@ -261,12 +261,13 @@ l2_disabled:
 	lis     r7,FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256K)@h
 	ori     r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256K)@l
 
-	lis     r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE, (MAS2_I))@h
-	ori     r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE,
+	lis     r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE & 0xfffc0000,
+							(MAS2_I))@h
+	ori     r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE & 0xfffc000,
 							(MAS2_I))@l
-	lis     r9,FSL_BOOKE_MAS3(CONFIG_SYS_MONITOR_BASE, 0,
+	lis     r9,FSL_BOOKE_MAS3(CONFIG_SYS_MONITOR_BASE & 0xfffc0000, 0,
 						(MAS3_SX|MAS3_SW|MAS3_SR))@h
-	ori     r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_MONITOR_BASE, 0,
+	ori     r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_MONITOR_BASE & 0xfffc0000, 0,
 						(MAS3_SX|MAS3_SW|MAS3_SR))@l
 #endif
 	mtspr   MAS0,r6

@@ -1050,11 +1051,15 @@ create_init_ram_area:
 	lis     r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_1M)@h
 	ori     r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_1M)@l
 
-	lis     r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE, (MAS2_I|MAS2_G))@h
-	ori     r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE, (MAS2_I|MAS2_G))@l
+	lis     r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE & 0xfff00000,
+			(MAS2_I|MAS2_G))@h
+	ori     r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE,
+			(MAS2_I|MAS2_G))@l
 
-	lis     r9,FSL_BOOKE_MAS3(CONFIG_SYS_MONITOR_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h
-	ori     r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_MONITOR_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l
+	lis     r9,FSL_BOOKE_MAS3(CONFIG_SYS_MONITOR_BASE & 0xfff00000,
+			0, (MAS3_SX|MAS3_SW|MAS3_SR))@h
+	ori     r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_MONITOR_BASE & 0xfff00000,
+			0, (MAS3_SX|MAS3_SW|MAS3_SR))@l
 #endif
 
 	mtspr   MAS0,r6

Signature · 1 line

1.7.9.5

Scott Wood

author

2012-09-22 00:01 UTC #8 lore raw

RFC PATCH 5/17 powerpc/mpc8xxx: move LAW code into arch/powerpc/cpu/mpc8xxx

In reply to Scott Wood

It's arch code and not a driver, so move it where it belongs. When it originally went into drivers/misc there was no 8xxx CPU directory.

This will make new-SPL support a little easier since we can keep the CPU stuff together and not need to pull stuff in from drivers/misc.

Signed-off-by Scott Wood <[email protected]>

Cc Andy Fleming <[email protected]>

---
 arch/powerpc/cpu/mpc8xxx/Makefile                  |    1 +
 .../fsl_law.c => arch/powerpc/cpu/mpc8xxx/law.c    |    0
 drivers/misc/Makefile                              |    1 -
 nand_spl/board/freescale/mpc8536ds/Makefile        |    2 +-
 nand_spl/board/freescale/mpc8569mds/Makefile       |    2 +-
 nand_spl/board/freescale/mpc8572ds/Makefile        |    2 +-
 nand_spl/board/freescale/p1010rdb/Makefile         |    2 +-
 nand_spl/board/freescale/p1023rds/Makefile         |    2 +-
 nand_spl/board/freescale/p1_p2_rdb/Makefile        |    2 +-
 nand_spl/board/freescale/p1_p2_rdb_pc/Makefile     |    2 +-
 10 files changed, 8 insertions(+), 8 deletions(-)
 rename drivers/misc/fsl_law.c => arch/powerpc/cpu/mpc8xxx/law.c (100%)

arch/powerpc/cpu/mpc8xxx/Makefile +1 -0

index 4ae26e4..86344a7 100644
@@ -18,6 +18,7 @@ COBJS-$(CONFIG_OF_LIBFDT) += fdt.o
 COBJS-$(CONFIG_FSL_IFC) += fsl_ifc.o
 COBJS-$(CONFIG_FSL_LBC) += fsl_lbc.o
 COBJS-$(CONFIG_SYS_SRIO) += srio.o
+COBJS-$(CONFIG_FSL_LAW) += law.o
 
 SRCS	:= $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
 OBJS	:= $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))

arch/powerpc/cpu/mpc8xxx/law.c renamed from drivers/misc/fsl_law.c +0 -0

similarity index 100%
rename from drivers/misc/fsl_law.c
rename to arch/powerpc/cpu/mpc8xxx/law.c

drivers/misc/Makefile +0 -1

index 271463c..3b19e5f 100644
@@ -27,7 +27,6 @@ LIB	:= $(obj)libmisc.o
 
 COBJS-$(CONFIG_ALI152X) += ali512x.o
 COBJS-$(CONFIG_DS4510)  += ds4510.o
-COBJS-$(CONFIG_FSL_LAW) += fsl_law.o
 COBJS-$(CONFIG_GPIO_LED) += gpio_led.o
 COBJS-$(CONFIG_FSL_MC9SDZ60) += mc9sdz60.o
 COBJS-$(CONFIG_NS87308) += ns87308.o

nand_spl/board/freescale/mpc8536ds/Makefile +1 -1

index 43da3df..cd1b864 100644
@@ -80,7 +80,7 @@ $(obj)cpu_init_nand.c:
 
 $(obj)fsl_law.c:
 	@rm -f $(obj)fsl_law.c
-	ln -sf $(SRCTREE)/drivers/misc/fsl_law.c $(obj)fsl_law.c
+	ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc8xxx/law.c $(obj)fsl_law.c
 
 $(obj)law.c:
 	@rm -f $(obj)law.c

nand_spl/board/freescale/mpc8569mds/Makefile +1 -1

index 43da3df..cd1b864 100644
@@ -80,7 +80,7 @@ $(obj)cpu_init_nand.c:
 
 $(obj)fsl_law.c:
 	@rm -f $(obj)fsl_law.c
-	ln -sf $(SRCTREE)/drivers/misc/fsl_law.c $(obj)fsl_law.c
+	ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc8xxx/law.c $(obj)fsl_law.c
 
 $(obj)law.c:
 	@rm -f $(obj)law.c

nand_spl/board/freescale/mpc8572ds/Makefile +1 -1

index 43da3df..cd1b864 100644
@@ -80,7 +80,7 @@ $(obj)cpu_init_nand.c:
 
 $(obj)fsl_law.c:
 	@rm -f $(obj)fsl_law.c
-	ln -sf $(SRCTREE)/drivers/misc/fsl_law.c $(obj)fsl_law.c
+	ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc8xxx/law.c $(obj)fsl_law.c
 
 $(obj)law.c:
 	@rm -f $(obj)law.c

nand_spl/board/freescale/p1010rdb/Makefile +1 -1

index cdbd492..8cc1e72 100644
@@ -81,7 +81,7 @@ $(obj)cpu_init_nand.c:
 
 $(obj)fsl_law.c:
 	@rm -f $(obj)fsl_law.c
-	ln -sf $(SRCTREE)/drivers/misc/fsl_law.c $(obj)fsl_law.c
+	ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc8xxx/law.c $(obj)fsl_law.c
 
 $(obj)law.c:
 	@rm -f $(obj)law.c

nand_spl/board/freescale/p1023rds/Makefile +1 -1

index da43521..c1c179e 100644
@@ -76,7 +76,7 @@ $(obj)cpu_init_nand.c:
 
 $(obj)fsl_law.c:
 	@rm -f $(obj)fsl_law.c
-	ln -sf $(SRCTREE)/drivers/misc/fsl_law.c $(obj)fsl_law.c
+	ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc8xxx/law.c $(obj)fsl_law.c
 
 $(obj)law.c:
 	@rm -f $(obj)law.c

nand_spl/board/freescale/p1_p2_rdb/Makefile +1 -1

index 43da3df..cd1b864 100644
@@ -80,7 +80,7 @@ $(obj)cpu_init_nand.c:
 
 $(obj)fsl_law.c:
 	@rm -f $(obj)fsl_law.c
-	ln -sf $(SRCTREE)/drivers/misc/fsl_law.c $(obj)fsl_law.c
+	ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc8xxx/law.c $(obj)fsl_law.c
 
 $(obj)law.c:
 	@rm -f $(obj)law.c

nand_spl/board/freescale/p1_p2_rdb_pc/Makefile +1 -1

index 46cf709..eb0cd2a 100644
@@ -81,7 +81,7 @@ $(obj)cpu_init_nand.c:
 
 $(obj)fsl_law.c:
 	@rm -f $(obj)fsl_law.c
-	ln -sf $(SRCTREE)/drivers/misc/fsl_law.c $(obj)fsl_law.c
+	ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc8xxx/law.c $(obj)fsl_law.c
 
 $(obj)law.c:
 	@rm -f $(obj)law.c

Signature · 1 line

1.7.9.5

Scott Wood

author

2012-09-22 00:01 UTC #9 lore raw

RFC PATCH 6/17 spl/mpc85xx: move udelay to cpu code

In reply to Scott Wood

It applies to non-Freescale 85xx boards as well as Freescale boards, so it doesn't belong in board/freescale. Plus, it needs to come out of nand_spl if it's to be used by the new SPL.

Signed-off-by Scott Wood <[email protected]>

Cc Andy Fleming <[email protected]>

---
 arch/powerpc/cpu/mpc85xx/cpu_init_nand.c       |   17 ++++++++++
 nand_spl/board/freescale/common.c              |   40 ------------------------
 nand_spl/board/freescale/p1010rdb/Makefile     |    6 +---
 nand_spl/board/freescale/p1023rds/Makefile     |    6 +---
 nand_spl/board/freescale/p1_p2_rdb_pc/Makefile |    6 +---
 5 files changed, 20 insertions(+), 55 deletions(-)
 delete mode 100644 nand_spl/board/freescale/common.c

arch/powerpc/cpu/mpc85xx/cpu_init_nand.c +17 -0

index bf7a6f6..0589497 100644
@@ -21,9 +21,13 @@
  */
 
 #include <common.h>
+#include <asm/processor.h>
+#include <asm/global_data.h>
 #include <asm/fsl_ifc.h>
 #include <asm/io.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 void cpu_init_f(void)
 {
 #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)

@@ -40,3 +44,16 @@ void cpu_init_f(void)
 		(MPC85xx_L2CTL_L2E | MPC85xx_L2CTL_L2SRAM_ENTIRE));
 #endif
 }
+
+#ifndef CONFIG_SYS_FSL_TBCLK_DIV
+#define CONFIG_SYS_FSL_TBCLK_DIV 8
+#endif
+
+void udelay(unsigned long usec)
+{
+	u32 ticks_per_usec = gd->bus_clk / (CONFIG_SYS_FSL_TBCLK_DIV * 1000000);
+	u32 ticks = ticks_per_usec * usec;
+	u32 s = mfspr(SPRN_TBRL);
+
+	while ((mfspr(SPRN_TBRL) - s) < ticks);
+}

nand_spl/board/freescale/common.c deleted +0 ~~-40~~

deleted file mode 100644
index 0e099bc..0000000
@@ -1,40 +0,0 @@
-/*
- * Copyright 2012 Freescale Semiconductor, Inc.
- * Author: Matthew McClintock <[email protected]>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- *
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- */
-
-#include <common.h>
-#include <asm/processor.h>
-#include <asm/global_data.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#ifndef CONFIG_SYS_FSL_TBCLK_DIV
-#define CONFIG_SYS_FSL_TBCLK_DIV 8
-#endif
-
-void udelay(unsigned long usec)
-{
-	u32 ticks_per_usec = gd->bus_clk / (CONFIG_SYS_FSL_TBCLK_DIV * 1000000);
-	u32 ticks = ticks_per_usec * usec;
-	u32 s = mfspr(SPRN_TBRL);
-
-	while ((mfspr(SPRN_TBRL) - s) < ticks);
-}

nand_spl/board/freescale/p1010rdb/Makefile +1 -5

index 8cc1e72..9f3bec7 100644
@@ -39,8 +39,7 @@ CFLAGS	+= -DCONFIG_NAND_SPL
 
 SOBJS	= start.o resetvec.o ticks.o
 COBJS	= cache.o cpu_init_early.o cpu_init_nand.o fsl_law.o law.o \
-	  nand_boot.o nand_boot_fsl_ifc.o ns16550.o tlb.o tlb_table.o \
-	  ../common.o
+	  nand_boot.o nand_boot_fsl_ifc.o ns16550.o tlb.o tlb_table.o
 
 SRCS	:= $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
 OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))

@@ -124,9 +123,6 @@ ifneq ($(OBJTREE), $(SRCTREE))
 $(obj)nand_boot.c:
 	@rm -f $(obj)nand_boot.c
 	ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/nand_boot.c $(obj)nand_boot.c
-$(obj)../common.c:
-	@rm -f $(obj)../common.c
-	ln -s $(SRCTREE)/nand_spl/board/freescale/common.c $(obj)../common.c
 endif
 
 #########################################################################

nand_spl/board/freescale/p1023rds/Makefile +1 -5

index c1c179e..582ceb5 100644
@@ -34,8 +34,7 @@ CFLAGS	+= -DCONFIG_NAND_SPL
 
 SOBJS	= start.o resetvec.o
 COBJS	= cache.o cpu_init_early.o cpu_init_nand.o fsl_law.o law.o \
-	  nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o \
-	  ../common.o
+	  nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o
 
 SRCS	:= $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
 OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))

@@ -115,9 +114,6 @@ ifneq ($(OBJTREE), $(SRCTREE))
 $(obj)nand_boot.c:
 	@rm -f $(obj)nand_boot.c
 	ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/nand_boot.c $(obj)nand_boot.c
-$(obj)../common.c:
-	@rm -f $(obj)../common.c
-	ln -s $(SRCTREE)/nand_spl/board/freescale/common.c $(obj)../common.c
 endif
 
 #########################################################################

nand_spl/board/freescale/p1_p2_rdb_pc/Makefile +1 -5

index eb0cd2a..1c4d079 100644
@@ -39,8 +39,7 @@ CFLAGS	+= -DCONFIG_NAND_SPL
 
 SOBJS	= start.o resetvec.o
 COBJS	= cache.o cpu_init_early.o cpu_init_nand.o fsl_law.o law.o \
-	  nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o \
-	  ../common.o
+	  nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o
 
 SRCS	:= $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
 OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))

@@ -120,9 +119,6 @@ ifneq ($(OBJTREE), $(SRCTREE))
 $(obj)nand_boot.c:
 	@rm -f $(obj)nand_boot.c
 	ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/nand_boot.c $(obj)nand_boot.c
-$(obj)../common.c:
-	@rm -f $(obj)../common.c
-	ln -s $(SRCTREE)/nand_spl/board/freescale/common.c $(obj)../common.c
 endif
 
 #########################################################################

Signature · 1 line

1.7.9.5

Scott Wood

author

2012-09-22 00:01 UTC #10 lore raw

RFC PATCH 7/17 spl: include resetvec and lib8xxx

In reply to Scott Wood

The toplevel makefile hardcodes this stuff, so spl/Makefile needs to as well.

Signed-off-by Scott Wood <[email protected]>

---
 spl/Makefile |   21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

spl/Makefile +21 -0

index 0954f51..7085224 100644
@@ -32,9 +32,30 @@ START_PATH := $(CPUDIR)
 endif
 
 START := $(START_PATH)/start.o
+ifeq ($(CPU),x86)
+START += $(START_PATH)/start16.o
+START += $(START_PATH)/resetvec.o
+endif
+ifeq ($(CPU),ppc4xx)
+START += $(START_PATH)/resetvec.o
+endif
+ifeq ($(CPU),mpc85xx)
+START += $(START_PATH)/resetvec.o
+endif
 
 LIBS-y += arch/$(ARCH)/lib/lib$(ARCH).o
+
 LIBS-y += $(CPUDIR)/lib$(CPU).o
+ifeq ($(CPU),mpc83xx)
+LIBS-y += arch/powerpc/cpu/mpc8xxx/lib8xxx.o
+endif
+ifeq ($(CPU),mpc85xx)
+LIBS-y += arch/powerpc/cpu/mpc8xxx/lib8xxx.o
+endif
+ifeq ($(CPU),mpc86xx)
+LIBS-y += arch/powerpc/cpu/mpc8xxx/lib8xxx.o
+endif
+
 ifdef SOC
 LIBS-y += $(CPUDIR)/$(SOC)/lib$(SOC).o
 endif

Signature · 1 line

1.7.9.5

Scott Wood

author

2012-09-22 00:01 UTC #11 lore raw

RFC PATCH 8/17 spl/powerpc: introduce CONFIG_SPL_INIT_MINIMAL

In reply to Scott Wood

Signed-off-by Scott Wood <[email protected]>

---
 README                            |    3 +++
 arch/powerpc/cpu/mpc85xx/Makefile |   39 ++++++++++++++++++++++++++++---------
 arch/powerpc/cpu/mpc85xx/start.S  |   37 +++++++++++++++++++++--------------
 arch/powerpc/cpu/mpc8xxx/Makefile |   16 +++++++++++++++
 arch/powerpc/lib/Makefile         |   17 +++++++++++++++-
 5 files changed, 87 insertions(+), 25 deletions(-)

README +3 -0

index 13af86b..5c6a467 100644
@@ -2667,6 +2667,9 @@ FIT uImage format:
 		CONFIG_SPL_LIBGENERIC_SUPPORT
 		Support for lib/libgeneric.o in SPL binary
 
+		CONFIG_SPL_INIT_MINIMAL
+		Arch init code should be built for a very small image
+
 Modem Support:
 --------------

arch/powerpc/cpu/mpc85xx/Makefile +30 -9

index 33e93c8..c51a774 100644
@@ -28,7 +28,25 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(CPU).o
 
+MINIMAL=
+
+ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_SPL_INIT_MINIMAL
+MINIMAL=y
+endif
+endif
+
+ifdef MINIMAL
+
+START = start.o resetvec.o
+
+COBJS-y	+= cpu_init_early.o tlb.o
+COBJS-$(CONFIG_SPL_NAND_MINIMAL) += cpu_init_nand.o
+
+else
+
 START	= start.o resetvec.o
+
 SOBJS-$(CONFIG_MP)	+= release.o
 SOBJS	= $(SOBJS-y)

@@ -111,17 +129,20 @@ COBJS-$(CONFIG_PPC_P3041) += p3041_serdes.o
 COBJS-$(CONFIG_PPC_P4080) += p4080_serdes.o
 COBJS-$(CONFIG_PPC_P5020) += p5020_serdes.o
 
-COBJS	= $(COBJS-y)
-COBJS	+= cpu.o
-COBJS	+= cpu_init.o
-COBJS	+= cpu_init_early.o
-COBJS	+= interrupts.o
-COBJS	+= speed.o
-COBJS	+= tlb.o
-COBJS	+= traps.o
+COBJS-y	+= cpu.o
+COBJS-y	+= cpu_init.o
+COBJS-y	+= cpu_init_early.o
+COBJS-y	+= interrupts.o
+COBJS-y	+= speed.o
+COBJS-y	+= tlb.o
+COBJS-y	+= traps.o
 
 # Stub implementations of cache management functions for USB
-COBJS += cache.o
+COBJS-y += cache.o
+
+endif # not minimal
+
+COBJS	= $(COBJS-y)
 
 SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))

arch/powerpc/cpu/mpc85xx/start.S +22 ~~-15~~

index 958ed6f..cbccec3 100644
@@ -44,6 +44,15 @@
 #undef	MSR_KERNEL
 #define MSR_KERNEL ( MSR_ME )	/* Machine Check */
 
+#if defined(CONFIG_NAND_SPL) || \
+	(defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL))
+#define MINIMAL_SPL
+#endif
+
+#if !defined(CONFIG_SPL) && !defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SECURE_BOOT)
+#define NOR_BOOT
+#endif
+
 /*
  * Set up GOT: Global Offset Table
  *

@@ -53,7 +62,7 @@
 	GOT_ENTRY(_GOT2_TABLE_)
 	GOT_ENTRY(_FIXUP_TABLE_)
 
-#ifndef CONFIG_NAND_SPL
+#ifndef MINIMAL_SPL
 	GOT_ENTRY(_start)
 	GOT_ENTRY(_start_of_vectors)
 	GOT_ENTRY(_end_of_vectors)

@@ -211,7 +220,7 @@ l2_disabled:
 	andi.	r1,r3,L1CSR0_DCE at l
 	beq	2b
 
-#if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) && !defined(CONFIG_NAND_SPL)
+#if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) && !defined(MINIMAL_SPL)
 /*
  * TLB entry for debuggging in AS1
  * Create temporary TLB entry in AS0 to handle debug exception

@@ -225,7 +234,7 @@ l2_disabled:
 	ori     r6,r6,FSL_BOOKE_MAS0(1,
 			CONFIG_SYS_PPC_E500_DEBUG_TLB, 0)@l
 
-#if !defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SECURE_BOOT)
+#ifdef NOR_BOOT
 /*
  * TLB entry is created for IVPR + IVOR15 to map on valid OP code address
  * bacause flash's virtual address maps to 0xff800000 - 0xffffffff.

@@ -278,11 +287,8 @@ l2_disabled:
 	isync
 #endif
 
-/*
- * Ne need to setup interrupt vector for NAND SPL
- * because NAND SPL never compiles it.
- */
-#if !defined(CONFIG_NAND_SPL)
+/* Interrupt vectors do not fit in minimal SPL. */
+#if !defined(MINIMAL_SPL)
 	/* Setup interrupt vectors */
 	lis	r1,CONFIG_SYS_MONITOR_BASE at h
 	mtspr	IVPR,r1

@@ -506,7 +512,7 @@ nexti:	mflr	r1		/* R1 = our PC */
 	li	r3, 0
 	mtspr	MAS1, r3
 1:	cmpw	r3, r14
-#if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) && !defined(CONFIG_NAND_SPL)
+#if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) && !defined(MINIMAL_SPL)
 	cmpwi	cr1, r3, CONFIG_SYS_PPC_E500_DEBUG_TLB
 	cror	cr0*4+eq, cr0*4+eq, cr1*4+eq
 #endif

@@ -1018,7 +1024,7 @@ create_init_ram_area:
 	lis     r6,FSL_BOOKE_MAS0(1, 15, 0)@h
 	ori     r6,r6,FSL_BOOKE_MAS0(1, 15, 0)@l
 
-#if !defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SECURE_BOOT)
+#ifdef NOR_BOOT
 	/* create a temp mapping in AS=1 to the 4M boot window */
 	lis     r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_4M)@h
 	ori     r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_4M)@l

@@ -1130,7 +1136,8 @@ switch_as:
 	bdnz	1b
 
 	/* Jump out the last 4K page and continue to 'normal' start */
-#ifdef CONFIG_SYS_RAMBOOT
+#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)
+	/* We assume that we're already running at the address we're linked at */
 	b	_start_cont
 #else
 	/* Calculate absolute address in FLASH and jump there		*/

@@ -1176,7 +1183,7 @@ _start_cont:
 
 	/* NOTREACHED - board_init_f() does not return */
 
-#ifndef CONFIG_NAND_SPL
+#ifndef MINIMAL_SPL
 	. = EXC_OFF_SYS_RESET
 	.globl	_start_of_vectors
 _start_of_vectors:

@@ -1620,7 +1627,7 @@ in32:
 in32r:
 	lwbrx	r3,r0,r3
 	blr
-#endif  /* !CONFIG_NAND_SPL */
+#endif  /* !MINIMAL_SPL */
 
 /*------------------------------------------------------------------------------*/

@@ -1817,7 +1824,7 @@ clear_bss:
 	mr	r4,r10		/* Destination Address		*/
 	bl	board_init_r
 
-#ifndef CONFIG_NAND_SPL
+#ifndef MINIMAL_SPL
 	/*
 	 * Copy exception vector code to low memory
 	 *

@@ -1990,4 +1997,4 @@ setup_ivors:
 
 #include "fixed_ivor.S"
 	blr
-#endif /* !CONFIG_NAND_SPL */
+#endif /* !MINIMAL_SPL */

arch/powerpc/cpu/mpc8xxx/Makefile +16 -0

index 86344a7..3dc8e05 100644
@@ -10,6 +10,20 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib8xxx.o
 
+MINIMAL=
+
+ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_SPL_INIT_MINIMAL
+MINIMAL=y
+endif
+endif
+
+ifdef MINIMAL
+
+COBJS-$(CONFIG_FSL_LAW) += law.o
+
+else
+
 ifneq ($(CPU),mpc83xx)
 COBJS-y	+= cpu.o
 endif

@@ -20,6 +34,8 @@ COBJS-$(CONFIG_FSL_LBC) += fsl_lbc.o
 COBJS-$(CONFIG_SYS_SRIO) += srio.o
 COBJS-$(CONFIG_FSL_LAW) += law.o
 
+endif
+
 SRCS	:= $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
 OBJS	:= $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))

arch/powerpc/lib/Makefile +16 -1

index 6e92005..419ce14 100644
@@ -38,8 +38,21 @@ endif
 
 LIB	= $(obj)lib$(ARCH).o
 
-SOBJS-y	+= ppccache.o
+MINIMAL=
+
+ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_SPL_INIT_MINIMAL
+MINIMAL=y
+endif
+endif
+
+ifdef MINIMAL
+COBJS-y += cache.o
+else
+
 SOBJS-y	+= ppcstring.o
+
+SOBJS-y	+= ppccache.o
 SOBJS-y	+= ticks.o
 SOBJS-y	+= reloc.o

@@ -64,6 +77,8 @@ $(obj)ppcstring.o: AFLAGS += -Dmemcpy=__memcpy
 COBJS-y += memcpy_mpc5200.o
 endif
 
+endif # not minimal
+
 COBJS	+= $(sort $(COBJS-y))
 
 SRCS	:= $(GLSOBJS:.o=.S) $(GLCOBJS:.o=.c) \

Signature · 1 line

1.7.9.5

Tom Rini

2012-09-24 23:48 UTC #12 lore raw

RFC PATCH 8/17 spl/powerpc: introduce CONFIG_SPL_INIT_MINIMAL

Quoted 1 line · Scott Wood

Signed-off-by Scott Wood <[email protected]>

[snip]

Quoted 14 lines

arch/powerpc/cpu/mpc85xx/Makefile +6 -0

index 33e93c8..c51a774 100644
@@ -28,7 +28,25 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(CPU).o
 
+MINIMAL=
+
+ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_SPL_INIT_MINIMAL
+MINIMAL=y
+endif

arch/powerpc/cpu/mpc85xx/Makefile include $(TOPDIR)/config.mk · line 46

Quoted 10 lines

arch/powerpc/cpu/mpc85xx/Makefile +10 -0

+endif
+
+ifdef MINIMAL
+
+START = start.o resetvec.o
+
+COBJS-y	+= cpu_init_early.o tlb.o
+COBJS-$(CONFIG_SPL_NAND_MINIMAL) += cpu_init_nand.o
+
+else

So, maybe it's just personal preference by why not:
START = start.o resetvec.o
ifdef CONFIG_SPL_BUILD COBJS-$(CONFIG_SPL_INIT_MINIMAL) += cpu_init_early.o tlb.o COBJS-$(CONFIG_SPL_NAND_MINIMAL) += cpu_init_nand.o else
....

And break out the rest of the COBJS -> COBJS-y changes into their own cleanup patch before of course.

Signature · 8 lines

Tom
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Scott Wood

author

2012-09-24 23:52 UTC #13 lore raw

RFC PATCH 8/17 spl/powerpc: introduce CONFIG_SPL_INIT_MINIMAL

Quoted 30 lines · Tom Rini

Quoted 1 line · Scott Wood
Signed-off-by Scott Wood <[email protected]>
[snip]
Review
Quoted 1 line
(quoted diff) +0 -0
b/arch/powerpc/cpu/mpc85xx/Makefile
Quoted 13 lines
index 33e93c8..c51a774 100644
arch/powerpc/cpu/mpc85xx/Makefile +6 -0
@@ -28,7 +28,25 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(CPU).o
 
+MINIMAL=
+
+ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_SPL_INIT_MINIMAL
+MINIMAL=y
+endif
arch/powerpc/cpu/mpc85xx/Makefile include $(TOPDIR)/config.mk · line 46
Quoted 10 lines
arch/powerpc/cpu/mpc85xx/Makefile +10 -0
+endif
+
+ifdef MINIMAL
+
+START = start.o resetvec.o
+
+COBJS-y	+= cpu_init_early.o tlb.o
+COBJS-$(CONFIG_SPL_NAND_MINIMAL) += cpu_init_nand.o
+
+else

Quoted 7 lines

So, maybe it's just personal preference by why not:
START = start.o resetvec.o
ifdef CONFIG_SPL_BUILD COBJS-$(CONFIG_SPL_INIT_MINIMAL) += cpu_init_early.o tlb.o COBJS-$(CONFIG_SPL_NAND_MINIMAL) += cpu_init_nand.o else
....

The START line could be factored out, but I don't think the rest works -- where would non-minimal SPL pull in its files?

-Scott

Tom Rini

2012-09-25 00:03 UTC #14 lore raw

RFC PATCH 8/17 spl/powerpc: introduce CONFIG_SPL_INIT_MINIMAL

Quoted 39 lines · Scott Wood

Quoted 30 lines · Tom Rini
Quoted 1 line · Scott Wood
Signed-off-by Scott Wood <[email protected]>
[snip]
Review
Quoted 1 line
(quoted diff) +0 -0
b/arch/powerpc/cpu/mpc85xx/Makefile
Quoted 13 lines
index 33e93c8..c51a774 100644
arch/powerpc/cpu/mpc85xx/Makefile +6 -0
@@ -28,7 +28,25 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(CPU).o
 
+MINIMAL=
+
+ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_SPL_INIT_MINIMAL
+MINIMAL=y
+endif
arch/powerpc/cpu/mpc85xx/Makefile include $(TOPDIR)/config.mk · line 46
Quoted 10 lines
arch/powerpc/cpu/mpc85xx/Makefile +10 -0
+endif
+
+ifdef MINIMAL
+
+START = start.o resetvec.o
+
+COBJS-y	+= cpu_init_early.o tlb.o
+COBJS-$(CONFIG_SPL_NAND_MINIMAL) += cpu_init_nand.o
+
+else
Quoted 7 lines
So, maybe it's just personal preference by why not:
START = start.o resetvec.o
ifdef CONFIG_SPL_BUILD COBJS-$(CONFIG_SPL_INIT_MINIMAL) += cpu_init_early.o tlb.o COBJS-$(CONFIG_SPL_NAND_MINIMAL) += cpu_init_nand.o else
....

Quoted 2 lines

The START line could be factored out, but I don't think the rest works -- where would non-minimal SPL pull in its files?

COBJS-$(CONFIG_WHATEVER_IT_USES) ? MINIMAL means CONFIG_SPL_BUILD (true of all SPLs) and CONFIG_SPL_INIT_MINIMAL. So setting CONFIG_SPL_NAND_MINIMAL and not being compatible with it could be a problem. But is that a likely problem to run into? And probably a problem that would best be solved by making cpu_init_nand.o more re-usable? Or did you mean something else?

Signature · 8 lines

Tom
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Scott Wood

author

2012-09-25 00:17 UTC #15 lore raw

RFC PATCH 8/17 spl/powerpc: introduce CONFIG_SPL_INIT_MINIMAL

Quoted 40 lines · Tom Rini

Quoted 39 lines · Scott Wood
Quoted 37 lines · Tom Rini
Quoted 1 line · Scott Wood
Signed-off-by Scott Wood <[email protected]>
[snip]
Review
Quoted 1 line
(quoted diff) +0 -0
b/arch/powerpc/cpu/mpc85xx/Makefile
Quoted 13 lines
index 33e93c8..c51a774 100644
arch/powerpc/cpu/mpc85xx/Makefile +6 -0
@@ -28,7 +28,25 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(CPU).o
 
+MINIMAL=
+
+ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_SPL_INIT_MINIMAL
+MINIMAL=y
+endif
arch/powerpc/cpu/mpc85xx/Makefile include $(TOPDIR)/config.mk · line 46
Quoted 10 lines
arch/powerpc/cpu/mpc85xx/Makefile +10 -0
+endif
+
+ifdef MINIMAL
+
+START = start.o resetvec.o
+
+COBJS-y	+= cpu_init_early.o tlb.o
+COBJS-$(CONFIG_SPL_NAND_MINIMAL) += cpu_init_nand.o
+
+else
So, maybe it's just personal preference by why not:
START = start.o resetvec.o
ifdef CONFIG_SPL_BUILD COBJS-$(CONFIG_SPL_INIT_MINIMAL) += cpu_init_early.o tlb.o COBJS-$(CONFIG_SPL_NAND_MINIMAL) += cpu_init_nand.o else
....

Quoted 4 lines

Quoted 2 lines
The START line could be factored out, but I don't think the rest works -- where would non-minimal SPL pull in its files?
COBJS-$(CONFIG_WHATEVER_IT_USES) ?

You're assuming that every WHATEVER_IT_USES has its own symbol (separate from symbols needed by a minimal build), which is something I was unsuccessful at pushing people to do early in the SPL development. I'm not optimistic that things will suddenly change. MINIMAL is a wall that avoids breakage when non-minimal SPL developers add things sloppily.

Plus, this way non-minimal SPL can just get the whole arch/powerpc/cpu/mpc85xx and rely on gc-sections, without having to duplicate things in the makefile and do fine-grained config.

Quoted 2 lines

MINIMAL means CONFIG_SPL_BUILD (true
of all SPLs) and CONFIG_SPL_INIT_MINIMAL.

CONFIG_SPL_BUILD is always true when you're building the SPL itself, but it's not always true when CONFIG_SPL_INIT_MINIMAL is defined, because other than CONFIG_SPL_BUILD the config symbols don't change when building the main U-Boot.

Quoted 5 lines

So setting
CONFIG_SPL_NAND_MINIMAL and not being compatible with it could be a problem. But is that a likely problem to run into? And probably a problem that would best be solved by making cpu_init_nand.o more re-usable? Or did you mean something else?

I don't quite understand the above, though cpu_init_nand.o should be renamed to cpu_init_minimal.o and depend on CONFIG_SPL_INIT_MINIMAL rather than CONFIG_SPL_NAND_MINIMAL. There's nothing really NAND-specific about it, other than that NAND is the only place we need a minimal SPL.

-Scott

Scott Wood

author

2012-09-22 00:01 UTC #16 lore raw

RFC PATCH 9/17 spl/85xx: new SPL support

In reply to Scott Wood

Update CONFIG_RAMBOOT and CONFIG_NAND_SPL references to accept CONFIG_SPL and CONFIG_SPL_BUILD, respectively. CONFIG_NAND_SPL can be removed once the last mpc85xx nand_spl target is gone.

CONFIG_RAMBOOT will need to remain for other use cases, but it doesn't seem right to overload it for meaning SPL as well as nand_spl does. Even if it's somewhat appropriate for the main u-boot, the SPL itself isn't (necessarily) ramboot, and we don't have separate configs for SPL and main u-boot. It was also inconsistent, as other platforms such as mpc83xx didn't use CONFIG_RAMBOOT in this way.

Signed-off-by Scott Wood <[email protected]>

Cc Andy Fleming <[email protected]>

---
 arch/powerpc/cpu/mpc85xx/cpu.c           |    3 +-
 arch/powerpc/cpu/mpc85xx/cpu_init_nand.c |    2 +-
 arch/powerpc/cpu/mpc85xx/tlb.c           |    4 +-
 arch/powerpc/cpu/mpc85xx/u-boot-spl.lds  |   81 ++++++++++++++++++++++++++++++
 arch/powerpc/cpu/mpc8xxx/law.c           |   11 ++--
 doc/README.mpc85xx                       |    2 +-
 6 files changed, 93 insertions(+), 10 deletions(-)
 create mode 100644 arch/powerpc/cpu/mpc85xx/u-boot-spl.lds

arch/powerpc/cpu/mpc85xx/cpu.c +2 -1

index 5ddb294..38ff1f2 100644
@@ -310,7 +310,8 @@ void mpc85xx_reginfo(void)
 
 /* Common ddr init for non-corenet fsl 85xx platforms */
 #ifndef CONFIG_FSL_CORENET
-#if defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SYS_INIT_L2_ADDR)
+#if (defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)) && \
+	!defined(CONFIG_SYS_INIT_L2_ADDR)
 phys_size_t initdram(int board_type)
 {
 #if defined(CONFIG_SPD_EEPROM) || defined(CONFIG_DDR_SPD)

arch/powerpc/cpu/mpc85xx/cpu_init_nand.c +1 -1

index 0589497..c6b9cd0 100644
@@ -30,7 +30,7 @@ DECLARE_GLOBAL_DATA_PTR;
 
 void cpu_init_f(void)
 {
-#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
+#ifdef CONFIG_SYS_INIT_L2_ADDR
 	ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR;
 
 	out_be32(&l2cache->l2srbar0, CONFIG_SYS_INIT_L2_ADDR);

arch/powerpc/cpu/mpc85xx/tlb.c +2 -2

index 929f6a6..2dcd8cc 100644
@@ -55,7 +55,7 @@ void init_tlbs(void)
 	return ;
 }
 
-#ifndef CONFIG_NAND_SPL
+#if !defined(CONFIG_NAND_SPL) && !defined(CONFIG_SPL_BUILD)
 void read_tlbcam_entry(int idx, u32 *valid, u32 *tsize, unsigned long *epn,
 		       phys_addr_t *rpn)
 {

@@ -332,4 +332,4 @@ void clear_ddr_tlbs(unsigned int memsize_in_meg)
 }
 
 
-#endif /* !CONFIG_NAND_SPL */
+#endif /* not SPL */

arch/powerpc/cpu/mpc85xx/u-boot-spl.lds new file +81 -0

81 lines not on this page · raw message

arch/powerpc/cpu/mpc8xxx/law.c +6 -5

index 223cd5d..ce1d71e 100644
@@ -92,7 +92,7 @@ void disable_law(u8 idx)
 	return;
 }
 
-#ifndef CONFIG_NAND_SPL
+#if !defined(CONFIG_NAND_SPL) && !defined(CONFIG_SPL_BUILD)
 static int get_law_entry(u8 i, struct law_entry *e)
 {
 	u32 lawar;

@@ -122,7 +122,7 @@ int set_next_law(phys_addr_t addr, enum law_size sz, enum law_trgt_if id)
 	return idx;
 }
 
-#ifndef CONFIG_NAND_SPL
+#if !defined(CONFIG_NAND_SPL) && !defined(CONFIG_SPL_BUILD)
 int set_last_law(phys_addr_t addr, enum law_size sz, enum law_trgt_if id)
 {
 	u32 idx;

@@ -233,7 +233,7 @@ int set_ddr_laws(u64 start, u64 sz, enum law_trgt_if id)
 
 	return 0;
 }
-#endif
+#endif /* not SPL */
 
 void init_laws(void)
 {

@@ -258,9 +258,10 @@ void init_laws(void)
 			gd->used_laws |= (1 << i);
 	}
 
-#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
+#if (defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)) || \
+	(defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD))
 	/*
-	 * in NAND boot we've already parsed the law_table and setup those LAWs
+	 * in SPL boot we've already parsed the law_table and setup those LAWs
 	 * so don't do it again.
 	 */
 	return;

doc/README.mpc85xx +1 -1

index 5a4b591..f9b023f 100644
@@ -26,7 +26,7 @@ Major Config Switches during various boot Modes
 ----------------------------------------------
 
 NOR boot
-		!defined(CONFIG_SYS_RAMBOOT)
+		!defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SPL)
 NOR boot Secure
 		!defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SECURE_BOOT)
 RAMBOOT(SD, SPI & NAND boot)

Signature · 1 line

1.7.9.5

Tom Rini

2012-09-24 23:51 UTC #17 lore raw

RFC PATCH 9/17 spl/85xx: new SPL support

Quoted 13 lines · Scott Wood

Update CONFIG_RAMBOOT and CONFIG_NAND_SPL references to accept CONFIG_SPL and CONFIG_SPL_BUILD, respectively. CONFIG_NAND_SPL can be removed once the last mpc85xx nand_spl target is gone.
CONFIG_RAMBOOT will need to remain for other use cases, but it doesn't seem right to overload it for meaning SPL as well as nand_spl does. Even if it's somewhat appropriate for the main u-boot, the SPL itself isn't (necessarily) ramboot, and we don't have separate configs for SPL and main u-boot. It was also inconsistent, as other platforms such as mpc83xx didn't use CONFIG_RAMBOOT in this way.
Signed-off-by Scott Wood <[email protected]>
Cc Andy Fleming <[email protected]>

[snip]

Quoted 6 lines

arch/powerpc/cpu/mpc85xx/u-boot-spl.lds new file +0 -0
new file mode 100644
index 0000000..372195d
@@ -0,0 +1,81 @@

[snip]

arch/powerpc/cpu/mpc85xx/u-boot-spl.lds line 29

Quoted 2 lines

arch/powerpc/cpu/mpc85xx/u-boot-spl.lds new file +2 -0
+OUTPUT_ARCH(powerpc)
+SECTIONS

Can we add MEMORY declarations like (some) of the ARM linker scripts do so when we grow beyond the max size it's a link error?

Signature · 8 lines

Tom
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Scott Wood

author

2012-09-24 23:54 UTC #18 lore raw

RFC PATCH 9/17 spl/85xx: new SPL support

Quoted 30 lines · Tom Rini

Quoted 1 line · Scott Wood
Update CONFIG_RAMBOOT and CONFIG_NAND_SPL references to accept
CONFIG_SPL
Quoted 1 line
and CONFIG_SPL_BUILD, respectively. CONFIG_NAND_SPL can be removed
once
Quoted 3 lines
the last mpc85xx nand_spl target is gone.
CONFIG_RAMBOOT will need to remain for other use cases, but it
doesn't
Quoted 1 line
seem right to overload it for meaning SPL as well as nand_spl
does. Even
Quoted 1 line
if it's somewhat appropriate for the main u-boot, the SPL itself
isn't
Quoted 1 line
(necessarily) ramboot, and we don't have separate configs for SPL
and
Quoted 5 lines
main u-boot. It was also inconsistent, as other platforms such as mpc83xx didn't use CONFIG_RAMBOOT in this way.
Signed-off-by Scott Wood <[email protected]>
Cc Andy Fleming <[email protected]>
[snip]
Review
Quoted 1 line
(quoted diff) +0 -0
b/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds
Quoted 5 lines
new file mode 100644
index 0000000..372195d
arch/powerpc/cpu/mpc85xx/u-boot-spl.lds new file +0 -0
@@ -0,0 +1,81 @@
[snip]

Quoted 6 lines

arch/powerpc/cpu/mpc85xx/u-boot-spl.lds line 29
Quoted 2 lines
arch/powerpc/cpu/mpc85xx/u-boot-spl.lds new file +2 -0
+OUTPUT_ARCH(powerpc)
+SECTIONS
Can we add MEMORY declarations like (some) of the ARM linker scripts do
so when we grow beyond the max size it's a link error?

It's already a linker error, because you get an overlap with the reset vector.

-Scott

Tom Rini

2012-09-25 00:04 UTC #19 lore raw

RFC PATCH 9/17 spl/85xx: new SPL support

Quoted 38 lines · Scott Wood

Quoted 30 lines · Tom Rini
Quoted 1 line · Scott Wood
Update CONFIG_RAMBOOT and CONFIG_NAND_SPL references to accept
CONFIG_SPL
Quoted 1 line
and CONFIG_SPL_BUILD, respectively. CONFIG_NAND_SPL can be
removed once
Quoted 3 lines
the last mpc85xx nand_spl target is gone.
CONFIG_RAMBOOT will need to remain for other use cases, but it
doesn't
Quoted 1 line
seem right to overload it for meaning SPL as well as nand_spl
does. Even
Quoted 1 line
if it's somewhat appropriate for the main u-boot, the SPL itself
isn't
Quoted 1 line
(necessarily) ramboot, and we don't have separate configs for
SPL and
Quoted 5 lines
main u-boot. It was also inconsistent, as other platforms such as mpc83xx didn't use CONFIG_RAMBOOT in this way.
Signed-off-by Scott Wood <[email protected]>
Cc Andy Fleming <[email protected]>
[snip]
Review
Quoted 1 line
(quoted diff) +0 -0
b/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds
Quoted 5 lines
new file mode 100644
index 0000000..372195d
arch/powerpc/cpu/mpc85xx/u-boot-spl.lds new file +0 -0
@@ -0,0 +1,81 @@
[snip]
Quoted 6 lines
arch/powerpc/cpu/mpc85xx/u-boot-spl.lds line 29
Quoted 2 lines
arch/powerpc/cpu/mpc85xx/u-boot-spl.lds new file +2 -0
+OUTPUT_ARCH(powerpc)
+SECTIONS
Can we add MEMORY declarations like (some) of the ARM linker scripts do
so when we grow beyond the max size it's a link error?

Quoted 2 lines

It's already a linker error, because you get an overlap with the reset vector.

OK. Then you can drop the CONFIG_SPL_MAX_SIZE you have later on since that's where we check against it. Or did I miss a user of it in the series?

Signature · 8 lines

Tom
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Scott Wood

author

2012-09-25 00:08 UTC #20 lore raw

RFC PATCH 9/17 spl/85xx: new SPL support

Quoted 40 lines · Tom Rini

Quoted 10 lines · Scott Wood
Quoted 9 lines · Tom Rini
Quoted 1 line · Scott Wood
Update CONFIG_RAMBOOT and CONFIG_NAND_SPL references to accept
CONFIG_SPL
Quoted 1 line
and CONFIG_SPL_BUILD, respectively. CONFIG_NAND_SPL can be
removed once
Quoted 3 lines
the last mpc85xx nand_spl target is gone.
CONFIG_RAMBOOT will need to remain for other use cases, but it
Quoted 8 lines
Quoted 8 lines
doesn't
Quoted 1 line
seem right to overload it for meaning SPL as well as nand_spl
does. Even
Quoted 1 line
if it's somewhat appropriate for the main u-boot, the SPL itself
isn't
Quoted 1 line
(necessarily) ramboot, and we don't have separate configs for
SPL and
Quoted 1 line
main u-boot. It was also inconsistent, as other platforms such
as
Quoted 20 lines
Quoted 19 lines
Quoted 4 lines
mpc83xx didn't use CONFIG_RAMBOOT in this way.
Signed-off-by Scott Wood <[email protected]>
Cc Andy Fleming <[email protected]>
[snip]
Review
Quoted 1 line
(quoted diff) +0 -0
b/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds
Quoted 5 lines
new file mode 100644
index 0000000..372195d
arch/powerpc/cpu/mpc85xx/u-boot-spl.lds new file +0 -0
@@ -0,0 +1,81 @@
[snip]
arch/powerpc/cpu/mpc85xx/u-boot-spl.lds line 29
Quoted 2 lines
arch/powerpc/cpu/mpc85xx/u-boot-spl.lds new file +2 -0
+OUTPUT_ARCH(powerpc)
+SECTIONS
Can we add MEMORY declarations like (some) of the ARM linker scripts do
so when we grow beyond the max size it's a link error?

Quoted 6 lines

Quoted 2 lines
It's already a linker error, because you get an overlap with the reset vector.
OK. Then you can drop the CONFIG_SPL_MAX_SIZE you have later on since that's where we check against it. Or did I miss a user of it in the series?

It's used by the definition of CONFIG_SYS_NAND_U_BOOT_SIZE/DST within that same patch. Plus it's nice to document somewhere prominent, and to conform to standard SPL symbols.

-Scott

Tom Rini

2012-09-25 00:13 UTC #21 lore raw

RFC PATCH 9/17 spl/85xx: new SPL support

Quoted 44 lines · Scott Wood

Quoted 43 lines · Tom Rini
Quoted 10 lines · Scott Wood
Quoted 9 lines · Tom Rini
Quoted 1 line · Scott Wood
Update CONFIG_RAMBOOT and CONFIG_NAND_SPL references to accept
CONFIG_SPL
Quoted 1 line
and CONFIG_SPL_BUILD, respectively. CONFIG_NAND_SPL can be
removed once
Quoted 3 lines
the last mpc85xx nand_spl target is gone.
CONFIG_RAMBOOT will need to remain for other use cases, but it
Quoted 8 lines
Quoted 8 lines
doesn't
Quoted 1 line
seem right to overload it for meaning SPL as well as nand_spl
does. Even
Quoted 1 line
if it's somewhat appropriate for the main u-boot, the SPL itself
isn't
Quoted 1 line
(necessarily) ramboot, and we don't have separate configs for
SPL and
Quoted 1 line
main u-boot. It was also inconsistent, as other platforms
such as
Quoted 22 lines
Quoted 13 lines
Quoted 4 lines
mpc83xx didn't use CONFIG_RAMBOOT in this way.
Signed-off-by Scott Wood <[email protected]>
Cc Andy Fleming <[email protected]>
[snip]
Review
Quoted 1 line
(quoted diff) +0 -0
b/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds
Quoted 5 lines
new file mode 100644
index 0000000..372195d
arch/powerpc/cpu/mpc85xx/u-boot-spl.lds new file +0 -0
@@ -0,0 +1,81 @@
[snip]
Quoted 6 lines
arch/powerpc/cpu/mpc85xx/u-boot-spl.lds line 29
Quoted 2 lines
arch/powerpc/cpu/mpc85xx/u-boot-spl.lds new file +2 -0
+OUTPUT_ARCH(powerpc)
+SECTIONS
Can we add MEMORY declarations like (some) of the ARM linker scripts do
so when we grow beyond the max size it's a link error?
It's already a linker error, because you get an overlap with the reset vector.

Quoted 7 lines

Quoted 3 lines
OK. Then you can drop the CONFIG_SPL_MAX_SIZE you have later on since that's where we check against it. Or did I miss a user of it in the series?
It's used by the definition of CONFIG_SYS_NAND_U_BOOT_SIZE/DST within that same patch. Plus it's nice to document somewhere prominent, and to conform to standard SPL symbols.

OK, just read that part too quick then, thanks for the explanation.

Signature · 8 lines

Tom
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Scott Wood

author

2012-09-22 00:01 UTC #22 lore raw

RFC PATCH 10/17 powerpc/p1_p2_rdb_pc: new SPL support

In reply to Scott Wood

Introduces CONFIG_SPL_RELOC_TEXT_BASE and CONFIG_SPL_RELOC_STACK.

Signed-off-by Scott Wood <[email protected]>

Cc Andy Fleming <[email protected]>

---
 README                                      |    9 ++
 board/freescale/p1_p2_rdb_pc/Makefile       |   16 ++++
 board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c |    2 +-
 board/freescale/p1_p2_rdb_pc/spl_minimal.c  |  131 +++++++++++++++++++++++++++
 board/freescale/p1_p2_rdb_pc/tlb.c          |    7 +-
 5 files changed, 160 insertions(+), 5 deletions(-)
 create mode 100644 board/freescale/p1_p2_rdb_pc/spl_minimal.c

README +9 -0

index 5c6a467..8e07d41 100644
@@ -2574,6 +2574,10 @@ FIT uImage format:
 		CONFIG_SPL_TEXT_BASE
 		TEXT_BASE for linking the SPL binary.
 
+		CONFIG_SPL_RELOC_TEXT_BASE
+		Address to relocate to.  If unspecified, this is equal to
+		CONFIG_SPL_TEXT_BASE (i.e. no relocation is done).
+
 		CONFIG_SPL_BSS_START_ADDR
 		Link address for the BSS within the SPL binary.

@@ -2583,6 +2587,11 @@ FIT uImage format:
 		CONFIG_SPL_STACK
 		Adress of the start of the stack SPL will use
 
+		CONFIG_SPL_RELOC_STACK
+		Adress of the start of the stack SPL will use after
+		relocation.  If unspecified, this is equal to
+		CONFIG_SPL_STACK.
+
 		CONFIG_SYS_SPL_MALLOC_START
 		Starting address of the malloc pool used in SPL.

board/freescale/p1_p2_rdb_pc/Makefile +16 -0

index 0dcf7d1..5b45d72 100644
@@ -24,11 +24,27 @@ include $(TOPDIR)/config.mk
 
 LIB    = $(obj)lib$(BOARD).o
 
+MINIMAL=
+
+ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_SPL_INIT_MINIMAL
+MINIMAL=y
+endif
+endif
+
+ifdef MINIMAL
+
+COBJS-y	+= spl_minimal.o tlb.o law.o
+
+else
+
 COBJS-y        += $(BOARD).o
 COBJS-y        += ddr.o
 COBJS-y        += law.o
 COBJS-y        += tlb.o
 
+endif
+
 SRCS   := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
 OBJS   := $(addprefix $(obj),$(COBJS-y))
 SOBJS  := $(addprefix $(obj),$(SOBJS))

board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c +1 -1

index aa39260..5b5b86c 100644
@@ -177,7 +177,7 @@ void board_gpio_init(void)
 	 */
 
 	setbits_be32(&pgpio->gpdir, 0x02130000);
-#ifndef CONFIG_SYS_RAMBOOT
+#if !defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SPL)
 	/* init DDR3 reset signal */
 	setbits_be32(&pgpio->gpdir, 0x00200000);
 	setbits_be32(&pgpio->gpodr, 0x00200000);

board/freescale/p1_p2_rdb_pc/spl_minimal.c new file +131 -0

131 lines not on this page · raw message

board/freescale/p1_p2_rdb_pc/tlb.c +3 -4

index 6d22463..0873dd7 100644
@@ -53,7 +53,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
 			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 			0, 1, BOOKE_PAGESZ_1M, 1),
 
-#ifndef CONFIG_NAND_SPL
+#ifndef CONFIG_SPL_BUILD
 	/* W**G* - Flash/promjet, localbus */
 	/* This will be changed to *I*G* after relocation to RAM. */
 	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,

@@ -85,7 +85,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
 	SET_TLB_ENTRY(1, CONFIG_SYS_PMC_BASE, CONFIG_SYS_PMC_BASE_PHYS,
 			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 			0, 10, BOOKE_PAGESZ_64K, 1),
-#endif
+#endif /* not SPL */
 
 #ifdef CONFIG_SYS_NAND_BASE
 	/* *I*G - NAND */

@@ -94,7 +94,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
 			0, 7, BOOKE_PAGESZ_1M, 1),
 #endif
 
-#ifdef CONFIG_SYS_RAMBOOT
+#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)
 	/* *I*G - eSDHC/eSPI/NAND boot */
 	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
 			MAS3_SX|MAS3_SW|MAS3_SR, 0,

@@ -108,7 +108,6 @@ struct fsl_e_tlb_entry tlb_table[] = {
 			0, 9, BOOKE_PAGESZ_1G, 1),
 #endif
 #endif
-
 };
 
 int num_tlb_entries = ARRAY_SIZE(tlb_table);

Signature · 1 line

1.7.9.5

Scott Wood

author

2012-09-22 00:01 UTC #23 lore raw

RFC PATCH 11/17 spl/nand: introduce CONFIG_SPL_NAND_MINIMAL

In reply to Scott Wood

This will be used by SPL builds that do not use the standard nand_base.c and friends.

Signed-off-by Scott Wood <[email protected]>

---
 README                    |    3 +++
 drivers/mtd/nand/Makefile |   41 +++++++++++++++++++++++++++++++----------
 2 files changed, 34 insertions(+), 10 deletions(-)

README +3 -0

index 8e07d41..5a57a14 100644
@@ -2637,6 +2637,9 @@ FIT uImage format:
 		CONFIG_SPL_NAND_SIMPLE
 		Support for drivers/mtd/nand/libnand.o in SPL binary
 
+		CONFIG_SPL_NAND_MINIMAL
+		Do not build the standard NAND subsystem files.
+
 		CONFIG_SYS_NAND_5_ADDR_CYCLE, CONFIG_SYS_NAND_PAGE_COUNT,
 		CONFIG_SYS_NAND_PAGE_SIZE, CONFIG_SYS_NAND_OOBSIZE,
 		CONFIG_SYS_NAND_BLOCK_SIZE, CONFIG_SYS_NAND_BAD_BLOCK_POS,

drivers/mtd/nand/Makefile +31 ~~-10~~

59 lines not on this page · raw message

Signature · 1 line

1.7.9.5

Tom Rini

2012-09-24 23:55 UTC #24 lore raw

RFC PATCH 11/17 spl/nand: introduce CONFIG_SPL_NAND_MINIMAL

Quoted 2 lines · Scott Wood

This will be used by SPL builds that do not use the standard nand_base.c and friends.

[snip]

Quoted 2 lines

drivers/mtd/nand/Makefile +0 -0

[snip]

drivers/mtd/nand/Makefile include $(TOPDIR)/config.mk · line 38

Quoted 7 lines

drivers/mtd/nand/Makefile +6 -0

+ifdef CONFIG_SPL_NAND_MINIMAL
+# minimal-only files go here
 else
+CONFIG_SPL_NAND_ECC=y
+CONFIG_SPL_NAND_BASE=y
+CONFIG_SPL_NAND_DRIVERS=y
+endif

OK, why don't we just use these as regular board-config.h file based options? We already have to set a number of CONFIG_SYS_NAND defines.

Signature · 8 lines

Tom
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Scott Wood

author

2012-09-25 00:02 UTC #25 lore raw

RFC PATCH 11/17 spl/nand: introduce CONFIG_SPL_NAND_MINIMAL

Quoted 9 lines · Tom Rini

Quoted 1 line · Scott Wood
This will be used by SPL builds that do not use the standard
nand_base.c
Quoted 1 line
and friends.
[snip]
Quoted 2 lines
drivers/mtd/nand/Makefile +0 -0
[snip]

Quoted 10 lines

drivers/mtd/nand/Makefile include $(TOPDIR)/config.mk · line 38
Quoted 7 lines
drivers/mtd/nand/Makefile +6 -0
+ifdef CONFIG_SPL_NAND_MINIMAL
+# minimal-only files go here
 else
+CONFIG_SPL_NAND_ECC=y
+CONFIG_SPL_NAND_BASE=y
+CONFIG_SPL_NAND_DRIVERS=y
+endif
OK, why don't we just use these as regular board-config.h file based options? We already have to set a number of CONFIG_SYS_NAND defines.

OK -- just add them to all boards that currently have CONFIG_SPL_NAND_SUPPORT?

-Scott

Tom Rini

2012-09-25 00:13 UTC #26 lore raw

RFC PATCH 11/17 spl/nand: introduce CONFIG_SPL_NAND_MINIMAL

Quoted 21 lines · Scott Wood

Quoted 9 lines · Tom Rini
Quoted 1 line · Scott Wood
This will be used by SPL builds that do not use the standard
nand_base.c
Quoted 1 line
and friends.
[snip]
Quoted 2 lines
drivers/mtd/nand/Makefile +0 -0
[snip]
Quoted 10 lines
drivers/mtd/nand/Makefile include $(TOPDIR)/config.mk · line 38
Quoted 7 lines
drivers/mtd/nand/Makefile +6 -0
+ifdef CONFIG_SPL_NAND_MINIMAL
+# minimal-only files go here
 else
+CONFIG_SPL_NAND_ECC=y
+CONFIG_SPL_NAND_BASE=y
+CONFIG_SPL_NAND_DRIVERS=y
+endif
OK, why don't we just use these as regular board-config.h file based options? We already have to set a number of CONFIG_SYS_NAND defines.

Quoted 2 lines

OK -- just add them to all boards that currently have CONFIG_SPL_NAND_SUPPORT?

Yeah, and maybe some quick checking to see which are really needed (just need to build-check say omap3_beagle and da850evm to cover all of the "omap" and then davinci platforms). Looking at the omap3_beagle discard map I have handy, we might be able to toss some stuff out.

Signature · 8 lines

Tom
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Scott Wood

author

2012-09-22 00:01 UTC #27 lore raw

RFC PATCH 12/17 spl/nand: config symbol documentation

In reply to Scott Wood

Document parameters used for specifying the NAND image to be loaded.

Also fix the definition of CONFIG_SPL_NAND_SIMPLE -- it's only nand_spl_simple.c, not the entire nand directory. The word "simple" is there for a reason. :-)

Signed-off-by Scott Wood <[email protected]>

---
 README |   17 +++++++++++------
 1 file changed, 11 insertions(+), 6 deletions(-)

README +11 -6

index 5a57a14..b7159ee 100644
@@ -2635,7 +2635,8 @@ FIT uImage format:
 		Filename to read to load U-Boot when reading from FAT
 
 		CONFIG_SPL_NAND_SIMPLE
-		Support for drivers/mtd/nand/libnand.o in SPL binary
+		Support for NAND boot using simple NAND drivers that
+		expose the cmd_ctrl() interface.
 
 		CONFIG_SPL_NAND_MINIMAL
 		Do not build the standard NAND subsystem files.

@@ -2646,15 +2647,19 @@ FIT uImage format:
 		CONFIG_SYS_NAND_ECCPOS, CONFIG_SYS_NAND_ECCSIZE,
 		CONFIG_SYS_NAND_ECCBYTES
 		Defines the size and behavior of the NAND that SPL uses
-		to read U-Boot with CONFIG_SPL_NAND_SIMPLE
+		to read U-Boot
 
 		CONFIG_SYS_NAND_U_BOOT_OFFS
-		Location in NAND for CONFIG_SPL_NAND_SIMPLE to read U-Boot
-		from.
+		Location in NAND to read U-Boot from
+
+		CONFIG_SYS_NAND_U_BOOT_DST
+		Location in memory to load U-Boot to
+
+		CONFIG_SYS_NAND_U_BOOT_SIZE
+		Size of image to load
 
 		CONFIG_SYS_NAND_U_BOOT_START
-		Location in memory for CONFIG_SPL_NAND_SIMPLE to load U-Boot
-		to.
+		Entry point in loaded image to jump to
 
 		CONFIG_SYS_NAND_HW_ECC_OOBFIRST
 		Define this if you need to first read the OOB and then the

Signature · 1 line

1.7.9.5

Scott Wood

author

2012-09-22 00:01 UTC #28 lore raw

RFC PATCH 13/17 spl/nand: Add minimal-spl driver for Freescale eLBC NAND

In reply to Scott Wood

This is basically a copy of nand_spl/nand_boot_fsl_elbc.c (which will go away when its last user does). Unlike the old file, CONFIG_NAND_ENV_DST is supported.

nand_spl_load.c is not used because I found that keeping it in the same file (and thus able to use static functions) kept things smaller.

Signed-off-by Scott Wood <[email protected]>

---
 drivers/mtd/nand/Makefile       |    2 +-
 drivers/mtd/nand/fsl_elbc_spl.c |  168 +++++++++++++++++++++++++++++++++++++++
 2 files changed, 169 insertions(+), 1 deletion(-)
 create mode 100644 drivers/mtd/nand/fsl_elbc_spl.c

drivers/mtd/nand/Makefile +1 -1

index 5be1270..4450d63 100644
@@ -30,7 +30,7 @@ ifdef CONFIG_CMD_NAND
 ifdef CONFIG_SPL_BUILD
 
 ifdef CONFIG_SPL_NAND_MINIMAL
-# minimal-only files go here
+COBJS-$(CONFIG_NAND_FSL_ELBC) += fsl_elbc_spl.o
 else
 CONFIG_SPL_NAND_ECC=y
 CONFIG_SPL_NAND_BASE=y

drivers/mtd/nand/fsl_elbc_spl.c new file +168 -0

168 lines not on this page · raw message

Signature · 1 line

1.7.9.5

Scott Wood

author

2012-09-22 00:01 UTC #29 lore raw

RFC PATCH 14/17 spl: introduce CONFIG_SPL_TARGET

In reply to Scott Wood

Currently it seems that SPLs rely on the user to specify the final target on the make command line. This is a departure from traditional U-Boot practice and results in a lack of build coverage in MAKEALL.

Now boards can specify CONFIG_SPL_TARGET to determine what gets built by default. Eventually all SPL boards should specify CONFIG_SPL_TARGET, but for now default to at least building the SPL code.

Signed-off-by Scott Wood <[email protected]>

---
 Makefile |   13 ++++++++++++-
 1 file changed, 12 insertions(+), 1 deletion(-)

Makefile +12 -1

index dd879a5..8feb6e1 100644
@@ -371,10 +371,21 @@ endif
 # Always append ALL so that arch config.mk's can add custom ones
 ALL-y += $(obj)u-boot.srec $(obj)u-boot.bin $(obj)System.map
 
+# This default can be removed when all SPLs define CONFIG_SPL_TARGET.
+# Until then this ensures that at least the SPL gets built by MAKEALL.
+ifdef CONFIG_SPL
+	ifdef CONFIG_SPL_TARGET
+		# need to strip off double quotes
+		SPL_TARGET := $(subst ",,$(CONFIG_SPL_TARGET))
+	else
+		SPL_TARGET ?= spl/u-boot-spl.bin
+	endif
+endif
+
 ALL-$(CONFIG_NAND_U_BOOT) += $(obj)u-boot-nand.bin
 ALL-$(CONFIG_ONENAND_U_BOOT) += $(obj)u-boot-onenand.bin
 ONENAND_BIN ?= $(obj)onenand_ipl/onenand-ipl-2k.bin
-ALL-$(CONFIG_SPL) += $(obj)spl/u-boot-spl.bin
+ALL-$(CONFIG_SPL) += $(obj)$(SPL_TARGET)
 ALL-$(CONFIG_OF_SEPARATE) += $(obj)u-boot.dtb $(obj)u-boot-dtb.bin
 
 all:		$(ALL-y) $(SUBDIR_EXAMPLES)

Signature · 1 line

1.7.9.5

Tom Rini

2012-09-22 00:12 UTC #30 lore raw

RFC PATCH 14/17 spl: introduce CONFIG_SPL_TARGET

Quoted 9 lines · Scott Wood

Currently it seems that SPLs rely on the user to specify the final target on the make command line. This is a departure from traditional U-Boot practice and results in a lack of build coverage in MAKEALL.
Now boards can specify CONFIG_SPL_TARGET to determine what gets built by default. Eventually all SPL boards should specify CONFIG_SPL_TARGET, but for now default to at least building the SPL code.
Signed-off-by Scott Wood <[email protected]>

Note that this is sometimes handled via config.mk fragments:
ifdef CONFIG_SPL_BUILD
ALL-y += $(OBJTREE)/MLO
else
ALL-y += $(obj)u-boot.img
endif

Or similar. I don't know what's better.

Signature · 8 lines

Tom
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Scott Wood

author

2012-09-24 18:54 UTC #31 lore raw

RFC PATCH 14/17 spl: introduce CONFIG_SPL_TARGET

Quoted 16 lines · Tom Rini

Quoted 1 line · Scott Wood
Currently it seems that SPLs rely on the user to specify the final
target
Quoted 1 line
on the make command line. This is a departure from traditional
U-Boot practice
Quoted 3 lines
and results in a lack of build coverage in MAKEALL.
Now boards can specify CONFIG_SPL_TARGET to determine what gets
built by default.
Quoted 1 line
Eventually all SPL boards should specify CONFIG_SPL_TARGET, but for
now default
Quoted 3 lines
to at least building the SPL code.
Signed-off-by Scott Wood <[email protected]>

Quoted 8 lines

Note that this is sometimes handled via config.mk fragments:
ifdef CONFIG_SPL_BUILD
ALL-y += $(OBJTREE)/MLO
else
ALL-y += $(obj)u-boot.img
endif
Or similar. I don't know what's better.

Ah. I was wondering if there were some magic that existing boards were using, but couldn't find it.

I think I'd prefer having a simple CONFIG_SPL_TARGET, and boards that need something more complicated can still provide a config.mk fragment. What is the CONFIG_SPL_BUILD test for? Is ALL-y really evaluated twice?

-Scott

Tom Rini

2012-09-24 19:03 UTC #32 lore raw

RFC PATCH 14/17 spl: introduce CONFIG_SPL_TARGET

Quoted 26 lines · Scott Wood

Quoted 16 lines · Tom Rini
Quoted 1 line · Scott Wood
Currently it seems that SPLs rely on the user to specify the
final target
Quoted 1 line
on the make command line. This is a departure from traditional
U-Boot practice
Quoted 3 lines
and results in a lack of build coverage in MAKEALL.
Now boards can specify CONFIG_SPL_TARGET to determine what gets
built by default.
Quoted 1 line
Eventually all SPL boards should specify CONFIG_SPL_TARGET, but
for now default
Quoted 3 lines
to at least building the SPL code.
Signed-off-by Scott Wood <[email protected]>
Quoted 8 lines
Note that this is sometimes handled via config.mk fragments:
ifdef CONFIG_SPL_BUILD
ALL-y += $(OBJTREE)/MLO
else
ALL-y += $(obj)u-boot.img
endif
Or similar. I don't know what's better.

Quoted 7 lines

Ah. I was wondering if there were some magic that existing boards were using, but couldn't find it.
I think I'd prefer having a simple CONFIG_SPL_TARGET, and boards that need something more complicated can still provide a config.mk fragment. What is the CONFIG_SPL_BUILD test for? Is ALL-y really evaluated twice?

I'm not sure. And thinking about what Wolfgang said in the other thread about SoC specific Makefile fragment for the custom rules, it might work out easily enough to convert things like this. And yes, unless I'm missing something, we evaulate everything again for the SPL build (and each side of that if/else only would make sense in that context).

Signature · 8 lines

Tom
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Scott Wood

author

2012-09-24 20:05 UTC #33 lore raw

RFC PATCH 14/17 spl: introduce CONFIG_SPL_TARGET

Quoted 35 lines · Tom Rini

Quoted 26 lines · Scott Wood
Quoted 16 lines · Tom Rini
Quoted 1 line · Scott Wood
Currently it seems that SPLs rely on the user to specify the
final target
Quoted 1 line
on the make command line. This is a departure from traditional
U-Boot practice
Quoted 3 lines
and results in a lack of build coverage in MAKEALL.
Now boards can specify CONFIG_SPL_TARGET to determine what gets
built by default.
Quoted 1 line
Eventually all SPL boards should specify CONFIG_SPL_TARGET, but
for now default
Quoted 3 lines
to at least building the SPL code.
Signed-off-by Scott Wood <[email protected]>
Quoted 8 lines
Note that this is sometimes handled via config.mk fragments:
ifdef CONFIG_SPL_BUILD
ALL-y += $(OBJTREE)/MLO
else
ALL-y += $(obj)u-boot.img
endif
Or similar. I don't know what's better.
Quoted 7 lines
Ah. I was wondering if there were some magic that existing boards were using, but couldn't find it.
I think I'd prefer having a simple CONFIG_SPL_TARGET, and boards that need something more complicated can still provide a config.mk fragment. What is the CONFIG_SPL_BUILD test for? Is ALL-y really evaluated twice?

Quoted 5 lines

I'm not sure. And thinking about what Wolfgang said in the other thread
about SoC specific Makefile fragment for the custom rules, it might work
out easily enough to convert things like this.

Right, s/boards/SoCs/

Quoted 3 lines

And yes, unless I'm
missing something, we evaulate everything again for the SPL build (and each side of that if/else only would make sense in that context).

OK, it's not that you evaluate everything (most makefiles, yes, but I don't think this applies to the toplevel makefile) so much as that spl/Makefile has its own ALL-y.

-Scott

Scott Wood

author

2012-09-22 00:01 UTC #34 lore raw

RFC PATCH 15/17 p1_p2_rdb_pc: convert from nand_spl to new spl

In reply to Scott Wood

Signed-off-by Scott Wood <[email protected]>

Cc Andy Fleming <[email protected]>

---
 include/configs/p1_p2_rdb_pc.h                    |   54 ++++----
 nand_spl/board/freescale/p1_p2_rdb_pc/Makefile    |  137 ---------------------
 nand_spl/board/freescale/p1_p2_rdb_pc/nand_boot.c |  132 --------------------
 3 files changed, 28 insertions(+), 295 deletions(-)
 delete mode 100644 nand_spl/board/freescale/p1_p2_rdb_pc/Makefile
 delete mode 100644 nand_spl/board/freescale/p1_p2_rdb_pc/nand_boot.c

include/configs/p1_p2_rdb_pc.h +28 ~~-26~~

index b18f4a0..b3c4793 100644
@@ -140,16 +140,25 @@
 #define CONFIG_RESET_VECTOR_ADDRESS	0x1107fffc
 #endif
 
-#if defined(CONFIG_NAND) && defined(CONFIG_NAND_FSL_ELBC)
-#define CONFIG_NAND_U_BOOT
-#define CONFIG_SYS_EXTRA_ENV_RELOC
-#define CONFIG_SYS_RAMBOOT
-#define CONFIG_SYS_TEXT_BASE_SPL	0xff800000
-#ifdef CONFIG_NAND_SPL
-#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE_SPL
-#else
-#define CONFIG_SYS_TEXT_BASE		0x11001000
-#endif /* CONFIG_NAND_SPL */
+#ifdef CONFIG_NAND
+#define CONFIG_SPL
+#define CONFIG_SPL_INIT_MINIMAL
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_NAND_MINIMAL
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
+
+#define CONFIG_SYS_TEXT_BASE		0x00201000
+#define CONFIG_SPL_TEXT_BASE		0xfffff000
+#define CONFIG_SPL_MAX_SIZE		(4 * 1024)
+#define CONFIG_SPL_RELOC_TEXT_BASE	0x00100000
+#define CONFIG_SPL_RELOC_STACK		0x00100000
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	((512 << 10) + CONFIG_SPL_MAX_SIZE)
+#define CONFIG_SYS_NAND_U_BOOT_DST	(0x00200000 - CONFIG_SPL_MAX_SIZE)
+#define CONFIG_SYS_NAND_U_BOOT_START	0x00200000
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	0
+#define CONFIG_SYS_LDSCRIPT		"arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
 #endif
 
 #ifndef CONFIG_SYS_TEXT_BASE

@@ -161,8 +170,12 @@
 #endif
 
 #ifndef CONFIG_SYS_MONITOR_BASE
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SPL_TEXT_BASE
+#else
 #define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
 #endif
+#endif
 
 /* High Level Configuration Options */
 #define CONFIG_BOOKE

@@ -221,7 +234,7 @@
 
 /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k
        SPL code*/
-#if defined(CONFIG_NAND_SPL)
+#ifdef CONFIG_SPL_BUILD
 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
 #endif

@@ -392,15 +405,6 @@
 #define CONFIG_CMD_NAND
 #define CONFIG_SYS_NAND_BLOCK_SIZE	(16 * 1024)
 
-/* NAND boot: 4K NAND loader config */
-#define CONFIG_SYS_NAND_SPL_SIZE	0x1000
-#define CONFIG_SYS_NAND_U_BOOT_SIZE	((512 << 10) + CONFIG_SYS_NAND_SPL_SIZE)
-#define CONFIG_SYS_NAND_U_BOOT_DST	(0x11000000 - CONFIG_SYS_NAND_SPL_SIZE)
-#define CONFIG_SYS_NAND_U_BOOT_START	0x11000000
-#define CONFIG_SYS_NAND_U_BOOT_OFFS	(0)
-#define CONFIG_SYS_NAND_U_BOOT_RELOC	0x00010000
-#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP	(CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000)
-
 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 	| (2<<BR_DECC_SHIFT)	/* Use HW ECC */ \
 	| BR_PS_8	/* Port Size = 8 bit */ \

@@ -461,7 +465,7 @@
 				 OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \
 				 OR_GPCM_EAD)
 
-#ifdef CONFIG_NAND_U_BOOT
+#ifdef CONFIG_NAND
 #define CONFIG_SYS_BR0_PRELIM	CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */
 #define CONFIG_SYS_OR0_PRELIM	CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 #define CONFIG_SYS_BR1_PRELIM	CONFIG_FLASH_BR_PRELIM	/* NOR Base Address */

@@ -511,7 +515,7 @@
 #define CONFIG_SYS_NS16550_SERIAL
 #define CONFIG_SYS_NS16550_REG_SIZE	1
 #define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
-#ifdef CONFIG_NAND_SPL
+#ifdef CONFIG_SPL_BUILD
 #define CONFIG_NS16550_MIN_FUNCTIONS
 #endif

@@ -709,7 +713,6 @@
 /*
  * Environment
  */
-#ifdef CONFIG_SYS_RAMBOOT
 #ifdef CONFIG_RAMBOOT_SPIFLASH
 #define CONFIG_ENV_IS_IN_SPI_FLASH
 #define CONFIG_ENV_SPI_BUS	0

@@ -724,16 +727,15 @@
 #define CONFIG_FSL_FIXED_MMC_LOCATION
 #define CONFIG_ENV_SIZE		0x2000
 #define CONFIG_SYS_MMC_ENV_DEV	0
-#elif defined(CONFIG_NAND_U_BOOT)
+#elif defined(CONFIG_NAND)
 #define CONFIG_ENV_IS_IN_NAND
 #define CONFIG_ENV_SIZE		CONFIG_SYS_NAND_BLOCK_SIZE
 #define CONFIG_ENV_OFFSET	((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
 #define CONFIG_ENV_RANGE	(3 * CONFIG_ENV_SIZE)
-#else
+#elif defined(CONFIG_SYS_RAMBOOT)
 #define CONFIG_ENV_IS_NOWHERE	/* Store ENV in memory only */
 #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
 #define CONFIG_ENV_SIZE		0x2000
-#endif
 #else
 #define CONFIG_ENV_IS_IN_FLASH
 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000

nand_spl/board/freescale/p1_p2_rdb_pc/Makefile deleted +0 ~~-137~~

137 lines not on this page · raw message

nand_spl/board/freescale/p1_p2_rdb_pc/nand_boot.c deleted +0 ~~-132~~

132 lines not on this page · raw message

Signature · 1 line

1.7.9.5

Scott Wood

author

2012-09-22 00:01 UTC #35 lore raw

RFC PATCH 16/17 powerpc/mpc85xx/p2020rdb-pc: fix SPL DDR config

In reply to Scott Wood

This is a temporary fix, and may not be appropriate for all revisions of the board. Presumably the original numbers worked for someone. These values are what the SPD code came up with on a P2020RDB-PCA.

The real solution is to have the SPL load into L2 cache, so that the main U-Boot can use SPD. I hope to implement that for the non-RFC version of this patchset. This makes the board work in the meantime, though.

Signed-off-by Scott Wood <[email protected]>

Cc Andy Fleming <[email protected]>

---
 include/configs/p1_p2_rdb_pc.h |   20 ++++++++++----------
 1 file changed, 10 insertions(+), 10 deletions(-)

include/configs/p1_p2_rdb_pc.h +10 ~~-10~~

index b3c4793..9d5383e 100644
@@ -275,22 +275,22 @@
 #define CONFIG_SYS_DDR_MODE_CONTROL	0x00000000
 
 #define CONFIG_SYS_DDR_ZQ_CONTROL	0x89080600
-#define CONFIG_SYS_DDR_WRLVL_CONTROL	0x8645F607
+#define CONFIG_SYS_DDR_WRLVL_CONTROL	0x8675f608
 #define CONFIG_SYS_DDR_SR_CNTR		0x00000000
 #define CONFIG_SYS_DDR_RCW_1		0x00000000
 #define CONFIG_SYS_DDR_RCW_2		0x00000000
-#define CONFIG_SYS_DDR_CONTROL		0xC7000000	/* Type = DDR3	*/
-#define CONFIG_SYS_DDR_CONTROL_2	0x24401000
+#define CONFIG_SYS_DDR_CONTROL		0xC7000008	/* Type = DDR3	*/
+#define CONFIG_SYS_DDR_CONTROL_2	0x24401040
 #define CONFIG_SYS_DDR_TIMING_4		0x00220001
 #define CONFIG_SYS_DDR_TIMING_5		0x02401400
 
-#define CONFIG_SYS_DDR_TIMING_3		0x00020000
-#define CONFIG_SYS_DDR_TIMING_0		0x00330104
-#define CONFIG_SYS_DDR_TIMING_1		0x6f6B4644
-#define CONFIG_SYS_DDR_TIMING_2		0x0FA88CCF
-#define CONFIG_SYS_DDR_CLK_CTRL		0x02000000
-#define CONFIG_SYS_DDR_MODE_1		0x00421422
-#define CONFIG_SYS_DDR_MODE_2		0x04000000
+#define CONFIG_SYS_DDR_TIMING_3		0x00030000
+#define CONFIG_SYS_DDR_TIMING_0		0x00110104
+#define CONFIG_SYS_DDR_TIMING_1		0x6f6b8846
+#define CONFIG_SYS_DDR_TIMING_2		0x0fa8c8cc
+#define CONFIG_SYS_DDR_CLK_CTRL		0x03000000
+#define CONFIG_SYS_DDR_MODE_1		0x00421421
+#define CONFIG_SYS_DDR_MODE_2		0x00000000
 #define CONFIG_SYS_DDR_INTERVAL		0x0C300100
 
 #else

Signature · 1 line

1.7.9.5

Scott Wood

author

2012-09-22 00:01 UTC #36 lore raw

RFC PATCH 17/17 ns16550: wait for TENT before initializing

In reply to Scott Wood

This prevents output problems (including a loss of synchronization observed on p2020 that persisted for quite a while) if SPL has output still on its way out. I'm not sure why this is only now beginning to happen, though.

Signed-off-by Scott Wood <[email protected]>

---
 drivers/serial/ns16550.c |    3 +++
 1 file changed, 3 insertions(+)

drivers/serial/ns16550.c +3 -0

index 0c23955..66201b6 100644
@@ -36,6 +36,9 @@
 
 void NS16550_init(NS16550_t com_port, int baud_divisor)
 {
+	while (!(serial_in(&com_port->lsr) & UART_LSR_TEMT))
+		;
+
 	serial_out(CONFIG_SYS_NS16550_IER, &com_port->ier);
 #if (defined(CONFIG_OMAP) && !defined(CONFIG_OMAP3_ZOOM2)) || \
 					defined(CONFIG_AM33XX)

Signature · 1 line

1.7.9.5

Timur Tabi

2012-10-01 14:27 UTC #37 lore raw

RFC PATCH 17/17 ns16550: wait for TENT before initializing

Quoted 4 lines · Scott Wood

This prevents output problems (including a loss of synchronization observed on p2020 that persisted for quite a while) if SPL has output still on its way out. I'm not sure why this is only now beginning to happen, though.

The subject line says "TENT", but the macro says "TEMT".

Also, it would be nice to see a description of this bit somewhere.

Quoted 20 lines

Signed-off-by Scott Wood <[email protected]>

---
 drivers/serial/ns16550.c |    3 +++
 1 file changed, 3 insertions(+)

drivers/serial/ns16550.c +3 -0

index 0c23955..66201b6 100644
@@ -36,6 +36,9 @@
 
 void NS16550_init(NS16550_t com_port, int baud_divisor)
 {
+	while (!(serial_in(&com_port->lsr) & UART_LSR_TEMT))
+		;
+
 	serial_out(CONFIG_SYS_NS16550_IER, &com_port->ier);
 #if (defined(CONFIG_OMAP) && !defined(CONFIG_OMAP3_ZOOM2)) || \
 					defined(CONFIG_AM33XX)

Signature · 2 lines

Timur Tabi
Linux kernel developer at Freescale

Tom Rini

2012-09-22 00:13 UTC #38 lore raw

cover Convert p1_p2_rdb_pc to new spl

In reply to Scott Wood

Quoted 5 lines · Scott Wood

This is based on a merge of top-of-tree plus the 85xx tree and the spl framework branch (it doesn't use the SPL framework code because of size constraints, but I wanted to make sure there were no conflicts with it).
Tested on P2020RDB-PC_NAND and P1021RDB-PC_36BIT_NAND.

How close (or far) is this from using the framework due to size? And I will give the whole series a proper read and comment Monday.

Signature · 8 lines

Tom
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Scott Wood

author

2012-09-24 18:50 UTC #39 lore raw

cover Convert p1_p2_rdb_pc to new spl

Quoted 6 lines · Tom Rini

Quoted 1 line · Scott Wood
This is based on a merge of top-of-tree plus the 85xx tree and the
spl
Quoted 1 line
framework branch (it doesn't use the SPL framework code because of
size

Quoted 8 lines

Quoted 1 line
constraints, but I wanted to make sure there were no conflicts with
it).
Quoted 2 lines
Tested on P2020RDB-PC_NAND and P1021RDB-PC_36BIT_NAND.
How close (or far) is this from using the framework due to size? And I
will give the whole series a proper read and comment Monday.

Configuring for P2020RDB-PC_NAND - Board: p1_p2_rdb_pc, Options:
P2020RDB,NAND
text data bss dec hex filename
393179 31912 267088 692179 a8fd3 /tmp/u-boot//u-boot

    3612	    388	      0	   4000	    fa0

/tmp/u-boot//spl/u-boot-spl

--------------------- SUMMARY ---------------------------- Boards compiled: 1
----------------------------------------------------------

Size limit is 4096 bytes.

-Scott

Tom Rini

2012-09-24 19:06 UTC #40 lore raw

cover Convert p1_p2_rdb_pc to new spl

Quoted 22 lines · Scott Wood

Quoted 6 lines · Tom Rini
Quoted 1 line · Scott Wood
This is based on a merge of top-of-tree plus the 85xx tree and
the spl
Quoted 1 line
framework branch (it doesn't use the SPL framework code because
of size
Quoted 8 lines
Quoted 1 line
constraints, but I wanted to make sure there were no conflicts
with it).
Quoted 2 lines
Tested on P2020RDB-PC_NAND and P1021RDB-PC_36BIT_NAND.
How close (or far) is this from using the framework due to size? And I
will give the whole series a proper read and comment Monday.
Configuring for P2020RDB-PC_NAND - Board: p1_p2_rdb_pc, Options:
P2020RDB,NAND
text data bss dec hex filename
393179 31912 267088 692179 a8fd3 /tmp/u-boot//u-boot
3612 388 0 4000 fa0 /tmp/u-boot//spl/u-boot-spl

Quoted 5 lines

--------------------- SUMMARY ---------------------------- Boards compiled: 1
----------------------------------------------------------
Size limit is 4096 bytes.

Right. But that's with your changes yes? Do you have the how-much for using the common framework was? Or just going (and I agree, it won't fit today) by the 96 bytes to spare that a new framework won't fit?

Signature · 8 lines

Tom
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Scott Wood

author

2012-09-24 19:15 UTC #41 lore raw

cover Convert p1_p2_rdb_pc to new spl

Quoted 24 lines · Tom Rini

Quoted 16 lines · Scott Wood
Quoted 6 lines · Tom Rini
Quoted 1 line · Scott Wood
This is based on a merge of top-of-tree plus the 85xx tree and
the spl
Quoted 1 line
framework branch (it doesn't use the SPL framework code because
of size
Quoted 8 lines
Quoted 1 line
constraints, but I wanted to make sure there were no conflicts
with it).
Quoted 2 lines
Tested on P2020RDB-PC_NAND and P1021RDB-PC_36BIT_NAND.
How close (or far) is this from using the framework due to size? And I
will give the whole series a proper read and comment Monday.
Quoted 5 lines
Configuring for P2020RDB-PC_NAND - Board: p1_p2_rdb_pc, Options:
P2020RDB,NAND
text data bss dec hex filename
393179 31912 267088 692179 a8fd3 /tmp/u-boot//u-boot
3612 388 0 4000 fa0
/tmp/u-boot//spl/u-boot-spl
Quoted 1 line

Quoted 7 lines

Quoted 5 lines
--------------------- SUMMARY ---------------------------- Boards compiled: 1
----------------------------------------------------------
Size limit is 4096 bytes.
Right. But that's with your changes yes?

Yes, pretty much the same as with the old nand_spl.

Quoted 3 lines

Do you have the how-much for using the common framework was? Or just going (and I agree, it won't fit today) by the 96 bytes to spare that a new framework won't fit?

The latter. When I get to a board with IFC (which has an 8K limit), such as p1010rdb, I'll give it a try.

-Scott

Scott Wood

author

2012-10-30 02:04 UTC #42 lore raw

v2 cover Convert p1_p2_rdb_pc to new spl

In reply to Scott Wood

Tested on p2020rdb-pca and p1020rdb-pc.

Jos? Miguel Gon?alves (1):
Add u-boot-pad.bin target to the Makefile

Scott Wood (21):
serial/ns16550: don't build serial_ns16550 with MIN_FUNCTIONS serial/ns16550: wait for TEMT before initializing powerpc/mpc85xx: move debug tlb entry after TLB is in known state powerpc/mpc85xx: add comma before "already enabled"
spl: rename u-boot-pad.bin to u-boot-with-spl.bin
spl: introduce CONFIG_SPL_TARGET
powerpc: change .fixup test to a GCC version test powerpc/mpc85xx: fix TLB alignment
powerpc/mpc8xxx: move LAW code into arch/powerpc/cpu/mpc8xxx spl/mpc85xx: move udelay to cpu code
spl: include resetvec and lib8xxx
spl/mpc85xx: rename cpu_init_nand.c to spl_minimal.c powerpc/mpc85xx: consistently use COBJS-y
spl/powerpc: introduce CONFIG_SPL_INIT_MINIMAL spl/85xx: new SPL support powerpc/mpc85xx/p1_p2_rdb_pc: new SPL support spl/nand: introduce CONFIG_SPL_NAND_DRIVERS, _BASE, and _ECC. spl/nand: config symbol documentation powerpc/mpc85xx/p1_p2_rdb_pc: convert from nand_spl to new spl powerpc/mpc85xx/p1_p2_rdb_pc: clean up memory map powerpc/mpc85xx/p2020rdb-pca: Use L2 SRAM for SPL boot

 Makefile                                          |   22 +-
 README                                            |   44 ++-
 arch/powerpc/config.mk                            |    5 +
 arch/powerpc/cpu/mpc85xx/Makefile                 |   38 ++-
 arch/powerpc/cpu/mpc85xx/cpu.c                    |    3 +-
 arch/powerpc/cpu/mpc85xx/cpu_init.c               |    2 +-
 arch/powerpc/cpu/mpc85xx/cpu_init_nand.c          |   42 ---
 arch/powerpc/cpu/mpc85xx/spl_minimal.c            |   59 ++++
 arch/powerpc/cpu/mpc85xx/start.S                  |  123 ++++----
 arch/powerpc/cpu/mpc85xx/tlb.c                    |    4 +-
 arch/powerpc/cpu/mpc85xx/u-boot-spl.lds           |   87 ++++++
 arch/powerpc/cpu/mpc8xxx/Makefile                 |   17 ++
 arch/powerpc/cpu/mpc8xxx/law.c                    |  334 +++++++++++++++++++++
 arch/powerpc/lib/Makefile                         |   23 +-
 board/freescale/p1_p2_rdb_pc/Makefile             |   16 +
 board/freescale/p1_p2_rdb_pc/law.c                |    2 +-
 board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c       |    2 +-
 board/freescale/p1_p2_rdb_pc/spl_minimal.c        |  134 +++++++++
 board/freescale/p1_p2_rdb_pc/tlb.c                |   22 +-
 doc/README.mpc85xx                                |    2 +-
 drivers/misc/Makefile                             |    1 -
 drivers/misc/fsl_law.c                            |  333 --------------------
 drivers/mtd/nand/Makefile                         |   34 ++-
 drivers/mtd/nand/fsl_elbc_spl.c                   |  168 +++++++++++
 drivers/serial/ns16550.c                          |    3 +
 drivers/serial/serial_ns16550.c                   |    4 +
 include/configs/am3517_crane.h                    |    3 +
 include/configs/am3517_evm.h                      |    3 +
 include/configs/cam_enc_4xx.h                     |    3 +
 include/configs/da850evm.h                        |    3 +
 include/configs/devkit8000.h                      |    3 +
 include/configs/hawkboard.h                       |    3 +
 include/configs/igep00x0.h                        |    3 +
 include/configs/mcx.h                             |    3 +
 include/configs/omap3_beagle.h                    |    3 +
 include/configs/omap3_evm.h                       |    3 +
 include/configs/omap3_evm_quick_nand.h            |    3 +
 include/configs/omap3_overo.h                     |    3 +
 include/configs/p1_p2_rdb_pc.h                    |  133 ++++----
 include/configs/tam3517-common.h                  |    3 +
 include/configs/tricorder.h                       |    3 +
 nand_spl/board/freescale/common.c                 |   40 ---
 nand_spl/board/freescale/mpc8536ds/Makefile       |   10 +-
 nand_spl/board/freescale/mpc8569mds/Makefile      |   10 +-
 nand_spl/board/freescale/mpc8572ds/Makefile       |   10 +-
 nand_spl/board/freescale/p1010rdb/Makefile        |   16 +-
 nand_spl/board/freescale/p1023rds/Makefile        |   16 +-
 nand_spl/board/freescale/p1_p2_rdb/Makefile       |   10 +-
 nand_spl/board/freescale/p1_p2_rdb_pc/Makefile    |  146 ---------
 nand_spl/board/freescale/p1_p2_rdb_pc/nand_boot.c |  132 --------
 spl/Makefile                                      |   21 ++
 51 files changed, 1196 insertions(+), 914 deletions(-)
 delete mode 100644 arch/powerpc/cpu/mpc85xx/cpu_init_nand.c
 create mode 100644 arch/powerpc/cpu/mpc85xx/spl_minimal.c
 create mode 100644 arch/powerpc/cpu/mpc85xx/u-boot-spl.lds
 create mode 100644 arch/powerpc/cpu/mpc8xxx/law.c
 create mode 100644 board/freescale/p1_p2_rdb_pc/spl_minimal.c
 delete mode 100644 drivers/misc/fsl_law.c
 create mode 100644 drivers/mtd/nand/fsl_elbc_spl.c
 delete mode 100644 nand_spl/board/freescale/common.c
 delete mode 100644 nand_spl/board/freescale/p1_p2_rdb_pc/Makefile
 delete mode 100644 nand_spl/board/freescale/p1_p2_rdb_pc/nand_boot.c

Signature · 1 line

1.7.9.5

Scott Wood

author

2012-10-30 02:04 UTC #43 lore raw

PATCH v2 1/22 serial/ns16550: don't build serial_ns16550 with MIN_FUNCTIONS

CONFIG_NS16550_MIN_FUNCTIONS is used by small SPLs to gain access to basic ns16550 output code without pulling in things not needed by the SPL.

This previously only worked with non-MULTI configs. Recently MULTI was made mandatory, and MIN_FUNCTIONS fails like this:

drivers/serial/libserial.o: In function `calc_divisor.clone.0':
serial_ns16550.c:(.text.calc_divisor.clone.0+0x24): undefined reference to get_bus_freq' drivers/serial/libserial.o: In function _serial_getc':
(.text._serial_getc+0x30): undefined reference to NS16550_getc' drivers/serial/libserial.o: In function _serial_tstc':
(.text._serial_tstc+0x30): undefined reference to NS16550_tstc' drivers/serial/libserial.o: In function _serial_setbrg':
(.text._serial_setbrg+0x3c): undefined reference to `NS16550_reinit' make[1]: *** [/tmp/u-boot/spl/u-boot-spl] Error 1
make: *** [/tmp/u-boot/spl/u-boot-spl.bin] Error 2

With MIN_FUNCTIONS we don't need anything from this file, so don't build it. The conditional needs to be in the file itself rather than the makefile, because the config symbols are only imported to the makefiles once, not separately for the SPL phase of the build.

Signed-off-by Scott Wood <[email protected]>

---
 drivers/serial/serial_ns16550.c |    4 ++++
 1 file changed, 4 insertions(+)

drivers/serial/serial_ns16550.c +4 -0

index 4176e25..6e374f2 100644
@@ -31,6 +31,8 @@
 
 #include <serial.h>
 
+#ifndef CONFIG_NS16550_MIN_FUNCTIONS
+
 DECLARE_GLOBAL_DATA_PTR;
 
 #if !defined(CONFIG_CONS_INDEX)

@@ -262,3 +264,5 @@ void ns16550_serial_initialize(void)
 	serial_register(&eserial4_device);
 #endif
 }
+
+#endif /* !CONFIG_NS16550_MIN_FUNCTIONS */

Signature · 1 line

1.7.9.5

Scott Wood

author

2012-10-30 02:04 UTC #44 lore raw

PATCH v2 2/22 serial/ns16550: wait for TEMT before initializing

In reply to Scott Wood

TEMT is set when the transmitter is totally empty and all output has finished.

This prevents output problems (including a loss of synchronization observed on p2020 that persisted for quite a while) if SPL has output still on its way out.

Signed-off-by Scott Wood <[email protected]>

--
v2: fixed typo in subject, and explained what the bit does in the changelog

---
 drivers/serial/ns16550.c |    3 +++
 1 file changed, 3 insertions(+)

drivers/serial/ns16550.c +3 -0

index 9027781..bbd91ca 100644
@@ -36,6 +36,9 @@
 
 void NS16550_init(NS16550_t com_port, int baud_divisor)
 {
+	while (!(serial_in(&com_port->lsr) & UART_LSR_TEMT))
+		;
+
 	serial_out(CONFIG_SYS_NS16550_IER, &com_port->ier);
 #if (defined(CONFIG_OMAP) && !defined(CONFIG_OMAP3_ZOOM2)) || \
 					defined(CONFIG_AM33XX)

Signature · 1 line

1.7.9.5

Scott Wood

author

2012-10-30 02:04 UTC #45 lore raw

PATCH v2 3/22 powerpc/mpc85xx: move debug tlb entry after TLB is in known state

In reply to Scott Wood

Previously, in many if not all configs we were creating overlapping TLB entries which is illegal. This caused a crash during boot when moving p2020rdb NAND SPL into L2 SRAM.

Signed-off-by Scott Wood <[email protected]>

Cc Prabhakar Kushwaha <[email protected]>

Cc Andy Fleming <[email protected]>

--
Prabhakar, please test that debug still works.

---
 arch/powerpc/cpu/mpc85xx/start.S |   84 ++++++++++++++++++--------------------
 1 file changed, 40 insertions(+), 44 deletions(-)

arch/powerpc/cpu/mpc85xx/start.S +40 ~~-44~~

index ac17f9d..7912a4b 100644
@@ -282,46 +282,6 @@ l2_disabled:
 	isync
 	.endm
 
-#if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) && !defined(CONFIG_NAND_SPL)
-/*
- * TLB entry for debuggging in AS1
- * Create temporary TLB entry in AS0 to handle debug exception
- * As on debug exception MSR is cleared i.e. Address space is changed
- * to 0. A TLB entry (in AS0) is required to handle debug exception generated
- * in AS1.
- */
-
-#if !defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SECURE_BOOT)
-/*
- * TLB entry is created for IVPR + IVOR15 to map on valid OP code address
- * bacause flash's virtual address maps to 0xff800000 - 0xffffffff.
- * and this window is outside of 4K boot window.
- */
-	create_tlb1_entry CONFIG_SYS_PPC_E500_DEBUG_TLB, \
-		0, BOOKE_PAGESZ_4M, \
-		CONFIG_SYS_MONITOR_BASE & 0xffc00000,  MAS2_I|MAS2_G, \
-		0xffc00000, MAS3_SX|MAS3_SW|MAS3_SR, \
-		0, r6
-
-#elif !defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SECURE_BOOT)
-	create_tlb1_entry CONFIG_SYS_PPC_E500_DEBUG_TLB, \
-		0, BOOKE_PAGESZ_1M, \
-		CONFIG_SYS_MONITOR_BASE, MAS2_I|MAS2_G, \
-		CONFIG_SYS_PBI_FLASH_WINDOW, MAS3_SX|MAS3_SW|MAS3_SR, \
-		0, r6
-#else
-/*
- * TLB entry is created for IVPR + IVOR15 to map on valid OP code address
- * because "nexti" will resize TLB to 4K
- */
-	create_tlb1_entry CONFIG_SYS_PPC_E500_DEBUG_TLB, \
-		0, BOOKE_PAGESZ_256K, \
-		CONFIG_SYS_MONITOR_BASE, MAS2_I, \
-		CONFIG_SYS_MONITOR_BASE, MAS3_SX|MAS3_SW|MAS3_SR, \
-		0, r6
-#endif
-#endif
-
 /*
  * Ne need to setup interrupt vector for NAND SPL
  * because NAND SPL never compiles it.

@@ -534,10 +494,6 @@ nexti:	mflr	r1		/* R1 = our PC */
 	li	r3, 0
 	mtspr	MAS1, r3
 1:	cmpw	r3, r14
-#if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) && !defined(CONFIG_NAND_SPL)
-	cmpwi	cr1, r3, CONFIG_SYS_PPC_E500_DEBUG_TLB
-	cror	cr0*4+eq, cr0*4+eq, cr1*4+eq
-#endif
 	rlwinm	r5, r3, 16, MAS0_ESEL_MSK
 	addi	r3, r3, 1
 	beq	2f		/* skip the entry we're executing from */

@@ -553,6 +509,46 @@ nexti:	mflr	r1		/* R1 = our PC */
 2:	cmpw	r3, r4
 	blt	1b
 
+#if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) && !defined(MINIMAL_SPL)
+/*
+ * TLB entry for debuggging in AS1
+ * Create temporary TLB entry in AS0 to handle debug exception
+ * As on debug exception MSR is cleared i.e. Address space is changed
+ * to 0. A TLB entry (in AS0) is required to handle debug exception generated
+ * in AS1.
+ */
+
+#if !defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SECURE_BOOT)
+/*
+ * TLB entry is created for IVPR + IVOR15 to map on valid OP code address
+ * bacause flash's virtual address maps to 0xff800000 - 0xffffffff.
+ * and this window is outside of 4K boot window.
+ */
+	create_tlb1_entry CONFIG_SYS_PPC_E500_DEBUG_TLB, \
+		0, BOOKE_PAGESZ_4M, \
+		CONFIG_SYS_MONITOR_BASE & 0xffc00000,  MAS2_I|MAS2_G, \
+		0xffc00000, MAS3_SX|MAS3_SW|MAS3_SR, \
+		0, r6
+
+#elif !defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SECURE_BOOT)
+	create_tlb1_entry CONFIG_SYS_PPC_E500_DEBUG_TLB, \
+		0, BOOKE_PAGESZ_1M, \
+		CONFIG_SYS_MONITOR_BASE, MAS2_I|MAS2_G, \
+		CONFIG_SYS_PBI_FLASH_WINDOW, MAS3_SX|MAS3_SW|MAS3_SR, \
+		0, r6
+#else
+/*
+ * TLB entry is created for IVPR + IVOR15 to map on valid OP code address
+ * because "nexti" will resize TLB to 4K
+ */
+	create_tlb1_entry CONFIG_SYS_PPC_E500_DEBUG_TLB, \
+		0, BOOKE_PAGESZ_256K, \
+		CONFIG_SYS_MONITOR_BASE & 0xfffc0000, MAS2_I, \
+		CONFIG_SYS_MONITOR_BASE & 0xfffc0000, MAS3_SX|MAS3_SW|MAS3_SR, \
+		0, r6
+#endif
+#endif
+
 /*
  * Relocate CCSR, if necessary.  We relocate CCSR if (obviously) the default
  * location is not where we want it.  This typically happens on a 36-bit

Signature · 1 line

1.7.9.5

Prabhakar Kushwaha

2012-10-30 09:26 UTC #46 lore raw

PATCH v2 3/22 powerpc/mpc85xx: move debug tlb entry after TLB is in known state

Quoted 10 lines · Scott Wood

Previously, in many if not all configs we were creating overlapping TLB entries which is illegal. This caused a crash during boot when moving p2020rdb NAND SPL into L2 SRAM.
Signed-off-by Scott Wood <[email protected]>
Cc Prabhakar Kushwaha <[email protected]>
Cc Andy Fleming <[email protected]>
--
Prabhakar, please test that debug still works.

During RAMBOOT, both "temporary debug TLB entry" and "execution TLB entry" is same. So moving "temporary debug TLB entry" creation after "execution TLB entry resizing" will make sure of debugging during NAND ramboot, SPI and SD boot.

But for NOR & NAND SPL there is a problem because boot-up TLB as 0xfffff000 and temporary debug TLB as 0xEFF80000. So we require to create temporary TLB entry to support early debugging.

I will suggest to split the CONFIG_SYS_PPC_E500_DEBUG_TLB define into 2 parts.
1) For NOR , NAND spl debugging
2) For RAMBoot: After resizing of execution TLB

I made following changes in the patch and tested across P1010RDB for NOR, NAND-SPL, NAND Ramboot and SPI boot debugging.

Please note I used only this patch after replacing MINIMAL_SPL with CONFIG_NAND_SPL.

(quoted diff) +0 -0

b/arch/powerpc/cpu/mpc85xx/start.S
index ac17f9d..c00db4a 100644

arch/powerpc/cpu/mpc85xx/start.S +8 ~~-11~~

@@ -282,7 +282,7 @@ l2_disabled:
         isync
         .endm
 
-#if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) && !defined(CONFIG_NAND_SPL)
+#if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) && !defined(MINIMAL_SPL)
  /*
   * TLB entry for debuggging in AS1
   * Create temporary TLB entry in AS0 to handle debug exception

@@ -309,16 +309,6 @@ l2_disabled:
                 CONFIG_SYS_MONITOR_BASE, MAS2_I|MAS2_G, \
                 CONFIG_SYS_PBI_FLASH_WINDOW, MAS3_SX|MAS3_SW|MAS3_SR, \
                 0, r6
-#else
-/*
- * TLB entry is created for IVPR + IVOR15 to map on valid OP code address
- * because "nexti" will resize TLB to 4K
- */
-       create_tlb1_entry CONFIG_SYS_PPC_E500_DEBUG_TLB, \
-               0, BOOKE_PAGESZ_256K, \
-               CONFIG_SYS_MONITOR_BASE, MAS2_I, \
-               CONFIG_SYS_MONITOR_BASE, MAS3_SX|MAS3_SW|MAS3_SR, \
-               0, r6
  #endif
  #endif

@@ -520,6 +510,24 @@ nexti:     mflr    r1              /* R1 = our PC */
         msync
         tlbwe
 
+#if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) && !defined(MINIMAL_SPL)\
+   && defined(CONFIG_SYS_RAMBOOT)
+/*
+ * TLB entry for debuggging in AS1
+ * Create temporary TLB entry in AS0 to handle debug exception
+ * As on debug exception MSR is cleared i.e. Address space is changed
+ * to 0. A TLB entry (in AS0) is required to handle debug exception

generated
+ * in AS1.
+ * TLB entry is created for IVPR + IVOR15 to map on valid OP code address
+ * because "nexti" has resized execution TLB entry to 4K
+ */
+ create_tlb1_entry CONFIG_SYS_PPC_E500_DEBUG_TLB, \

+               0, BOOKE_PAGESZ_256K, \
+               CONFIG_SYS_MONITOR_BASE & 0xfffc0000, MAS2_I, \
+               CONFIG_SYS_MONITOR_BASE & 0xfffc0000,

MAS3_SX|MAS3_SW|MAS3_SR, \
+ 0, r6
+#endif
+
/*
* Clear out any other TLB entries that may exist, to avoid conflicts.
* Our TLB entry is in r14.
@@ -534,7 +542,7 @@ nexti: mflr r1 /* R1 = our PC */

         li      r3, 0
         mtspr   MAS1, r3
  1:     cmpw    r3, r14
-#if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) && !defined(CONFIG_NAND_SPL)
+#if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) && !defined(MINIMAL_SPL)
         cmpwi   cr1, r3, CONFIG_SYS_PPC_E500_DEBUG_TLB
         cror    cr0*4+eq, cr0*4+eq, cr1*4+eq

#endif

Regards,
Prabhakar

Scott Wood

author

2012-10-30 21:07 UTC #47 lore raw

PATCH v2 3/22 powerpc/mpc85xx: move debug tlb entry after TLB is in known state

Quoted 19 lines · Prabhakar Kushwaha

Quoted 6 lines · Scott Wood
Previously, in many if not all configs we were creating overlapping TLB entries
which is illegal. This caused a crash during boot when moving p2020rdb NAND SPL
into L2 SRAM.
Quoted 6 lines
Signed-off-by Scott Wood <[email protected]>
Cc Prabhakar Kushwaha <[email protected]>
Cc Andy Fleming <[email protected]>
--
Prabhakar, please test that debug still works.
During RAMBOOT, both "temporary debug TLB entry" and "execution TLB entry" is same. So moving "temporary debug TLB entry" creation after "execution TLB entry resizing" will make sure of debugging during NAND ramboot, SPI and SD boot.

Quoted 8 lines

But for NOR & NAND SPL there is a problem because boot-up TLB as 0xfffff000 and temporary debug TLB as 0xEFF80000. So we require to create temporary TLB entry to support early debugging.
I will suggest to split the CONFIG_SYS_PPC_E500_DEBUG_TLB define into 2 parts.
1) For NOR , NAND spl debugging
2) For RAMBoot: After resizing of execution TLB

I'd rather not see this split this up. This file is too much of a complicated ifdef mess already.

The window during which you won't be able to use breakpoints is not that large. There are other debugging techniques that can be used. Meanwhile, I wasted time debugging the problems that this extra TLB entry caused -- and every time I try to reason about what's going on in this file, I now have one more thing to consider (which is really several more things due to all the different scenarios). Not exactly the desired outcome of something meant to help debugging.

Also, we should not be creating this entry at any time during the SPL.

Quoted 45 lines

I made following changes in the patch and tested across P1010RDB for NOR, NAND-SPL, NAND Ramboot and SPI boot debugging.

Please note I used only this patch after replacing MINIMAL_SPL with CONFIG_NAND_SPL.

arch/powerpc/cpu/mpc85xx/start.S +1 -1

index ac17f9d..c00db4a 100644
@@ -282,7 +282,7 @@ l2_disabled:
        isync
        .endm
 
-#if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) &&  
 !defined(CONFIG_NAND_SPL)
+#if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) && !defined(MINIMAL_SPL)
 /*
  * TLB entry for debuggging in AS1

* Create temporary TLB entry in AS0 to handle debug exception

arch/powerpc/cpu/mpc85xx/start.S +0 -3

@@ -309,16 +309,6 @@ l2_disabled:
                CONFIG_SYS_MONITOR_BASE, MAS2_I|MAS2_G, \
                CONFIG_SYS_PBI_FLASH_WINDOW, MAS3_SX|MAS3_SW|MAS3_SR,  
 \
                0, r6
-#else
-/*
- * TLB entry is created for IVPR + IVOR15 to map on valid OP code

address
- * because "nexti" will resize TLB to 4K
- */

arch/powerpc/cpu/mpc85xx/start.S +0 -5

-       create_tlb1_entry CONFIG_SYS_PPC_E500_DEBUG_TLB, \
-               0, BOOKE_PAGESZ_256K, \
-               CONFIG_SYS_MONITOR_BASE, MAS2_I, \
-               CONFIG_SYS_MONITOR_BASE, MAS3_SX|MAS3_SW|MAS3_SR, \
-               0, r6
 #endif
 #endif

@@ -520,6 +510,24 @@ nexti:     mflr    r1              /* R1 = our

PC */
msync
tlbwe

arch/powerpc/cpu/mpc85xx/start.S nexti: mflr r1 /* R1 = our PC */ · line 514

Quoted 2 lines

arch/powerpc/cpu/mpc85xx/start.S +2 -0

+#if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) && !defined(MINIMAL_SPL)\
+   && defined(CONFIG_SYS_RAMBOOT)

Get rid of that CONFIG_SYS_RAMBOOT. We don't set it anymore for SPL as of this patchset. And the SPL payload is precisely when I saw problems with this!

Quoted 21 lines

+/*
+ * TLB entry for debuggging in AS1
+ * Create temporary TLB entry in AS0 to handle debug exception
+ * As on debug exception MSR is cleared i.e. Address space is changed
+ * to 0. A TLB entry (in AS0) is required to handle debug exception generated
+ * in AS1.
+ * TLB entry is created for IVPR + IVOR15 to map on valid OP code address
+ * because "nexti" has resized execution TLB entry to 4K
+ */
arch/powerpc/cpu/mpc85xx/start.S +4 -0
+       create_tlb1_entry CONFIG_SYS_PPC_E500_DEBUG_TLB, \
+               0, BOOKE_PAGESZ_256K, \
+               CONFIG_SYS_MONITOR_BASE & 0xfffc0000, MAS2_I, \
+               CONFIG_SYS_MONITOR_BASE & 0xfffc0000,  
MAS3_SX|MAS3_SW|MAS3_SR, \
arch/powerpc/cpu/mpc85xx/start.S +3 -0
+               0, r6
+#endif
+
 /*
  * Clear out any other TLB entries that may exist, to avoid  

Quoted 2 lines

conflicts.
* Our TLB entry is in r14.

You *cannot* put this entry into the TLB until we've cleared out the unknown previous contents of the TLB.

-Scott

Prabhakar Kushwaha

2012-10-31 06:17 UTC #48 lore raw

PATCH v2 3/22 powerpc/mpc85xx: move debug tlb entry after TLB is in known state

Quoted 29 lines · Scott Wood

Quoted 19 lines · Prabhakar Kushwaha
Quoted 6 lines · Scott Wood
Previously, in many if not all configs we were creating overlapping TLB entries
which is illegal. This caused a crash during boot when moving p2020rdb NAND SPL
into L2 SRAM.
Quoted 6 lines
Signed-off-by Scott Wood <[email protected]>
Cc Prabhakar Kushwaha <[email protected]>
Cc Andy Fleming <[email protected]>
Signature · 1 line
Prabhakar, please test that debug still works.
During RAMBOOT, both "temporary debug TLB entry" and "execution TLB entry" is same. So moving "temporary debug TLB entry" creation after "execution TLB entry resizing" will make sure of debugging during NAND ramboot, SPI and SD boot.
Quoted 8 lines
But for NOR & NAND SPL there is a problem because boot-up TLB as 0xfffff000 and temporary debug TLB as 0xEFF80000. So we require to create temporary TLB entry to support early debugging.
I will suggest to split the CONFIG_SYS_PPC_E500_DEBUG_TLB define into 2 parts.
1) For NOR , NAND spl debugging
2) For RAMBoot: After resizing of execution TLB

Quoted 6 lines

I'd rather not see this split this up. This file is too much of a complicated ifdef mess already.
The window during which you won't be able to use breakpoints is not that large.
There are other debugging techniques that can be used.

Can you please share the other techniques. It will help us in future.

Quoted 6 lines

Meanwhile, I wasted time debugging the problems that this extra TLB entry caused -- and every time I try to reason about what's going on in this file, I now have one more thing to consider (which is really several more things due to all the different scenarios). Not exactly the desired outcome of something meant to help debugging.

Debugger is present to help in these scenario for faster and effective debugging.
My effort is to make as much as possible u-boot code to be debbug-able.

From now on, we have to take care of extra temporary debug TLB entry.
But this should not mean, no new TLB entries can be created depending upon requirement. This TLB entry is required for debugging in AS1 execution space.

if everything is perfect, debugging is even not required. but if something broken in AS1, debugger is best/shortest way to debug.

Quoted 1 line

Also, we should not be creating this entry at any time during the SPL.

I believe it should not be required as NAND SPL never required. But still need to check once this framework is pushed for mpx85xx platforms

Quoted 44 lines

I made following changes in the patch and tested across P1010RDB for NOR, NAND-SPL, NAND Ramboot and SPI boot debugging.

Please note I used only this patch after replacing MINIMAL_SPL with CONFIG_NAND_SPL.

arch/powerpc/cpu/mpc85xx/start.S +1 -4

index ac17f9d..c00db4a 100644
@@ -282,7 +282,7 @@ l2_disabled:
        isync
        .endm
 
-#if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) && !defined(CONFIG_NAND_SPL)
+#if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) && !defined(MINIMAL_SPL)
 /*
  * TLB entry for debuggging in AS1
  * Create temporary TLB entry in AS0 to handle debug exception

@@ -309,16 +309,6 @@ l2_disabled:
                CONFIG_SYS_MONITOR_BASE, MAS2_I|MAS2_G, \
                CONFIG_SYS_PBI_FLASH_WINDOW, MAS3_SX|MAS3_SW|MAS3_SR, \
                0, r6
-#else
-/*
- * TLB entry is created for IVPR + IVOR15 to map on valid OP code

address
- * because "nexti" will resize TLB to 4K
- */

arch/powerpc/cpu/mpc85xx/start.S +0 -5

-       create_tlb1_entry CONFIG_SYS_PPC_E500_DEBUG_TLB, \
-               0, BOOKE_PAGESZ_256K, \
-               CONFIG_SYS_MONITOR_BASE, MAS2_I, \
-               CONFIG_SYS_MONITOR_BASE, MAS3_SX|MAS3_SW|MAS3_SR, \
-               0, r6
 #endif
 #endif

@@ -520,6 +510,24 @@ nexti:     mflr    r1              /* R1 = our

PC */
msync
tlbwe

Quoted 7 lines

arch/powerpc/cpu/mpc85xx/start.S nexti: mflr r1 /* R1 = our PC */ · line 514
Quoted 2 lines
arch/powerpc/cpu/mpc85xx/start.S +2 -0
+#if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) && !defined(MINIMAL_SPL)\
+   && defined(CONFIG_SYS_RAMBOOT)
Get rid of that CONFIG_SYS_RAMBOOT. We don't set it anymore for SPL as of this patchset. And the SPL payload is precisely when I saw problems with this!

I paste this just for reference. It should be updated in v2 version of this SPL patch series.

Quoted 17 lines

Quoted 17 lines
+/*
+ * TLB entry for debuggging in AS1
+ * Create temporary TLB entry in AS0 to handle debug exception
+ * As on debug exception MSR is cleared i.e. Address space is changed
+ * to 0. A TLB entry (in AS0) is required to handle debug exception generated
+ * in AS1.
+ * TLB entry is created for IVPR + IVOR15 to map on valid OP code address
+ * because "nexti" has resized execution TLB entry to 4K
+ */
arch/powerpc/cpu/mpc85xx/start.S +4 -0
+       create_tlb1_entry CONFIG_SYS_PPC_E500_DEBUG_TLB, \
+               0, BOOKE_PAGESZ_256K, \
+               CONFIG_SYS_MONITOR_BASE & 0xfffc0000, MAS2_I, \
+               CONFIG_SYS_MONITOR_BASE & 0xfffc0000, 
MAS3_SX|MAS3_SW|MAS3_SR, \
+ 0, r6

Quoted 9 lines

arch/powerpc/cpu/mpc85xx/start.S
Quoted 5 lines
arch/powerpc/cpu/mpc85xx/start.S +2 -0
+#endif
+
 /*
  * Clear out any other TLB entries that may exist, to avoid conflicts.
  * Our TLB entry is in r14.
You *cannot* put this entry into the TLB until we've cleared out the unknown previous contents of the TLB.

OK. We can put it just after clearing TLB entries.

Regards,
Prabhakar

Scott Wood

author

2012-10-31 22:08 UTC #49 lore raw

PATCH v2 3/22 powerpc/mpc85xx: move debug tlb entry after TLB is in known state

Quoted 10 lines · Prabhakar Kushwaha

Quoted 7 lines · Scott Wood
On 10/30/2012 04:26:16 AM, Prabhakar Kushwaha wrote:
I'd rather not see this split this up. This file is too much of a complicated ifdef mess already.
The window during which you won't be able to use breakpoints is not that large.
There are other debugging techniques that can be used.
Can you please share the other techniques. It will help us in future.

For debugging early boot hangs I usually put a branch-to-self somewhere in the sequence, and use CCS to see if we're spinning there or if we went off to some exception or other badness. Then I do a binary search, moving the branch to self around, to determine where things went wrong.

-Scott

McClintock Matthew-B29882

2012-10-31 22:44 UTC #50 lore raw

PATCH v2 3/22 powerpc/mpc85xx: move debug tlb entry after TLB is in known state

Quoted 13 lines · Scott Wood

Quoted 12 lines · Prabhakar Kushwaha
Quoted 8 lines · Scott Wood
On 10/30/2012 04:26:16 AM, Prabhakar Kushwaha wrote:
I'd rather not see this split this up. This file is too much of a complicated ifdef mess already.
The window during which you won't be able to use breakpoints is not that large.
There are other debugging techniques that can be used.

Quoted 7 lines

Quoted 1 line
Can you please share the other techniques. It will help us in future.
For debugging early boot hangs I usually put a branch-to-self somewhere in the sequence, and use CCS to see if we're spinning there or if we went off to some exception or other badness. Then I do a binary search, moving the branch to self around, to determine where things went wrong.

LR can be handy to look at too to see what the calling function / branch was.

-M

A message that is not in the archive (sent off-list or not yet received): CAEsOVNeZAyH1nxfgnjPYUG4=7yxjF9rjsRWrpa=WYW8edfiM3Q@mail.gmail.com

McClintock Matthew-B29882

2012-10-31 22:45 UTC #52 lore raw

PATCH v2 3/22 powerpc/mpc85xx: move debug tlb entry after TLB is in known state

Quoted 17 lines · Matthew McClintock

Quoted 16 lines · Scott Wood
Quoted 13 lines · Prabhakar Kushwaha
Quoted 8 lines · Scott Wood
On 10/30/2012 04:26:16 AM, Prabhakar Kushwaha wrote:
I'd rather not see this split this up. This file is too much of a complicated ifdef mess already.
The window during which you won't be able to use breakpoints is not that large.
There are other debugging techniques that can be used.
Can you please share the other techniques. It will help us in future.

Quoted 6 lines

Quoted 4 lines
For debugging early boot hangs I usually put a branch-to-self somewhere in the sequence, and use CCS to see if we're spinning there or if we went off to some exception or other badness. Then I do a binary search, moving the branch to self around, to determine where things went wrong.
LR can be handy to look at too to see what the calling function / branch was.

And to add more... It's even more helpful when you did not instrument your code with a branch to self yet, since sometimes you can find out a good starting point for placing the branch to self in the first place.

-M

Scott Wood

author

2012-10-31 22:51 UTC #53 lore raw

PATCH v2 3/22 powerpc/mpc85xx: move debug tlb entry after TLB is in known state

Quoted 31 lines · On 10/31/2012 05:45:00 PM, McClintock Matthew-B29882 wrote:

Quoted 1 line · Matthew McClintock
On Wed, Oct 31, 2012 at 5:08 PM, Scott Wood
Quoted 6 lines · <[email protected]> wrote:
Quoted 6 lines · Prabhakar Kushwaha
Quoted 5 lines · Scott Wood
Quoted 3 lines · Prabhakar Kushwaha
I'd rather not see this split this up. This file is too much of
a
Quoted 3 lines
Quoted 3 lines
Quoted 3 lines
Quoted 3 lines
complicated ifdef mess already.
The window during which you won't be able to use breakpoints is
not that
Quoted 5 lines
Quoted 5 lines
Quoted 5 lines
Quoted 2 lines
large.
There are other debugging techniques that can be used.
Can you please share the other techniques. It will help us in
future.
Quoted 3 lines
Quoted 3 lines
For debugging early boot hangs I usually put a branch-to-self
somewhere in
Quoted 1 line
Quoted 1 line
the sequence, and use CCS to see if we're spinning there or if we
went off
Quoted 1 line
Quoted 1 line
to some exception or other badness. Then I do a binary search,
moving the
Quoted 2 lines
Quoted 1 line
branch to self around, to determine where things went wrong.

Quoted 7 lines

Quoted 1 line
LR can be handy to look at too to see what the calling function /
branch was.
And to add more... It's even more helpful when you did not instrument your code with a branch to self yet, since sometimes you can find out a good starting point for placing the branch to self in the first place.

Sure, what I wrote was meant for situations where the register dump after you get in a bad state is not very useful, as was often the case when debugging this code (infrequent use of LR, stuck in an exception handler that repeatedly raises itself, obliterating the original SRR0). Sometimes I've seen the chip get stuck so hard that you can't even get register info out.

-Scott

Scott Wood

author

2012-11-16 02:12 UTC #54 lore raw

PATCH v2 3/22 powerpc/mpc85xx: move debug tlb entry after TLB is in known state

In reply to Scott Wood

Quoted 9 lines · Scott Wood

Previously, in many if not all configs we were creating overlapping TLB entries
which is illegal. This caused a crash during boot when moving p2020rdb NAND SPL
into L2 SRAM.
Signed-off-by Scott Wood <[email protected]>
Cc Prabhakar Kushwaha <[email protected]>
Cc Andy Fleming <[email protected]>

Quoted 6 lines

--
Prabhakar, please test that debug still works.

---
 arch/powerpc/cpu/mpc85xx/start.S |   84  
++++++++++++++++++--------------------
 1 file changed, 40 insertions(+), 44 deletions(-)

Andy, could you ack (or nack) this and the other 85xx patches to go via the NAND tree?

-Scott

Andy Fleming

2012-11-26 20:53 UTC #55 lore raw

PATCH v2 3/22 powerpc/mpc85xx: move debug tlb entry after TLB is in known state

In reply to Scott Wood

Quoted 10 lines · Scott Wood

Previously, in many if not all configs we were creating overlapping TLB entries
which is illegal. This caused a crash during boot when moving p2020rdb NAND SPL
into L2 SRAM.
Signed-off-by Scott Wood <[email protected]>
Cc Prabhakar Kushwaha <[email protected]>
Cc Andy Fleming <[email protected]>

Acked-by Andy Fleming <[email protected]>

Prabhakar, we can discuss whether to modify this code in the future to support earlier debug. I'm inclined to agree with Scott's argument, but with the right solution, we might be able to make it work.

Andy

Scott Wood

author

2012-10-30 02:04 UTC #56 lore raw

PATCH v2 4/22 powerpc/mpc85xx: add comma before "already enabled"

In reply to Scott Wood

Now outputs like this:

L2: 512 KB already enabled, moving to 0xf8f80000

rather than this:

L2: 512 KB already enabledmoving to 0xf8f80000

Signed-off-by Scott Wood <[email protected]>

Cc Andy Fleming <[email protected]>

---
 arch/powerpc/cpu/mpc85xx/cpu_init.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

arch/powerpc/cpu/mpc85xx/cpu_init.c +1 -1

index 736293c..c34738e 100644
@@ -470,7 +470,7 @@ int cpu_init_r(void)
 				&& l2srbar >= CONFIG_SYS_FLASH_BASE) {
 			l2srbar = CONFIG_SYS_INIT_L2_ADDR;
 			l2cache->l2srbar0 = l2srbar;
-			printf("moving to 0x%08x", CONFIG_SYS_INIT_L2_ADDR);
+			printf(", moving to 0x%08x", CONFIG_SYS_INIT_L2_ADDR);
 		}
 #endif /* CONFIG_SYS_INIT_L2_ADDR */
 		puts("\n");

Signature · 1 line

1.7.9.5

Scott Wood

author

2012-10-30 02:04 UTC #57 lore raw

PATCH v2 5/22 Add u-boot-pad.bin target to the Makefile

In reply to Scott Wood

From: Jos? Miguel Gon?alves <[email protected]>

Samsung's S3C24XX SoCs need this in order to generate a binary image with a padded SPL concatenated with U-Boot.

Signed-off-by Jos? Miguel Gon?alves <[email protected]>

[scottwood at freescale.com: fixed prereq of u-boot.ubl]

Signed-off-by Scott Wood <[email protected]>

--
v2: Removed spl/ prefix from u-boot.ubl prerequisite.

---
 Makefile |   11 ++++++-----
 1 file changed, 6 insertions(+), 5 deletions(-)

Makefile +6 -5

index d385467..366096f 100644
@@ -470,14 +470,15 @@ $(obj)u-boot.sha1:	$(obj)u-boot.bin
 $(obj)u-boot.dis:	$(obj)u-boot
 		$(OBJDUMP) -d $< > $@
 
-$(obj)u-boot.ubl:       $(obj)spl/u-boot-spl.bin $(obj)u-boot.bin
+$(obj)u-boot-pad.bin:       $(obj)spl/u-boot-spl.bin $(obj)u-boot.bin
 		$(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $(obj)spl/u-boot-spl $(obj)spl/u-boot-spl-pad.bin
-		cat $(obj)spl/u-boot-spl-pad.bin $(obj)u-boot.bin > $(obj)u-boot-ubl.bin
-		$(obj)tools/mkimage -n $(UBL_CONFIG) -T ublimage \
-		-e $(CONFIG_SYS_TEXT_BASE) -d $(obj)u-boot-ubl.bin $(obj)u-boot.ubl
-		rm $(obj)u-boot-ubl.bin
+		cat $(obj)spl/u-boot-spl-pad.bin $(obj)u-boot.bin > $(obj)u-boot-pad.bin
 		rm $(obj)spl/u-boot-spl-pad.bin
 
+$(obj)u-boot.ubl:       $(obj)u-boot-pad.bin
+		$(obj)tools/mkimage -n $(UBL_CONFIG) -T ublimage \
+		-e $(CONFIG_SYS_TEXT_BASE) -d $(obj)u-boot-pad.bin $(obj)u-boot.ubl
+
 $(obj)u-boot.ais:       $(obj)spl/u-boot-spl.bin $(obj)u-boot.img
 		$(obj)tools/mkimage -s -n $(if $(CONFIG_AIS_CONFIG_FILE),$(CONFIG_AIS_CONFIG_FILE),"/dev/null") \
 			-T aisimage \

Signature · 1 line

1.7.9.5

Scott Wood

author

2012-10-30 02:04 UTC #58 lore raw

PATCH v2 6/22 spl: rename u-boot-pad.bin to u-boot-with-spl.bin

In reply to Scott Wood

Signed-off-by Scott Wood <[email protected]>

---
 Makefile |    8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

Makefile +4 -4

index 366096f..61f4d69 100644
@@ -470,14 +470,14 @@ $(obj)u-boot.sha1:	$(obj)u-boot.bin
 $(obj)u-boot.dis:	$(obj)u-boot
 		$(OBJDUMP) -d $< > $@
 
-$(obj)u-boot-pad.bin:       $(obj)spl/u-boot-spl.bin $(obj)u-boot.bin
+$(obj)u-boot-with-spl.bin: $(obj)spl/u-boot-spl.bin $(obj)u-boot.bin
 		$(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $(obj)spl/u-boot-spl $(obj)spl/u-boot-spl-pad.bin
-		cat $(obj)spl/u-boot-spl-pad.bin $(obj)u-boot.bin > $(obj)u-boot-pad.bin
+		cat $(obj)spl/u-boot-spl-pad.bin $(obj)u-boot.bin > $@
 		rm $(obj)spl/u-boot-spl-pad.bin
 
-$(obj)u-boot.ubl:       $(obj)u-boot-pad.bin
+$(obj)u-boot.ubl:       $(obj)u-boot-with-spl.bin
 		$(obj)tools/mkimage -n $(UBL_CONFIG) -T ublimage \
-		-e $(CONFIG_SYS_TEXT_BASE) -d $(obj)u-boot-pad.bin $(obj)u-boot.ubl
+		-e $(CONFIG_SYS_TEXT_BASE) -d $< $(obj)u-boot.ubl
 
 $(obj)u-boot.ais:       $(obj)spl/u-boot-spl.bin $(obj)u-boot.img
 		$(obj)tools/mkimage -s -n $(if $(CONFIG_AIS_CONFIG_FILE),$(CONFIG_AIS_CONFIG_FILE),"/dev/null") \

Signature · 1 line

1.7.9.5

Scott Wood

author

2012-10-30 02:04 UTC #59 lore raw

PATCH v2 7/22 spl: introduce CONFIG_SPL_TARGET

In reply to Scott Wood

Currently the SPL target is specified in a CPU-specific makefile
fragment. While some targets may need something more complicated than a
simple target name, targets which don't need this shouldn't have to provide a makefile fragment just for this.

Signed-off-by Scott Wood <[email protected]>

---
v2: Removed default target as it's been pointed out to me how existing platforms cause the SPL to be built.

---
 Makefile |    1 +
 README   |    5 +++++
 2 files changed, 6 insertions(+)

Makefile +1 -0

index 61f4d69..7630ce9 100644
@@ -403,6 +403,7 @@ ALL-y += $(obj)u-boot.srec $(obj)u-boot.bin $(obj)System.map
 ALL-$(CONFIG_NAND_U_BOOT) += $(obj)u-boot-nand.bin
 ALL-$(CONFIG_ONENAND_U_BOOT) += $(obj)u-boot-onenand.bin
 ALL-$(CONFIG_SPL) += $(obj)spl/u-boot-spl.bin
+ALL-$(CONFIG_SPL) += $(obj)$(subst ",,$(CONFIG_SPL_TARGET))
 ALL-$(CONFIG_OF_SEPARATE) += $(obj)u-boot.dtb $(obj)u-boot-dtb.bin
 
 # enable combined SPL/u-boot/dtb rules for tegra

README +5 -0

index 4f16240..4294c2e 100644
@@ -2726,6 +2726,11 @@ FIT uImage format:
 		CONFIG_SPL_LIBGENERIC_SUPPORT
 		Support for lib/libgeneric.o in SPL binary
 
+		CONFIG_SPL_TARGET
+		Final target image containing SPL and payload.  Some SPLs
+		use an arch-specific makefile fragment instead, for
+		example if more than one image needs to be produced.
+
 Modem Support:
 --------------

Signature · 1 line

1.7.9.5

Scott Wood

author

2012-10-30 02:04 UTC #60 lore raw

PATCH v2 8/22 powerpc: change .fixup test to a GCC version test

In reply to Scott Wood

The problem is reported to occur with GCC 3.x, so insist on GCC 4.0 or newer. Patterned after checkthumb as suggested by Tom Rini.

Signed-off-by Scott Wood <[email protected]>

Cc Peter Tyser <[email protected]>

Cc Tom Rini <[email protected]>

--
v2: test gcc version instead of testing nothing

---
 Makefile                  |   10 ++++++++++
 arch/powerpc/config.mk    |    5 +++++
 arch/powerpc/lib/Makefile |    6 ------
 3 files changed, 15 insertions(+), 6 deletions(-)

Makefile +10 -0

index 7630ce9..751179c 100644
@@ -638,6 +638,16 @@ checkthumb:
 		echo '*** Your board is configured for THUMB mode.'; \
 		false; \
 	fi
+
+# GCC 3.x is reported to have problems generating the type of relocation
+# that U-Boot wants.
+# See http://lists.denx.de/pipermail/u-boot/2012-September/135156.html
+checkgcc4:
+	@if test $(call cc-version) -lt 0400; then \
+		echo -n '*** Your GCC is too old, please upgrade to GCC 4.x or newer'; \
+		false; \
+	fi
+
 #
 # Auto-generate the autoconf.mk file (which is included by all makefiles)
 #

arch/powerpc/config.mk +5 -0

index a307154..b706281 100644
@@ -42,3 +42,8 @@ endif
 ifeq ($(CROSS_COMPILE),powerpc-openbsd-)
 PLATFORM_CPPFLAGS+= -D__PPC__
 endif
+
+# Only test once
+ifneq ($(CONFIG_SPL_BUILD),y)
+ALL-y += checkgcc4
+endif

arch/powerpc/lib/Makefile +0 -6

index 808021c..4a41635 100644
@@ -75,12 +75,6 @@ TARGETS += $(LIB)
 all: $(TARGETS)
 
 $(LIB):	$(obj).depend $(OBJS)
-	@if ! $(CROSS_COMPILE)readelf -S $(OBJS) | grep -q '\.fixup.*PROGBITS';\
-	then \
-		echo "ERROR: Your compiler doesn't generate .fixup sections!";\
-		echo "       Upgrade to a recent toolchain."; \
-		exit 1; \
-	fi;
 	$(call cmd_link_o_target, $(OBJS))
 
 $(LIBGCC): $(obj).depend $(LGOBJS)

Signature · 1 line

1.7.9.5

Scott Wood

author

2012-10-30 02:04 UTC #61 lore raw

PATCH v2 9/22 powerpc/mpc85xx: fix TLB alignment

In reply to Scott Wood

Fix the TLB entry to always start at a proper alignment. We still assume that CONFIG_SYS_MONITOR_BASE doesn't start immediately before a large-page boundary thus requiring multiple TLB entries.

Signed-off-by Scott Wood <[email protected]>

Cc Andy Fleming <[email protected]>

---
 arch/powerpc/cpu/mpc85xx/start.S |    8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

arch/powerpc/cpu/mpc85xx/start.S +4 -4

index 7912a4b..577d687 100644
@@ -1046,8 +1046,8 @@ create_init_ram_area:
 	*/
 	create_tlb1_entry 15, \
 		1, BOOKE_PAGESZ_1M, \
-		CONFIG_SYS_MONITOR_BASE, MAS2_I|MAS2_G, \
-		CONFIG_SYS_PBI_FLASH_WINDOW, MAS3_SX|MAS3_SW|MAS3_SR, \
+		CONFIG_SYS_MONITOR_BASE & 0xfff00000, MAS2_I|MAS2_G, \
+		CONFIG_SYS_PBI_FLASH_WINDOW & 0xfff00000, MAS3_SX|MAS3_SW|MAS3_SR, \
 		0, r6
 #else
 	/*

@@ -1056,8 +1056,8 @@ create_init_ram_area:
 	 */
 	create_tlb1_entry 15, \
 		1, BOOKE_PAGESZ_1M, \
-		CONFIG_SYS_MONITOR_BASE, MAS2_I|MAS2_G, \
-		CONFIG_SYS_MONITOR_BASE, MAS3_SX|MAS3_SW|MAS3_SR, \
+		CONFIG_SYS_MONITOR_BASE & 0xfff00000, MAS2_I|MAS2_G, \
+		CONFIG_SYS_MONITOR_BASE & 0xfff00000, MAS3_SX|MAS3_SW|MAS3_SR, \
 		0, r6
 #endif

Signature · 1 line

1.7.9.5

Scott Wood

author

2012-10-30 02:04 UTC #62 lore raw

PATCH v2 10/22 powerpc/mpc8xxx: move LAW code into arch/powerpc/cpu/mpc8xxx

In reply to Scott Wood

It's arch code and not a driver, so move it where it belongs. When it originally went into drivers/misc there was no 8xxx CPU directory.

This will make new-SPL support a little easier since we can keep the CPU stuff together and not need to pull stuff in from drivers/misc.

Signed-off-by Scott Wood <[email protected]>

Cc Andy Fleming <[email protected]>

---
 arch/powerpc/cpu/mpc8xxx/Makefile              |    1 +
 arch/powerpc/cpu/mpc8xxx/law.c                 |  333 ++++++++++++++++++++++++
 drivers/misc/Makefile                          |    1 -
 drivers/misc/fsl_law.c                         |  333 ------------------------
 nand_spl/board/freescale/mpc8536ds/Makefile    |    2 +-
 nand_spl/board/freescale/mpc8569mds/Makefile   |    2 +-
 nand_spl/board/freescale/mpc8572ds/Makefile    |    2 +-
 nand_spl/board/freescale/p1010rdb/Makefile     |    2 +-
 nand_spl/board/freescale/p1023rds/Makefile     |    2 +-
 nand_spl/board/freescale/p1_p2_rdb/Makefile    |    2 +-
 nand_spl/board/freescale/p1_p2_rdb_pc/Makefile |    2 +-
 11 files changed, 341 insertions(+), 341 deletions(-)
 create mode 100644 arch/powerpc/cpu/mpc8xxx/law.c
 delete mode 100644 drivers/misc/fsl_law.c

arch/powerpc/cpu/mpc8xxx/Makefile +1 -0

index 4ae26e4..86344a7 100644
@@ -18,6 +18,7 @@ COBJS-$(CONFIG_OF_LIBFDT) += fdt.o
 COBJS-$(CONFIG_FSL_IFC) += fsl_ifc.o
 COBJS-$(CONFIG_FSL_LBC) += fsl_lbc.o
 COBJS-$(CONFIG_SYS_SRIO) += srio.o
+COBJS-$(CONFIG_FSL_LAW) += law.o
 
 SRCS	:= $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
 OBJS	:= $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))

arch/powerpc/cpu/mpc8xxx/law.c new file +333 -0

333 lines not on this page · raw message

drivers/misc/Makefile +0 -1

index 271463c..3b19e5f 100644
@@ -27,7 +27,6 @@ LIB	:= $(obj)libmisc.o
 
 COBJS-$(CONFIG_ALI152X) += ali512x.o
 COBJS-$(CONFIG_DS4510)  += ds4510.o
-COBJS-$(CONFIG_FSL_LAW) += fsl_law.o
 COBJS-$(CONFIG_GPIO_LED) += gpio_led.o
 COBJS-$(CONFIG_FSL_MC9SDZ60) += mc9sdz60.o
 COBJS-$(CONFIG_NS87308) += ns87308.o

drivers/misc/fsl_law.c deleted +0 ~~-333~~

333 lines not on this page · raw message

nand_spl/board/freescale/mpc8536ds/Makefile +1 -1

index e5388d8..707273b 100644
@@ -85,7 +85,7 @@ $(obj)cpu_init_nand.c:
 
 $(obj)fsl_law.c:
 	@rm -f $(obj)fsl_law.c
-	ln -sf $(SRCTREE)/drivers/misc/fsl_law.c $(obj)fsl_law.c
+	ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc8xxx/law.c $(obj)fsl_law.c
 
 $(obj)law.c:
 	@rm -f $(obj)law.c

nand_spl/board/freescale/mpc8569mds/Makefile +1 -1

index e5388d8..707273b 100644
@@ -85,7 +85,7 @@ $(obj)cpu_init_nand.c:
 
 $(obj)fsl_law.c:
 	@rm -f $(obj)fsl_law.c
-	ln -sf $(SRCTREE)/drivers/misc/fsl_law.c $(obj)fsl_law.c
+	ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc8xxx/law.c $(obj)fsl_law.c
 
 $(obj)law.c:
 	@rm -f $(obj)law.c

nand_spl/board/freescale/mpc8572ds/Makefile +1 -1

index e5388d8..707273b 100644
@@ -85,7 +85,7 @@ $(obj)cpu_init_nand.c:
 
 $(obj)fsl_law.c:
 	@rm -f $(obj)fsl_law.c
-	ln -sf $(SRCTREE)/drivers/misc/fsl_law.c $(obj)fsl_law.c
+	ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc8xxx/law.c $(obj)fsl_law.c
 
 $(obj)law.c:
 	@rm -f $(obj)law.c

nand_spl/board/freescale/p1010rdb/Makefile +1 -1

index f270faa..bbf73c5 100644
@@ -86,7 +86,7 @@ $(obj)cpu_init_nand.c:
 
 $(obj)fsl_law.c:
 	@rm -f $(obj)fsl_law.c
-	ln -sf $(SRCTREE)/drivers/misc/fsl_law.c $(obj)fsl_law.c
+	ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc8xxx/law.c $(obj)fsl_law.c
 
 $(obj)law.c:
 	@rm -f $(obj)law.c

nand_spl/board/freescale/p1023rds/Makefile +1 -1

index b2882844..d7e95df 100644
@@ -81,7 +81,7 @@ $(obj)cpu_init_nand.c:
 
 $(obj)fsl_law.c:
 	@rm -f $(obj)fsl_law.c
-	ln -sf $(SRCTREE)/drivers/misc/fsl_law.c $(obj)fsl_law.c
+	ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc8xxx/law.c $(obj)fsl_law.c
 
 $(obj)law.c:
 	@rm -f $(obj)law.c

nand_spl/board/freescale/p1_p2_rdb/Makefile +1 -1

index e5388d8..707273b 100644
@@ -85,7 +85,7 @@ $(obj)cpu_init_nand.c:
 
 $(obj)fsl_law.c:
 	@rm -f $(obj)fsl_law.c
-	ln -sf $(SRCTREE)/drivers/misc/fsl_law.c $(obj)fsl_law.c
+	ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc8xxx/law.c $(obj)fsl_law.c
 
 $(obj)law.c:
 	@rm -f $(obj)law.c

nand_spl/board/freescale/p1_p2_rdb_pc/Makefile +1 -1

index 7146d16..481d1d9 100644
@@ -86,7 +86,7 @@ $(obj)cpu_init_nand.c:
 
 $(obj)fsl_law.c:
 	@rm -f $(obj)fsl_law.c
-	ln -sf $(SRCTREE)/drivers/misc/fsl_law.c $(obj)fsl_law.c
+	ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc8xxx/law.c $(obj)fsl_law.c
 
 $(obj)law.c:
 	@rm -f $(obj)law.c

Signature · 1 line

1.7.9.5

Scott Wood

author

2012-10-30 02:04 UTC #63 lore raw

PATCH v2 11/22 spl/mpc85xx: move udelay to cpu code

In reply to Scott Wood

It applies to non-Freescale 85xx boards as well as Freescale boards, so it doesn't belong in board/freescale. Plus, it needs to come out of nand_spl if it's to be used by the new SPL.

Signed-off-by Scott Wood <[email protected]>

Cc Andy Fleming <[email protected]>

---
 arch/powerpc/cpu/mpc85xx/cpu_init_nand.c       |   17 ++++++++++
 nand_spl/board/freescale/common.c              |   40 ------------------------
 nand_spl/board/freescale/p1010rdb/Makefile     |    6 +---
 nand_spl/board/freescale/p1023rds/Makefile     |    6 +---
 nand_spl/board/freescale/p1_p2_rdb_pc/Makefile |    6 +---
 5 files changed, 20 insertions(+), 55 deletions(-)
 delete mode 100644 nand_spl/board/freescale/common.c

arch/powerpc/cpu/mpc85xx/cpu_init_nand.c +17 -0

index bf7a6f6..0589497 100644
@@ -21,9 +21,13 @@
  */
 
 #include <common.h>
+#include <asm/processor.h>
+#include <asm/global_data.h>
 #include <asm/fsl_ifc.h>
 #include <asm/io.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 void cpu_init_f(void)
 {
 #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)

@@ -40,3 +44,16 @@ void cpu_init_f(void)
 		(MPC85xx_L2CTL_L2E | MPC85xx_L2CTL_L2SRAM_ENTIRE));
 #endif
 }
+
+#ifndef CONFIG_SYS_FSL_TBCLK_DIV
+#define CONFIG_SYS_FSL_TBCLK_DIV 8
+#endif
+
+void udelay(unsigned long usec)
+{
+	u32 ticks_per_usec = gd->bus_clk / (CONFIG_SYS_FSL_TBCLK_DIV * 1000000);
+	u32 ticks = ticks_per_usec * usec;
+	u32 s = mfspr(SPRN_TBRL);
+
+	while ((mfspr(SPRN_TBRL) - s) < ticks);
+}

nand_spl/board/freescale/common.c deleted +0 ~~-40~~

deleted file mode 100644
index 0e099bc..0000000
@@ -1,40 +0,0 @@
-/*
- * Copyright 2012 Freescale Semiconductor, Inc.
- * Author: Matthew McClintock <[email protected]>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- *
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- */
-
-#include <common.h>
-#include <asm/processor.h>
-#include <asm/global_data.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#ifndef CONFIG_SYS_FSL_TBCLK_DIV
-#define CONFIG_SYS_FSL_TBCLK_DIV 8
-#endif
-
-void udelay(unsigned long usec)
-{
-	u32 ticks_per_usec = gd->bus_clk / (CONFIG_SYS_FSL_TBCLK_DIV * 1000000);
-	u32 ticks = ticks_per_usec * usec;
-	u32 s = mfspr(SPRN_TBRL);
-
-	while ((mfspr(SPRN_TBRL) - s) < ticks);
-}

nand_spl/board/freescale/p1010rdb/Makefile +1 -5

index bbf73c5..187ff4e 100644
@@ -40,8 +40,7 @@ CFLAGS	+= -DCONFIG_NAND_SPL
 
 SOBJS	= start.o resetvec.o ticks.o
 COBJS	= cache.o cpu_init_early.o cpu_init_nand.o fsl_law.o law.o \
-	  nand_boot.o nand_boot_fsl_ifc.o ns16550.o tlb.o tlb_table.o \
-	  ../common.o
+	  nand_boot.o nand_boot_fsl_ifc.o ns16550.o tlb.o tlb_table.o
 
 SRCS	:= $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
 OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))

@@ -129,9 +128,6 @@ ifneq ($(OBJTREE), $(SRCTREE))
 $(obj)nand_boot.c:
 	@rm -f $(obj)nand_boot.c
 	ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/nand_boot.c $(obj)nand_boot.c
-$(obj)../common.c:
-	@rm -f $(obj)../common.c
-	ln -s $(SRCTREE)/nand_spl/board/freescale/common.c $(obj)../common.c
 endif
 
 #########################################################################

nand_spl/board/freescale/p1023rds/Makefile +1 -5

index d7e95df..60fdd90 100644
@@ -35,8 +35,7 @@ CFLAGS	+= -DCONFIG_NAND_SPL
 
 SOBJS	= start.o resetvec.o
 COBJS	= cache.o cpu_init_early.o cpu_init_nand.o fsl_law.o law.o \
-	  nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o \
-	  ../common.o
+	  nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o
 
 SRCS	:= $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
 OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))

@@ -120,9 +119,6 @@ ifneq ($(OBJTREE), $(SRCTREE))
 $(obj)nand_boot.c:
 	@rm -f $(obj)nand_boot.c
 	ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/nand_boot.c $(obj)nand_boot.c
-$(obj)../common.c:
-	@rm -f $(obj)../common.c
-	ln -s $(SRCTREE)/nand_spl/board/freescale/common.c $(obj)../common.c
 endif
 
 #########################################################################

nand_spl/board/freescale/p1_p2_rdb_pc/Makefile +1 -5

index 481d1d9..98d3ad0 100644
@@ -40,8 +40,7 @@ CFLAGS	+= -DCONFIG_NAND_SPL
 
 SOBJS	= start.o resetvec.o
 COBJS	= cache.o cpu_init_early.o cpu_init_nand.o fsl_law.o law.o \
-	  nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o \
-	  ../common.o
+	  nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o
 
 SRCS	:= $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
 OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))

@@ -125,9 +124,6 @@ ifneq ($(OBJTREE), $(SRCTREE))
 $(obj)nand_boot.c:
 	@rm -f $(obj)nand_boot.c
 	ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/nand_boot.c $(obj)nand_boot.c
-$(obj)../common.c:
-	@rm -f $(obj)../common.c
-	ln -s $(SRCTREE)/nand_spl/board/freescale/common.c $(obj)../common.c
 endif
 
 #########################################################################

Signature · 1 line

1.7.9.5

Scott Wood

author

2012-10-30 02:05 UTC #64 lore raw

PATCH v2 12/22 spl: include resetvec and lib8xxx

In reply to Scott Wood

The toplevel makefile hardcodes this stuff, so spl/Makefile needs to as well.

Signed-off-by Scott Wood <[email protected]>

---
 spl/Makefile |   21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

spl/Makefile +21 -0

index 3195390..eacf4a2 100644
@@ -32,9 +32,30 @@ START_PATH := $(CPUDIR)
 endif
 
 START := $(START_PATH)/start.o
+ifeq ($(CPU),x86)
+START += $(START_PATH)/start16.o
+START += $(START_PATH)/resetvec.o
+endif
+ifeq ($(CPU),ppc4xx)
+START += $(START_PATH)/resetvec.o
+endif
+ifeq ($(CPU),mpc85xx)
+START += $(START_PATH)/resetvec.o
+endif
 
 LIBS-y += arch/$(ARCH)/lib/lib$(ARCH).o
+
 LIBS-y += $(CPUDIR)/lib$(CPU).o
+ifeq ($(CPU),mpc83xx)
+LIBS-y += arch/powerpc/cpu/mpc8xxx/lib8xxx.o
+endif
+ifeq ($(CPU),mpc85xx)
+LIBS-y += arch/powerpc/cpu/mpc8xxx/lib8xxx.o
+endif
+ifeq ($(CPU),mpc86xx)
+LIBS-y += arch/powerpc/cpu/mpc8xxx/lib8xxx.o
+endif
+
 ifdef SOC
 LIBS-y += $(CPUDIR)/$(SOC)/lib$(SOC).o
 endif

Signature · 1 line

1.7.9.5

Scott Wood

author

2012-10-30 02:05 UTC #65 lore raw

PATCH v2 13/22 spl/mpc85xx: rename cpu_init_nand.c to spl_minimal.c

In reply to Scott Wood

There is nothing really NAND-specific about this file.

Signed-off-by Scott Wood <[email protected]>

Cc Andy Fleming <[email protected]>

---
 arch/powerpc/cpu/mpc85xx/cpu_init_nand.c       |   59 ------------------------
 arch/powerpc/cpu/mpc85xx/spl_minimal.c         |   59 ++++++++++++++++++++++++
 nand_spl/board/freescale/mpc8536ds/Makefile    |    8 ++--
 nand_spl/board/freescale/mpc8569mds/Makefile   |    8 ++--
 nand_spl/board/freescale/mpc8572ds/Makefile    |    8 ++--
 nand_spl/board/freescale/p1010rdb/Makefile     |    8 ++--
 nand_spl/board/freescale/p1023rds/Makefile     |    8 ++--
 nand_spl/board/freescale/p1_p2_rdb/Makefile    |    8 ++--
 nand_spl/board/freescale/p1_p2_rdb_pc/Makefile |    8 ++--
 9 files changed, 87 insertions(+), 87 deletions(-)
 delete mode 100644 arch/powerpc/cpu/mpc85xx/cpu_init_nand.c
 create mode 100644 arch/powerpc/cpu/mpc85xx/spl_minimal.c

arch/powerpc/cpu/mpc85xx/cpu_init_nand.c deleted +0 ~~-59~~

deleted file mode 100644
index 0589497..0000000
@@ -1,59 +0,0 @@
-/*
- * Copyright 2009 Freescale Semiconductor, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/processor.h>
-#include <asm/global_data.h>
-#include <asm/fsl_ifc.h>
-#include <asm/io.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-void cpu_init_f(void)
-{
-#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
-	ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR;
-
-	out_be32(&l2cache->l2srbar0, CONFIG_SYS_INIT_L2_ADDR);
-
-	/* set MBECCDIS=1, SBECCDIS=1 */
-	out_be32(&l2cache->l2errdis,
-		(MPC85xx_L2ERRDIS_MBECC | MPC85xx_L2ERRDIS_SBECC));
-
-	/* set L2E=1 & L2SRAM=001 */
-	out_be32(&l2cache->l2ctl,
-		(MPC85xx_L2CTL_L2E | MPC85xx_L2CTL_L2SRAM_ENTIRE));
-#endif
-}
-
-#ifndef CONFIG_SYS_FSL_TBCLK_DIV
-#define CONFIG_SYS_FSL_TBCLK_DIV 8
-#endif
-
-void udelay(unsigned long usec)
-{
-	u32 ticks_per_usec = gd->bus_clk / (CONFIG_SYS_FSL_TBCLK_DIV * 1000000);
-	u32 ticks = ticks_per_usec * usec;
-	u32 s = mfspr(SPRN_TBRL);
-
-	while ((mfspr(SPRN_TBRL) - s) < ticks);
-}

arch/powerpc/cpu/mpc85xx/spl_minimal.c new file +59 -0

59 lines not on this page · raw message

nand_spl/board/freescale/mpc8536ds/Makefile +4 -4

index 707273b..c923557 100644
@@ -39,7 +39,7 @@ AFLAGS	+= -DCONFIG_NAND_SPL
 CFLAGS	+= -DCONFIG_NAND_SPL
 
 SOBJS	= start.o resetvec.o
-COBJS	= cache.o cpu_init_early.o cpu_init_nand.o fsl_law.o law.o \
+COBJS	= cache.o cpu_init_early.o spl_minimal.o fsl_law.o law.o \
 	  nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o
 
 SRCS	:= $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))

@@ -79,9 +79,9 @@ $(obj)cpu_init_early.c:
 	@rm -f $(obj)cpu_init_early.c
 	ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/cpu_init_early.c $(obj)cpu_init_early.c
 
-$(obj)cpu_init_nand.c:
-	@rm -f $(obj)cpu_init_nand.c
-	ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c $(obj)cpu_init_nand.c
+$(obj)spl_minimal.c:
+	@rm -f $(obj)spl_minimal.c
+	ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/spl_minimal.c $(obj)spl_minimal.c
 
 $(obj)fsl_law.c:
 	@rm -f $(obj)fsl_law.c

nand_spl/board/freescale/mpc8569mds/Makefile +4 -4

index 707273b..c923557 100644
@@ -39,7 +39,7 @@ AFLAGS	+= -DCONFIG_NAND_SPL
 CFLAGS	+= -DCONFIG_NAND_SPL
 
 SOBJS	= start.o resetvec.o
-COBJS	= cache.o cpu_init_early.o cpu_init_nand.o fsl_law.o law.o \
+COBJS	= cache.o cpu_init_early.o spl_minimal.o fsl_law.o law.o \
 	  nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o
 
 SRCS	:= $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))

@@ -79,9 +79,9 @@ $(obj)cpu_init_early.c:
 	@rm -f $(obj)cpu_init_early.c
 	ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/cpu_init_early.c $(obj)cpu_init_early.c
 
-$(obj)cpu_init_nand.c:
-	@rm -f $(obj)cpu_init_nand.c
-	ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c $(obj)cpu_init_nand.c
+$(obj)spl_minimal.c:
+	@rm -f $(obj)spl_minimal.c
+	ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/spl_minimal.c $(obj)spl_minimal.c
 
 $(obj)fsl_law.c:
 	@rm -f $(obj)fsl_law.c

nand_spl/board/freescale/mpc8572ds/Makefile +4 -4

index 707273b..c923557 100644
@@ -39,7 +39,7 @@ AFLAGS	+= -DCONFIG_NAND_SPL
 CFLAGS	+= -DCONFIG_NAND_SPL
 
 SOBJS	= start.o resetvec.o
-COBJS	= cache.o cpu_init_early.o cpu_init_nand.o fsl_law.o law.o \
+COBJS	= cache.o cpu_init_early.o spl_minimal.o fsl_law.o law.o \
 	  nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o
 
 SRCS	:= $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))

@@ -79,9 +79,9 @@ $(obj)cpu_init_early.c:
 	@rm -f $(obj)cpu_init_early.c
 	ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/cpu_init_early.c $(obj)cpu_init_early.c
 
-$(obj)cpu_init_nand.c:
-	@rm -f $(obj)cpu_init_nand.c
-	ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c $(obj)cpu_init_nand.c
+$(obj)spl_minimal.c:
+	@rm -f $(obj)spl_minimal.c
+	ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/spl_minimal.c $(obj)spl_minimal.c
 
 $(obj)fsl_law.c:
 	@rm -f $(obj)fsl_law.c

nand_spl/board/freescale/p1010rdb/Makefile +4 -4

index 187ff4e..ccff1c7 100644
@@ -39,7 +39,7 @@ AFLAGS	+= -DCONFIG_NAND_SPL
 CFLAGS	+= -DCONFIG_NAND_SPL
 
 SOBJS	= start.o resetvec.o ticks.o
-COBJS	= cache.o cpu_init_early.o cpu_init_nand.o fsl_law.o law.o \
+COBJS	= cache.o cpu_init_early.o spl_minimal.o fsl_law.o law.o \
 	  nand_boot.o nand_boot_fsl_ifc.o ns16550.o tlb.o tlb_table.o
 
 SRCS	:= $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))

@@ -79,9 +79,9 @@ $(obj)cpu_init_early.c:
 	@rm -f $(obj)cpu_init_early.c
 	ln -sf $(SRCTREE)/$(CPUDIR)/cpu_init_early.c $(obj)cpu_init_early.c
 
-$(obj)cpu_init_nand.c:
-	@rm -f $(obj)cpu_init_nand.c
-	ln -sf $(SRCTREE)/$(CPUDIR)/cpu_init_nand.c $(obj)cpu_init_nand.c
+$(obj)spl_minimal.c:
+	@rm -f $(obj)spl_minimal.c
+	ln -sf $(SRCTREE)/$(CPUDIR)/spl_minimal.c $(obj)spl_minimal.c
 
 $(obj)fsl_law.c:
 	@rm -f $(obj)fsl_law.c

nand_spl/board/freescale/p1023rds/Makefile +4 -4

index 60fdd90..ffe29c8 100644
@@ -34,7 +34,7 @@ AFLAGS	+= -DCONFIG_NAND_SPL
 CFLAGS	+= -DCONFIG_NAND_SPL
 
 SOBJS	= start.o resetvec.o
-COBJS	= cache.o cpu_init_early.o cpu_init_nand.o fsl_law.o law.o \
+COBJS	= cache.o cpu_init_early.o spl_minimal.o fsl_law.o law.o \
 	  nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o
 
 SRCS	:= $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))

@@ -74,9 +74,9 @@ $(obj)cpu_init_early.c:
 	@rm -f $(obj)cpu_init_early.c
 	ln -sf $(SRCTREE)/$(CPUDIR)/cpu_init_early.c $(obj)cpu_init_early.c
 
-$(obj)cpu_init_nand.c:
-	@rm -f $(obj)cpu_init_nand.c
-	ln -sf $(SRCTREE)/$(CPUDIR)/cpu_init_nand.c $(obj)cpu_init_nand.c
+$(obj)spl_minimal.c:
+	@rm -f $(obj)spl_minimal.c
+	ln -sf $(SRCTREE)/$(CPUDIR)/spl_minimal.c $(obj)spl_minimal.c
 
 $(obj)fsl_law.c:
 	@rm -f $(obj)fsl_law.c

nand_spl/board/freescale/p1_p2_rdb/Makefile +4 -4

index 707273b..c923557 100644
@@ -39,7 +39,7 @@ AFLAGS	+= -DCONFIG_NAND_SPL
 CFLAGS	+= -DCONFIG_NAND_SPL
 
 SOBJS	= start.o resetvec.o
-COBJS	= cache.o cpu_init_early.o cpu_init_nand.o fsl_law.o law.o \
+COBJS	= cache.o cpu_init_early.o spl_minimal.o fsl_law.o law.o \
 	  nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o
 
 SRCS	:= $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))

@@ -79,9 +79,9 @@ $(obj)cpu_init_early.c:
 	@rm -f $(obj)cpu_init_early.c
 	ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/cpu_init_early.c $(obj)cpu_init_early.c
 
-$(obj)cpu_init_nand.c:
-	@rm -f $(obj)cpu_init_nand.c
-	ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c $(obj)cpu_init_nand.c
+$(obj)spl_minimal.c:
+	@rm -f $(obj)spl_minimal.c
+	ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/spl_minimal.c $(obj)spl_minimal.c
 
 $(obj)fsl_law.c:
 	@rm -f $(obj)fsl_law.c

nand_spl/board/freescale/p1_p2_rdb_pc/Makefile +4 -4

index 98d3ad0..797a800 100644
@@ -39,7 +39,7 @@ AFLAGS	+= -DCONFIG_NAND_SPL
 CFLAGS	+= -DCONFIG_NAND_SPL
 
 SOBJS	= start.o resetvec.o
-COBJS	= cache.o cpu_init_early.o cpu_init_nand.o fsl_law.o law.o \
+COBJS	= cache.o cpu_init_early.o spl_minimal.o fsl_law.o law.o \
 	  nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o
 
 SRCS	:= $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))

@@ -79,9 +79,9 @@ $(obj)cpu_init_early.c:
 	@rm -f $(obj)cpu_init_early.c
 	ln -sf $(SRCTREE)/$(CPUDIR)/cpu_init_early.c $(obj)cpu_init_early.c
 
-$(obj)cpu_init_nand.c:
-	@rm -f $(obj)cpu_init_nand.c
-	ln -sf $(SRCTREE)/$(CPUDIR)/cpu_init_nand.c $(obj)cpu_init_nand.c
+$(obj)spl_minimal.c:
+	@rm -f $(obj)spl_minimal.c
+	ln -sf $(SRCTREE)/$(CPUDIR)/spl_minimal.c $(obj)spl_minimal.c
 
 $(obj)fsl_law.c:
 	@rm -f $(obj)fsl_law.c

Signature · 1 line

1.7.9.5

Scott Wood

author

2012-10-30 02:05 UTC #66 lore raw

PATCH v2 14/22 powerpc/mpc85xx: consistently use COBJS-y

In reply to Scott Wood

A subsequent patch will conditionalize some of the files that are currently unconditional.

Signed-off-by Scott Wood <[email protected]>

Cc Andy Fleming <[email protected]>

---
 arch/powerpc/cpu/mpc85xx/Makefile |   19 ++++++++++---------
 1 file changed, 10 insertions(+), 9 deletions(-)

arch/powerpc/cpu/mpc85xx/Makefile +10 -9

index 78c412d..a7dbfa7 100644
@@ -121,17 +121,18 @@ COBJS-$(CONFIG_PPC_P5040) += p5040_serdes.o
 COBJS-$(CONFIG_PPC_T4240) += t4240_serdes.o
 COBJS-$(CONFIG_PPC_B4860) += b4860_serdes.o
 
-COBJS	= $(COBJS-y)
-COBJS	+= cpu.o
-COBJS	+= cpu_init.o
-COBJS	+= cpu_init_early.o
-COBJS	+= interrupts.o
-COBJS	+= speed.o
-COBJS	+= tlb.o
-COBJS	+= traps.o
+COBJS-y	+= cpu.o
+COBJS-y	+= cpu_init.o
+COBJS-y	+= cpu_init_early.o
+COBJS-y	+= interrupts.o
+COBJS-y	+= speed.o
+COBJS-y	+= tlb.o
+COBJS-y	+= traps.o
 
 # Stub implementations of cache management functions for USB
-COBJS += cache.o
+COBJS-y += cache.o
+
+COBJS	= $(COBJS-y)
 
 SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))

Signature · 1 line

1.7.9.5

Scott Wood

author

2012-10-30 02:05 UTC #67 lore raw

PATCH v2 15/22 spl/powerpc: introduce CONFIG_SPL_INIT_MINIMAL

In reply to Scott Wood

cpu_init_nand.c is renamed to spl_minimal.c as it is not really NAND-specific.

Signed-off-by Scott Wood <[email protected]>

---
v2: factor out START, and change cpu_init_nand.c to spl_minimal.c
Cc: Andy Fleming <[email protected]>

---
 README                            |    3 +++
 arch/powerpc/cpu/mpc85xx/Makefile |   19 ++++++++++++++++++-
 arch/powerpc/cpu/mpc85xx/start.S  |   33 ++++++++++++++++++++-------------
 arch/powerpc/cpu/mpc8xxx/Makefile |   16 ++++++++++++++++
 arch/powerpc/lib/Makefile         |   17 ++++++++++++++++-
 5 files changed, 73 insertions(+), 15 deletions(-)

README +3 -0

index 4294c2e..cf83c47 100644
@@ -2657,6 +2657,9 @@ FIT uImage format:
 		For ARM, enable an optional function to print more information
 		about the running system.
 
+		CONFIG_SPL_INIT_MINIMAL
+		Arch init code should be built for a very small image
+
 		CONFIG_SPL_LIBCOMMON_SUPPORT
 		Support for common/libcommon.o in SPL binary

arch/powerpc/cpu/mpc85xx/Makefile +18 -1

index a7dbfa7..4c2b104 100644
@@ -28,7 +28,22 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(CPU).o
 
-START	= start.o resetvec.o
+MINIMAL=
+
+ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_SPL_INIT_MINIMAL
+MINIMAL=y
+endif
+endif
+
+START = start.o resetvec.o
+
+ifdef MINIMAL
+
+COBJS-y	+= cpu_init_early.o tlb.o spl_minimal.o
+
+else
+
 SOBJS-$(CONFIG_MP)	+= release.o
 SOBJS	= $(SOBJS-y)

@@ -132,6 +147,8 @@ COBJS-y	+= traps.o
 # Stub implementations of cache management functions for USB
 COBJS-y += cache.o
 
+endif # not minimal
+
 COBJS	= $(COBJS-y)
 
 SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)

arch/powerpc/cpu/mpc85xx/start.S +20 ~~-13~~

index 577d687..bb0dc1a 100644
@@ -44,6 +44,15 @@
 #undef	MSR_KERNEL
 #define MSR_KERNEL ( MSR_ME )	/* Machine Check */
 
+#if defined(CONFIG_NAND_SPL) || \
+	(defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL))
+#define MINIMAL_SPL
+#endif
+
+#if !defined(CONFIG_SPL) && !defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SECURE_BOOT)
+#define NOR_BOOT
+#endif
+
 /*
  * Set up GOT: Global Offset Table
  *

@@ -53,7 +62,7 @@
 	GOT_ENTRY(_GOT2_TABLE_)
 	GOT_ENTRY(_FIXUP_TABLE_)
 
-#ifndef CONFIG_NAND_SPL
+#ifndef MINIMAL_SPL
 	GOT_ENTRY(_start)
 	GOT_ENTRY(_start_of_vectors)
 	GOT_ENTRY(_end_of_vectors)

@@ -282,11 +291,8 @@ l2_disabled:
 	isync
 	.endm
 
-/*
- * Ne need to setup interrupt vector for NAND SPL
- * because NAND SPL never compiles it.
- */
-#if !defined(CONFIG_NAND_SPL)
+/* Interrupt vectors do not fit in minimal SPL. */
+#if !defined(MINIMAL_SPL)
 	/* Setup interrupt vectors */
 	lis	r1,CONFIG_SYS_MONITOR_BASE at h
 	mtspr	IVPR,r1

@@ -518,7 +524,7 @@ nexti:	mflr	r1		/* R1 = our PC */
  * in AS1.
  */
 
-#if !defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SECURE_BOOT)
+#ifdef NOR_BOOT
 /*
  * TLB entry is created for IVPR + IVOR15 to map on valid OP code address
  * bacause flash's virtual address maps to 0xff800000 - 0xffffffff.

@@ -1032,7 +1038,7 @@ create_init_ram_area:
 	lis     r6,FSL_BOOKE_MAS0(1, 15, 0)@h
 	ori     r6,r6,FSL_BOOKE_MAS0(1, 15, 0)@l
 
-#if !defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SECURE_BOOT)
+#ifdef NOR_BOOT
 	/* create a temp mapping in AS=1 to the 4M boot window */
 	create_tlb1_entry 15, \
 		1, BOOKE_PAGESZ_4M, \

@@ -1107,7 +1113,8 @@ switch_as:
 	bdnz	1b
 
 	/* Jump out the last 4K page and continue to 'normal' start */
-#ifdef CONFIG_SYS_RAMBOOT
+#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)
+	/* We assume that we're already running at the address we're linked at */
 	b	_start_cont
 #else
 	/* Calculate absolute address in FLASH and jump there		*/

@@ -1153,7 +1160,7 @@ _start_cont:
 
 	/* NOTREACHED - board_init_f() does not return */
 
-#ifndef CONFIG_NAND_SPL
+#ifndef MINIMAL_SPL
 	. = EXC_OFF_SYS_RESET
 	.globl	_start_of_vectors
 _start_of_vectors:

@@ -1597,7 +1604,7 @@ in32:
 in32r:
 	lwbrx	r3,r0,r3
 	blr
-#endif  /* !CONFIG_NAND_SPL */
+#endif  /* !MINIMAL_SPL */
 
 /*------------------------------------------------------------------------------*/

@@ -1794,7 +1801,7 @@ clear_bss:
 	mr	r4,r10		/* Destination Address		*/
 	bl	board_init_r
 
-#ifndef CONFIG_NAND_SPL
+#ifndef MINIMAL_SPL
 	/*
 	 * Copy exception vector code to low memory
 	 *

@@ -1967,4 +1974,4 @@ setup_ivors:
 
 #include "fixed_ivor.S"
 	blr
-#endif /* !CONFIG_NAND_SPL */
+#endif /* !MINIMAL_SPL */

arch/powerpc/cpu/mpc8xxx/Makefile +16 -0

index 86344a7..3dc8e05 100644
@@ -10,6 +10,20 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib8xxx.o
 
+MINIMAL=
+
+ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_SPL_INIT_MINIMAL
+MINIMAL=y
+endif
+endif
+
+ifdef MINIMAL
+
+COBJS-$(CONFIG_FSL_LAW) += law.o
+
+else
+
 ifneq ($(CPU),mpc83xx)
 COBJS-y	+= cpu.o
 endif

@@ -20,6 +34,8 @@ COBJS-$(CONFIG_FSL_LBC) += fsl_lbc.o
 COBJS-$(CONFIG_SYS_SRIO) += srio.o
 COBJS-$(CONFIG_FSL_LAW) += law.o
 
+endif
+
 SRCS	:= $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
 OBJS	:= $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))

arch/powerpc/lib/Makefile +16 -1

index 4a41635..20c5c38 100644
@@ -38,8 +38,21 @@ endif
 
 LIB	= $(obj)lib$(ARCH).o
 
-SOBJS-y	+= ppccache.o
+MINIMAL=
+
+ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_SPL_INIT_MINIMAL
+MINIMAL=y
+endif
+endif
+
+ifdef MINIMAL
+COBJS-y += cache.o
+else
+
 SOBJS-y	+= ppcstring.o
+
+SOBJS-y	+= ppccache.o
 SOBJS-y	+= ticks.o
 SOBJS-y	+= reloc.o

@@ -64,6 +77,8 @@ $(obj)ppcstring.o: AFLAGS += -Dmemcpy=__memcpy
 COBJS-y += memcpy_mpc5200.o
 endif
 
+endif # not minimal
+
 COBJS	+= $(sort $(COBJS-y))
 
 SRCS	:= $(GLSOBJS:.o=.S) $(GLCOBJS:.o=.c) \

Signature · 1 line

1.7.9.5

Scott Wood

author

2012-10-30 02:05 UTC #68 lore raw

PATCH v2 16/22 spl/85xx: new SPL support

In reply to Scott Wood

Update CONFIG_RAMBOOT and CONFIG_NAND_SPL references to accept CONFIG_SPL and CONFIG_SPL_BUILD, respectively. CONFIG_NAND_SPL can be removed once the last mpc85xx nand_spl target is gone.

Signed-off-by Scott Wood <[email protected]>

Cc Andy Fleming <[email protected]>

---
 arch/powerpc/cpu/mpc85xx/cpu.c          |    3 +-
 arch/powerpc/cpu/mpc85xx/spl_minimal.c  |    2 +-
 arch/powerpc/cpu/mpc85xx/tlb.c          |    4 +-
 arch/powerpc/cpu/mpc85xx/u-boot-spl.lds |   87 +++++++++++++++++++++++++++++++
 arch/powerpc/cpu/mpc8xxx/law.c          |   11 ++--
 doc/README.mpc85xx                      |    2 +-
 6 files changed, 99 insertions(+), 10 deletions(-)
 create mode 100644 arch/powerpc/cpu/mpc85xx/u-boot-spl.lds

arch/powerpc/cpu/mpc85xx/cpu.c +2 -1

index db232e6..78486aa 100644
@@ -332,7 +332,8 @@ void mpc85xx_reginfo(void)
 
 /* Common ddr init for non-corenet fsl 85xx platforms */
 #ifndef CONFIG_FSL_CORENET
-#if defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SYS_INIT_L2_ADDR)
+#if (defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)) && \
+	!defined(CONFIG_SYS_INIT_L2_ADDR)
 phys_size_t initdram(int board_type)
 {
 #if defined(CONFIG_SPD_EEPROM) || defined(CONFIG_DDR_SPD)

arch/powerpc/cpu/mpc85xx/spl_minimal.c +1 -1

index 0589497..c6b9cd0 100644
@@ -30,7 +30,7 @@ DECLARE_GLOBAL_DATA_PTR;
 
 void cpu_init_f(void)
 {
-#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
+#ifdef CONFIG_SYS_INIT_L2_ADDR
 	ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR;
 
 	out_be32(&l2cache->l2srbar0, CONFIG_SYS_INIT_L2_ADDR);

arch/powerpc/cpu/mpc85xx/tlb.c +2 -2

index a548dec..f44fadc 100644
@@ -55,7 +55,7 @@ void init_tlbs(void)
 	return ;
 }
 
-#ifndef CONFIG_NAND_SPL
+#if !defined(CONFIG_NAND_SPL) && !defined(CONFIG_SPL_BUILD)
 void read_tlbcam_entry(int idx, u32 *valid, u32 *tsize, unsigned long *epn,
 		       phys_addr_t *rpn)
 {

@@ -332,4 +332,4 @@ void clear_ddr_tlbs(unsigned int memsize_in_meg)
 }
 
 
-#endif /* !CONFIG_NAND_SPL */
+#endif /* not SPL */

arch/powerpc/cpu/mpc85xx/u-boot-spl.lds new file +87 -0

87 lines not on this page · raw message

arch/powerpc/cpu/mpc8xxx/law.c +6 -5

index 223cd5d..ce1d71e 100644
@@ -92,7 +92,7 @@ void disable_law(u8 idx)
 	return;
 }
 
-#ifndef CONFIG_NAND_SPL
+#if !defined(CONFIG_NAND_SPL) && !defined(CONFIG_SPL_BUILD)
 static int get_law_entry(u8 i, struct law_entry *e)
 {
 	u32 lawar;

@@ -122,7 +122,7 @@ int set_next_law(phys_addr_t addr, enum law_size sz, enum law_trgt_if id)
 	return idx;
 }
 
-#ifndef CONFIG_NAND_SPL
+#if !defined(CONFIG_NAND_SPL) && !defined(CONFIG_SPL_BUILD)
 int set_last_law(phys_addr_t addr, enum law_size sz, enum law_trgt_if id)
 {
 	u32 idx;

@@ -233,7 +233,7 @@ int set_ddr_laws(u64 start, u64 sz, enum law_trgt_if id)
 
 	return 0;
 }
-#endif
+#endif /* not SPL */
 
 void init_laws(void)
 {

@@ -258,9 +258,10 @@ void init_laws(void)
 			gd->used_laws |= (1 << i);
 	}
 
-#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
+#if (defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)) || \
+	(defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD))
 	/*
-	 * in NAND boot we've already parsed the law_table and setup those LAWs
+	 * in SPL boot we've already parsed the law_table and setup those LAWs
 	 * so don't do it again.
 	 */
 	return;

doc/README.mpc85xx +1 -1

index 5a4b591..f9b023f 100644
@@ -26,7 +26,7 @@ Major Config Switches during various boot Modes
 ----------------------------------------------
 
 NOR boot
-		!defined(CONFIG_SYS_RAMBOOT)
+		!defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SPL)
 NOR boot Secure
 		!defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SECURE_BOOT)
 RAMBOOT(SD, SPI & NAND boot)

Signature · 1 line

1.7.9.5

Scott Wood

author

2012-10-30 02:05 UTC #69 lore raw

PATCH v2 17/22 powerpc/mpc85xx/p1_p2_rdb_pc: new SPL support

In reply to Scott Wood

Introduces CONFIG_SPL_RELOC_TEXT_BASE and CONFIG_SPL_RELOC_STACK.

Signed-off-by Scott Wood <[email protected]>

Cc Andy Fleming <[email protected]>

---
 README                                      |    9 ++
 board/freescale/p1_p2_rdb_pc/Makefile       |   16 ++++
 board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c |    2 +-
 board/freescale/p1_p2_rdb_pc/spl_minimal.c  |  131 +++++++++++++++++++++++++++
 board/freescale/p1_p2_rdb_pc/tlb.c          |    7 +-
 5 files changed, 160 insertions(+), 5 deletions(-)
 create mode 100644 board/freescale/p1_p2_rdb_pc/spl_minimal.c

README +9 -0

index cf83c47..b03796b 100644
@@ -2633,6 +2633,10 @@ FIT uImage format:
 		CONFIG_SPL_TEXT_BASE
 		TEXT_BASE for linking the SPL binary.
 
+		CONFIG_SPL_RELOC_TEXT_BASE
+		Address to relocate to.  If unspecified, this is equal to
+		CONFIG_SPL_TEXT_BASE (i.e. no relocation is done).
+
 		CONFIG_SPL_BSS_START_ADDR
 		Link address for the BSS within the SPL binary.

@@ -2642,6 +2646,11 @@ FIT uImage format:
 		CONFIG_SPL_STACK
 		Adress of the start of the stack SPL will use
 
+		CONFIG_SPL_RELOC_STACK
+		Adress of the start of the stack SPL will use after
+		relocation.  If unspecified, this is equal to
+		CONFIG_SPL_STACK.
+
 		CONFIG_SYS_SPL_MALLOC_START
 		Starting address of the malloc pool used in SPL.

board/freescale/p1_p2_rdb_pc/Makefile +16 -0

index 0dcf7d1..5b45d72 100644
@@ -24,11 +24,27 @@ include $(TOPDIR)/config.mk
 
 LIB    = $(obj)lib$(BOARD).o
 
+MINIMAL=
+
+ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_SPL_INIT_MINIMAL
+MINIMAL=y
+endif
+endif
+
+ifdef MINIMAL
+
+COBJS-y	+= spl_minimal.o tlb.o law.o
+
+else
+
 COBJS-y        += $(BOARD).o
 COBJS-y        += ddr.o
 COBJS-y        += law.o
 COBJS-y        += tlb.o
 
+endif
+
 SRCS   := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
 OBJS   := $(addprefix $(obj),$(COBJS-y))
 SOBJS  := $(addprefix $(obj),$(SOBJS))

board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c +1 -1

index aa39260..5b5b86c 100644
@@ -177,7 +177,7 @@ void board_gpio_init(void)
 	 */
 
 	setbits_be32(&pgpio->gpdir, 0x02130000);
-#ifndef CONFIG_SYS_RAMBOOT
+#if !defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SPL)
 	/* init DDR3 reset signal */
 	setbits_be32(&pgpio->gpdir, 0x00200000);
 	setbits_be32(&pgpio->gpodr, 0x00200000);

board/freescale/p1_p2_rdb_pc/spl_minimal.c new file +131 -0

131 lines not on this page · raw message

board/freescale/p1_p2_rdb_pc/tlb.c +3 -4

index 6d22463..0873dd7 100644
@@ -53,7 +53,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
 			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 			0, 1, BOOKE_PAGESZ_1M, 1),
 
-#ifndef CONFIG_NAND_SPL
+#ifndef CONFIG_SPL_BUILD
 	/* W**G* - Flash/promjet, localbus */
 	/* This will be changed to *I*G* after relocation to RAM. */
 	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,

@@ -85,7 +85,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
 	SET_TLB_ENTRY(1, CONFIG_SYS_PMC_BASE, CONFIG_SYS_PMC_BASE_PHYS,
 			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 			0, 10, BOOKE_PAGESZ_64K, 1),
-#endif
+#endif /* not SPL */
 
 #ifdef CONFIG_SYS_NAND_BASE
 	/* *I*G - NAND */

@@ -94,7 +94,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
 			0, 7, BOOKE_PAGESZ_1M, 1),
 #endif
 
-#ifdef CONFIG_SYS_RAMBOOT
+#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)
 	/* *I*G - eSDHC/eSPI/NAND boot */
 	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
 			MAS3_SX|MAS3_SW|MAS3_SR, 0,

@@ -108,7 +108,6 @@ struct fsl_e_tlb_entry tlb_table[] = {
 			0, 9, BOOKE_PAGESZ_1G, 1),
 #endif
 #endif
-
 };
 
 int num_tlb_entries = ARRAY_SIZE(tlb_table);

Signature · 1 line

1.7.9.5

Scott Wood

author

2012-10-30 02:05 UTC #70 lore raw

PATCH v2 18/22 spl/nand: introduce CONFIG_SPL_NAND_DRIVERS, _BASE, and _ECC.

In reply to Scott Wood

Some small SPLs do not use nand_base.c, and a subset of those also require a special driver. Some SPLs need software ECC but others can't fit it.

All existing boards that specify CONFIG_SPL_NAND_SUPPORT have these symbols added to preserve existing behavior.

Signed-off-by Scott Wood <[email protected]>

--
v2: use positive logic for including bits of NAND, rather than a MINIMAL symbol that excludes things.

---
 README                                 |   10 ++++++++++
 drivers/mtd/nand/Makefile              |   30 ++++++++++++++++++++++--------
 include/configs/am3517_crane.h         |    3 +++
 include/configs/am3517_evm.h           |    3 +++
 include/configs/cam_enc_4xx.h          |    3 +++
 include/configs/da850evm.h             |    3 +++
 include/configs/devkit8000.h           |    3 +++
 include/configs/hawkboard.h            |    3 +++
 include/configs/igep00x0.h             |    3 +++
 include/configs/mcx.h                  |    3 +++
 include/configs/omap3_beagle.h         |    3 +++
 include/configs/omap3_evm.h            |    3 +++
 include/configs/omap3_evm_quick_nand.h |    3 +++
 include/configs/omap3_overo.h          |    3 +++
 include/configs/tam3517-common.h       |    3 +++
 include/configs/tricorder.h            |    3 +++
 16 files changed, 74 insertions(+), 8 deletions(-)

README +10 -0

index b03796b..efa19a4 100644
@@ -2696,6 +2696,16 @@ FIT uImage format:
 		CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME
 		Filename to read to load U-Boot when reading from FAT
 
+		CONFIG_SPL_NAND_BASE
+		Include nand_base.c in the SPL.  Requires
+		CONFIG_SPL_NAND_DRIVERS.
+
+		CONFIG_SPL_NAND_DRIVERS
+		SPL uses normal NAND drivers, not minimal drivers.
+
+		CONFIG_SPL_NAND_ECC
+		Include standard software ECC in the SPL
+
 		CONFIG_SPL_NAND_SIMPLE
 		Support for drivers/mtd/nand/libnand.o in SPL binary

drivers/mtd/nand/Makefile +22 -8

index beb99ca..d8a2dfc 100644
@@ -26,21 +26,33 @@ include $(TOPDIR)/config.mk
 LIB	:= $(obj)libnand.o
 
 ifdef CONFIG_CMD_NAND
+
 ifdef CONFIG_SPL_BUILD
-ifdef CONFIG_SPL_NAND_SIMPLE
-COBJS-y += nand_spl_simple.o
-endif
-ifdef CONFIG_SPL_NAND_LOAD
-COBJS-y	+= nand_spl_load.o
+
+ifdef CONFIG_SPL_NAND_DRIVERS
+NORMAL_DRIVERS=y
 endif
-else
+
+COBJS-$(CONFIG_SPL_NAND_SIMPLE) += nand_spl_simple.o
+COBJS-$(CONFIG_SPL_NAND_LOAD) += nand_spl_load.o
+COBJS-$(CONFIG_SPL_NAND_ECC) += nand_ecc.o
+COBJS-$(CONFIG_SPL_NAND_BASE) += nand_base.o
+
+else # not spl
+
+NORMAL_DRIVERS=y
+
 COBJS-y += nand.o
 COBJS-y += nand_bbt.o
 COBJS-y += nand_ids.o
 COBJS-y += nand_util.o
-endif
 COBJS-y += nand_ecc.o
 COBJS-y += nand_base.o
+
+endif # not spl
+
+ifdef NORMAL_DRIVERS
+
 COBJS-$(CONFIG_NAND_ECC_BCH) += nand_bch.o
 
 COBJS-$(CONFIG_NAND_ATMEL) += atmel_nand.o

@@ -65,7 +77,9 @@ COBJS-$(CONFIG_NAND_SPEAR) += spr_nand.o
 COBJS-$(CONFIG_TEGRA_NAND) += tegra_nand.o
 COBJS-$(CONFIG_NAND_OMAP_GPMC) += omap_gpmc.o
 COBJS-$(CONFIG_NAND_PLAT) += nand_plat.o
-endif
+
+endif # drivers
+endif # nand
 
 COBJS	:= $(COBJS-y)
 SRCS	:= $(COBJS:.o=.c)

include/configs/am3517_crane.h +3 -0

index 20a3df5..e1ad1e5 100644
@@ -337,6 +337,9 @@
 #define CONFIG_SPL_FAT_SUPPORT
 #define CONFIG_SPL_SERIAL_SUPPORT
 #define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_NAND_BASE
+#define CONFIG_SPL_NAND_DRIVERS
+#define CONFIG_SPL_NAND_ECC
 #define CONFIG_SPL_POWER_SUPPORT
 #define CONFIG_SPL_LDSCRIPT		"$(CPUDIR)/omap-common/u-boot-spl.lds"

include/configs/am3517_evm.h +3 -0

index ce71d13..f833275 100644
@@ -336,6 +336,9 @@
 #define CONFIG_SPL_FAT_SUPPORT
 #define CONFIG_SPL_SERIAL_SUPPORT
 #define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_NAND_BASE
+#define CONFIG_SPL_NAND_DRIVERS
+#define CONFIG_SPL_NAND_ECC
 #define CONFIG_SPL_POWER_SUPPORT
 #define CONFIG_SPL_LDSCRIPT		"$(CPUDIR)/omap-common/u-boot-spl.lds"

include/configs/cam_enc_4xx.h +3 -0

index 56dc1cb..a7a698c 100644
@@ -219,6 +219,9 @@
 #define CONFIG_SPL_BOARD_INIT
 #define CONFIG_SPL_LIBGENERIC_SUPPORT
 #define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_NAND_BASE
+#define CONFIG_SPL_NAND_DRIVERS
+#define CONFIG_SPL_NAND_ECC
 #define CONFIG_SPL_NAND_SIMPLE
 #define CONFIG_SYS_NAND_HW_ECC_OOBFIRST
 #define CONFIG_SPL_SERIAL_SUPPORT

include/configs/da850evm.h +3 -0

index ddd6155..99b4de7 100644
@@ -227,6 +227,9 @@
 #define CONFIG_SYS_NAND_ECCBYTES	10
 #define CONFIG_SYS_NAND_OOBSIZE		64
 #define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_NAND_BASE
+#define CONFIG_SPL_NAND_DRIVERS
+#define CONFIG_SPL_NAND_ECC
 #define CONFIG_SPL_NAND_SIMPLE
 #define CONFIG_SPL_NAND_LOAD
 #endif

include/configs/devkit8000.h +3 -0

index da3263f..83a8b5d 100644
@@ -316,6 +316,9 @@
 #define CONFIG_SPL_GPIO_SUPPORT
 #define CONFIG_SPL_POWER_SUPPORT
 #define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_NAND_BASE
+#define CONFIG_SPL_NAND_DRIVERS
+#define CONFIG_SPL_NAND_ECC
 #define CONFIG_SPL_MMC_SUPPORT
 #define CONFIG_SPL_FAT_SUPPORT
 #define CONFIG_SPL_LDSCRIPT		"$(CPUDIR)/omap-common/u-boot-spl.lds"

include/configs/hawkboard.h +3 -0

index c0e3ed3..8d27590 100644
@@ -63,6 +63,9 @@
 #define CONFIG_SPL_FRAMEWORK
 #define CONFIG_SPL_BOARD_INIT
 #define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_NAND_BASE
+#define CONFIG_SPL_NAND_DRIVERS
+#define CONFIG_SPL_NAND_ECC
 #define CONFIG_SPL_NAND_SIMPLE
 #define CONFIG_SPL_LIBGENERIC_SUPPORT	/* for udelay and __div64_32 for NAND */
 #define CONFIG_SPL_SERIAL_SUPPORT

include/configs/igep00x0.h +3 -0

index c81ab76..be7937d 100644
@@ -338,6 +338,9 @@
 
 #ifdef CONFIG_BOOT_NAND
 #define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_NAND_BASE
+#define CONFIG_SPL_NAND_DRIVERS
+#define CONFIG_SPL_NAND_ECC
 
 /* NAND boot config */
 #define CONFIG_SYS_NAND_5_ADDR_CYCLE

include/configs/mcx.h +3 -0

index bf49cc1..b5bcba7 100644
@@ -379,6 +379,9 @@
 #define CONFIG_SPL_SERIAL_SUPPORT
 #define CONFIG_SPL_POWER_SUPPORT
 #define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_NAND_BASE
+#define CONFIG_SPL_NAND_DRIVERS
+#define CONFIG_SPL_NAND_ECC
 #define CONFIG_SPL_LDSCRIPT		"$(CPUDIR)/omap-common/u-boot-spl.lds"
 
 #define CONFIG_SPL_TEXT_BASE		0x40200000 /*CONFIG_SYS_SRAM_START*/

include/configs/omap3_beagle.h +3 -0

index 7a3cc16..e6f2f29 100644
@@ -414,6 +414,9 @@
 #define CONFIG_SPL_FAT_SUPPORT
 #define CONFIG_SPL_SERIAL_SUPPORT
 #define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_NAND_BASE
+#define CONFIG_SPL_NAND_DRIVERS
+#define CONFIG_SPL_NAND_ECC
 #define CONFIG_SPL_GPIO_SUPPORT
 #define CONFIG_SPL_POWER_SUPPORT
 #define CONFIG_SPL_OMAP3_ID_NAND

include/configs/omap3_evm.h +3 -0

index f6e4236..b4d925e 100644
@@ -113,6 +113,9 @@
 /* NAND SPL */
 #define CONFIG_SPL_NAND_SIMPLE
 #define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_NAND_BASE
+#define CONFIG_SPL_NAND_DRIVERS
+#define CONFIG_SPL_NAND_ECC
 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
 #define CONFIG_SYS_NAND_PAGE_COUNT	64
 #define CONFIG_SYS_NAND_PAGE_SIZE	2048

include/configs/omap3_evm_quick_nand.h +3 -0

index 362fa1d..8f02584 100644
@@ -81,6 +81,9 @@
  */
 #define CONFIG_SPL_NAND_SIMPLE
 #define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_NAND_BASE
+#define CONFIG_SPL_NAND_DRIVERS
+#define CONFIG_SPL_NAND_ECC
 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
 #define CONFIG_SYS_NAND_PAGE_COUNT	64
 #define CONFIG_SYS_NAND_PAGE_SIZE	2048

include/configs/omap3_overo.h +3 -0

index 626cf7a..fd31c73 100644
@@ -319,6 +319,9 @@
 #define CONFIG_SPL_FAT_SUPPORT
 #define CONFIG_SPL_SERIAL_SUPPORT
 #define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_NAND_BASE
+#define CONFIG_SPL_NAND_DRIVERS
+#define CONFIG_SPL_NAND_ECC
 #define CONFIG_SPL_GPIO_SUPPORT
 #define CONFIG_SPL_POWER_SUPPORT
 #define CONFIG_SPL_LDSCRIPT		"$(CPUDIR)/omap-common/u-boot-spl.lds"

include/configs/tam3517-common.h +3 -0

index dd7757c..fb56a93 100644
@@ -254,6 +254,9 @@
 #define CONFIG_SPL_GPIO_SUPPORT
 #define CONFIG_SPL_POWER_SUPPORT
 #define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_NAND_BASE
+#define CONFIG_SPL_NAND_DRIVERS
+#define CONFIG_SPL_NAND_ECC
 #define CONFIG_SPL_LDSCRIPT		"$(CPUDIR)/omap-common/u-boot-spl.lds"
 
 #define CONFIG_SPL_TEXT_BASE		0x40200000 /*CONFIG_SYS_SRAM_START*/

include/configs/tricorder.h +3 -0

index 5859a73..be0d2ec 100644
@@ -282,6 +282,9 @@
 #define CONFIG_SPL_SERIAL_SUPPORT
 #define CONFIG_SPL_POWER_SUPPORT
 #define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_NAND_BASE
+#define CONFIG_SPL_NAND_DRIVERS
+#define CONFIG_SPL_NAND_ECC
 #define CONFIG_SPL_MMC_SUPPORT
 #define CONFIG_SPL_FAT_SUPPORT
 #define CONFIG_SPL_LDSCRIPT		"$(CPUDIR)/omap-common/u-boot-spl.lds"

Signature · 1 line

1.7.9.5

Scott Wood

author

2012-10-30 02:05 UTC #71 lore raw

PATCH v2 19/22 spl/nand: config symbol documentation

In reply to Scott Wood

Document parameters used for specifying the NAND image to be loaded.

Also fix the definition of CONFIG_SPL_NAND_SIMPLE -- it's only nand_spl_simple.c, not the entire nand directory. The word "simple" is there for a reason. :-)

Signed-off-by Scott Wood <[email protected]>

---
v2: updated for makefile changes earlier in patchset

---
 README                          |   17 ++--
 drivers/mtd/nand/Makefile       |    4 +
 drivers/mtd/nand/fsl_elbc_spl.c |  168 +++++++++++++++++++++++++++++++++++++++
 3 files changed, 183 insertions(+), 6 deletions(-)
 create mode 100644 drivers/mtd/nand/fsl_elbc_spl.c

README +11 -6

index efa19a4..b27c843 100644
@@ -2707,7 +2707,8 @@ FIT uImage format:
 		Include standard software ECC in the SPL
 
 		CONFIG_SPL_NAND_SIMPLE
-		Support for drivers/mtd/nand/libnand.o in SPL binary
+		Support for NAND boot using simple NAND drivers that
+		expose the cmd_ctrl() interface.
 
 		CONFIG_SYS_NAND_5_ADDR_CYCLE, CONFIG_SYS_NAND_PAGE_COUNT,
 		CONFIG_SYS_NAND_PAGE_SIZE, CONFIG_SYS_NAND_OOBSIZE,

@@ -2715,15 +2716,19 @@ FIT uImage format:
 		CONFIG_SYS_NAND_ECCPOS, CONFIG_SYS_NAND_ECCSIZE,
 		CONFIG_SYS_NAND_ECCBYTES
 		Defines the size and behavior of the NAND that SPL uses
-		to read U-Boot with CONFIG_SPL_NAND_SIMPLE
+		to read U-Boot
 
 		CONFIG_SYS_NAND_U_BOOT_OFFS
-		Location in NAND for CONFIG_SPL_NAND_SIMPLE to read U-Boot
-		from.
+		Location in NAND to read U-Boot from
+
+		CONFIG_SYS_NAND_U_BOOT_DST
+		Location in memory to load U-Boot to
+
+		CONFIG_SYS_NAND_U_BOOT_SIZE
+		Size of image to load
 
 		CONFIG_SYS_NAND_U_BOOT_START
-		Location in memory for CONFIG_SPL_NAND_SIMPLE to load U-Boot
-		to.
+		Entry point in loaded image to jump to
 
 		CONFIG_SYS_NAND_HW_ECC_OOBFIRST
 		Define this if you need to first read the OOB and then the

drivers/mtd/nand/Makefile +4 -0

index d8a2dfc..28e52bd 100644
@@ -78,6 +78,10 @@ COBJS-$(CONFIG_TEGRA_NAND) += tegra_nand.o
 COBJS-$(CONFIG_NAND_OMAP_GPMC) += omap_gpmc.o
 COBJS-$(CONFIG_NAND_PLAT) += nand_plat.o
 
+else  # minimal SPL drivers
+
+COBJS-$(CONFIG_NAND_FSL_ELBC) += fsl_elbc_spl.o
+
 endif # drivers
 endif # nand

drivers/mtd/nand/fsl_elbc_spl.c new file +168 -0

168 lines not on this page · raw message

Signature · 1 line

1.7.9.5

Scott Wood

author

2012-10-30 02:05 UTC #72 lore raw

PATCH v2 20/22 powerpc/mpc85xx/p1_p2_rdb_pc: convert from nand_spl to new spl

In reply to Scott Wood

Signed-off-by Scott Wood <[email protected]>

Cc Andy Fleming <[email protected]>

---
 include/configs/p1_p2_rdb_pc.h                    |   54 ++++----
 nand_spl/board/freescale/p1_p2_rdb_pc/Makefile    |  142 ---------------------
 nand_spl/board/freescale/p1_p2_rdb_pc/nand_boot.c |  132 -------------------
 3 files changed, 28 insertions(+), 300 deletions(-)
 delete mode 100644 nand_spl/board/freescale/p1_p2_rdb_pc/Makefile
 delete mode 100644 nand_spl/board/freescale/p1_p2_rdb_pc/nand_boot.c

include/configs/p1_p2_rdb_pc.h +28 ~~-26~~

index 350150b..7af4d93 100644
@@ -140,16 +140,25 @@
 #define CONFIG_RESET_VECTOR_ADDRESS	0x1107fffc
 #endif
 
-#if defined(CONFIG_NAND) && defined(CONFIG_NAND_FSL_ELBC)
-#define CONFIG_NAND_U_BOOT
-#define CONFIG_SYS_EXTRA_ENV_RELOC
-#define CONFIG_SYS_RAMBOOT
-#define CONFIG_SYS_TEXT_BASE_SPL	0xff800000
-#ifdef CONFIG_NAND_SPL
-#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE_SPL
-#else
-#define CONFIG_SYS_TEXT_BASE		0x11001000
-#endif /* CONFIG_NAND_SPL */
+#ifdef CONFIG_NAND
+#define CONFIG_SPL
+#define CONFIG_SPL_INIT_MINIMAL
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_NAND_MINIMAL
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
+
+#define CONFIG_SYS_TEXT_BASE		0x00201000
+#define CONFIG_SPL_TEXT_BASE		0xfffff000
+#define CONFIG_SPL_MAX_SIZE		(4 * 1024)
+#define CONFIG_SPL_RELOC_TEXT_BASE	0x00100000
+#define CONFIG_SPL_RELOC_STACK		0x00100000
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	((512 << 10) + CONFIG_SPL_MAX_SIZE)
+#define CONFIG_SYS_NAND_U_BOOT_DST	(0x00200000 - CONFIG_SPL_MAX_SIZE)
+#define CONFIG_SYS_NAND_U_BOOT_START	0x00200000
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	0
+#define CONFIG_SYS_LDSCRIPT		"arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
 #endif
 
 #ifndef CONFIG_SYS_TEXT_BASE

@@ -161,8 +170,12 @@
 #endif
 
 #ifndef CONFIG_SYS_MONITOR_BASE
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SPL_TEXT_BASE
+#else
 #define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
 #endif
+#endif
 
 /* High Level Configuration Options */
 #define CONFIG_BOOKE

@@ -221,7 +234,7 @@
 
 /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k
        SPL code*/
-#if defined(CONFIG_NAND_SPL)
+#ifdef CONFIG_SPL_BUILD
 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
 #endif

@@ -392,15 +405,6 @@
 #define CONFIG_CMD_NAND
 #define CONFIG_SYS_NAND_BLOCK_SIZE	(16 * 1024)
 
-/* NAND boot: 4K NAND loader config */
-#define CONFIG_SYS_NAND_SPL_SIZE	0x1000
-#define CONFIG_SYS_NAND_U_BOOT_SIZE	((512 << 10) + CONFIG_SYS_NAND_SPL_SIZE)
-#define CONFIG_SYS_NAND_U_BOOT_DST	(0x11000000 - CONFIG_SYS_NAND_SPL_SIZE)
-#define CONFIG_SYS_NAND_U_BOOT_START	0x11000000
-#define CONFIG_SYS_NAND_U_BOOT_OFFS	(0)
-#define CONFIG_SYS_NAND_U_BOOT_RELOC	0x00010000
-#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP	(CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000)
-
 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 	| (2<<BR_DECC_SHIFT)	/* Use HW ECC */ \
 	| BR_PS_8	/* Port Size = 8 bit */ \

@@ -461,7 +465,7 @@
 				 OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \
 				 OR_GPCM_EAD)
 
-#ifdef CONFIG_NAND_U_BOOT
+#ifdef CONFIG_NAND
 #define CONFIG_SYS_BR0_PRELIM	CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */
 #define CONFIG_SYS_OR0_PRELIM	CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 #define CONFIG_SYS_BR1_PRELIM	CONFIG_FLASH_BR_PRELIM	/* NOR Base Address */

@@ -511,7 +515,7 @@
 #define CONFIG_SYS_NS16550_SERIAL
 #define CONFIG_SYS_NS16550_REG_SIZE	1
 #define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
-#ifdef CONFIG_NAND_SPL
+#ifdef CONFIG_SPL_BUILD
 #define CONFIG_NS16550_MIN_FUNCTIONS
 #endif

@@ -709,7 +713,6 @@
 /*
  * Environment
  */
-#ifdef CONFIG_SYS_RAMBOOT
 #ifdef CONFIG_RAMBOOT_SPIFLASH
 #define CONFIG_ENV_IS_IN_SPI_FLASH
 #define CONFIG_ENV_SPI_BUS	0

@@ -724,16 +727,15 @@
 #define CONFIG_FSL_FIXED_MMC_LOCATION
 #define CONFIG_ENV_SIZE		0x2000
 #define CONFIG_SYS_MMC_ENV_DEV	0
-#elif defined(CONFIG_NAND_U_BOOT)
+#elif defined(CONFIG_NAND)
 #define CONFIG_ENV_IS_IN_NAND
 #define CONFIG_ENV_SIZE		CONFIG_SYS_NAND_BLOCK_SIZE
 #define CONFIG_ENV_OFFSET	((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
 #define CONFIG_ENV_RANGE	(3 * CONFIG_ENV_SIZE)
-#else
+#elif defined(CONFIG_SYS_RAMBOOT)
 #define CONFIG_ENV_IS_NOWHERE	/* Store ENV in memory only */
 #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
 #define CONFIG_ENV_SIZE		0x2000
-#endif
 #else
 #define CONFIG_ENV_IS_IN_FLASH
 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000

nand_spl/board/freescale/p1_p2_rdb_pc/Makefile deleted +0 ~~-142~~

142 lines not on this page · raw message

nand_spl/board/freescale/p1_p2_rdb_pc/nand_boot.c deleted +0 ~~-132~~

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Signature · 1 line

1.7.9.5

Scott Wood

author

2012-10-30 02:05 UTC #73 lore raw

PATCH v2 21/22 powerpc/mpc85xx/p1_p2_rdb_pc: clean up memory map

In reply to Scott Wood

- Sort by address, and fix column alignment

- Don't label things as localbus that aren't. Instead, put chipselect info at the end of the description for localbus windows. Note that NAND/NOR have their chipselects swapped when booting from NAND, and CS2 can be either PMC or VSC7385 depending on hwconfig.

- Shrink NAND to the 32K that's actually mapped in the localbus

- Assign an address and size to L2 SRAM. Remove the similarly named but unintelligible "L2 SDRAM(REV.)".

- Remove the untrue comment about L1 stack being mapped with TLB0.

Signed-off-by Scott Wood <[email protected]>

Cc Andy Fleming <[email protected]>

---
 board/freescale/p1_p2_rdb_pc/law.c |    2 +-
 include/configs/p1_p2_rdb_pc.h     |   22 +++++++++-------------
 2 files changed, 10 insertions(+), 14 deletions(-)

board/freescale/p1_p2_rdb_pc/law.c +1 -1

index 0da8300..cb5e7b7 100644
@@ -32,7 +32,7 @@ struct law_entry law_table[] = {
 #endif
 	SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_64M, LAW_TRGT_IF_LBC),
 #ifdef CONFIG_SYS_NAND_BASE_PHYS
-	SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
+	SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_32K, LAW_TRGT_IF_LBC),
 #endif
 };

include/configs/p1_p2_rdb_pc.h +9 ~~-13~~

index 7af4d93..ba7a364 100644
@@ -331,21 +331,17 @@
 /*
  * Memory map
  *
- * 0x0000_0000 0x7fff_ffff	DDR	Up to 2GB cacheable
+ * 0x0000_0000 0x7fff_ffff	DDR		Up to 2GB cacheable
  * 0x8000_0000 0xdfff_ffff	PCI Express Mem	1.5G non-cacheable(PCIe * 3)
+ * 0xec00_0000 0xefff_ffff	NOR flash	Up to 64M non-cacheable	CS0/1
+ * 0xff80_0000 0xff80_7fff	NAND flash	32K non-cacheable	CS1/0
+ * 0xff98_0000 0xff98_ffff	PMC		64K non-cacheable	CS2
+ * 0xffa0_0000 0xffaf_ffff	CPLD		1M non-cacheable	CS3
+ * 0xffb0_0000 0xffbf_ffff	VSC7385 switch  1M non-cacheable	CS2
  * 0xffc0_0000 0xffc3_ffff	PCI IO range	256k non-cacheable
- *
- * Localbus cacheable (TBD)
- * 0xXXXX_XXXX 0xXXXX_XXXX	SRAM	YZ M Cacheable
- *
- * Localbus non-cacheable
- * 0xec00_0000 0xefff_ffff	FLASH	Up to 64M non-cacheable
- * 0xff80_0000 0xff8f_ffff	NAND flash	1M non-cacheable
- * 0xff90_0000 0xff97_ffff	L2 SDRAM(REV.)  512K cacheable(optional)
- * 0xffa0_0000 0xffaf_ffff	CPLD	1M non-cacheable
- * 0xffb0_0000 0xffbf_ffff	VSC7385 switch  1M non-cacheable
- * 0xffd0_0000 0xffd0_3fff	L1 for stack	16K Cacheable TLB0
- * 0xffe0_0000 0xffef_ffff	CCSR	1M non-cacheable
+ * 0xffd0_0000 0xffd0_3fff	L1 for stack	16K cacheable
+ * 0xffd8_0000 0xffdf_ffff	L2 SRAM		Up to 512K cacheable
+ * 0xffe0_0000 0xffef_ffff	CCSR		1M non-cacheable
  */

Signature · 1 line

1.7.9.5

Scott Wood

author

2012-10-30 02:05 UTC #74 lore raw

PATCH v2 22/22 powerpc/mpc85xx/p2020rdb-pca: Use L2 SRAM for SPL boot

In reply to Scott Wood

This allows DDR configuration to be deferred to the final U-Boot image, which is able to make use of SPD data. The SPL itself cannot use SPD due to code size constraints. It previously used fixed register values for DDR configuration, and those values did not work on the p2020rdb-pca board I tested with. It's possible that different revisions of the board require different settings. Using SPD eliminates that problem.

Signed-off-by Scott Wood <[email protected]>

Cc Andy Fleming <[email protected]>

---
 board/freescale/p1_p2_rdb_pc/spl_minimal.c |    5 ++-
 board/freescale/p1_p2_rdb_pc/tlb.c         |   15 ++++++-
 include/configs/p1_p2_rdb_pc.h             |   65 +++++++++++++---------------
 3 files changed, 46 insertions(+), 39 deletions(-)

board/freescale/p1_p2_rdb_pc/spl_minimal.c +4 -1

index 5c893ee..8e2725f 100644
@@ -23,6 +23,7 @@
 #include <ns16550.h>
 #include <asm/io.h>
 #include <nand.h>
+#include <linux/compiler.h>
 #include <asm/fsl_law.h>
 #include <asm/fsl_ddr_sdram.h>
 #include <asm/global_data.h>

@@ -32,7 +33,7 @@ DECLARE_GLOBAL_DATA_PTR;
 /*
  * Fixed sdram init -- doesn't use serial presence detect.
  */
-void sdram_init(void)
+static void __maybe_unused sdram_init(void)
 {
 	ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC85xx_DDR_ADDR;

@@ -101,8 +102,10 @@ void board_init_f(ulong bootflag)
 	__raw_writel(0x00000000, &pgpio->gpdir);
 #endif
 
+#ifndef CONFIG_SYS_INIT_L2_ADDR
 	/* Initialize the DDR3 */
 	sdram_init();
+#endif
 
 	/* copy code to RAM and jump to it - this should not return */
 	/* NOTE - code has to be copied out of NAND buffer before

board/freescale/p1_p2_rdb_pc/tlb.c +13 -2

index 0873dd7..3e4dffd 100644
@@ -95,6 +95,16 @@ struct fsl_e_tlb_entry tlb_table[] = {
 #endif
 
 #if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)
+#ifdef CONFIG_SYS_INIT_L2_ADDR
+	/* L2SRAM */
+	SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 8, BOOKE_PAGESZ_256K, 1),
+	SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000,
+		      CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 12, BOOKE_PAGESZ_256K, 1),
+#else
 	/* *I*G - eSDHC/eSPI/NAND boot */
 	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
 			MAS3_SX|MAS3_SW|MAS3_SR, 0,

@@ -106,8 +116,9 @@ struct fsl_e_tlb_entry tlb_table[] = {
 			CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
 			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 			0, 9, BOOKE_PAGESZ_1G, 1),
-#endif
-#endif
+#endif /* P1020MBG */
+#endif /* not L2 SRAM */
+#endif /* RAMBOOT/SPL */
 };
 
 int num_tlb_entries = ARRAY_SIZE(tlb_table);

include/configs/p1_p2_rdb_pc.h +29 ~~-36~~

137 lines not on this page · raw message

Signature · 1 line

1.7.9.5

Tabi Timur-B04825

2012-10-30 03:17 UTC #75 lore raw

PATCH v2 22/22 powerpc/mpc85xx/p2020rdb-pca: Use L2 SRAM for SPL boot

include/configs/p1_p2_rdb_pc.h line 41

Quoted 9 lines · Scott Wood

include/configs/p1_p2_rdb_pc.h +1 -0

index ba7a364..f02ba2b 100644
@@ -38,6 +38,7 @@
 #define __SW_BOOT_MASK         0x03
 #define __SW_BOOT_NOR          0xe4
 #define __SW_BOOT_SD           0x54
+#define CONFIG_SYS_L2_SIZE     (256 << 10)

Shouldn't this be in config_mpc85xx.h?

Signature · 2 lines

Timur Tabi
Linux kernel developer@Freescale

Scott Wood

author

2012-10-30 23:37 UTC #76 lore raw

PATCH v2 22/22 powerpc/mpc85xx/p2020rdb-pca: Use L2 SRAM for SPL boot

Quoted 5 lines · On 10/29/2012 10:17:20 PM, Tabi Timur-B04825 wrote:

Review
Quoted 1 line · Scott Wood
(quoted diff) +0 -0
b/include/configs/p1_p2_rdb_pc.h

Quoted 10 lines

include/configs/p1_p2_rdb_pc.h line 41
Quoted 8 lines
index ba7a364..f02ba2b 100644
include/configs/p1_p2_rdb_pc.h +1 -0
@@ -38,6 +38,7 @@
 #define __SW_BOOT_MASK         0x03
 #define __SW_BOOT_NOR          0xe4
 #define __SW_BOOT_SD           0x54
+#define CONFIG_SYS_L2_SIZE     (256 << 10)
Shouldn't this be in config_mpc85xx.h?

Ideally yes, but we use the result later in the board-specific config file, so it becomes a depedency mess. We can move it if we start including config_mpc85xx.h from the board config file instead of later on.

-Scott

Scott Wood

author

2012-11-13 22:41 UTC #77 lore raw

PATCH v3 1/1 powerpc/mpc85xx/p2020rdb-pca: Use L2 SRAM for SPL boot

In reply to Scott Wood

Signed-off-by Scott Wood <[email protected]>

Cc Andy Fleming <[email protected]>

---
v3: Fix a build break due to removal of fixed DDR defines -- this was a last minute change in the previous patch, but I thought I had tested it... :-P

v2: new patch in v2 of patchset

 board/freescale/p1_p2_rdb_pc/ddr.c         |    2 +
 board/freescale/p1_p2_rdb_pc/spl_minimal.c |    7 ++-
 board/freescale/p1_p2_rdb_pc/tlb.c         |   15 +++++-
 include/configs/p1_p2_rdb_pc.h             |   69 +++++++++++++---------------
 4 files changed, 54 insertions(+), 39 deletions(-)

board/freescale/p1_p2_rdb_pc/ddr.c +2 -0

index 88ba56f..9355536 100644
@@ -206,6 +206,7 @@ int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
 }
 #endif /* CONFIG_SYS_DDR_RAW_TIMING */
 
+#ifdef CONFIG_SYS_DDR_CS0_BNDS
 /* Fixed sdram init -- doesn't use serial presence detect. */
 phys_size_t fixed_sdram(void)
 {

@@ -260,6 +261,7 @@ phys_size_t fixed_sdram(void)
 
 	return ddr_size;
 }
+#endif
 
 void fsl_ddr_board_options(memctl_options_t *popts,
 				dimm_params_t *pdimm,

board/freescale/p1_p2_rdb_pc/spl_minimal.c +6 -1

index 5c893ee..d48fb01 100644
@@ -23,16 +23,18 @@
 #include <ns16550.h>
 #include <asm/io.h>
 #include <nand.h>
+#include <linux/compiler.h>
 #include <asm/fsl_law.h>
 #include <asm/fsl_ddr_sdram.h>
 #include <asm/global_data.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#ifndef CONFIG_SYS_INIT_L2_ADDR
 /*
  * Fixed sdram init -- doesn't use serial presence detect.
  */
-void sdram_init(void)
+static void sdram_init(void)
 {
 	ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC85xx_DDR_ADDR;

@@ -71,6 +73,7 @@ void sdram_init(void)
 
 	set_next_law(0, CONFIG_SYS_SDRAM_SIZE_LAW, LAW_TRGT_IF_DDR_1);
 }
+#endif
 
 void board_init_f(ulong bootflag)
 {

@@ -101,8 +104,10 @@ void board_init_f(ulong bootflag)
 	__raw_writel(0x00000000, &pgpio->gpdir);
 #endif
 
+#ifndef CONFIG_SYS_INIT_L2_ADDR
 	/* Initialize the DDR3 */
 	sdram_init();
+#endif
 
 	/* copy code to RAM and jump to it - this should not return */
 	/* NOTE - code has to be copied out of NAND buffer before

board/freescale/p1_p2_rdb_pc/tlb.c +13 -2

index 0873dd7..3e4dffd 100644
@@ -95,6 +95,16 @@ struct fsl_e_tlb_entry tlb_table[] = {
 #endif
 
 #if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)
+#ifdef CONFIG_SYS_INIT_L2_ADDR
+	/* L2SRAM */
+	SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 8, BOOKE_PAGESZ_256K, 1),
+	SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000,
+		      CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 12, BOOKE_PAGESZ_256K, 1),
+#else
 	/* *I*G - eSDHC/eSPI/NAND boot */
 	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
 			MAS3_SX|MAS3_SW|MAS3_SR, 0,

@@ -106,8 +116,9 @@ struct fsl_e_tlb_entry tlb_table[] = {
 			CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
 			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 			0, 9, BOOKE_PAGESZ_1G, 1),
-#endif
-#endif
+#endif /* P1020MBG */
+#endif /* not L2 SRAM */
+#endif /* RAMBOOT/SPL */
 };
 
 int num_tlb_entries = ARRAY_SIZE(tlb_table);

include/configs/p1_p2_rdb_pc.h +33 ~~-36~~

141 lines not on this page · raw message

Signature · 1 line

1.7.9.5

Tom Rini

2012-10-30 17:04 UTC #78 lore raw

v2 cover Convert p1_p2_rdb_pc to new spl

In reply to Scott Wood

Quoted 6 lines · Scott Wood

Tested on p2020rdb-pca and p1020rdb-pc.
Jos?? Miguel Gon??alves (1):
Add u-boot-pad.bin target to the Makefile
Scott Wood (21):

[snip]

Quoted 1 line

spl: rename u-boot-pad.bin to u-boot-with-spl.bin

OK, one thing I'm missing is where is PAD_TO being set? I thought when this was talked about before I was saying we should set a soft default of 1 or something so we can re-use this target? Looking at Stefan's mpc5200 SPL series, u-boot-with-spl.bin would be fine there, if there was a default PAD_TO set.

Signature · 8 lines

Tom
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Scott Wood

author

2012-10-30 20:17 UTC #79 lore raw

v2 cover Convert p1_p2_rdb_pc to new spl

Quoted 4 lines · Tom Rini

Quoted 2 lines · Scott Wood
Tested on p2020rdb-pca and p1020rdb-pc.

Quoted 8 lines

Quoted 4 lines
Jos?? Miguel Gon??alves (1):
Add u-boot-pad.bin target to the Makefile
Scott Wood (21):
[snip]
Quoted 1 line
spl: rename u-boot-pad.bin to u-boot-with-spl.bin
OK, one thing I'm missing is where is PAD_TO being set?

It isn't.

Quoted 3 lines

I thought when this was talked about before I was saying we should set a soft default
of 1 or something so we can re-use this target?

Right, I'd forgotten about that. It seems to work though with PAD_TO being empty.

-Scott

Tom Rini

2012-10-30 21:12 UTC #80 lore raw

v2 cover Convert p1_p2_rdb_pc to new spl

Quoted 14 lines · Scott Wood

Quoted 4 lines · Tom Rini
Quoted 2 lines · Scott Wood
Tested on p2020rdb-pca and p1020rdb-pc.
Quoted 8 lines
Quoted 4 lines
Jos?? Miguel Gon??alves (1):
Add u-boot-pad.bin target to the Makefile
Scott Wood (21):
[snip]
Quoted 1 line
spl: rename u-boot-pad.bin to u-boot-with-spl.bin
OK, one thing I'm missing is where is PAD_TO being set?

Quoted 8 lines

It isn't.
Quoted 3 lines
I thought when this was talked about before I was saying we should set a soft default
of 1 or something so we can re-use this target?
Right, I'd forgotten about that. It seems to work though with PAD_TO being empty.

Indeed. Shame on me for not checking that before but a trivial test locally shows that works.

Assuming you have no further comments about Stefan's mpc5200 series I'll pull his in tomorrow'ish, but with a few parts of your series (these two patches, the fixup gcc test one) as well instead of what he has, to try and make things go a little quicker.

Signature · 8 lines

Tom
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Scott Wood

author

2012-11-13 22:42 UTC #81 lore raw

v2 cover Convert p1_p2_rdb_pc to new spl

Quoted 27 lines · Tom Rini

Quoted 14 lines · Scott Wood
Quoted 4 lines · Tom Rini
Quoted 2 lines · Scott Wood
Tested on p2020rdb-pca and p1020rdb-pc.
Quoted 8 lines
Quoted 4 lines
Jos?? Miguel Gon??alves (1):
Add u-boot-pad.bin target to the Makefile
Scott Wood (21):
[snip]
Quoted 1 line
spl: rename u-boot-pad.bin to u-boot-with-spl.bin
OK, one thing I'm missing is where is PAD_TO being set?
Quoted 8 lines
It isn't.
Quoted 3 lines
I thought when this was talked about before I was saying we should set a soft default
of 1 or something so we can re-use this target?
Right, I'd forgotten about that. It seems to work though with PAD_TO being empty.
Indeed. Shame on me for not checking that before but a trivial test locally shows that works.

Quoted 7 lines

Assuming you have no further comments about Stefan's mpc5200 series I'll
pull his in tomorrow'ish, but with a few parts of your series (these two
patches, the fixup gcc test one) as well instead of what he has, to try
and make things go a little quicker.

Were you still going to do this, or should I go ahead and prepare a pull request for my stuff?

-Scott