NAND support for AM33XX

PATCH Superseded Ilya Yanok 2 participants 16 messages Oct 30, 2012 – Nov 5, 2012

Subsystems (3)

Arm (32-bit) Memory technology devices (MTD) NAND flash

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Ilya Yanok

author

2012-10-30 22:47 UTC #0 lore raw

cover NAND support for AM33XX

These series add support for NAND on AM33XX. AM33XX has the same GPMC controller as OMAP3 so the first part of the series just add required defines/initialization to enable the existing omap_gpmc driver to work on AM33XX. The rest of the series adds support for BCH8 error correction code. We use GPMC to generate codes/syndromes and ELM to find the errors.

Ilya Yanok (6):
OMAP: include sys_proto.h from boot-common
am335x_evm: add nand pinmux definition
am33xx: NAND support
am335x_evm: enable NAND support
am33xx_spl_bch: simple SPL nand loader for AM33XX
am335x_evm: enable SPL NAND support

Mansoor Ahamed (2):
am33xx: add ELM support
omap_gpmc: BCH8 support (ELM based)

 arch/arm/cpu/armv7/am33xx/Makefile           |    2 +
 arch/arm/cpu/armv7/am33xx/board.c            |   36 +++
 arch/arm/cpu/armv7/am33xx/clock.c            |   10 +
 arch/arm/cpu/armv7/am33xx/elm.c              |  213 ++++++++++++++
 arch/arm/cpu/armv7/am33xx/mem.c              |  104 +++++++
 arch/arm/cpu/armv7/omap-common/boot-common.c |    1 +
 arch/arm/include/asm/arch-am33xx/cpu.h       |   53 ++++
 arch/arm/include/asm/arch-am33xx/elm.h       |   93 ++++++
 arch/arm/include/asm/arch-am33xx/hardware.h  |    3 +
 arch/arm/include/asm/arch-am33xx/mem.h       |  174 +++++++++++
 arch/arm/include/asm/arch-am33xx/omap_gpmc.h |  130 +++++++++
 arch/arm/include/asm/arch-am33xx/sys_proto.h |    3 +
 board/ti/am335x/mux.c                        |   26 ++
 drivers/mtd/nand/Makefile                    |    1 +
 drivers/mtd/nand/am335x_spl_bch.c            |  238 +++++++++++++++
 drivers/mtd/nand/omap_gpmc.c                 |  403 +++++++++++++++++++++++++-
 include/configs/am335x_evm.h                 |   49 ++++
 17 files changed, 1538 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/cpu/armv7/am33xx/elm.c
 create mode 100644 arch/arm/cpu/armv7/am33xx/mem.c
 create mode 100644 arch/arm/include/asm/arch-am33xx/elm.h
 create mode 100644 arch/arm/include/asm/arch-am33xx/mem.h
 create mode 100644 arch/arm/include/asm/arch-am33xx/omap_gpmc.h
 create mode 100644 drivers/mtd/nand/am335x_spl_bch.c

Signature · 1 line

1.7.10.2 (Apple Git-33)

Ilya Yanok

author

2012-10-30 22:47 UTC #1 lore raw

PATCH 1/8 OMAP: include sys_proto.h from boot-common

Include asm/arch/sys_proto.h for gpmc_init prototype. Without this we get a warning while building for AM335x.

Signed-off-by Ilya Yanok <[email protected]>

---
 arch/arm/cpu/armv7/omap-common/boot-common.c |    1 +
 1 file changed, 1 insertion(+)

arch/arm/cpu/armv7/omap-common/boot-common.c +1 -0

index 0f19141..2b584e0 100644
@@ -21,6 +21,7 @@
 #include <asm/omap_common.h>
 #include <asm/arch/omap.h>
 #include <asm/arch/mmc_host_def.h>
+#include <asm/arch/sys_proto.h>
 
 /*
  * This is used to verify if the configuration header

Signature · 1 line

1.7.10.2 (Apple Git-33)

Ilya Yanok

author

2012-10-30 22:47 UTC #2 lore raw

PATCH 2/8 am335x_evm: add nand pinmux definition

In reply to Ilya Yanok

Add NAND pins mux settings for AM335X devices. Enable NAND pins for AM335X EVM board.

Signed-off-by Ilya Yanok <[email protected]>

---
 board/ti/am335x/mux.c |   26 ++++++++++++++++++++++++++
 1 file changed, 26 insertions(+)

board/ti/am335x/mux.c +26 -0

index 80becd5..a46c680 100644
@@ -362,6 +362,27 @@ static struct module_pin_mux mii1_pin_mux[] = {
 	{-1},
 };
 
+#ifdef CONFIG_NAND_OMAP_GPMC
+static struct module_pin_mux nand_pin_mux[] = {
+	{OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD0 */
+	{OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD1 */
+	{OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD2 */
+	{OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD3 */
+	{OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD4 */
+	{OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD5 */
+	{OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD6 */
+	{OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD7 */
+	{OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */
+	{OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)},	/* NAND_WPN */
+	{OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)},	/* NAND_CS0 */
+	{OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */
+	{OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)},	/* NAND_OE */
+	{OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)},	/* NAND_WEN */
+	{OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)},	/* NAND_BE_CLE */
+	{-1},
+};
+#endif
+
 /*
  * Configure the pin mux for the module
  */

@@ -435,11 +456,16 @@ void enable_board_pin_mux(struct am335x_baseboard_id *header)
 		unsigned short profile = detect_daughter_board_profile();
 		configure_module_pin_mux(rgmii1_pin_mux);
 		configure_module_pin_mux(mmc0_pin_mux);
+#ifdef CONFIG_NAND_OMAP_GPMC
+		configure_module_pin_mux(nand_pin_mux);
+#endif
 		/* In profile #2 i2c1 and spi0 conflict. */
 		if (profile & ~PROFILE_2)
 			configure_module_pin_mux(i2c1_pin_mux);
 		else if (profile == PROFILE_2) {
+#ifndef CONFIG_NAND_OMAP_GPMC
 			configure_module_pin_mux(mmc1_pin_mux);
+#endif
 			configure_module_pin_mux(spi0_pin_mux);
 		}
 	} else if (!strncmp(header->name, "A335X_SK", HDR_NAME_LEN)) {

Signature · 1 line

1.7.10.2 (Apple Git-33)

Tom Rini

2012-10-30 23:45 UTC #3 lore raw

PATCH 2/8 am335x_evm: add nand pinmux definition

-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1

Quoted 4 lines · Ilya Yanok

Add NAND pins mux settings for AM335X devices. Enable NAND pins for AM335X EVM board.
Signed-off-by Ilya Yanok <[email protected]>

[snip]

Quoted 10 lines

(quoted diff) +0 -0
@@ -435,11 +456,16 @@ void enable_board_pin_mux(struct
am335x_baseboard_id *header) unsigned short profile = detect_daughter_board_profile(); configure_module_pin_mux(rgmii1_pin_mux); configure_module_pin_mux(mmc0_pin_mux); +#ifdef
CONFIG_NAND_OMAP_GPMC + configure_module_pin_mux(nand_pin_mux);
+#endif /* In profile #2 i2c1 and spi0 conflict. */ if (profile & ~PROFILE_2) configure_module_pin_mux(i2c1_pin_mux); else if (profile == PROFILE_2) { +#ifndef CONFIG_NAND_OMAP_GPMC configure_module_pin_mux(mmc1_pin_mux); +#endif

Minor problem, NAND just isn't available in PROFILE_2 or PROFILE_3. We should just do the pinmux when we're in anything but those profiles.

- --
Tom

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Ilya Yanok

author

2012-10-30 22:47 UTC #4 lore raw

PATCH 3/8 am33xx: NAND support

In reply to Ilya Yanok

TI AM33XX has the same GPMC controller as OMAP3 so we could just use the existing omap_gpmc driver. This patch adds adds required definitions/intialization.

Signed-off-by Ilya Yanok <[email protected]>

---
 arch/arm/cpu/armv7/am33xx/Makefile           |    1 +
 arch/arm/cpu/armv7/am33xx/board.c            |   34 +++++
 arch/arm/cpu/armv7/am33xx/clock.c            |    5 +
 arch/arm/cpu/armv7/am33xx/mem.c              |  104 +++++++++++++++
 arch/arm/include/asm/arch-am33xx/cpu.h       |   53 ++++++++
 arch/arm/include/asm/arch-am33xx/hardware.h  |    3 +
 arch/arm/include/asm/arch-am33xx/mem.h       |  174 ++++++++++++++++++++++++++
 arch/arm/include/asm/arch-am33xx/omap_gpmc.h |  130 +++++++++++++++++++
 arch/arm/include/asm/arch-am33xx/sys_proto.h |    3 +
 9 files changed, 507 insertions(+)
 create mode 100644 arch/arm/cpu/armv7/am33xx/mem.c
 create mode 100644 arch/arm/include/asm/arch-am33xx/mem.h
 create mode 100644 arch/arm/include/asm/arch-am33xx/omap_gpmc.h

arch/arm/cpu/armv7/am33xx/Makefile +1 -0

index 7768912..c93ac19 100644
@@ -18,6 +18,7 @@ LIB	= $(obj)lib$(SOC).o
 
 COBJS	+= clock.o
 COBJS	+= sys_info.o
+COBJS	+= mem.o
 COBJS	+= ddr.o
 COBJS	+= emif4.o
 COBJS	+= board.o

arch/arm/cpu/armv7/am33xx/board.c +34 -0

index 978b184..71f66ef 100644
@@ -25,6 +25,7 @@
 #include <asm/arch/ddr_defs.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/gpio.h>
+#include <asm/arch/mem.h>
 #include <asm/arch/mmc_host_def.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/io.h>

@@ -220,6 +221,8 @@ int board_init(void)
 
 	gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100;
 
+	gpmc_init();
+
 	return 0;
 }

@@ -298,3 +301,34 @@ int board_eth_init(bd_t *bis)
 	return cpsw_register(&cpsw_data);
 }
 #endif
+
+#if defined(CONFIG_NAND_OMAP_GPMC) & !defined(CONFIG_SPL_BUILD)
+/******************************************************************************
+ * AM33xx specific command to switch between NAND HW and SW ecc
+ *****************************************************************************/
+static int
+do_switch_ecc(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	if (argc != 2)
+		goto usage;
+	if (strncmp(argv[1], "hw", 2) == 0)
+		omap_nand_switch_ecc(1);
+	else if (strncmp(argv[1], "sw", 2) == 0)
+		omap_nand_switch_ecc(0);
+	else
+		goto usage;
+
+	return 0;
+
+usage:
+	printf("Usage: nandecc %s\n", cmdtp->usage);
+	return 1;
+}
+
+U_BOOT_CMD(
+	nandecc, 2, 1,	do_switch_ecc,
+	"switch OMAP3 NAND ECC calculation algorithm",
+	"[bch8/hw/sw] - Switch between NAND hardware (hw) or software (sw) ecc algorithm"
+);
+
+#endif /* CONFIG_NAND_OMAP_GPMC & !CONFIG_SPL_BUILD */

arch/arm/cpu/armv7/am33xx/clock.c +5 -0

index 2b19506..75ec860 100644
@@ -114,6 +114,11 @@ static void enable_per_clocks(void)
 	while (readl(&cmwkup->wkup_uart0ctrl) != PRCM_MOD_EN)
 		;
 
+	/* GPMC */
+	writel(PRCM_MOD_EN, &cmper->gpmcclkctrl);
+	while (readl(&cmper->gpmcclkctrl) != PRCM_MOD_EN)
+		;
+
 	/* MMC0*/
 	writel(PRCM_MOD_EN, &cmper->mmc0clkctrl);
 	while (readl(&cmper->mmc0clkctrl) != PRCM_MOD_EN)

arch/arm/cpu/armv7/am33xx/mem.c new file +104 -0

104 lines not on this page · raw message

arch/arm/include/asm/arch-am33xx/cpu.h +53 -0

59 lines not on this page · raw message

arch/arm/include/asm/arch-am33xx/hardware.h +3 -0

index 62332f2..a7cf66e 100644
@@ -79,6 +79,9 @@
 #define DDRPHY_0_CONFIG_BASE		(CTRL_BASE + 0x1400)
 #define DDRPHY_CONFIG_BASE		DDRPHY_0_CONFIG_BASE
 
+/* GPMC Base address */
+#define GPMC_BASE			0x50000000
+
 /* CPSW Config space */
 #define AM335X_CPSW_BASE		0x4A100000
 #define AM335X_CPSW_MDIO_BASE		0x4A101000

arch/arm/include/asm/arch-am33xx/mem.h new file +174 -0

174 lines not on this page · raw message

arch/arm/include/asm/arch-am33xx/omap_gpmc.h new file +130 -0

130 lines not on this page · raw message

arch/arm/include/asm/arch-am33xx/sys_proto.h +3 -0

index 819ea65..b07ec18 100644
@@ -60,4 +60,7 @@ void ddr_pll_config(unsigned int ddrpll_M);
 void enable_uart0_pin_mux(void);
 void enable_i2c0_pin_mux(void);
 void enable_board_pin_mux(struct am335x_baseboard_id *header);
+void sdelay(unsigned long);
+void gpmc_init(void);
+void omap_nand_switch_ecc(int);
 #endif

Signature · 1 line

1.7.10.2 (Apple Git-33)

Tom Rini

2012-10-30 23:51 UTC #5 lore raw

PATCH 3/8 am33xx: NAND support

-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1

Quoted 3 lines · Ilya Yanok

TI AM33XX has the same GPMC controller as OMAP3 so we could just use the existing omap_gpmc driver. This patch adds adds required definitions/intialization.

[snip]

Quoted 2 lines

--- a/arch/arm/cpu/armv7/am33xx/board.c +++
b/arch/arm/cpu/armv7/am33xx/board.c

[snip]

Quoted 3 lines

+U_BOOT_CMD( + nandecc, 2, 1, do_switch_ecc, + "switch OMAP3 NAND
ECC calculation algorithm", + "[bch8/hw/sw] - Switch between NAND
hardware (hw) or software (sw) ecc algorithm" +);

While useful for testing, I don't want to add this command to am33xx since we don't need it like we do on omap3. We can be consistent and be whole chip BCH8, or later BCH16 (and use the same logic ROM does and Linux does or will).

[snip]

Quoted 2 lines

+++ b/arch/arm/cpu/armv7/am33xx/mem.c +#if defined(CONFIG_CMD_NAND) || defined(CONFIG_CMD_ONENAND)

There will be no ONENAND. ANd please fixup comment style issues that we're copying from omap3.

[snip]

Quoted 3 lines

+++ b/arch/arm/include/asm/arch-am33xx/mem.h +#ifndef __ASSEMBLY__
+enum { + STACKED = 0, + IP_DDR = 1, + COMBO_DDR = 2, + IP_SDR =
3, +}; +#endif /* __ASSEMBLY__ */ + +#define EARLY_INIT 1 +

We don't need that enum I think. We shouldn't need EARLY_INIT either.

Quoted 13 lines

+/* + * GPMC settings - + * Definitions is as per the following format + * #define <PART>_GPMC_CONFIG<x> <value> + * Where: + * PART is the part name e.g. STNOR - Intel Strata Flash + * x is GPMC config registers from 1 to 6 (there will be 6 macros) + * Value is corresponding value + * + * For every valid PRCM configuration there should be only one definition of + * the same. if values are independent of the board, this definition will be + * present in this file if values are dependent on the board, then this should +
* go into corresponding mem-boardName.h file + * + * Currently valid part Names are (PART): + * STNOR - Intel Strata Flash + * SMNAND - Samsung NAND + * MPDB - H4 MPDB board + * SBNOR - Sibley NOR + * MNAND - Micron Large page x16 NAND + * ONNAND - Samsung One NAND + * + * include/configs/file.h contains the defn - for all CS

Quoted 8 lines

we are interested + * #define OMAP34XX_GPMC_CSx PART + * #define OMAP34XX_GPMC_CSx_SIZE Size + * #define OMAP34XX_GPMC_CSx_MAP Map +
* Where: + * x - CS number + * PART - Part Name as defined above +
* SIZE - how big is the mapping to be + * GPMC_SIZE_128M - 0x8 +
* GPMC_SIZE_64M - 0xC + * GPMC_SIZE_32M - 0xE + *
GPMC_SIZE_16M - 0xF + * MAP - Map this CS to which address(GPMC
address space)- Absolute address + * >>24 before being used. +
*/

Lets correct this comment and drop out the GPMC values for chips other than what we have available on the GP EVM. We can add in more later as needed.

[snip]

Quoted 9 lines

+/* GPMC CS configuration for an SMSC LAN9221 ethernet controller
*/ +#define NET_LAN9221_GPMC_CONFIG1 0x00001000 +#define
NET_LAN9221_GPMC_CONFIG2    0x00060700 +#define
NET_LAN9221_GPMC_CONFIG3    0x00020201 +#define
NET_LAN9221_GPMC_CONFIG4    0x06000700 +#define
NET_LAN9221_GPMC_CONFIG5    0x0006090A +#define
NET_LAN9221_GPMC_CONFIG6    0x87030000 +#define
NET_LAN9221_GPMC_CONFIG7    0x00000f6c + +#endif /*
__ASM_ARCH_OMAP_GPMC_H */

Also don't need those, right?

- --
Tom
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Ilya Yanok

author

2012-10-30 22:47 UTC #6 lore raw

PATCH 4/8 am335x_evm: enable NAND support

In reply to Ilya Yanok

Enable NAND support for AM335X boards.

Signed-off-by Ilya Yanok <[email protected]>

---
 include/configs/am335x_evm.h |   15 +++++++++++++++
 1 file changed, 15 insertions(+)

include/configs/am335x_evm.h +15 -0

index 339d4bd..a89cdcd 100644
@@ -254,4 +254,19 @@
 #define CONFIG_PHYLIB
 #define CONFIG_PHY_SMSC
 
+#define CONFIG_NAND
+/* NAND support */
+#ifdef CONFIG_NAND
+#define CONFIG_CMD_NAND
+#define CONFIG_NAND_OMAP_GPMC
+#define GPMC_NAND_ECC_LP_x16_LAYOUT	1
+#define NAND_BASE			(0x08000000)
+#define CONFIG_SYS_NAND_ADDR		NAND_BASE	/* physical address */
+							/* to access nand */
+#define CONFIG_SYS_NAND_BASE		NAND_BASE	/* physical address */
+							/* to access nand at */
+							/* CS0 */
+#define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of NAND */
+#endif							/* devices */
+
 #endif	/* ! __CONFIG_AM335X_EVM_H */

Signature · 1 line

1.7.10.2 (Apple Git-33)

Tom Rini

2012-10-30 23:53 UTC #7 lore raw

PATCH 4/8 am335x_evm: enable NAND support

-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1

Quoted 10 lines · Ilya Yanok

Enable NAND support for AM335X boards.
Signed-off-by Ilya Yanok <[email protected]> ---
include/configs/am335x_evm.h | 15 +++++++++++++++ 1 file changed,
15 insertions(+)
(quoted diff) +0 -0
b/include/configs/am335x_evm.h index 339d4bd..a89cdcd 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h

Review #define CONFIG_PHYLIB #define CONFIG_PHY_SMSC · line 259

Quoted 6 lines

(quoted diff) +3 -0

@@ -254,4 +254,19 @@ #define CONFIG_PHYLIB #define CONFIG_PHY_SMSC
 
+#define CONFIG_NAND +/* NAND support */ +#ifdef CONFIG_NAND 
+#define CONFIG_CMD_NAND +#define CONFIG_NAND_OMAP_GPMC +#define
 GPMC_NAND_ECC_LP_x16_LAYOUT	1 +#define NAND_BASE			(0x08000000) 
+#define CONFIG_SYS_NAND_ADDR		NAND_BASE	/* physical address */ +
 /* to access nand */

This is unused

include/configs/am335x_evm.h line 266

Quoted 1 line

include/configs/am335x_evm.h +1 -0

+#define CONFIG_SYS_NAND_BASE		NAND_BASE	/* physical address */

So just define this to 0x08000000

- --
Tom
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Comment: Using GnuPG with Mozilla - http://www.enigmail.net/

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Ilya Yanok

author

2012-10-30 22:47 UTC #8 lore raw

PATCH 5/8 am33xx: add ELM support

In reply to Ilya Yanok

From: Mansoor Ahamed <[email protected]>

AM33XX has Error Location Module (ELM) that can be used in conjuction with GPMC controller to implement BCH codes fully in hardware. This code is mostly taken from arago tree.

Signed-off-by Mansoor Ahamed <[email protected]>

Signed-off-by Ilya Yanok <[email protected]>

---
 arch/arm/cpu/armv7/am33xx/Makefile     |    1 +
 arch/arm/cpu/armv7/am33xx/clock.c      |    5 +
 arch/arm/cpu/armv7/am33xx/elm.c        |  213 ++++++++++++++++++++++++++++++++
 arch/arm/include/asm/arch-am33xx/elm.h |   93 ++++++++++++++
 4 files changed, 312 insertions(+)
 create mode 100644 arch/arm/cpu/armv7/am33xx/elm.c
 create mode 100644 arch/arm/include/asm/arch-am33xx/elm.h

arch/arm/cpu/armv7/am33xx/Makefile +1 -0

index c93ac19..96d7304 100644
@@ -22,6 +22,7 @@ COBJS	+= mem.o
 COBJS	+= ddr.o
 COBJS	+= emif4.o
 COBJS	+= board.o
+COBJS-${CONFIG_NAND_OMAP_GPMC}	+= elm.o
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS) $(COBJS-y) $(SOBJS))

arch/arm/cpu/armv7/am33xx/clock.c +5 -0

index 75ec860..ec46f0b 100644
@@ -119,6 +119,11 @@ static void enable_per_clocks(void)
 	while (readl(&cmper->gpmcclkctrl) != PRCM_MOD_EN)
 		;
 
+	/* ELM */
+	writel(PRCM_MOD_EN, &cmper->elmclkctrl);
+	while (readl(&cmper->elmclkctrl) != PRCM_MOD_EN)
+		;
+
 	/* MMC0*/
 	writel(PRCM_MOD_EN, &cmper->mmc0clkctrl);
 	while (readl(&cmper->mmc0clkctrl) != PRCM_MOD_EN)

arch/arm/cpu/armv7/am33xx/elm.c new file +213 -0

213 lines not on this page · raw message

arch/arm/include/asm/arch-am33xx/elm.h new file +93 -0

93 lines not on this page · raw message

Signature · 1 line

1.7.10.2 (Apple Git-33)

Tom Rini

2012-10-30 23:54 UTC #9 lore raw

PATCH 5/8 am33xx: add ELM support

-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1

Quoted 17 lines · Ilya Yanok

From: Mansoor Ahamed <[email protected]>
AM33XX has Error Location Module (ELM) that can be used in conjuction with GPMC controller to implement BCH codes fully in hardware. This code is mostly taken from arago tree.
Signed-off-by Mansoor Ahamed <[email protected]>
Signed-off-by Ilya Yanok <[email protected]> ---
arch/arm/cpu/armv7/am33xx/Makefile     |    1 + 
arch/arm/cpu/armv7/am33xx/clock.c      |    5 + 
arch/arm/cpu/armv7/am33xx/elm.c        |  213
++++++++++++++++++++++++++++++++
arch/arm/include/asm/arch-am33xx/elm.h | 93 ++++++++++++++ 4
files changed, 312 insertions(+) create mode 100644 arch/arm/cpu/armv7/am33xx/elm.c create mode 100644 arch/arm/include/asm/arch-am33xx/elm.h

Quoted 6 lines

(quoted diff) +0 -0
b/arch/arm/cpu/armv7/am33xx/Makefile index c93ac19..96d7304 100644 --- a/arch/arm/cpu/armv7/am33xx/Makefile +++
b/arch/arm/cpu/armv7/am33xx/Makefile @@ -22,6 +22,7 @@ COBJS +=
mem.o COBJS += ddr.o COBJS += emif4.o COBJS += board.o
+COBJS-${CONFIG_NAND_OMAP_GPMC} += elm.o

Wrong braces.

- --
Tom

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Ilya Yanok

author

2012-10-30 22:47 UTC #10 lore raw

PATCH 6/8 omap_gpmc: BCH8 support (ELM based)

In reply to Ilya Yanok

From: Mansoor Ahamed <[email protected]>

This patch adds support for BCH8 error correction code to omap_gpmc driver. We use GPMC to generate codes/syndromes but we need ELM to find error locations from given syndrome.

Signed-off-by Mansoor Ahamed <[email protected]>

[ilya: merge it with omap_gpmc driver, some fixes and cleanup]

Signed-off-by Ilya Yanok <[email protected]>

---
 arch/arm/cpu/armv7/am33xx/board.c |    4 +-
 drivers/mtd/nand/omap_gpmc.c      |  403 ++++++++++++++++++++++++++++++++++++-
 2 files changed, 405 insertions(+), 2 deletions(-)

arch/arm/cpu/armv7/am33xx/board.c +3 -1

index 71f66ef..eed0c0a 100644
@@ -311,7 +311,9 @@ do_switch_ecc(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
 	if (argc != 2)
 		goto usage;
-	if (strncmp(argv[1], "hw", 2) == 0)
+	if (strncmp(argv[1], "bch8", 4) == 0)
+		omap_nand_switch_ecc(2);
+	else if (strncmp(argv[1], "hw", 2) == 0)
 		omap_nand_switch_ecc(1);
 	else if (strncmp(argv[1], "sw", 2) == 0)
 		omap_nand_switch_ecc(0);

drivers/mtd/nand/omap_gpmc.c +402 -1

440 lines not on this page · raw message

Signature · 1 line

1.7.10.2 (Apple Git-33)

Ilya Yanok

author

2012-10-30 22:47 UTC #11 lore raw

PATCH 7/8 am33xx_spl_bch: simple SPL nand loader for AM33XX

In reply to Ilya Yanok

AM33XX with BCH8 can't work with nand_spl_simple correctly because custom read_page implementation is required for proper syndrome generation.

This simple driver mostly duplicates nand_spl_simple but has nand_read_page changed to suit our needs.

Signed-off-by Ilya Yanok <[email protected]>

---
 drivers/mtd/nand/Makefile         |    1 +
 drivers/mtd/nand/am335x_spl_bch.c |  238 +++++++++++++++++++++++++++++++++++++
 2 files changed, 239 insertions(+)
 create mode 100644 drivers/mtd/nand/am335x_spl_bch.c

drivers/mtd/nand/Makefile +1 -0

index beb99ca..5322f3a 100644
@@ -30,6 +30,7 @@ ifdef CONFIG_SPL_BUILD
 ifdef CONFIG_SPL_NAND_SIMPLE
 COBJS-y += nand_spl_simple.o
 endif
+COBJS-$(CONFIG_SPL_NAND_AM33XX_BCH) += am335x_spl_bch.o
 ifdef CONFIG_SPL_NAND_LOAD
 COBJS-y	+= nand_spl_load.o
 endif

drivers/mtd/nand/am335x_spl_bch.c new file +238 -0

238 lines not on this page · raw message

Signature · 1 line

1.7.10.2 (Apple Git-33)

Tom Rini

2012-10-31 00:03 UTC #12 lore raw

PATCH 7/8 am33xx_spl_bch: simple SPL nand loader for AM33XX

-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1

Quoted 6 lines · Ilya Yanok

AM33XX with BCH8 can't work with nand_spl_simple correctly because custom read_page implementation is required for proper syndrome generation.
This simple driver mostly duplicates nand_spl_simple but has nand_read_page changed to suit our needs.

[snip]

Quoted 7 lines

(quoted diff) +2 -0
+	for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { 
+		this->ecc.hwctl(&mtd, NAND_ECC_READ); +		nand_command(block,
page, data_pos, NAND_CMD_RNDOUT); + + this->read_buf(&mtd, p,
eccsize); + + nand_command(block, page, oob_pos,
NAND_CMD_RNDOUT); + + this->read_buf(&mtd, oob, eccbytes); +
this->ecc.calculate(&mtd, p, &ecc_calc[i]); + + data_pos +=
eccsize; + oob_pos += eccbytes; + oob += eccbytes; + }

This is where the function differs. If we can't merge things together, I'd like to see about putting just this function into nand_spl_simple.c under CONFIG_SYS_NAND_HW_BCH8 since if I follow what's going on, and I need to play with the code to confirm I do, it's a generic change related to how much more we're reading back out now. But good catch finding what was going wrong with nand_spl_simple here.

- --
Tom
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Ilya Yanok

author

2012-11-03 16:21 UTC #13 lore raw

PATCH 7/8 am33xx_spl_bch: simple SPL nand loader for AM33XX

Hi Tom,

Quoted 9 lines · Tom Rini

Review
Quoted 3 lines
(quoted diff) +2 -0
+     for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
+             this->ecc.hwctl(&mtd, NAND_ECC_READ); +
nand_command(block,
Quoted 5 lines
page, data_pos, NAND_CMD_RNDOUT); + + this->read_buf(&mtd, p,
eccsize); + + nand_command(block, page, oob_pos,
NAND_CMD_RNDOUT); + + this->read_buf(&mtd, oob, eccbytes); +
this->ecc.calculate(&mtd, p, &ecc_calc[i]); + + data_pos +=
eccsize; + oob_pos += eccbytes; + oob += eccbytes; +

Quoted 8 lines

     }
This is where the function differs. If we can't merge things together, I'd like to see about putting just this function into nand_spl_simple.c under CONFIG_SYS_NAND_HW_BCH8 since if I follow what's going on, and I need to play with the code to confirm I do, it's a generic change related to how much more we're reading back out

Not exactly. This change is rather GPMC-specific: we have to read data block then it's ecc code to get the syndrome. And even with GPMC in another configuration we will need another reading order...
I'm not sure if we can do this in some generic way...

Regards, Ilya.

Tom Rini

2012-11-05 16:57 UTC #14 lore raw

PATCH 7/8 am33xx_spl_bch: simple SPL nand loader for AM33XX

Quoted 20 lines · Ilya Yanok

Hi Tom,
Quoted 9 lines · Tom Rini
Review
Quoted 3 lines
(quoted diff) +2 -0
+     for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
+             this->ecc.hwctl(&mtd, NAND_ECC_READ); +
nand_command(block,
Quoted 5 lines
page, data_pos, NAND_CMD_RNDOUT); + + this->read_buf(&mtd, p,
eccsize); + + nand_command(block, page, oob_pos,
NAND_CMD_RNDOUT); + + this->read_buf(&mtd, oob, eccbytes); +
this->ecc.calculate(&mtd, p, &ecc_calc[i]); + + data_pos +=
eccsize; + oob_pos += eccbytes; + oob += eccbytes; +
Quoted 7 lines
     }
This is where the function differs. If we can't merge things together, I'd like to see about putting just this function into nand_spl_simple.c under CONFIG_SYS_NAND_HW_BCH8 since if I follow what's going on, and I need to play with the code to confirm I do, it's a generic change related to how much more we're reading back out

Quoted 4 lines

Not exactly. This change is rather GPMC-specific: we have to read data block then it's ecc code to get the syndrome. And even with GPMC in another configuration we will need another reading order...
I'm not sure if we can do this in some generic way...

OK, lets just leave that part alone for now. Maybe we need to allow for some abstraction or __weak in the SPL read case, but we can revisit this a little later on once we're able to see how say BCH16 behaves too.

Signature · 8 lines

Tom
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Ilya Yanok

author

2012-10-30 22:47 UTC #15 lore raw

PATCH 8/8 am335x_evm: enable SPL NAND support

In reply to Ilya Yanok

Enable booting from NAND support from AM335x boards as well as environment in NAND.

Signed-off-by Ilya Yanok <[email protected]>

---
 include/configs/am335x_evm.h |   38 ++++++++++++++++++++++++++++++++++++--
 1 file changed, 36 insertions(+), 2 deletions(-)

include/configs/am335x_evm.h +36 -2

index a89cdcd..67e99aa 100644
@@ -220,6 +220,35 @@
 #define CONFIG_SPL_ETH_SUPPORT
 #define CONFIG_SPL_LDSCRIPT		"$(CPUDIR)/omap-common/u-boot-spl.lds"
 
+#define CONFIG_SPL_BOARD_INIT
+#define CONFIG_SPL_NAND_AM33XX_BCH
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_PAGE_COUNT	(CONFIG_SYS_NAND_BLOCK_SIZE / \
+					 CONFIG_SYS_NAND_PAGE_SIZE)
+#define CONFIG_SYS_NAND_PAGE_SIZE	2048
+#define CONFIG_SYS_NAND_OOBSIZE		64
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(128*1024)
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS	NAND_LARGE_BADBLOCK_POS
+#define CONFIG_SYS_NAND_ECCPOS		{ 2, 3, 4, 5, 6, 7, 8, 9, \
+					 10, 11, 12, 13, 14, 15, 16, 17, \
+					 18, 19, 20, 21, 22, 23, 24, 25, \
+					 26, 27, 28, 29, 30, 31, 32, 33, \
+					 34, 35, 36, 37, 38, 39, 40, 41, \
+					 42, 43, 44, 45, 46, 47, 48, 49, \
+					 50, 51, 52, 53, 54, 55, 56, 57, }
+
+#define CONFIG_SYS_NAND_ECCSIZE		512
+#define CONFIG_SYS_NAND_ECCBYTES	14
+
+#define CONFIG_SYS_NAND_ECCSTEPS	4
+#define	CONFIG_SYS_NAND_ECCTOTAL	(CONFIG_SYS_NAND_ECCBYTES * \
+						CONFIG_SYS_NAND_ECCSTEPS)
+
+#define	CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE
+
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x80000
+
 /*
  * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
  * 64 bytes before this address should be set aside for u-boot.img's

@@ -266,7 +295,12 @@
 #define CONFIG_SYS_NAND_BASE		NAND_BASE	/* physical address */
 							/* to access nand at */
 							/* CS0 */
-#define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of NAND */
-#endif							/* devices */
+#define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of NAND
+							   devices */
+#undef CONFIG_ENV_IS_NOWHERE
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET		0x260000 /* environment starts here */
+#define CONFIG_SYS_ENV_SECT_SIZE	(128 << 10)	/* 128 KiB */
+#endif
 
 #endif	/* ! __CONFIG_AM335X_EVM_H */

Signature · 1 line

1.7.10.2 (Apple Git-33)