lpc32xx: Add the motor PWM clock

PATCH New Alban Bedel 3 participants 3 messages Nov 7, 2012 – Nov 8, 2012

Subsystems (3)

Arm (32-bit) Arm sub-architectures Arm/LPC32XX SoC support

lore

Share & tools

lore

Alban Bedel

author

2012-11-07 15:47 UTC #0 lore raw

PATCH 1/1 lpc32xx: Add the motor PWM clock

Signed-off-by Alban Bedel <[email protected]>

---
 arch/arm/mach-lpc32xx/clock.c                 |    8 ++++++++
 arch/arm/mach-lpc32xx/include/mach/platform.h |    1 +
 2 files changed, 9 insertions(+), 0 deletions(-)

arch/arm/mach-lpc32xx/clock.c +8 -0

index f48c2e9..dd5d6f5 100644
@@ -585,6 +585,13 @@ static struct clk clk_timer3 = {
 	.enable_mask	= LPC32XX_CLKPWR_TMRPWMCLK_TIMER3_EN,
 	.get_rate	= local_return_parent_rate,
 };
+static struct clk clk_mpwm = {
+	.parent		= &clk_pclk,
+	.enable		= local_onoff_enable,
+	.enable_reg	= LPC32XX_CLKPWR_TIMERS_PWMS_CLK_CTRL_1,
+	.enable_mask	= LPC32XX_CLKPWR_TMRPWMCLK_MPWM_EN,
+	.get_rate	= local_return_parent_rate,
+};
 static struct clk clk_wdt = {
 	.parent		= &clk_pclk,
 	.enable		= local_onoff_enable,

@@ -1202,6 +1209,7 @@ static struct clk_lookup lookups[] = {
 	CLKDEV_INIT("pl08xdmac", NULL, &clk_dma),
 	CLKDEV_INIT("4003c000.watchdog", NULL, &clk_wdt),
 	CLKDEV_INIT("4005c000.pwm", NULL, &clk_pwm),
+	CLKDEV_INIT("400e8000.mpwm", NULL, &clk_mpwm),
 	CLKDEV_INIT(NULL, "uart3_ck", &clk_uart3),
 	CLKDEV_INIT(NULL, "uart4_ck", &clk_uart4),
 	CLKDEV_INIT(NULL, "uart5_ck", &clk_uart5),

arch/arm/mach-lpc32xx/include/mach/platform.h +1 -0

index acc4aab..b5612a1 100644
@@ -515,6 +515,7 @@
 /*
  * clkpwr_timers_pwms_clk_ctrl_1 register definitions
  */
+#define LPC32XX_CLKPWR_TMRPWMCLK_MPWM_EN	0x40
 #define LPC32XX_CLKPWR_TMRPWMCLK_TIMER3_EN	0x20
 #define LPC32XX_CLKPWR_TMRPWMCLK_TIMER2_EN	0x10
 #define LPC32XX_CLKPWR_TMRPWMCLK_TIMER1_EN	0x08

Signature · 1 line

1.7.0.4

Alexandre Pereira da Silva

2012-11-07 15:55 UTC #1 lore raw

PATCH 1/1 lpc32xx: Add the motor PWM clock

Quoted 1 line · Alban Bedel

Signed-off-by Alban Bedel <[email protected]>

Acked-by Alexandre Pereira da Silva <[email protected]>

Quoted 46 lines

---
 arch/arm/mach-lpc32xx/clock.c                 |    8 ++++++++
 arch/arm/mach-lpc32xx/include/mach/platform.h |    1 +
 2 files changed, 9 insertions(+), 0 deletions(-)

arch/arm/mach-lpc32xx/clock.c +8 -0

index f48c2e9..dd5d6f5 100644
@@ -585,6 +585,13 @@ static struct clk clk_timer3 = {
        .enable_mask    = LPC32XX_CLKPWR_TMRPWMCLK_TIMER3_EN,
        .get_rate       = local_return_parent_rate,
 };
+static struct clk clk_mpwm = {
+       .parent         = &clk_pclk,
+       .enable         = local_onoff_enable,
+       .enable_reg     = LPC32XX_CLKPWR_TIMERS_PWMS_CLK_CTRL_1,
+       .enable_mask    = LPC32XX_CLKPWR_TMRPWMCLK_MPWM_EN,
+       .get_rate       = local_return_parent_rate,
+};
 static struct clk clk_wdt = {
        .parent         = &clk_pclk,
        .enable         = local_onoff_enable,

@@ -1202,6 +1209,7 @@ static struct clk_lookup lookups[] = {
        CLKDEV_INIT("pl08xdmac", NULL, &clk_dma),
        CLKDEV_INIT("4003c000.watchdog", NULL, &clk_wdt),
        CLKDEV_INIT("4005c000.pwm", NULL, &clk_pwm),
+       CLKDEV_INIT("400e8000.mpwm", NULL, &clk_mpwm),
        CLKDEV_INIT(NULL, "uart3_ck", &clk_uart3),
        CLKDEV_INIT(NULL, "uart4_ck", &clk_uart4),
        CLKDEV_INIT(NULL, "uart5_ck", &clk_uart5),

arch/arm/mach-lpc32xx/include/mach/platform.h +1 -1

index acc4aab..b5612a1 100644
@@ -515,6 +515,7 @@
 /*
  * clkpwr_timers_pwms_clk_ctrl_1 register definitions
  */
+#define LPC32XX_CLKPWR_TMRPWMCLK_MPWM_EN       0x40
 #define LPC32XX_CLKPWR_TMRPWMCLK_TIMER3_EN     0x20
 #define LPC32XX_CLKPWR_TMRPWMCLK_TIMER2_EN     0x10
 #define LPC32XX_CLKPWR_TMRPWMCLK_TIMER1_EN     0x08
--

1.7.0.4

Roland Stigge

2012-11-08 10:00 UTC #2 lore raw

PATCH 1/1 lpc32xx: Add the motor PWM clock

Quoted 5 lines · Alexandre Pereira da Silva

Quoted 1 line · Alban Bedel
Signed-off-by Alban Bedel <[email protected]>
Acked-by Alexandre Pereira da Silva <[email protected]>

Acked-by Roland Stigge <[email protected]>

I'm adding this to the lpc32xx tree.

Thanks,

Roland

Quoted 47 lines

---
 arch/arm/mach-lpc32xx/clock.c                 |    8 ++++++++
 arch/arm/mach-lpc32xx/include/mach/platform.h |    1 +
 2 files changed, 9 insertions(+), 0 deletions(-)

arch/arm/mach-lpc32xx/clock.c +8 -0

index f48c2e9..dd5d6f5 100644
@@ -585,6 +585,13 @@ static struct clk clk_timer3 = {
        .enable_mask    = LPC32XX_CLKPWR_TMRPWMCLK_TIMER3_EN,
        .get_rate       = local_return_parent_rate,
 };
+static struct clk clk_mpwm = {
+       .parent         = &clk_pclk,
+       .enable         = local_onoff_enable,
+       .enable_reg     = LPC32XX_CLKPWR_TIMERS_PWMS_CLK_CTRL_1,
+       .enable_mask    = LPC32XX_CLKPWR_TMRPWMCLK_MPWM_EN,
+       .get_rate       = local_return_parent_rate,
+};
 static struct clk clk_wdt = {
        .parent         = &clk_pclk,
        .enable         = local_onoff_enable,

@@ -1202,6 +1209,7 @@ static struct clk_lookup lookups[] = {
        CLKDEV_INIT("pl08xdmac", NULL, &clk_dma),
        CLKDEV_INIT("4003c000.watchdog", NULL, &clk_wdt),
        CLKDEV_INIT("4005c000.pwm", NULL, &clk_pwm),
+       CLKDEV_INIT("400e8000.mpwm", NULL, &clk_mpwm),
        CLKDEV_INIT(NULL, "uart3_ck", &clk_uart3),
        CLKDEV_INIT(NULL, "uart4_ck", &clk_uart4),
        CLKDEV_INIT(NULL, "uart5_ck", &clk_uart5),

arch/arm/mach-lpc32xx/include/mach/platform.h +1 -1

index acc4aab..b5612a1 100644
@@ -515,6 +515,7 @@
 /*
  * clkpwr_timers_pwms_clk_ctrl_1 register definitions
  */
+#define LPC32XX_CLKPWR_TMRPWMCLK_MPWM_EN       0x40
 #define LPC32XX_CLKPWR_TMRPWMCLK_TIMER3_EN     0x20
 #define LPC32XX_CLKPWR_TMRPWMCLK_TIMER2_EN     0x10
 #define LPC32XX_CLKPWR_TMRPWMCLK_TIMER1_EN     0x08
--

1.7.0.4