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ARM: tegra: enable data prefetch on L2

PATCH New Joseph Lo 3 participants 5 messages Nov 7, 2012 – Nov 12, 2012

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Arm (32-bit) Arm sub-architectures Tegra architecture support
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Joseph Lo

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#0 lore raw

PATCH 1/1 ARM: tegra: enable data prefetch on L2

Enable the data prefetch on L2. The bit28 in aux ctrl register.

Signed-off-by Joseph Lo <[email protected]>
---
 arch/arm/mach-tegra/common.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)
arch/arm/mach-tegra/common.c +1 -1
index c25746e..c3dee56 100644
@@ -124,7 +124,7 @@ static void __init tegra_init_cache(void)
 
 	cache_type = readl(p + L2X0_CACHE_TYPE);
 	aux_ctrl = (cache_type & 0x700) << (17-8);
-	aux_ctrl |= 0x6C000001;
+	aux_ctrl |= 0x7C000001;
 
 	ret = l2x0_of_init(aux_ctrl, 0x8200c3fe);
 	if (!ret)
Signature · 1 line
1.7.0.4
Applied
#2 lore raw

PATCH 1/1 ARM: tegra: enable data prefetch on L2

In reply to Joseph Lo
Quoted 1 line · Joseph Lo

Enable the data prefetch on L2. The bit28 in aux ctrl register.

Applied to Tegra's for-3.8/soc branch. Thanks.

#3 lore raw

PATCH 1/1 ARM: tegra: enable data prefetch on L2

In reply to Joseph Lo
Quoted 12 lines · Joseph Lo

Enable the data prefetch on L2. The bit28 in aux ctrl register.

Signed-off-by Joseph Lo <[email protected]>
---
 arch/arm/mach-tegra/common.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)
arch/arm/mach-tegra/common.c +0 -0
index c25746e..c3dee56 100644

arch/arm/mach-tegra/common.c static void __init tegra_init_cache(void) · line 127

Quoted 5 lines
arch/arm/mach-tegra/common.c +1 -1
@@ -124,7 +124,7 @@ static void __init tegra_init_cache(void)
 
 	cache_type = readl(p + L2X0_CACHE_TYPE);
 	aux_ctrl = (cache_type & 0x700) << (17-8);
-	aux_ctrl |= 0x6C000001;
+	aux_ctrl |= 0x7C000001;

Just found out that we should also set bit 22 as per
http://www.arm.linux.org.uk/developer/patches/viewpatch.php?id=6395%2F1

Stephen, should I send a seperate patch for that?

Cheers,

Peter.

#4 lore raw

PATCH 1/1 ARM: tegra: enable data prefetch on L2

Quoted 22 lines · Peter De Schrijver
Quoted 12 lines · Joseph Lo

Enable the data prefetch on L2. The bit28 in aux ctrl register.

Signed-off-by Joseph Lo <[email protected]>
---
 arch/arm/mach-tegra/common.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)
arch/arm/mach-tegra/common.c +0 -0
index c25746e..c3dee56 100644

arch/arm/mach-tegra/common.c static void __init tegra_init_cache(void) · line 127

Quoted 5 lines
arch/arm/mach-tegra/common.c +1 -1
@@ -124,7 +124,7 @@ static void __init tegra_init_cache(void)
 
 	cache_type = readl(p + L2X0_CACHE_TYPE);
 	aux_ctrl = (cache_type & 0x700) << (17-8);
-	aux_ctrl |= 0x6C000001;
+	aux_ctrl |= 0x7C000001;

Just found out that we should also set bit 22 as per
http://www.arm.linux.org.uk/developer/patches/viewpatch.php?id=6395%2F1

Quoted 1 line

Stephen, should I send a seperate patch for that?

Yes please; I've applied the patch in this thread already.