SMP support for Armada XP

From: Yehuda Yitschak <[email protected]>

Signed-off-by Yehuda Yitschak <[email protected]>

Signed-off-by Gregory CLEMENT <[email protected]>

---
 arch/arm/mach-mvebu/Kconfig |    2 +-
 arch/arm/mm/Kconfig         |    4 ++++
 arch/arm/mm/proc-v7.S       |   51 +++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 56 insertions(+), 1 deletion(-)

arch/arm/mach-mvebu/Kconfig +1 -1

index 17d246b..9bfaa0c 100644
@@ -22,7 +22,7 @@ config MVEBU_CLK_CPU
 config MACH_ARMADA_370_XP
 	bool
 	select ARMADA_370_XP_TIMER
-	select CPU_V7
+	select CPU_PJ4B
 
 config MACH_ARMADA_370
 	bool "Marvell Armada 370 boards"

arch/arm/mm/Kconfig +4 -0

index 94186b6..3fd629d 100644
@@ -352,6 +352,10 @@ config CPU_PJ4
 	select ARM_THUMBEE
 	select CPU_V7
 
+config CPU_PJ4B
+	bool
+	select CPU_V7
+
 # ARMv6
 config CPU_V6
 	bool "Support ARM V6 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX

arch/arm/mm/proc-v7.S +51 -0

index 846d279..a4c0ccf 100644
@@ -169,6 +169,47 @@ __v7_ca15mp_setup:
 	orreq	r0, r0, r10			@ Enable CPU-specific SMP bits
 	mcreq	p15, 0, r0, c1, c0, 1
 #endif
+
+__v7_pj4b_setup:
+#ifdef CONFIG_CPU_PJ4B
+
+#define SNOOP_DATA    (1 << 25) /* Dont interleave write and snoop data */
+#define CWF           (1 << 27) /* Disable Critical Word First feature */
+#define OUTSANDING_NC (1 << 29) /* Disable outstanding non cacheable request */
+#define L1_REP_RR     (1 << 30) /* L1 replacement - Strict round robin */
+
+#define AUX_DBG_CTRL2 (SNOOP_DATA | CWF | OUTSANDING_NC | L1_REP_RR)
+
+	/* Auxiliary Debug Modes Control 1 Register */
+	mrc	p15, 1,	r0, c15, c1, 1
+	orr     r0, r0, #(1 << 16)     @ Disable data transfer for clean line.
+	orr     r0, r0, #(1 << 5)      @ Enable the back off of STREX instr
+	orr     r0, r0, #(1 << 8)      @ Disable Internal Parity Handling
+	bic	r0, r0, #(1 << 2)      @ Disable Static BP
+	mcr	p15, 1,	r0, c15, c1, 1
+
+	/* Auxiliary Debug Modes Control 2 Register */
+	mrc	p15, 1,	r0, c15, c1, 2
+	bic	r0, r0, #(1 << 23)   @ Enable fast LDR.
+	orr	r0, r0, #AUX_DBG_CTRL2
+	mcr	p15, 1,	r0, c15, c1, 2
+
+	/* Auxiliary Functional Modes Control Register 0 */
+	mrc	p15, 1,	r0, c15, c2, 0
+#ifdef CONFIG_SMP
+	orr	r0, r0, #(1 << 1)     @ Set SMP mode. Join the coherency fabric
+#endif
+	orr	r0, r0, #(1 << 2)     @ Support L1 parity checking
+	orr	r0, r0, #(1 << 8)     @ Broadcast Cache and TLB maintenance
+	mcr	p15, 1,	r0, c15, c2, 0
+
+	/* Auxiliary Debug Modes Control 0 Register */
+	mrc	p15, 1,	r0, c15, c1, 0
+	orr	r0, r0, #(1 << 22)   @ WFI/WFE - serve the DVM and back to idle
+	mcr	p15, 1,	r0, c15, c1, 0
+
+#endif /* CONFIG_CPU_PJ4B */
+
 __v7_setup:
 	adr	r12, __v7_setup_stack		@ the local stack
 	stmia	r12, {r0-r5, r7, r9, r11, lr}

@@ -342,6 +383,16 @@ __v7_ca9mp_proc_info:
 	.long	0xff0ffff0
 	__v7_proc __v7_ca9mp_setup
 	.size	__v7_ca9mp_proc_info, . - __v7_ca9mp_proc_info
+
+	/*
+	 * Marvell PJ4B processor.
+	 */
+	.type   __v7_pj4b_proc_info, #object
+__v7_pj4b_proc_info:
+	.long	0x562f5840
+	.long	0xfffffff0
+	__v7_proc __v7_pj4b_setup
+	.size	__v7_pj4b_proc_info, . - __v7_pj4b_proc_info
 #endif	/* CONFIG_ARM_LPAE */
 
 	/*

Hello Russell,

With the 2 changes I have done on according your comments do you think you can give your acked-by for this patch?

Quoted 108 lines

From: Yehuda Yitschak <[email protected]>

Signed-off-by Yehuda Yitschak <[email protected]>

Signed-off-by Gregory CLEMENT <[email protected]>

---
 arch/arm/mach-mvebu/Kconfig |    2 +-
 arch/arm/mm/Kconfig         |    4 ++++
 arch/arm/mm/proc-v7.S       |   51 +++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 56 insertions(+), 1 deletion(-)

arch/arm/mach-mvebu/Kconfig +1 -1

index 17d246b..9bfaa0c 100644
@@ -22,7 +22,7 @@ config MVEBU_CLK_CPU
 config MACH_ARMADA_370_XP
 	bool
 	select ARMADA_370_XP_TIMER
-	select CPU_V7
+	select CPU_PJ4B
 
 config MACH_ARMADA_370
 	bool "Marvell Armada 370 boards"

arch/arm/mm/Kconfig +4 -0

index 94186b6..3fd629d 100644
@@ -352,6 +352,10 @@ config CPU_PJ4
 	select ARM_THUMBEE
 	select CPU_V7
 
+config CPU_PJ4B
+	bool
+	select CPU_V7
+
 # ARMv6
 config CPU_V6
 	bool "Support ARM V6 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX

arch/arm/mm/proc-v7.S +51 -0

index 846d279..a4c0ccf 100644
@@ -169,6 +169,47 @@ __v7_ca15mp_setup:
 	orreq	r0, r0, r10			@ Enable CPU-specific SMP bits
 	mcreq	p15, 0, r0, c1, c0, 1
 #endif
+
+__v7_pj4b_setup:
+#ifdef CONFIG_CPU_PJ4B
+
+#define SNOOP_DATA    (1 << 25) /* Dont interleave write and snoop data */
+#define CWF           (1 << 27) /* Disable Critical Word First feature */
+#define OUTSANDING_NC (1 << 29) /* Disable outstanding non cacheable request */
+#define L1_REP_RR     (1 << 30) /* L1 replacement - Strict round robin */
+
+#define AUX_DBG_CTRL2 (SNOOP_DATA | CWF | OUTSANDING_NC | L1_REP_RR)
+
+	/* Auxiliary Debug Modes Control 1 Register */
+	mrc	p15, 1,	r0, c15, c1, 1
+	orr     r0, r0, #(1 << 16)     @ Disable data transfer for clean line.
+	orr     r0, r0, #(1 << 5)      @ Enable the back off of STREX instr
+	orr     r0, r0, #(1 << 8)      @ Disable Internal Parity Handling
+	bic	r0, r0, #(1 << 2)      @ Disable Static BP
+	mcr	p15, 1,	r0, c15, c1, 1
+
+	/* Auxiliary Debug Modes Control 2 Register */
+	mrc	p15, 1,	r0, c15, c1, 2
+	bic	r0, r0, #(1 << 23)   @ Enable fast LDR.
+	orr	r0, r0, #AUX_DBG_CTRL2
+	mcr	p15, 1,	r0, c15, c1, 2
+
+	/* Auxiliary Functional Modes Control Register 0 */
+	mrc	p15, 1,	r0, c15, c2, 0
+#ifdef CONFIG_SMP
+	orr	r0, r0, #(1 << 1)     @ Set SMP mode. Join the coherency fabric
+#endif
+	orr	r0, r0, #(1 << 2)     @ Support L1 parity checking
+	orr	r0, r0, #(1 << 8)     @ Broadcast Cache and TLB maintenance
+	mcr	p15, 1,	r0, c15, c2, 0
+
+	/* Auxiliary Debug Modes Control 0 Register */
+	mrc	p15, 1,	r0, c15, c1, 0
+	orr	r0, r0, #(1 << 22)   @ WFI/WFE - serve the DVM and back to idle
+	mcr	p15, 1,	r0, c15, c1, 0
+
+#endif /* CONFIG_CPU_PJ4B */
+
 __v7_setup:
 	adr	r12, __v7_setup_stack		@ the local stack
 	stmia	r12, {r0-r5, r7, r9, r11, lr}

@@ -342,6 +383,16 @@ __v7_ca9mp_proc_info:
 	.long	0xff0ffff0
 	__v7_proc __v7_ca9mp_setup
 	.size	__v7_ca9mp_proc_info, . - __v7_ca9mp_proc_info
+
+	/*
+	 * Marvell PJ4B processor.
+	 */
+	.type   __v7_pj4b_proc_info, #object
+__v7_pj4b_proc_info:
+	.long	0x562f5840
+	.long	0xfffffff0
+	__v7_proc __v7_pj4b_setup
+	.size	__v7_pj4b_proc_info, . - __v7_pj4b_proc_info
 #endif	/* CONFIG_ARM_LPAE */
 
 	/*

Quoted 5 lines · Gregory CLEMENT

Hello Russell,

With the 2 changes I have done on according your comments do you think you can give your acked-by for this patch?

Hello Russell,

I didn't have any feedback from you for this version. If you are fine with this, could you give your Acked-by?

From the looks of things, Russell has his head wrapped around buggy

Quoted 112 lines · Gregory CLEMENT

Quoted 108 lines

From: Yehuda Yitschak <[email protected]>

Signed-off-by Yehuda Yitschak <[email protected]>

Signed-off-by Gregory CLEMENT <[email protected]>

---
 arch/arm/mach-mvebu/Kconfig |    2 +-
 arch/arm/mm/Kconfig         |    4 ++++
 arch/arm/mm/proc-v7.S       |   51 +++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 56 insertions(+), 1 deletion(-)

arch/arm/mach-mvebu/Kconfig +1 -1

index 17d246b..9bfaa0c 100644
@@ -22,7 +22,7 @@ config MVEBU_CLK_CPU
 config MACH_ARMADA_370_XP
 	bool
 	select ARMADA_370_XP_TIMER
-	select CPU_V7
+	select CPU_PJ4B
 
 config MACH_ARMADA_370
 	bool "Marvell Armada 370 boards"

arch/arm/mm/Kconfig +4 -0

index 94186b6..3fd629d 100644
@@ -352,6 +352,10 @@ config CPU_PJ4
 	select ARM_THUMBEE
 	select CPU_V7
 
+config CPU_PJ4B
+	bool
+	select CPU_V7
+
 # ARMv6
 config CPU_V6
 	bool "Support ARM V6 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX

arch/arm/mm/proc-v7.S +51 -0

index 846d279..a4c0ccf 100644
@@ -169,6 +169,47 @@ __v7_ca15mp_setup:
 	orreq	r0, r0, r10			@ Enable CPU-specific SMP bits
 	mcreq	p15, 0, r0, c1, c0, 1
 #endif
+
+__v7_pj4b_setup:
+#ifdef CONFIG_CPU_PJ4B
+
+#define SNOOP_DATA    (1 << 25) /* Dont interleave write and snoop data */
+#define CWF           (1 << 27) /* Disable Critical Word First feature */
+#define OUTSANDING_NC (1 << 29) /* Disable outstanding non cacheable request */
+#define L1_REP_RR     (1 << 30) /* L1 replacement - Strict round robin */
+
+#define AUX_DBG_CTRL2 (SNOOP_DATA | CWF | OUTSANDING_NC | L1_REP_RR)
+
+	/* Auxiliary Debug Modes Control 1 Register */
+	mrc	p15, 1,	r0, c15, c1, 1
+	orr     r0, r0, #(1 << 16)     @ Disable data transfer for clean line.
+	orr     r0, r0, #(1 << 5)      @ Enable the back off of STREX instr
+	orr     r0, r0, #(1 << 8)      @ Disable Internal Parity Handling
+	bic	r0, r0, #(1 << 2)      @ Disable Static BP
+	mcr	p15, 1,	r0, c15, c1, 1
+
+	/* Auxiliary Debug Modes Control 2 Register */
+	mrc	p15, 1,	r0, c15, c1, 2
+	bic	r0, r0, #(1 << 23)   @ Enable fast LDR.
+	orr	r0, r0, #AUX_DBG_CTRL2
+	mcr	p15, 1,	r0, c15, c1, 2
+
+	/* Auxiliary Functional Modes Control Register 0 */
+	mrc	p15, 1,	r0, c15, c2, 0
+#ifdef CONFIG_SMP
+	orr	r0, r0, #(1 << 1)     @ Set SMP mode. Join the coherency fabric
+#endif
+	orr	r0, r0, #(1 << 2)     @ Support L1 parity checking
+	orr	r0, r0, #(1 << 8)     @ Broadcast Cache and TLB maintenance
+	mcr	p15, 1,	r0, c15, c2, 0
+
+	/* Auxiliary Debug Modes Control 0 Register */
+	mrc	p15, 1,	r0, c15, c1, 0
+	orr	r0, r0, #(1 << 22)   @ WFI/WFE - serve the DVM and back to idle
+	mcr	p15, 1,	r0, c15, c1, 0
+
+#endif /* CONFIG_CPU_PJ4B */
+
 __v7_setup:
 	adr	r12, __v7_setup_stack		@ the local stack
 	stmia	r12, {r0-r5, r7, r9, r11, lr}

@@ -342,6 +383,16 @@ __v7_ca9mp_proc_info:
 	.long	0xff0ffff0
 	__v7_proc __v7_ca9mp_setup
 	.size	__v7_ca9mp_proc_info, . - __v7_ca9mp_proc_info
+
+	/*
+	 * Marvell PJ4B processor.
+	 */
+	.type   __v7_pj4b_proc_info, #object
+__v7_pj4b_proc_info:
+	.long	0x562f5840
+	.long	0xfffffff0
+	__v7_proc __v7_pj4b_setup
+	.size	__v7_pj4b_proc_info, . - __v7_pj4b_proc_info
 #endif	/* CONFIG_ARM_LPAE */
 
 	/*

Signature · 9 lines

Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel at lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Quoted 13 lines · Gregory CLEMENT

Quoted 5 lines · Gregory CLEMENT

Hello Russell,

With the 2 changes I have done on according your comments do you think you can give your acked-by for this patch?

Hello Russell,

I didn't have any feedback from you for this version. If you are fine with this, could you give your Acked-by?

Gregory,

From the looks of things, Russell has his head wrapped around buggy sound driver code for the CuBox. Perhaps Will Deacon or Catalin Marinas would care to weigh in? I'm reluctant to take the series without an Acked-By from at least one of them.

Quoted 17 lines · Jason Cooper

Quoted 13 lines · Gregory CLEMENT

Quoted 5 lines · Gregory CLEMENT

Hello Russell,

With the 2 changes I have done on according your comments do you think you can give your acked-by for this patch?

Hello Russell,

I didn't have any feedback from you for this version. If you are fine with this, could you give your Acked-by?

Gregory,

Quoted 4 lines

From the looks of things, Russell has his head wrapped around buggy sound driver code for the CuBox. Perhaps Will Deacon or Catalin Marinas would care to weigh in? I'm reluctant to take the series without an Acked-By from at least one of them.

I am fine with this as Will already have done the review.

Quoted 13 lines · Gregory CLEMENT

Quoted 5 lines · Gregory CLEMENT

Hello Russell,

With the 2 changes I have done on according your comments do you think you can give your acked-by for this patch?

Hello Russell,

I didn't have any feedback from you for this version. If you are fine with this, could you give your Acked-by?

Gregory,

Quoted 1 line

From the looks of things, Russell has his head wrapped around buggy

sound driver code for the CuBox. Perhaps Will Deacon or Catalin Marinas would care to weigh in? I'm reluctant to take the series without an Acked-By from at least one of them.

Quoted 18 lines · Jason Cooper

Quoted 13 lines · Gregory CLEMENT

Quoted 5 lines · Gregory CLEMENT

Hello Russell,

With the 2 changes I have done on according your comments do you think you can give your acked-by for this patch?

Hello Russell,

I didn't have any feedback from you for this version. If you are fine with this, could you give your Acked-by?

Gregory,

Quoted 1 line

From the looks of things, Russell has his head wrapped around buggy

Quoted 3 lines

sound driver code for the CuBox. Perhaps Will Deacon or Catalin Marinas would care to weigh in? I'm reluctant to take the series without an Acked-By from at least one of them.

Well, I would like to say - it should go through my tree, as it's generic ARM changes, and as very little (even generic stuff) seems to come through my tree anymore. But that's going to make the remainder of your patches difficult to merge.

Quoted 18 lines · Jason Cooper

Quoted 13 lines · Gregory CLEMENT

Quoted 5 lines · Gregory CLEMENT

Hello Russell,

With the 2 changes I have done on according your comments do you think you can give your acked-by for this patch?

Hello Russell,

I didn't have any feedback from you for this version. If you are fine with this, could you give your Acked-by?

Gregory,

Quoted 1 line

From the looks of things, Russell has his head wrapped around buggy

Quoted 3 lines

sound driver code for the CuBox. Perhaps Will Deacon or Catalin Marinas would care to weigh in? I'm reluctant to take the series without an Acked-By from at least one of them.

Well, I would like to say - it should go through my tree, as it's generic ARM changes, and as very little (even generic stuff) seems to come through my tree anymore. But that's going to make the remainder of your patches difficult to merge.

arch/arm/mm/proc-v7.S +28 -0

index 846d279..a4c0ccf 100644
@@ -169,6 +169,47 @@ __v7_ca15mp_setup:
        orreq   r0, r0, r10                     @ Enable CPU-specific SMP bits
        mcreq   p15, 0, r0, c1, c0, 1
 #endif
+
+__v7_pj4b_setup:
+#ifdef CONFIG_CPU_PJ4B
+
+#define SNOOP_DATA    (1 << 25) /* Dont interleave write and snoop data */
+#define CWF           (1 << 27) /* Disable Critical Word First feature */
+#define OUTSANDING_NC (1 << 29) /* Disable outstanding non cacheable request */
+#define L1_REP_RR     (1 << 30) /* L1 replacement - Strict round robin */
+
+#define AUX_DBG_CTRL2 (SNOOP_DATA | CWF | OUTSANDING_NC | L1_REP_RR)
+
+       /* Auxiliary Debug Modes Control 1 Register */
+       mrc     p15, 1, r0, c15, c1, 1
+       orr     r0, r0, #(1 << 16)     @ Disable data transfer for clean line.
+       orr     r0, r0, #(1 << 5)      @ Enable the back off of STREX instr
+       orr     r0, r0, #(1 << 8)      @ Disable Internal Parity Handling
+       bic     r0, r0, #(1 << 2)      @ Disable Static BP
+       mcr     p15, 1, r0, c15, c1, 1
+
+       /* Auxiliary Debug Modes Control 2 Register */
+       mrc     p15, 1, r0, c15, c1, 2
+       bic     r0, r0, #(1 << 23)   @ Enable fast LDR.
+       orr     r0, r0, #AUX_DBG_CTRL2
+       mcr     p15, 1, r0, c15, c1, 2
+
+       /* Auxiliary Functional Modes Control Register 0 */
+       mrc     p15, 1, r0, c15, c2, 0
+#ifdef CONFIG_SMP

Hi Gregory,

Quoted 8 lines · Gregory CLEMENT

arch/arm/mm/Kconfig +0 -0

index 94186b6..3fd629d 100644
@@ -352,6 +352,10 @@ config CPU_PJ4
        select ARM_THUMBEE
        select CPU_V7
 

arch/arm/mm/Kconfig config CPU_PJ4 · line 357

Quoted 3 lines

arch/arm/mm/Kconfig +3 -0

+config CPU_PJ4B
+       bool
+       select CPU_V7

With ARMv6 we started just using the generic architecture name for different processors (i.e. CPU_V6, CPU_V7). Is PJ4B another ARMv7 implementation (like Cortex-A9)?

Quoted 44 lines

arch/arm/mm/proc-v7.S +35 -0

index 846d279..a4c0ccf 100644
@@ -169,6 +169,47 @@ __v7_ca15mp_setup:
        orreq   r0, r0, r10                     @ Enable CPU-specific SMP bits
        mcreq   p15, 0, r0, c1, c0, 1
 #endif
+
+__v7_pj4b_setup:
+#ifdef CONFIG_CPU_PJ4B
+
+#define SNOOP_DATA    (1 << 25) /* Dont interleave write and snoop data */
+#define CWF           (1 << 27) /* Disable Critical Word First feature */
+#define OUTSANDING_NC (1 << 29) /* Disable outstanding non cacheable request */
+#define L1_REP_RR     (1 << 30) /* L1 replacement - Strict round robin */
+
+#define AUX_DBG_CTRL2 (SNOOP_DATA | CWF | OUTSANDING_NC | L1_REP_RR)
+
+       /* Auxiliary Debug Modes Control 1 Register */
+       mrc     p15, 1, r0, c15, c1, 1
+       orr     r0, r0, #(1 << 16)     @ Disable data transfer for clean line.
+       orr     r0, r0, #(1 << 5)      @ Enable the back off of STREX instr
+       orr     r0, r0, #(1 << 8)      @ Disable Internal Parity Handling
+       bic     r0, r0, #(1 << 2)      @ Disable Static BP
+       mcr     p15, 1, r0, c15, c1, 1
+
+       /* Auxiliary Debug Modes Control 2 Register */
+       mrc     p15, 1, r0, c15, c1, 2
+       bic     r0, r0, #(1 << 23)   @ Enable fast LDR.
+       orr     r0, r0, #AUX_DBG_CTRL2
+       mcr     p15, 1, r0, c15, c1, 2
+
+       /* Auxiliary Functional Modes Control Register 0 */
+       mrc     p15, 1, r0, c15, c2, 0
+#ifdef CONFIG_SMP
+       orr     r0, r0, #(1 << 1)     @ Set SMP mode. Join the coherency fabric
+#endif
+       orr     r0, r0, #(1 << 2)     @ Support L1 parity checking
+       orr     r0, r0, #(1 << 8)     @ Broadcast Cache and TLB maintenance
+       mcr     p15, 1, r0, c15, c2, 0
+
+       /* Auxiliary Debug Modes Control 0 Register */

arch/arm/mm/proc-v7.S __v7_ca15mp_setup: · line 209

Quoted 3 lines

arch/arm/mm/proc-v7.S +3 -0

+       mrc     p15, 1, r0, c15, c1, 0
+       orr     r0, r0, #(1 << 22)   @ WFI/WFE - serve the DVM and back to idle
+       mcr     p15, 1, r0, c15, c1, 0

Any chance that these could be set by the firmware prior to starting the kernel? We don't have any guidance for Linux here but longer term it seems to cause problems (i.e. you add some secure layer in a new CPU version).

Quoted 26 lines · Catalin Marinas

Quoted 24 lines · Gregory CLEMENT

arch/arm/mm/proc-v7.S +16 -0

index 846d279..a4c0ccf 100644
@@ -169,6 +169,47 @@ __v7_ca15mp_setup:
        orreq   r0, r0, r10                     @ Enable CPU-specific SMP bits
        mcreq   p15, 0, r0, c1, c0, 1
 #endif
+
+__v7_pj4b_setup:
+#ifdef CONFIG_CPU_PJ4B
+
+#define SNOOP_DATA    (1 << 25) /* Dont interleave write and snoop data */
+#define CWF           (1 << 27) /* Disable Critical Word First feature */
+#define OUTSANDING_NC (1 << 29) /* Disable outstanding non cacheable request */
+#define L1_REP_RR     (1 << 30) /* L1 replacement - Strict round robin */
+
+#define AUX_DBG_CTRL2 (SNOOP_DATA | CWF | OUTSANDING_NC | L1_REP_RR)
+
+       /* Auxiliary Debug Modes Control 1 Register */
+       mrc     p15, 1, r0, c15, c1, 1
+       orr     r0, r0, #(1 << 16)     @ Disable data transfer for clean line.
+       orr     r0, r0, #(1 << 5)      @ Enable the back off of STREX instr
+       orr     r0, r0, #(1 << 8)      @ Disable Internal Parity Handling

Quoted 8 lines

arch/arm/mm/proc-v7.S __v7_ca15mp_setup: · line 195

Quoted 8 lines

arch/arm/mm/proc-v7.S +8 -0

+       bic     r0, r0, #(1 << 2)      @ Disable Static BP
+       mcr     p15, 1, r0, c15, c1, 1
+
+       /* Auxiliary Debug Modes Control 2 Register */
+       mrc     p15, 1, r0, c15, c1, 2
+       bic     r0, r0, #(1 << 23)   @ Enable fast LDR.
+       orr     r0, r0, #AUX_DBG_CTRL2
+       mcr     p15, 1, r0, c15, c1, 2

Quoted 11 lines

Quoted 11 lines

arch/arm/mm/proc-v7.S +11 -0

+
+       /* Auxiliary Functional Modes Control Register 0 */
+       mrc     p15, 1, r0, c15, c2, 0
+#ifdef CONFIG_SMP
+       orr     r0, r0, #(1 << 1)     @ Set SMP mode. Join the coherency fabric
+#endif
+       orr     r0, r0, #(1 << 2)     @ Support L1 parity checking
+       orr     r0, r0, #(1 << 8)     @ Broadcast Cache and TLB maintenance
+       mcr     p15, 1, r0, c15, c2, 0
+
+       /* Auxiliary Debug Modes Control 0 Register */

Quoted 8 lines

arch/arm/mm/proc-v7.S __v7_ca15mp_setup: · line 209

Quoted 3 lines

arch/arm/mm/proc-v7.S +3 -0

+       mrc     p15, 1, r0, c15, c1, 0
+       orr     r0, r0, #(1 << 22)   @ WFI/WFE - serve the DVM and back to idle
+       mcr     p15, 1, r0, c15, c1, 0

Any chance that these could be set by the firmware prior to starting the kernel? We don't have any guidance for Linux here but longer term it seems to cause problems (i.e. you add some secure layer in a new CPU version).

I will ask to Marvell engineers.

However I hope it won't be show stopper for merging this code in 3.8. This patch set was released 7 weeks ago, so would have though there was a lot of time to raise the issue related to this code.

Quoted 31 lines · Gregory CLEMENT

Quoted 30 lines · Catalin Marinas

Quoted 28 lines · Gregory CLEMENT

arch/arm/mm/proc-v7.S +20 -0

index 846d279..a4c0ccf 100644
@@ -169,6 +169,47 @@ __v7_ca15mp_setup:
        orreq   r0, r0, r10                     @ Enable CPU-specific SMP bits
        mcreq   p15, 0, r0, c1, c0, 1
 #endif
+
+__v7_pj4b_setup:
+#ifdef CONFIG_CPU_PJ4B
+
+#define SNOOP_DATA    (1 << 25) /* Dont interleave write and snoop data */
+#define CWF           (1 << 27) /* Disable Critical Word First feature */
+#define OUTSANDING_NC (1 << 29) /* Disable outstanding non cacheable request */
+#define L1_REP_RR     (1 << 30) /* L1 replacement - Strict round robin */
+
+#define AUX_DBG_CTRL2 (SNOOP_DATA | CWF | OUTSANDING_NC | L1_REP_RR)
+
+       /* Auxiliary Debug Modes Control 1 Register */
+       mrc     p15, 1, r0, c15, c1, 1
+       orr     r0, r0, #(1 << 16)     @ Disable data transfer for clean line.
+       orr     r0, r0, #(1 << 5)      @ Enable the back off of STREX instr
+       orr     r0, r0, #(1 << 8)      @ Disable Internal Parity Handling
+       bic     r0, r0, #(1 << 2)      @ Disable Static BP
+       mcr     p15, 1, r0, c15, c1, 1
+
+       /* Auxiliary Debug Modes Control 2 Register */

Quoted 4 lines

Quoted 4 lines

arch/arm/mm/proc-v7.S __v7_ca15mp_setup: · line 195

Quoted 4 lines

arch/arm/mm/proc-v7.S +4 -0

+       mrc     p15, 1, r0, c15, c1, 2
+       bic     r0, r0, #(1 << 23)   @ Enable fast LDR.
+       orr     r0, r0, #AUX_DBG_CTRL2
+       mcr     p15, 1, r0, c15, c1, 2

BTW, for some bits you defined macros while others are just immediate values. Just a cosmetic inconsistency (I would have preferred to use either macros or just immediate values).

Quoted 21 lines

Quoted 12 lines

Quoted 12 lines

arch/arm/mm/proc-v7.S +11 -0

+
+       /* Auxiliary Functional Modes Control Register 0 */
+       mrc     p15, 1, r0, c15, c2, 0
+#ifdef CONFIG_SMP
+       orr     r0, r0, #(1 << 1)     @ Set SMP mode. Join the coherency fabric
+#endif
+       orr     r0, r0, #(1 << 2)     @ Support L1 parity checking
+       orr     r0, r0, #(1 << 8)     @ Broadcast Cache and TLB maintenance
+       mcr     p15, 1, r0, c15, c2, 0
+
+       /* Auxiliary Debug Modes Control 0 Register */

Quoted 8 lines

arch/arm/mm/proc-v7.S __v7_ca15mp_setup: · line 209

Quoted 3 lines

arch/arm/mm/proc-v7.S +3 -0

+       mrc     p15, 1, r0, c15, c1, 0
+       orr     r0, r0, #(1 << 22)   @ WFI/WFE - serve the DVM and back to idle
+       mcr     p15, 1, r0, c15, c1, 0

Any chance that these could be set by the firmware prior to starting the kernel? We don't have any guidance for Linux here but longer term it seems to cause problems (i.e. you add some secure layer in a new CPU version).

Quoted 5 lines

I will ask to Marvell engineers.

However I hope it won't be show stopper for merging this code in 3.8. This patch set was released 7 weeks ago, so would have though there was a lot of time to raise the issue related to this code.

It shouldn't prevent the code being merged as we don't have clear requirement in Linux for this. But it would be good practice to push some sane defaults to the firmware. For example you set some option like L1 replacement which is optimal for your platform. Later you put the same CPU on a different SoC which may have different optimal value. There is no way in proc-v7.S to detect the SoC.

Otherwise the patch looks fine to me.

Acked-by Catalin Marinas <[email protected]>

From: Yehuda Yitschak <[email protected]>

1. added smp init functions in platsmp.c
2. added secondary cpu entry point in headsmp.S
3. added hotplog initial support in hotplug.c
4. added SMP support for PJ4B cpu

Signed-off-by Yehuda Yitschak <[email protected]>

Signed-off-by Gregory CLEMENT <[email protected]>

---
 arch/arm/boot/dts/armada-xp.dtsi    |    4 ++
 arch/arm/configs/mvebu_defconfig    |    3 +
 arch/arm/mach-mvebu/Kconfig         |    1 +
 arch/arm/mach-mvebu/Makefile        |    2 +
 arch/arm/mach-mvebu/armada-370-xp.c |    3 +
 arch/arm/mach-mvebu/common.h        |    3 +
 arch/arm/mach-mvebu/headsmp.S       |   66 +++++++++++++++++++
 arch/arm/mach-mvebu/hotplug.c       |   30 +++++++++
 arch/arm/mach-mvebu/platsmp.c       |  124 +++++++++++++++++++++++++++++++++++
 9 files changed, 236 insertions(+)
 create mode 100644 arch/arm/mach-mvebu/headsmp.S
 create mode 100644 arch/arm/mach-mvebu/hotplug.c
 create mode 100644 arch/arm/mach-mvebu/platsmp.c

arch/arm/boot/dts/armada-xp.dtsi +4 -0

index 531619f..7f968dc 100644
@@ -38,24 +38,28 @@
 	    #size-cells = <0>;
 
 	    cpu at 0 {
+		device_type = "cpu";
 	       	compatible = "marvell,sheeva-v7";
 		reg = <0>;
 		clocks = <&cpuclk 0>;
 	    };
 
 	    cpu at 1 {
+		device_type = "cpu";
 		compatible = "marvell,sheeva-v7";
 		reg = <1>;
 		clocks = <&cpuclk 1>;
 	    };
 
 	    cpu at 2 {
+		device_type = "cpu";
 		compatible = "marvell,sheeva-v7";
 		reg = <2>;
 		clocks = <&cpuclk 2>;
 	    };
 
 	    cpu at 3 {
+		device_type = "cpu";
 		compatible = "marvell,sheeva-v7";
 		reg = <3>;
 		clocks = <&cpuclk 3>;

arch/arm/configs/mvebu_defconfig +3 -0

index 3458752..da598d3 100644
@@ -12,6 +12,9 @@ CONFIG_ARCH_MVEBU=y
 CONFIG_MACH_ARMADA_370=y
 CONFIG_MACH_ARMADA_XP=y
 # CONFIG_CACHE_L2X0 is not set
+# CONFIG_SWP_EMULATE is not set
+CONFIG_SMP=y
+# CONFIG_LOCAL_TIMERS is not set
 CONFIG_AEABI=y
 CONFIG_HIGHMEM=y
 # CONFIG_COMPACTION is not set

arch/arm/mach-mvebu/Kconfig +1 -0

index 9bfaa0c..d70afe3 100644
@@ -22,6 +22,7 @@ config MVEBU_CLK_CPU
 config MACH_ARMADA_370_XP
 	bool
 	select ARMADA_370_XP_TIMER
+	select HAVE_SMP
 	select CPU_PJ4B
 
 config MACH_ARMADA_370

arch/arm/mach-mvebu/Makefile +2 -0

index 8e6e50b..eb3cbd1 100644
@@ -3,3 +3,5 @@ ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include \
 
 obj-y += system-controller.o
 obj-$(CONFIG_MACH_ARMADA_370_XP) += armada-370-xp.o irq-armada-370-xp.o addr-map.o coherency.o pmsu.o
+obj-$(CONFIG_SMP)                += platsmp.o headsmp.o
+obj-$(CONFIG_HOTPLUG_CPU)        += hotplug.o

arch/arm/mach-mvebu/armada-370-xp.c +3 -0

index 2af6ce5..66befa1 100644
@@ -22,6 +22,7 @@
 #include <asm/mach/time.h>
 #include "armada-370-xp.h"
 #include "common.h"
+#include "coherency.h"
 
 static struct map_desc armada_370_xp_io_desc[] __initdata = {
 	{

@@ -50,6 +51,7 @@ struct sys_timer armada_370_xp_timer = {
 static void __init armada_370_xp_dt_init(void)
 {
 	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+	coherency_init();
 }
 
 static const char * const armada_370_xp_dt_board_dt_compat[] = {

@@ -59,6 +61,7 @@ static const char * const armada_370_xp_dt_board_dt_compat[] = {
 };
 
 DT_MACHINE_START(ARMADA_XP_DT, "Marvell Aramada 370/XP (Device Tree)")
+	.smp		= smp_ops(armada_xp_smp_ops),
 	.init_machine	= armada_370_xp_dt_init,
 	.map_io		= armada_370_xp_map_io,
 	.init_irq	= armada_370_xp_init_irq,

arch/arm/mach-mvebu/common.h +3 -0

index 74ee0b2..86484bb 100644
@@ -21,7 +21,10 @@ void mvebu_clocks_init(void);
 void armada_370_xp_init_irq(void);
 void armada_370_xp_handle_irq(struct pt_regs *regs);
 
+void armada_xp_cpu_die(unsigned int cpu);
 
 int armada_370_xp_coherency_init(void);
 int armada_370_xp_pmsu_init(void);
+void armada_xp_secondary_startup(void);
+extern struct smp_operations armada_xp_smp_ops;
 #endif

arch/arm/mach-mvebu/headsmp.S new file +66 -0

new file mode 100644
index 0000000..33db1d5
@@ -0,0 +1,66 @@
+/*
+ * SMP support: Entry point for secondary CPUs
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Yehuda Yitschak <[email protected]>
+ * Gregory CLEMENT <[email protected]>
+ * Thomas Petazzoni <[email protected]>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ *
+ * This file implements the assembly entry point for secondary CPUs
+ * in an SMP kernel. The only thing we need to do is to add the CPU
+ * to the coherency fabric by writing to 2 registers. Currently these
+ * register addresses are hard coded due to the early initialisation problems.
+ */
+
+#include <linux/linkage.h>
+#include <linux/init.h>
+
+/*
+ * At this stage the secondary CPUs don't have acces yet to the MMU, so
+ * we have to provide physical addresses
+ */
+#define ARMADA_XP_COHERENCY_FABRIC_CTL_REG 0xD0020200
+#define ARMADA_XP_COHERENCY_FABRIC_CFG_REG 0xD0020204
+
+	__INIT
+
+/*
+ * Armada XP specific entry point for secondary CPUs.
+ * We add the CPU to the coherency fabric and then jump to secondary
+ * startup
+ */
+
+ENTRY(armada_xp_secondary_startup)
+
+	/* Read CPU id */
+ 	mrc     p15, 0, r1, c0, c0, 5
+	and     r1, r1, #0xF
+
+	/* Add CPU to coherency fabric */
+
+	/* Create bit by cpu index */
+	mov     r2,r1
+	add     r2,r2,#24
+	mov     r3, #1
+	lsl     r3, r3, r2
+
+	/* Add CPU to SMP group - Atomic */
+	ldr     r0, = ARMADA_XP_COHERENCY_FABRIC_CTL_REG
+	ldr     r10, [r0]
+	orr     r10 , r10, r3
+	str	r10,[r0]
+
+	/* Enable coherency on CPU - Atomic*/
+	ldr     r0, = ARMADA_XP_COHERENCY_FABRIC_CFG_REG
+	ldr     r10, [r0]
+	orr     r10 , r10, r3
+	str     r10,[r0]
+
+	b	secondary_startup
+
+ENDPROC(armada_xp_secondary_startup)

arch/arm/mach-mvebu/hotplug.c new file +30 -0

new file mode 100644
index 0000000..b228b6a
@@ -0,0 +1,30 @@
+/*
+ * Symmetric Multi Processing (SMP) support for Armada XP
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Lior Amsalem <[email protected]>
+ * Gregory CLEMENT <[email protected]>
+ * Thomas Petazzoni <[email protected]>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/smp.h>
+#include <asm/proc-fns.h>
+
+/*
+ * platform-specific code to shutdown a CPU
+ *
+ * Called with IRQs disabled
+ */
+void __ref armada_xp_cpu_die(unsigned int cpu)
+{
+	cpu_do_idle();
+
+	/* We should never return from idle */
+	panic("mvebu: cpu %d unexpectedly exit from shutdown\n", cpu);
+}

arch/arm/mach-mvebu/platsmp.c new file +75 -0

new file mode 100644
index 0000000..1cd6c08
@@ -0,0 +1,124 @@
+/*
+ * Symmetric Multi Processing (SMP) support for Armada XP
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Lior Amsalem <[email protected]>
+ * Yehuda Yitschak <[email protected]>
+ * Gregory CLEMENT <[email protected]>
+ * Thomas Petazzoni <[email protected]>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ *
+ * The Armada XP SoC has 4 ARMv7 PJ4B CPUs running in full HW coherency
+ * This file implements the routines for preparing the SMP infrastructure
+ * and waking up the secondary CPUs
+ */
+
+#include <linux/init.h>
+#include <linux/smp.h>
+#include <linux/clk.h>
+#include <linux/of.h>
+#include <asm/cacheflush.h>
+#include <asm/smp_plat.h>
+#include "common.h"
+#include "armada-370-xp.h"
+#include "pmsu.h"
+#include "coherency.h"
+
+void __init set_secondary_cpus_clock(void)
+{
+	int cpu;
+	unsigned long rate;
+	struct clk *cpu_clk = NULL;
+	struct device_node *np = NULL;
+
+	cpu = smp_processor_id();
+	np = of_find_node_by_type(np, "cpu");
+	np = NULL;
+	while ((np = of_find_node_by_type(np, "cpu"))) {
+		const u32 *reg;
+		int len;
+		reg = of_get_property(np, "reg", &len);
+		if (!reg || len != 4) {
+			pr_err("%s missing reg property\n", np->full_name);
+			continue;
+		}
+		if (be32_to_cpup(reg) == cpu) {
+			cpu_clk = of_clk_get(np, 0);
+			break;
+		}
+	}
+	WARN_ON(IS_ERR(cpu_clk));
+	clk_prepare_enable(cpu_clk);
+	rate = clk_get_rate(cpu_clk);
+
+	/* set all the other CPU clk to the same rate than the boot CPU */
+	np = NULL;
+	while ((np = of_find_node_by_type(np, "cpu"))) {
+		const u32 *reg;
+		int len;
+		reg = of_get_property(np, "reg", &len);
+		if (!reg || len != 4) {
+			pr_err("%s missing reg property\n", np->full_name);
+			continue;
+		}
+		if (be32_to_cpup(reg) != cpu) {
+			cpu_clk = of_clk_get(np, 0);
+			clk_set_rate(cpu_clk, rate);
+		}
+	}
+}
+
+static void __cpuinit armada_xp_secondary_init(unsigned int cpu)

Quoted 339 lines · Gregory CLEMENT

From: Yehuda Yitschak <[email protected]>

1. added smp init functions in platsmp.c
2. added secondary cpu entry point in headsmp.S
3. added hotplog initial support in hotplug.c
4. added SMP support for PJ4B cpu

Signed-off-by Yehuda Yitschak <[email protected]>

Signed-off-by Gregory CLEMENT <[email protected]>

---
arch/arm/boot/dts/armada-xp.dtsi | 4 ++
arch/arm/configs/mvebu_defconfig | 3 +
arch/arm/mach-mvebu/Kconfig | 1 +
arch/arm/mach-mvebu/Makefile | 2 +
arch/arm/mach-mvebu/armada-370-xp.c | 3 +
arch/arm/mach-mvebu/common.h | 3 +

arch/arm/mach-mvebu/headsmp.S | 66 +++++++++++++++++++
arch/arm/mach-mvebu/hotplug.c | 30 +++++++++
arch/arm/mach-mvebu/platsmp.c | 124 +++++++++++++++++++++++++++++++++++
9 files changed, 236 insertions(+)

create mode 100644 arch/arm/mach-mvebu/headsmp.S
create mode 100644 arch/arm/mach-mvebu/hotplug.c
create mode 100644 arch/arm/mach-mvebu/platsmp.c

arch/arm/boot/dts/armada-xp.dtsi +4 -0

index 531619f..7f968dc 100644
@@ -38,24 +38,28 @@
 #size-cells = <0>;
 
 cpu at 0 {
+ device_type = "cpu";
 compatible = "marvell,sheeva-v7";
 reg = <0>;
 clocks = <&cpuclk 0>;
 };
 
 cpu at 1 {
+ device_type = "cpu";
 compatible = "marvell,sheeva-v7";
 reg = <1>;
 clocks = <&cpuclk 1>;
 };
 
 cpu at 2 {
+ device_type = "cpu";
 compatible = "marvell,sheeva-v7";
 reg = <2>;
 clocks = <&cpuclk 2>;
 };
 
 cpu at 3 {
+ device_type = "cpu";
 compatible = "marvell,sheeva-v7";
 reg = <3>;
 clocks = <&cpuclk 3>;

arch/arm/configs/mvebu_defconfig +0 -0

index 3458752..da598d3 100644
@@ -12,6 +12,9 @@ CONFIG_ARCH_MVEBU=y

CONFIG_MACH_ARMADA_370=y
CONFIG_MACH_ARMADA_XP=y
# CONFIG_CACHE_L2X0 is not set

arch/arm/configs/mvebu_defconfig +3 -0

+# CONFIG_SWP_EMULATE is not set
+CONFIG_SMP=y
+# CONFIG_LOCAL_TIMERS is not set

CONFIG_AEABI=y
CONFIG_HIGHMEM=y
# CONFIG_COMPACTION is not set

arch/arm/mach-mvebu/Kconfig +0 -0

index 9bfaa0c..d70afe3 100644
@@ -22,6 +22,7 @@ config MVEBU_CLK_CPU

config MACH_ARMADA_370_XP
bool
select ARMADA_370_XP_TIMER
+ select HAVE_SMP
select CPU_PJ4B

config MACH_ARMADA_370

arch/arm/mach-mvebu/Makefile +0 -1

index 8e6e50b..eb3cbd1 100644
@@ -3,3 +3,5 @@ ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := 
-I$(srctree)/$(src)/include \
 

obj-y += system-controller.o obj-$(CONFIG_MACH_ARMADA_370_XP) += armada-370-xp.o irq-armada-370-xp.o addr-map.o coherency.o pmsu.o

arch/arm/mach-mvebu/Makefile +2 -0

+obj-$(CONFIG_SMP) += platsmp.o headsmp.o
+obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o

arch/arm/mach-mvebu/armada-370-xp.c +3 -0

index 2af6ce5..66befa1 100644
@@ -22,6 +22,7 @@
 #include <asm/mach/time.h>
 #include "armada-370-xp.h"
 #include "common.h"
+#include "coherency.h"
 
 static struct map_desc armada_370_xp_io_desc[] __initdata = {
 {

@@ -50,6 +51,7 @@ struct sys_timer armada_370_xp_timer = {
 static void __init armada_370_xp_dt_init(void)
 {
 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+ coherency_init();
 }
 
 static const char * const armada_370_xp_dt_board_dt_compat[] = {

@@ -59,6 +61,7 @@ static const char * const 
 armada_370_xp_dt_board_dt_compat[] = {
 };
 
 DT_MACHINE_START(ARMADA_XP_DT, "Marvell Aramada 370/XP (Device Tree)")
+ .smp = smp_ops(armada_xp_smp_ops),
 .init_machine = armada_370_xp_dt_init,
 .map_io = armada_370_xp_map_io,

.init_irq = armada_370_xp_init_irq,

arch/arm/mach-mvebu/common.h +3 -0

index 74ee0b2..86484bb 100644
@@ -21,7 +21,10 @@ void mvebu_clocks_init(void);
 void armada_370_xp_init_irq(void);
 void armada_370_xp_handle_irq(struct pt_regs *regs);
 
+void armada_xp_cpu_die(unsigned int cpu);
 
 int armada_370_xp_coherency_init(void);
 int armada_370_xp_pmsu_init(void);
+void armada_xp_secondary_startup(void);
+extern struct smp_operations armada_xp_smp_ops;
 #endif

arch/arm/mach-mvebu/headsmp.S new file +17 -0

new file mode 100644
index 0000000..33db1d5
@@ -0,0 +1,66 @@
+/*
+ * SMP support: Entry point for secondary CPUs
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Yehuda Yitschak <[email protected]>
+ * Gregory CLEMENT <[email protected]>
+ * Thomas Petazzoni <[email protected]>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ *
+ * This file implements the assembly entry point for secondary CPUs
+ * in an SMP kernel. The only thing we need to do is to add the CPU
+ * to the coherency fabric by writing to 2 registers. Currently these
+ * register addresses are hard coded due to the early initialisation 

problems.
+ */

arch/arm/mach-mvebu/headsmp.S new file +48 -0

+
+#include <linux/linkage.h>
+#include <linux/init.h>
+
+/*
+ * At this stage the secondary CPUs don't have acces yet to the MMU, so
+ * we have to provide physical addresses
+ */
+#define ARMADA_XP_COHERENCY_FABRIC_CTL_REG 0xD0020200
+#define ARMADA_XP_COHERENCY_FABRIC_CFG_REG 0xD0020204
+
+ __INIT
+
+/*
+ * Armada XP specific entry point for secondary CPUs.
+ * We add the CPU to the coherency fabric and then jump to secondary
+ * startup
+ */
+
+ENTRY(armada_xp_secondary_startup)
+
+ /* Read CPU id */
+ mrc p15, 0, r1, c0, c0, 5
+ and r1, r1, #0xF
+
+ /* Add CPU to coherency fabric */
+
+ /* Create bit by cpu index */
+ mov r2,r1
+ add r2,r2,#24
+ mov r3, #1
+ lsl r3, r3, r2
+
+ /* Add CPU to SMP group - Atomic */
+ ldr r0, = ARMADA_XP_COHERENCY_FABRIC_CTL_REG
+ ldr r10, [r0]
+ orr r10 , r10, r3
+ str r10,[r0]
+
+ /* Enable coherency on CPU - Atomic*/
+ ldr r0, = ARMADA_XP_COHERENCY_FABRIC_CFG_REG
+ ldr r10, [r0]
+ orr r10 , r10, r3
+ str r10,[r0]
+
+ b secondary_startup
+
+ENDPROC(armada_xp_secondary_startup)

arch/arm/mach-mvebu/hotplug.c new file +30 -0

new file mode 100644
index 0000000..b228b6a
@@ -0,0 +1,30 @@
+/*
+ * Symmetric Multi Processing (SMP) support for Armada XP
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Lior Amsalem <[email protected]>
+ * Gregory CLEMENT <[email protected]>
+ * Thomas Petazzoni <[email protected]>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/smp.h>
+#include <asm/proc-fns.h>
+
+/*
+ * platform-specific code to shutdown a CPU
+ *
+ * Called with IRQs disabled
+ */
+void __ref armada_xp_cpu_die(unsigned int cpu)
+{
+ cpu_do_idle();
+
+ /* We should never return from idle */
+ panic("mvebu: cpu %d unexpectedly exit from shutdown\n", cpu);
+}

arch/arm/mach-mvebu/platsmp.c new file +16 -0

new file mode 100644
index 0000000..1cd6c08
@@ -0,0 +1,124 @@
+/*
+ * Symmetric Multi Processing (SMP) support for Armada XP
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Lior Amsalem <[email protected]>
+ * Yehuda Yitschak <[email protected]>
+ * Gregory CLEMENT <[email protected]>
+ * Thomas Petazzoni <[email protected]>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ *
+ * The Armada XP SoC has 4 ARMv7 PJ4B CPUs running in full HW coherency
+ * This file implements the routines for preparing the SMP 

infrastructure
+ * and waking up the secondary CPUs
+ */

arch/arm/mach-mvebu/platsmp.c new file +60 -0

+
+#include <linux/init.h>
+#include <linux/smp.h>
+#include <linux/clk.h>
+#include <linux/of.h>
+#include <asm/cacheflush.h>
+#include <asm/smp_plat.h>
+#include "common.h"
+#include "armada-370-xp.h"
+#include "pmsu.h"
+#include "coherency.h"
+
+void __init set_secondary_cpus_clock(void)
+{
+ int cpu;
+ unsigned long rate;
+ struct clk *cpu_clk = NULL;
+ struct device_node *np = NULL;
+
+ cpu = smp_processor_id();
+ np = of_find_node_by_type(np, "cpu");
+ np = NULL;
+ while ((np = of_find_node_by_type(np, "cpu"))) {
+ const u32 *reg;
+ int len;
+ reg = of_get_property(np, "reg", &len);
+ if (!reg || len != 4) {
+ pr_err("%s missing reg property\n", np->full_name);
+ continue;
+ }
+ if (be32_to_cpup(reg) == cpu) {
+ cpu_clk = of_clk_get(np, 0);
+ break;
+ }
+ }
+ WARN_ON(IS_ERR(cpu_clk));
+ clk_prepare_enable(cpu_clk);
+ rate = clk_get_rate(cpu_clk);
+
+ /* set all the other CPU clk to the same rate than the boot CPU */
+ np = NULL;
+ while ((np = of_find_node_by_type(np, "cpu"))) {
+ const u32 *reg;
+ int len;
+ reg = of_get_property(np, "reg", &len);
+ if (!reg || len != 4) {
+ pr_err("%s missing reg property\n", np->full_name);
+ continue;
+ }
+ if (be32_to_cpup(reg) != cpu) {
+ cpu_clk = of_clk_get(np, 0);
+ clk_set_rate(cpu_clk, rate);
+ }
+ }
+}
+
+static void __cpuinit armada_xp_secondary_init(unsigned int cpu)
+{
+ armada_xp_mpic_smp_cpu_init();
+}

arch/arm/mach-mvebu/platsmp.c line 85

Quoted 7 lines

arch/arm/mach-mvebu/platsmp.c new file +7 -0

+
+static int __cpuinit armada_xp_boot_secondary(unsigned int cpu,
+ struct task_struct *idle)
+{
+ pr_info("Booting CPU %d\n", cpu);
+
+ armada_xp_boot_cpu(cpu, armada_xp_secondary_startup);

Where is this function implemented?

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Hello,

The purpose of this patch set is to add the SMP support for the Armada XP SoCs. Beside the SMP support itself brought by the last 3 patches, this patch set also adds the support for the coherency fabric unit and

Sorry for asking a question. Does it support CPU HOTPLUG? I am just testing the marvell 2012_Q4.1, and found the CPU HOTPLUG (echo 0|1 > /sys/devices/system/cpu/cpu1/online) doesn't work on the XP_GP board, does your BSP have the same problem?

Regards,
Hui.

Quoted 6 lines · Gregory CLEMENT

Hello,

The purpose of this patch set is to add the SMP support for the Armada XP SoCs. Beside the SMP support itself brought by the last 3 patches, this patch set also adds the support for the coherency fabric unit and

Hello Hui,

Quoted 6 lines · Hui Wang

Sorry for asking a question. Does it support CPU HOTPLUG? I am just testing the marvell 2012_Q4.1, and found the CPU HOTPLUG (echo 0|1 > /sys/devices/system/cpu/cpu1/online) doesn't work on the XP_GP board, does your BSP have the same problem?

Indeed, we don't support it yet, but we plan to add this feature once this "basic" support will be included in the 3.8.

Quoted 12 lines

Regards,
Hui.

Quoted 7 lines · Gregory CLEMENT

Hello,

The purpose of this patch set is to add the SMP support for the Armada XP SoCs. Beside the SMP support itself brought by the last 3 patches, this patch set also adds the support for the coherency fabric unit and