Add basic support for Allwinner A1X SoCs

+#define TIMER_CLKSRC 24000000

drivers/clocksource/sunxi_timer.c new file +4 -0

+	/* Enable timer0 interrupt */
+	val = readl(timer_base + TIMER_CTL_REG);
+	writel(val | TIMER_CTL_ENABLE, timer_base + TIMER_CTL_REG);
+

drivers/irqchip/irq-sunxi.c new file +42 -0

new file mode 100644
index 0000000..9dcb323
@@ -0,0 +1,173 @@
+/*
+ * Allwinner A1X SoCs IRQ chip driver.
+ *
+ * Copyright (C) 2012 Maxime Ripard
+ *
+ * Maxime Ripard <[email protected]>
+ *
+ * Based on code from
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ * Benn Huang <[email protected]>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+
+#include <linux/irqchip/sunxi.h>
+
+#define SUNXI_IRQ_PROTECTION_REG	0x08
+#define SUNXI_IRQ_NMI_CTRL_REG		0x0c
+#define SUNXI_IRQ_PENDING_REG(x)	(0x10 + 0x4 * x)
+#define SUNXI_IRQ_FIQ_PENDING_REG(x)	(0x20 + 0x4 * x)
+#define SUNXI_IRQ_ENABLE_REG(x)		(0x40 + 0x4 * x)
+#define SUNXI_IRQ_MASK_REG(x)		(0x50 + 0x4 * x)
+
+static void __iomem *sunxi_irq_base;
+static struct irq_domain *sunxi_irq_domain;
+
+void sunxi_irq_ack(struct irq_data *irqd)
+{
+	unsigned int irq = irqd_to_hwirq(irqd);
+	unsigned int irq_off = irq % 32;
+	int reg = irq / 32;
+	u32 val;
+
+	val = readl(sunxi_irq_base + SUNXI_IRQ_ENABLE_REG(reg));

drivers/irqchip/irq-sunxi.c new file +6 -0

+}
+
+static void sunxi_irq_mask(struct irq_data *irqd)
+{
+	unsigned int irq = irqd_to_hwirq(irqd);
+	unsigned int irq_off = irq % 32;

drivers/irqchip/irq-sunxi.c new file +10 -0

+}
+
+static void sunxi_irq_unmask(struct irq_data *irqd)
+{
+	unsigned int irq = irqd_to_hwirq(irqd);
+	unsigned int irq_off = irq % 32;
+	int reg = irq / 32;
+	u32 val;
+
+	val = readl(sunxi_irq_base + SUNXI_IRQ_ENABLE_REG(reg));

drivers/irqchip/irq-sunxi.c new file +4 -0

+}
+
+static struct irq_chip sunxi_irq_chip = {
+	.name		= "sunxi_irq",

drivers/irqchip/irq-sunxi.c new file +17 -0

+	set_irq_flags(virq, IRQF_VALID | IRQF_PROBE);
+
+	return 0;
+}
+
+static struct irq_domain_ops sunxi_irq_ops = {
+	.map = sunxi_irq_map,
+	.xlate = irq_domain_xlate_onecell,
+};
+
+static int __init sunxi_of_init(struct device_node *node,
+				struct device_node *parent)
+{
+	sunxi_irq_base = of_iomap(node, 0);
+	if (!sunxi_irq_base)
+		panic("%s: unable to map IC registers\n",
+			node->full_name);

drivers/irqchip/irq-sunxi.c new file +32 -0

+	/* Clear all the pending interrupts */
+	writel(0xffffffff, sunxi_irq_base + SUNXI_IRQ_PENDING_REG(0));
+	writel(0xffffffff, sunxi_irq_base + SUNXI_IRQ_PENDING_REG(1));
+	writel(0xffffffff, sunxi_irq_base + SUNXI_IRQ_PENDING_REG(2));
+
+	/* Enable protection mode */
+	writel(0x01, sunxi_irq_base + SUNXI_IRQ_PROTECTION_REG);
+
+	/* Configure the external interrupt source type */
+	writel(0x00, sunxi_irq_base + SUNXI_IRQ_NMI_CTRL_REG);
+
+	sunxi_irq_domain = irq_domain_add_linear(node, 3 * 32,
+						 &sunxi_irq_ops, NULL);
+	if (!sunxi_irq_domain)
+		panic("%s: unable to create IRQ domain\n", node->full_name);
+
+	return 0;
+}
+
+static struct of_device_id sunxi_irq_dt_ids[] __initconst = {
+	{ .compatible = "allwinner,sunxi-ic", .data = sunxi_of_init }
+};
+
+void __init sunxi_init_irq(void)
+{
+	of_irq_init(sunxi_irq_dt_ids);
+}
+
+asmlinkage void __exception_irq_entry sunxi_handle_irq(struct pt_regs *regs)
+{
+	u32 irq, reg;
+	int i;

<snip>

Quoted 55 lines

drivers/irqchip/irq-sunxi.c new file +49 -0

new file mode 100644
index 0000000..9dcb323
@@ -0,0 +1,173 @@
+/*
+ * Allwinner A1X SoCs IRQ chip driver.
+ *
+ * Copyright (C) 2012 Maxime Ripard
+ *
+ * Maxime Ripard <[email protected]>
+ *
+ * Based on code from
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ * Benn Huang <[email protected]>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+
+#include <linux/irqchip/sunxi.h>
+
+#define SUNXI_IRQ_PROTECTION_REG	0x08
+#define SUNXI_IRQ_NMI_CTRL_REG		0x0c
+#define SUNXI_IRQ_PENDING_REG(x)	(0x10 + 0x4 * x)
+#define SUNXI_IRQ_FIQ_PENDING_REG(x)	(0x20 + 0x4 * x)
+#define SUNXI_IRQ_ENABLE_REG(x)		(0x40 + 0x4 * x)
+#define SUNXI_IRQ_MASK_REG(x)		(0x50 + 0x4 * x)
+
+static void __iomem *sunxi_irq_base;
+static struct irq_domain *sunxi_irq_domain;
+
+void sunxi_irq_ack(struct irq_data *irqd)
+{
+	unsigned int irq = irqd_to_hwirq(irqd);
+	unsigned int irq_off = irq % 32;
+	int reg = irq / 32;
+	u32 val;
+
+	val = readl(sunxi_irq_base + SUNXI_IRQ_ENABLE_REG(reg));
+	writel(val & ~(1 << irq_off),
+	       sunxi_irq_base + SUNXI_IRQ_ENABLE_REG(reg));
+
+	val = readl(sunxi_irq_base + SUNXI_IRQ_MASK_REG(reg));
+	writel(val | (1 << irq_off),
+	       sunxi_irq_base + SUNXI_IRQ_MASK_REG(reg));
+

drivers/irqchip/irq-sunxi.c line 52

Quoted 3 lines

drivers/irqchip/irq-sunxi.c new file +3 -0

+	val = readl(sunxi_irq_base + SUNXI_IRQ_PENDING_REG(reg));
+	writel(val | (1 << irq_off),
+	       sunxi_irq_base + SUNXI_IRQ_PENDING_REG(reg));

Are you sure that you need to touch all those 23registers to ack the interrupt? I know that the original code provided by Allwinner does exactly this. My tests have shown though, that writing to the pending reg is enough.

Quoted 13 lines

drivers/irqchip/irq-sunxi.c new file +12 -0

+}
+
+static void sunxi_irq_mask(struct irq_data *irqd)
+{
+	unsigned int irq = irqd_to_hwirq(irqd);
+	unsigned int irq_off = irq % 32;
+	int reg = irq / 32;
+	u32 val;
+
+	val = readl(sunxi_irq_base + SUNXI_IRQ_ENABLE_REG(reg));
+	writel(val & ~(1 << irq_off),
+	       sunxi_irq_base + SUNXI_IRQ_ENABLE_REG(reg));

drivers/irqchip/irq-sunxi.c line 48

Quoted 4 lines

drivers/irqchip/irq-sunxi.c new file +4 -0

+
+	val = readl(sunxi_irq_base + SUNXI_IRQ_MASK_REG(reg));
+	writel(val | (1 << irq_off),
+	       sunxi_irq_base + SUNXI_IRQ_MASK_REG(reg));

I unmasked all interrupts in the mask register in the init function. Then only using the enable register for masking/unmasking seems to be enough. What do you think?

Quoted 14 lines

drivers/irqchip/irq-sunxi.c new file +14 -0

+}
+
+static void sunxi_irq_unmask(struct irq_data *irqd)
+{
+	unsigned int irq = irqd_to_hwirq(irqd);
+	unsigned int irq_off = irq % 32;
+	int reg = irq / 32;
+	u32 val;
+
+	val = readl(sunxi_irq_base + SUNXI_IRQ_ENABLE_REG(reg));
+	writel(val | (1 << irq_off),
+	       sunxi_irq_base + SUNXI_IRQ_ENABLE_REG(reg));
+
+	val = readl(sunxi_irq_base + SUNXI_IRQ_MASK_REG(reg));

drivers/irqchip/irq-sunxi.c line 88

Quoted 6 lines

drivers/irqchip/irq-sunxi.c new file +6 -0

+	writel(val & ~(1 << irq_off),
+	       sunxi_irq_base + SUNXI_IRQ_MASK_REG(reg));
+
+	/* Must clear pending bit when enabled */
+	if (irq == 0)
+		writel(1, sunxi_irq_base + SUNXI_IRQ_PENDING_REG(0));

Again. Might be that one register is enough here.

Quoted 8 lines

drivers/irqchip/irq-sunxi.c new file +8 -0

+}
+
+static struct irq_chip sunxi_irq_chip = {
+	.name		= "sunxi_irq",
+	.irq_ack	= sunxi_irq_ack,
+	.irq_mask	= sunxi_irq_mask,
+	.irq_unmask	= sunxi_irq_unmask,
+};

drivers/irqchip/irq-sunxi.c line 102

Quoted 6 lines

drivers/irqchip/irq-sunxi.c new file +6 -0

+
+static int sunxi_irq_map(struct irq_domain *d, unsigned int virq,
+			 irq_hw_number_t hw)
+{
+	irq_set_chip(virq, &sunxi_irq_chip);
+	irq_set_handler(virq, handle_level_irq);

irq_set_chip_and_handler()

Quoted 17 lines

drivers/irqchip/irq-sunxi.c new file +17 -0

+	set_irq_flags(virq, IRQF_VALID | IRQF_PROBE);
+
+	return 0;
+}
+
+static struct irq_domain_ops sunxi_irq_ops = {
+	.map = sunxi_irq_map,
+	.xlate = irq_domain_xlate_onecell,
+};
+
+static int __init sunxi_of_init(struct device_node *node,
+				struct device_node *parent)
+{
+	sunxi_irq_base = of_iomap(node, 0);
+	if (!sunxi_irq_base)
+		panic("%s: unable to map IC registers\n",
+			node->full_name);

drivers/irqchip/irq-sunxi.c line 129

Quoted 10 lines

drivers/irqchip/irq-sunxi.c new file +10 -0

+
+	/* Disable all interrupts */
+	writel(0, sunxi_irq_base + SUNXI_IRQ_ENABLE_REG(0));
+	writel(0, sunxi_irq_base + SUNXI_IRQ_ENABLE_REG(1));
+	writel(0, sunxi_irq_base + SUNXI_IRQ_ENABLE_REG(2));
+
+	/* Mask all the interrupts */
+	writel(0xffffffff, sunxi_irq_base + SUNXI_IRQ_MASK_REG(0));
+	writel(0xffffffff, sunxi_irq_base + SUNXI_IRQ_MASK_REG(1));
+	writel(0xffffffff, sunxi_irq_base + SUNXI_IRQ_MASK_REG(2));

Here is where I wrote 0 to the mask registers.

Quoted 32 lines

drivers/irqchip/irq-sunxi.c new file +32 -0

+	/* Clear all the pending interrupts */
+	writel(0xffffffff, sunxi_irq_base + SUNXI_IRQ_PENDING_REG(0));
+	writel(0xffffffff, sunxi_irq_base + SUNXI_IRQ_PENDING_REG(1));
+	writel(0xffffffff, sunxi_irq_base + SUNXI_IRQ_PENDING_REG(2));
+
+	/* Enable protection mode */
+	writel(0x01, sunxi_irq_base + SUNXI_IRQ_PROTECTION_REG);
+
+	/* Configure the external interrupt source type */
+	writel(0x00, sunxi_irq_base + SUNXI_IRQ_NMI_CTRL_REG);
+
+	sunxi_irq_domain = irq_domain_add_linear(node, 3 * 32,
+						 &sunxi_irq_ops, NULL);
+	if (!sunxi_irq_domain)
+		panic("%s: unable to create IRQ domain\n", node->full_name);
+
+	return 0;
+}
+
+static struct of_device_id sunxi_irq_dt_ids[] __initconst = {
+	{ .compatible = "allwinner,sunxi-ic", .data = sunxi_of_init }
+};
+
+void __init sunxi_init_irq(void)
+{
+	of_irq_init(sunxi_irq_dt_ids);
+}
+
+asmlinkage void __exception_irq_entry sunxi_handle_irq(struct pt_regs *regs)
+{
+	u32 irq, reg;
+	int i;

drivers/irqchip/irq-sunxi.c line 172

Quoted 10 lines

drivers/irqchip/irq-sunxi.c new file +10 -0

+
+	for (i = 0; i < 3; i++) {
+		reg = readl(sunxi_irq_base + SUNXI_IRQ_PENDING_REG(i));
+		if (reg == 0)
+			continue;
+		irq = ilog2(reg);
+		break;
+	}
+	irq = irq_find_mapping(sunxi_irq_domain, irq);
+	handle_IRQ(irq, regs);

Why don't you use the interrupt-vector register to get the active interrupt source? Here is my version:

asmlinkage void __exception_irq_entry sunxi_handle_irq(struct pt_regs *regs)

{
	u32 irq;

	irq = readl(int_base + SW_INT_VECTOR_REG) >> 2;
	irq = irq_find_mapping(sunxi_vic_domain, irq);
	handle_IRQ(irq, regs);
}

I suggest you give it a try.

Quoted 22 lines

Quoted 4 lines

drivers/irqchip/irq-sunxi.c new file +4 -0

+asmlinkage void __exception_irq_entry sunxi_handle_irq(struct pt_regs *regs)
+{
+	u32 irq, reg;
+	int i;

drivers/irqchip/irq-sunxi.c line 172

Quoted 10 lines

drivers/irqchip/irq-sunxi.c new file +10 -0

+
+	for (i = 0; i < 3; i++) {
+		reg = readl(sunxi_irq_base + SUNXI_IRQ_PENDING_REG(i));
+		if (reg == 0)
+			continue;
+		irq = ilog2(reg);
+		break;
+	}
+	irq = irq_find_mapping(sunxi_irq_domain, irq);
+	handle_IRQ(irq, regs);

Why don't you use the interrupt-vector register to get the active interrupt source? Here is my version:

asmlinkage void __exception_irq_entry sunxi_handle_irq(struct pt_regs *regs)

{
	u32 irq;

Quoted 6 lines

	irq = readl(int_base + SW_INT_VECTOR_REG) >> 2;
	irq = irq_find_mapping(sunxi_vic_domain, irq);
	handle_IRQ(irq, regs);
}

I suggest you give it a try.

It definitely looks nicer. I'll try that and update.

Quoted 9 lines

Quoted 9 lines

asmlinkage void __exception_irq_entry sunxi_handle_irq(struct pt_regs *regs)

{
	u32 irq;

	irq = readl(int_base + SW_INT_VECTOR_REG) >> 2;
	irq = irq_find_mapping(sunxi_vic_domain, irq);
	handle_IRQ(irq, regs);
}

Quoted 3 lines

Quoted 1 line

I suggest you give it a try.

It definitely looks nicer. I'll try that and update.

How does this SW_INT_VECTOR_REG behave when there are multiple interrupts pending?

Shouldn't the code be something like:

	do {
		hwirq = readl(int_base + SW_INT_VECTOR_REG) >> 2;
		irq = irq_find_mapping(sunxi_vic_domain, hwirq);
		handle_IRQ(irq, regs);
	} while(hwirq != 0);

Or maybe the != 0 is not the good condition, but the idea is to handle all pending interrupts. That said, the original code from Maxime was not doing that as well.

Signed-off-by Maxime Ripard <[email protected]>

Quoted 1 line

Signed-off-by Maxime Ripard <[email protected]>

Looks good. Thanks.

Acked-by Stefan Roese <[email protected]>

I'll add cubieboard support once this series has stabilized.

Signed-off-by Maxime Ripard <[email protected]>

---
 arch/arm/Kconfig.debug         |    8 ++++++++
 arch/arm/include/debug/sunxi.S |   22 ++++++++++++++++++++++
 2 files changed, 30 insertions(+)
 create mode 100644 arch/arm/include/debug/sunxi.S

arch/arm/Kconfig.debug +7 -0

index b0f3857..6672b02 100644
@@ -345,6 +345,13 @@ choice
 		  Say Y here if you want kernel low-level debugging support
 		  on SOCFPGA based platforms.
 
+	config DEBUG_SUNXI_UART
+		bool "Kernel low-level debugging messages via sunXi UART"
+		depends on ARCH_SUNXI
+		help
+		  Say Y here if you want kernel low-level debugging support
+		  on Allwinner A1X based platforms.
 
 	config DEBUG_VEXPRESS_UART0_DETECT
 		bool "Autodetect UART0 on Versatile Express Cortex-A core tiles"
 		depends on ARCH_VEXPRESS && CPU_CP15_MMU

@@ -416,6 +423,7 @@ config DEBUG_LL_INCLUDE
 	default "debug/mvebu.S" if DEBUG_MVEBU_UART
 	default "debug/picoxcell.S" if DEBUG_PICOXCELL_UART
 	default "debug/socfpga.S" if DEBUG_SOCFPGA_UART
+	default "debug/sunxi.S" if DEBUG_SUNXI_UART
 	default "debug/vexpress.S" if DEBUG_VEXPRESS_UART0_DETECT || \
 		DEBUG_VEXPRESS_UART0_CA9 || DEBUG_VEXPRESS_UART0_RS1
 	default "mach/debug-macro.S"

arch/arm/include/debug/sunxi.S new file +12 -0

new file mode 100644
index 0000000..ffd101f
@@ -0,0 +1,22 @@
+/*
+ * Early serial output macro for Allwinner A1X SoCs
+ *
+ * Copyright (C) 2012 Maxime Ripard
+ *
+ * Maxime Ripard <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+

Quoted 57 lines

Signed-off-by Maxime Ripard <[email protected]>

---
 arch/arm/Kconfig.debug         |    8 ++++++++
 arch/arm/include/debug/sunxi.S |   22 ++++++++++++++++++++++
 2 files changed, 30 insertions(+)
 create mode 100644 arch/arm/include/debug/sunxi.S

arch/arm/Kconfig.debug +7 -0

index b0f3857..6672b02 100644
@@ -345,6 +345,13 @@ choice
 		  Say Y here if you want kernel low-level debugging support
 		  on SOCFPGA based platforms.
 
+	config DEBUG_SUNXI_UART
+		bool "Kernel low-level debugging messages via sunXi UART"
+		depends on ARCH_SUNXI
+		help
+		  Say Y here if you want kernel low-level debugging support
+		  on Allwinner A1X based platforms.
 
 	config DEBUG_VEXPRESS_UART0_DETECT
 		bool "Autodetect UART0 on Versatile Express Cortex-A core tiles"
 		depends on ARCH_VEXPRESS && CPU_CP15_MMU

@@ -416,6 +423,7 @@ config DEBUG_LL_INCLUDE
 	default "debug/mvebu.S" if DEBUG_MVEBU_UART
 	default "debug/picoxcell.S" if DEBUG_PICOXCELL_UART
 	default "debug/socfpga.S" if DEBUG_SOCFPGA_UART
+	default "debug/sunxi.S" if DEBUG_SUNXI_UART
 	default "debug/vexpress.S" if DEBUG_VEXPRESS_UART0_DETECT || \
 		DEBUG_VEXPRESS_UART0_CA9 || DEBUG_VEXPRESS_UART0_RS1
 	default "mach/debug-macro.S"

arch/arm/include/debug/sunxi.S new file +18 -0

new file mode 100644
index 0000000..ffd101f
@@ -0,0 +1,22 @@
+/*
+ * Early serial output macro for Allwinner A1X SoCs
+ *
+ * Copyright (C) 2012 Maxime Ripard
+ *
+ * Maxime Ripard <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#define SUNXI_UART1_PHYS_BASE	0x01c28400
+#define SUNXI_UART1_VIRT_BASE	0xf1c28400
+
+	.macro	addruart, rp, rv, tmp
+	ldr	\rp, =SUNXI_UART1_PHYS_BASE
+	ldr	\rv, =SUNXI_UART1_VIRT_BASE

arch/arm/include/debug/sunxi.S line 22

Quoted 4 lines

arch/arm/include/debug/sunxi.S new file +4 -0

+	.endm
+
+#define UART_SHIFT	2
+#include <asm/hardware/debug-8250.S>

A10 (cubieboard) has debug the UART on UART0 instead of UART1 as on A13. So we need support this here as well. I suggest that I add support debug on UART0 with my cubieboard patches.

Signed-off-by Maxime Ripard <[email protected]>

---
 arch/arm/Kconfig.debug         |    8 ++++++++
 arch/arm/include/debug/sunxi.S |   22 ++++++++++++++++++++++
 2 files changed, 30 insertions(+)
 create mode 100644 arch/arm/include/debug/sunxi.S

arch/arm/Kconfig.debug +0 -0

index b0f3857..6672b02 100644

arch/arm/Kconfig.debug +0 -0

 	default "debug/vexpress.S" if DEBUG_VEXPRESS_UART0_DETECT || \
 		DEBUG_VEXPRESS_UART0_CA9 || DEBUG_VEXPRESS_UART0_RS1
 	default "mach/debug-macro.S"

arch/arm/include/debug/sunxi.S new file +4 -0

new file mode 100644
index 0000000..ffd101f
@@ -0,0 +1,22 @@
+/*
+ * Early serial output macro for Allwinner A1X SoCs
+ *
+ * Copyright (C) 2012 Maxime Ripard

Signed-off-by Maxime Ripard <[email protected]>

---
 arch/arm/boot/dts/Makefile            |    1 +
 arch/arm/boot/dts/sun5i-olinuxino.dts |   30 +++++++++++++++++
 arch/arm/boot/dts/sun5i.dtsi          |   58 +++++++++++++++++++++++++++++++++
 3 files changed, 89 insertions(+)
 create mode 100644 arch/arm/boot/dts/sun5i-olinuxino.dts
 create mode 100644 arch/arm/boot/dts/sun5i.dtsi

arch/arm/boot/dts/Makefile +1 -0

index f37cf9f..9b2d3f0 100644
@@ -84,6 +84,7 @@ dtb-$(CONFIG_ARCH_SPEAR3XX)+= spear300-evb.dtb \
 	spear310-evb.dtb \
 	spear320-evb.dtb
 dtb-$(CONFIG_ARCH_SPEAR6XX)+= spear600-evb.dtb
+dtb-$(CONFIG_ARCH_SUNXI) += sun5i-olinuxino.dtb
 dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \
 	tegra20-medcom-wide.dtb \
 	tegra20-paz00.dtb \

arch/arm/boot/dts/sun5i-olinuxino.dts new file +13 -0

new file mode 100644
index 0000000..add1e60
@@ -0,0 +1,30 @@
+/*
+ * Copyright 2012 Maxime Ripard
+ *
+ * Maxime Ripard <[email protected]>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+

arch/arm/boot/dts/sun5i-olinuxino.dts new file +6 -0

+	soc {
+		duart: uart at 01c28400 {
+			status = "okay";
+		};
+	};
+};

arch/arm/boot/dts/sun5i.dtsi new file +17 -0

new file mode 100644
index 0000000..5797323
@@ -0,0 +1,58 @@
+/*
+ * Copyright 2012 Maxime Ripard
+ *
+ * Maxime Ripard <[email protected]>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+	interrupt-parent = <&intc>;

arch/arm/boot/dts/sun5i.dtsi new file +20 -0

+	soc {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0x01c20000 0x300000>;
+		ranges;
+
+		timer at 01c20c00 {
+			compatible = "allwinner,sunxi-timer";
+			reg = <0x01c20c00 0x400>;
+			interrupts = <22>;
+		};
+
+		intc: interrupt-controller at 01c20400 {
+			compatible = "allwinner,sunxi-ic";
+			reg = <0x01c20400 0x400>;
+			interrupt-controller;
+			#interrupt-cells = <1>;
+		};
+

Quoted 45 lines

Signed-off-by Maxime Ripard <[email protected]>

---
 arch/arm/boot/dts/Makefile            |    1 +
 arch/arm/boot/dts/sun5i-olinuxino.dts |   30 +++++++++++++++++
 arch/arm/boot/dts/sun5i.dtsi          |   58 +++++++++++++++++++++++++++++++++
 3 files changed, 89 insertions(+)
 create mode 100644 arch/arm/boot/dts/sun5i-olinuxino.dts
 create mode 100644 arch/arm/boot/dts/sun5i.dtsi

arch/arm/boot/dts/Makefile +1 -0

index f37cf9f..9b2d3f0 100644
@@ -84,6 +84,7 @@ dtb-$(CONFIG_ARCH_SPEAR3XX)+= spear300-evb.dtb \
 	spear310-evb.dtb \
 	spear320-evb.dtb
 dtb-$(CONFIG_ARCH_SPEAR6XX)+= spear600-evb.dtb
+dtb-$(CONFIG_ARCH_SUNXI) += sun5i-olinuxino.dtb
 dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \
 	tegra20-medcom-wide.dtb \
 	tegra20-paz00.dtb \

arch/arm/boot/dts/sun5i-olinuxino.dts new file +18 -0

new file mode 100644
index 0000000..add1e60
@@ -0,0 +1,30 @@
+/*
+ * Copyright 2012 Maxime Ripard
+ *
+ * Maxime Ripard <[email protected]>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+/include/ "sun5i.dtsi"
+
+/ {
+	model = "Olimex A13-Olinuxino";

arch/arm/boot/dts/sun5i-olinuxino.dts line 23

Quoted 5 lines

arch/arm/boot/dts/sun5i-olinuxino.dts new file +5 -0

+	compatible = "olimex,a13-olinuxino", "allwinner,sun5i";
+
+	memory {
+		reg = <0x40000000 0x40000000>;
+	};

Sure that the board support 1GiB of RAM? AFAIK A13 only supports 512MiB. Please re-check.

Quoted 36 lines

arch/arm/boot/dts/sun5i-olinuxino.dts new file +6 -0

+	soc {
+		duart: uart at 01c28400 {
+			status = "okay";
+		};
+	};
+};

arch/arm/boot/dts/sun5i.dtsi new file +24 -0

new file mode 100644
index 0000000..5797323
@@ -0,0 +1,58 @@
+/*
+ * Copyright 2012 Maxime Ripard
+ *
+ * Maxime Ripard <[email protected]>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+	interrupt-parent = <&intc>;
+
+	cpus {
+		cpu at 0 {
+			compatible = "arm,cortex-a8";
+		};
+	};
+

arch/arm/boot/dts/sun5i.dtsi line 27

Quoted 3 lines

arch/arm/boot/dts/sun5i.dtsi new file +3 -0

+	chosen {
+		bootargs = "earlyprintk console=ttyS0,115200";
+	};

No memory node here? My experience is, that the soc.dtsi file should contain a memory node with the max possible memory size of the SoC. Which will be overwritten by the board dts file containing the max memory size of the board.

Quoted 21 lines

arch/arm/boot/dts/sun5i.dtsi new file +20 -0

+	soc {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0x01c20000 0x300000>;
+		ranges;
+
+		timer at 01c20c00 {
+			compatible = "allwinner,sunxi-timer";
+			reg = <0x01c20c00 0x400>;
+			interrupts = <22>;
+		};
+
+		intc: interrupt-controller at 01c20400 {
+			compatible = "allwinner,sunxi-ic";
+			reg = <0x01c20400 0x400>;
+			interrupt-controller;
+			#interrupt-cells = <1>;
+		};
+

arch/arm/boot/dts/sun5i.dtsi line 58

Quoted 10 lines

arch/arm/boot/dts/sun5i.dtsi new file +10 -0

+		uart1: uart at 01c28400 {
+			compatible = "ns8250";
+			reg = <0x01c28400 0x400>;
+			interrupts = <2>;
+			reg-shift = <2>;
+			clock-frequency = <24000000>;
+			status = "disabled";
+		};
+	};
+};

Looks good so far. I suggest that with the A10/cubieboard support we move to the following dts/dtsi organization:

sunxi.dtsi - Devices common to all Allwinner sunXi SoC's sun4i.dtsi - sun4i Devices, will include sunxi.dtsi sun5i.dtsi - sun5i Devices, will include sunxi.dtsi board.dts - will include either sun4i.dtsi or sun5i.dtsi

If we agree on this, then I'll send a patch with this re-organization with the cubieboard patches.

You'll find in this patchset the initial support for Allwinner A10 and A13 SoCs from Allwinner. Since the internal name of these SoCs are sun4i and sun5i, the mach- directory is named sunxi.

You can find these SoCs in the Cubieboard, the A13-olinuxino or the Melee A1000.

Both SoCs should work fine, as the A13 is a trimmed down version of the A10, but it has only been tested on a A13-OlinuXino from Olimex.

Support is quite minimal for now, since it only includes timer and IRQ controller drivers, so we can only boot to userspace through initramfs. Support for the other peripherals on these SoCs will come eventually.

You'll find in this patchset the initial support for Allwinner A10 and A13 SoCs from Allwinner. Since the internal name of these SoCs are sun4i and sun5i, the mach- directory is named sunxi.

You can find these SoCs in the Cubieboard, the A13-olinuxino or the Melee A1000.

Both SoCs should work fine, as the A13 is a trimmed down version of the A10, but it has only been tested on a A13-OlinuXino from Olimex.

Support is quite minimal for now, since it only includes timer and IRQ controller drivers, so we can only boot to userspace through initramfs. Support for the other peripherals on these SoCs will come eventually.

Quoted 7 lines · Maxime Ripard

You'll find in this patchset the initial support for Allwinner A10 and A13 SoCs from Allwinner. Since the internal name of these SoCs are sun4i and sun5i, the mach- directory is named sunxi.

You can find these SoCs in the Cubieboard, the A13-olinuxino or the Melee A1000.

Quoted 6 lines

Both SoCs should work fine, as the A13 is a trimmed down version of the A10, but it has only been tested on a A13-OlinuXino from Olimex.

Support is quite minimal for now, since it only includes timer and IRQ controller drivers, so we can only boot to userspace through initramfs. Support for the other peripherals on these SoCs will come eventually.

Hi Maxime,

Thanks for sending these, I'm pretty excited we actually get this far for 3.8. All patches look good for inclusion from my side, but I'll let Stefan and others comment first and then take your second version. We are getting closer to the merge window already, so I'd like to pull it in rather soon and maybe add some fixups later.

I've also ordered a Cubieboard myself now, so hopefully I'll also find some time to play with this.

Quoted 7 lines

You'll find in this patchset the initial support for Allwinner A10 and A13 SoCs from Allwinner. Since the internal name of these SoCs are sun4i and sun5i, the mach- directory is named sunxi.

You can find these SoCs in the Cubieboard, the A13-olinuxino or the Melee A1000.

Quoted 6 lines

Both SoCs should work fine, as the A13 is a trimmed down version of the A10, but it has only been tested on a A13-OlinuXino from Olimex.

Support is quite minimal for now, since it only includes timer and IRQ controller drivers, so we can only boot to userspace through initramfs. Support for the other peripherals on these SoCs will come eventually.

Hi Maxime,

Thanks for sending these, I'm pretty excited we actually get this far for 3.8. All patches look good for inclusion from my side, but I'll let Stefan and others comment first and then take your second version. We are getting closer to the merge window already, so I'd like to pull it in rather soon and maybe add some fixups later.

I've also ordered a Cubieboard myself now, so hopefully I'll also find some time to play with this.

You'll find in this patchset the initial support for Allwinner A10 and A13 SoCs from Allwinner. Since the internal name of these SoCs are sun4i and sun5i, the mach- directory is named sunxi.

You can find these SoCs in the Cubieboard, the A13-olinuxino or the Melee A1000.

Both SoCs should work fine, as the A13 is a trimmed down version of the A10, but it has only been tested on a A13-OlinuXino from Olimex.

Support is quite minimal for now, since it only includes timer and IRQ controller drivers, so we can only boot to userspace through initramfs. Support for the other peripherals on these SoCs will come eventually.