ARM: cti: fix manipulation of debug lock registers
PATCH 1/1 ARM: cti: fix manipulation of debug lock registers
The LOCKSTATUS register for memory-mapped coresight devices indicates whether or not the device in question implements hardware locking. If not, locking is not present (i.e. LSR.SLI == 0) and LAR is write-ignore, so software doesn't actually need to check the status register at all.
This patch removes the broken LSR checks.
--- arch/arm/include/asm/cti.h | 20 ++------------------ 1 files changed, 2 insertions(+), 18 deletions(-)
arch/arm/include/asm/cti.h +2 -18
@@ -146,15 +146,7 @@ static inline void cti_irq_ack(struct cti *cti)*/ static inline void cti_unlock (struct cti *cti) { -void __iomem *base = cti->base; -unsigned long val; - - val =__raw_readl (base +LOCKSTATUS ); - -if (val &1 ) { - val =LOCKCODE ; -__raw_writel (val, base +LOCKACCESS ); - } +__raw_writel (LOCKCODE , cti->base +LOCKACCESS ); }/**
@@ -166,14 +158,6 @@ static inline void cti_unlock(struct cti *cti)*/ static inline void cti_lock (struct cti *cti) { -void __iomem *base = cti->base; -unsigned long val; - - val =__raw_readl (base +LOCKSTATUS ); - -if (!(val &1 )) { - val = ~LOCKCODE ; -__raw_writel (val, base +LOCKACCESS ); - } +__raw_writel (~LOCKCODE , cti->base +LOCKACCESS ); }#endif
Signature · 1 line
1.7.4.1
PATCH 1/1 ARM: cti: fix manipulation of debug lock registers
Quoted 41 lines · Will Deacon
The LOCKSTATUS register for memory-mapped coresight devices indicates whether or not the device in question implements hardware locking. If not, locking is not present (i.e. LSR.SLI == 0) and LAR is write-ignore, so software doesn't actually need to check the status register at all.
This patch removes the broken LSR checks.
Cc Ming Lei <[email protected]>Reported-by Mike Williams <[email protected]>Signed-off-by Will Deacon <[email protected]>--- arch/arm/include/asm/cti.h | 20 ++------------------ 1 files changed, 2 insertions(+), 18 deletions(-)arch/arm/include/asm/cti.h +1
-11@@ -146,15 +146,7 @@ static inline void cti_irq_ack(struct cti *cti)*/ static inline void cti_unlock (struct cti *cti) { -void __iomem *base = cti->base; -unsigned long val; - - val =__raw_readl (base +LOCKSTATUS ); - -if (val &1 ) { - val =LOCKCODE ; -__raw_writel (val, base +LOCKACCESS ); - } +__raw_writel (LOCKCODE , cti->base +LOCKACCESS ); }/** @@ -166,14 +158,6 @@ static inline void cti_unlock(struct cti *cti)*/ static inline void cti_lock (struct cti *cti) { -void __iomem *base = cti->base; -unsigned long val;
arch/arm/include/asm/cti.h static inline void cti_unlock(struct cti *cti) · line 163
Quoted 10 lines
arch/arm/include/asm/cti.h +1
-7- - val =__raw_readl (base +LOCKSTATUS ); - -if (!(val &1 )) { - val = ~LOCKCODE ; -__raw_writel (val, base +LOCKACCESS ); - } + __raw_writel(~LOCKCODE, cti->base + LOCKACCESS); }#endif
I gave this a whirl on omap4430 and PMU is working fine with this, so ...
Cheers
Jon
PATCH 1/1 ARM: cti: fix manipulation of debug lock registers
Quoted 41 lines · Jon Hunter
Quoted 27 lines · Will Deacon
arch/arm/include/asm/cti.h +1
-11@@ -146,15 +146,7 @@ static inline void cti_irq_ack(struct cti *cti)*/ static inline void cti_unlock (struct cti *cti) { -void __iomem *base = cti->base; -unsigned long val; - - val =__raw_readl (base +LOCKSTATUS ); - -if (val &1 ) { - val =LOCKCODE ; -__raw_writel (val, base +LOCKACCESS ); - } +__raw_writel (LOCKCODE , cti->base +LOCKACCESS ); }/** @@ -166,14 +158,6 @@ static inline void cti_unlock(struct cti *cti)*/ static inline void cti_lock (struct cti *cti) { -void __iomem *base = cti->base; -unsigned long val;arch/arm/include/asm/cti.h static inline void cti_unlock(struct cti *cti) · line 163
Quoted 10 lines
arch/arm/include/asm/cti.h +1
-7- - val =__raw_readl (base +LOCKSTATUS ); - -if (!(val &1 )) { - val = ~LOCKCODE ; -__raw_writel (val, base +LOCKACCESS ); - } + __raw_writel(~LOCKCODE, cti->base + LOCKACCESS); }#endif I gave this a whirl on omap4430 and PMU is working fine with this, so ...
Quoted 1 line
Tested-by Jon Hunter <[email protected]>
Cheers Jon,
Will