ARM: dts: support pinctrl single in aspenite
PATCH 1/2 ARM: dts: support pinctrl single in aspenite
Support pinctrl-single driver in aspenite DTS file.
Signed-off-by Haojian Zhuang <[email protected]>
--- arch/arm/boot/dts/pxa168-aspenite.dts | 109 +++++++++++++++++++++++++++++++++ arch/arm/boot/dts/pxa168.dtsi | 109 +++++++++++++++++++++++++++++++++ 2 files changed, 218 insertions(+)
arch/arm/boot/dts/pxa168-aspenite.dts +109 -0
@@ -24,7 +24,116 @@ soc { apb at d4000000 { + pmx: pinmux at d401e000 { + pinctrl-names = "default"; + pinctrl-0 = <ðer_pins>; + + ether_pins: pinmux_ether_pins { + pinctrl-single,pins = < + 0x094 0x3 /* GPIO18_SMC_nCS0 */ + 0x0a8 0x0 /* GPIO23_SMC_nLUA */ + 0x0b0 0x0 /* GPIO25_SMC_nLLA */ + 0x0b8 0x0 /* GPIO27_GPIO as irq */ + 0x0bc 0x0 /* GPIO28_SMC_RDY */ + 0x0c0 0x0 /* GPIO29_SMC_SCLK */ + 0x0d4 0x2 /* GPIO34_SMC_nCS1 */ + 0x0d8 0x2 /* GPIO35_SMC_BE1 */ + 0x0dc 0x2 /* GPIO36_SMC_BE2 */ + >; + pinctrl-single,power-source = <0x0c00 0x0c00>; + pinctrl-single,bias = <0 0xe000 0 0xa000 0xc000>; + }; + uart1_pins: pinmux_uart1_pins { + pinctrl-single,pins = < + 0x1ac 0x2 /* GPIO107_UART1_RXD */ + 0x1b0 0x2 /* GPIO108_UART1_TXD */ + >; + pinctrl-single,power-source = <0x0c00 0x0c00>; + pinctrl-single,bias = <0 0xe000 0 0xa000 0xc000>; + }; + nand_pins: pinmux_nand_pins { + pinctrl-single,pins = < + 0x04c 0x0 /* ND_IO15 */ + 0x050 0x0 /* ND_IO14 */ + 0x054 0x0 /* ND_IO13 */ + 0x058 0x0 /* ND_IO12 */ + 0x05c 0x0 /* ND_IO11 */ + 0x060 0x0 /* ND_IO10 */ + 0x064 0x0 /* ND_IO9 */ + 0x068 0x0 /* ND_IO8 */ + 0x06c 0x0 /* ND_IO7 */ + 0x070 0x0 /* ND_IO6 */ + 0x074 0x0 /* ND_IO5 */ + 0x078 0x0 /* ND_IO4 */ + 0x07c 0x0 /* ND_IO3 */ + 0x080 0x0 /* ND_IO2 */ + 0x084 0x0 /* ND_IO1 */ + 0x088 0x0 /* ND_IO0 */ + >; + pinctrl-single,power-source = <0x0800 0x0c00>; + pinctrl-single,bias = <0 0xe000 0 0xa000 0xc000>; + }; + ssp1_pins: pinmux_ssp1_pins { + pinctrl-single,pins = < + 0x1c4 0x6 /* GPIO113_I2S_MCLK */ + 0x1c8 0x1 /* GPIO114_I2S_FRM */ + 0x1cc 0x1 /* GPIO115_I2S_BCLK */ + 0x120 0x2 /* GPIO116_I2S_RXD */ + 0x124 0x2 /* GPIO117_I2S_TXD */ + >; + pinctrl-single,power-source = <0x0800 0x0c00>; + pinctrl-single,bias = <0 0xe000 0 0xa000 0xc000>; + }; + keypad_pins: pinmux_keypad_pins { + pinctrl-single,pins = < + 0x1b4 0x7 /* GPIO109_KP_MKIN1 */ + 0x1b8 0x7 /* GPIO110_KP_MKIN0 */ + 0x1bc 0x7 /* GPIO111_KP_MKOUT7 */ + 0x1c0 0x7 /* GPIO112_KP_MKOUT6 */ + 0x1e4 0x7 /* GPIO121_MK_MKIN4 */ + >; + pinctrl-single,power-source = <0x0800 0x0c00>; + pinctrl-single,bias = <0 0xe000 0 0xa000 0xc000>; + }; + lcd_pins: pinmux_lcd_pins { + pinctrl-single,pins = < + 0x0e0 0x1 /* GPIO56_LCD_FCLK_RD */ + 0x0e4 0x1 /* GPIO57_LCD_LCLK_A0 */ + 0x0e8 0x1 /* GPIO58_LCD_ACLK_WR */ + 0x0ec 0x1 /* GPIO59_LCD_DENA_BIAS */ + 0x0f0 0x1 /* GPIO60_LCD_DD0 */ + 0x0f4 0x1 /* GPIO60_LCD_DD1 */ + 0x0f8 0x1 /* GPIO60_LCD_DD2 */ + 0x0fc 0x1 /* GPIO60_LCD_DD3 */ + 0x100 0x1 /* GPIO60_LCD_DD4 */ + 0x104 0x1 /* GPIO60_LCD_DD5 */ + 0x108 0x1 /* GPIO60_LCD_DD6 */ + 0x10c 0x1 /* GPIO60_LCD_DD7 */ + 0x110 0x1 /* GPIO60_LCD_DD8 */ + 0x114 0x1 /* GPIO60_LCD_DD9 */ + 0x118 0x1 /* GPIO60_LCD_DD10 */ + 0x11c 0x1 /* GPIO60_LCD_DD11 */ + 0x120 0x1 /* GPIO60_LCD_DD12 */ + 0x124 0x1 /* GPIO60_LCD_DD13 */ + 0x128 0x1 /* GPIO60_LCD_DD14 */ + 0x12c 0x1 /* GPIO60_LCD_DD15 */ + 0x130 0x1 /* GPIO60_LCD_DD16 */ + 0x134 0x1 /* GPIO60_LCD_DD17 */ + 0x138 0x1 /* GPIO60_LCD_DD18 */ + 0x13c 0x1 /* GPIO60_LCD_DD19 */ + 0x140 0x1 /* GPIO60_LCD_DD20 */ + 0x144 0x1 /* GPIO60_LCD_DD21 */ + 0x148 0x1 /* GPIO60_LCD_DD22 */ + 0x14c 0x1 /* GPIO60_LCD_DD23 */ + >; + pinctrl-single,power-source = <0x0800 0x0c00>; + pinctrl-single,bias = <0 0xe000 0 0xa000 0xc000>; + }; + }; + uart1: uart at d4017000 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; status = "okay"; }; twsi1: i2c at d4011000 {
arch/arm/boot/dts/pxa168.dtsi +109 -0
115 lines not on this page · raw message
Signature · 1 line
1.7.10.4
PATCH 2/2 ARM: mmp: support pinctrl single in brownstone
Support pinctrl-single driver in brownstone platform with DT.
Signed-off-by Haojian Zhuang <[email protected]>
--- arch/arm/boot/dts/mmp2-brownstone.dts | 173 +++++++++++++++++++++++++++- arch/arm/boot/dts/mmp2.dtsi | 204 +++++++++++++++++++++++++++++++++ 2 files changed, 376 insertions(+), 1 deletion(-)
arch/arm/boot/dts/mmp2-brownstone.dts +172 -1
@@ -15,7 +15,7 @@ compatible = "mrvl,mmp2-brownstone", "mrvl,mmp2"; chosen { - bootargs = "console=ttyS2,38400 root=/dev/nfs nfsroot=192.168.1.100:/nfsroot/ ip=192.168.1.101:192.168.1.100::255.255.255.0::eth0:on"; + bootargs = "console=ttyS2,38400 root=/dev/nfs nfsroot=192.168.1.100:/nfsroot/ ip=192.168.1.101:192.168.1.100::255.255.255.0::eth0:on earlyprintk"; }; memory {
@@ -24,10 +24,181 @@ soc { apb at d4000000 { + pmx: pinmux at d401e000 { + pinctrl-names = "default"; + pinctrl-0 = <&board_pins>; + + board_pins: pinmux_board_pins { + pinctrl-single,pins = < + 0x010 0x0 /* GPIO125_GPIO as version:0 */ + 0x014 0x0 /* GPIO126_GPIO as version:1 */ + 0x018 0x0 /* GPIO127_GPIO as version:2 */ + 0x01c 0x0 /* GPIO128_GPIO as version:3 */ + >; + pinctrl-single,power-source = <0x0800 0x1800>; + pinctrl-single,bias = <0 0xe000 0 0xa000 0xc000>; + pinctrl-single,input-schmitt = <0x40 0x70 0x40>; + }; + + uart1_pins: pinmux_uart1_pins { + pinctrl-single,pins = < + 0x0c8 0x1 /* GPIO29_UART1_RXD */ + 0x0cc 0x1 /* GPIO30_UART1_TXD */ + >; + /* power source, mask */ + pinctrl-single,power-source = <0x1000 0x1800>; + /* bias, mask, disable, pull down, pull up */ + pinctrl-single,bias = <0 0xe000 0 0xa000 0xc000>; + /* input schmitt, mask, disable */ + pinctrl-single,input-schmitt = <0x40 0x70 0x40>; + }; + uart2_pins: pinmux_uart2_pins { + pinctrl-single,pins = < + 0x110 0x1 /* GPIO47_UART2_RXD */ + 0x114 0x1 /* GPIO48_UART2_TXD */ + >; + pinctrl-single,power-source = <0x1000 0x1800>; + pinctrl-single,bias = <0 0xe000 0 0xa000 0xc000>; + pinctrl-single,input-schmitt = <0x40 0x70 0x40>; + }; + uart3_pins: pinmux_uart3_pins { + pinctrl-single,pins = < + 0x120 0x1 /* GPIO51_UART3_RXD */ + 0x124 0x1 /* GPIO52_UART3_TXD */ + >; + pinctrl-single,power-source = <0x1000 0x1800>; + pinctrl-single,bias = <0 0xe000 0 0xa000 0xc000>; + pinctrl-single,input-schmitt = <0x40 0x70 0x40>; + }; + twsi1_pins: pinmux_twsi1_pins { + pinctrl-single,pins = < + 0x140 0x0 /* TWSI_SCL */ + 0x144 0x0 /* TWSI_SDA */ + >; + pinctrl-single,power-source = <0x0800 0x1800>; + pinctrl-single,bias = <0 0xe000 0 0xa000 0xc000>; + pinctrl-single,input-schmitt = <0x40 0x70 0x40>; + }; + twsi2_pins: pinmux_twsi2_pins { + pinctrl-single,pins = < + 0x100 0x1 /* GPIO43_TWSI2_SCL */ + 0x104 0x1 /* GPIO44_TWSI2_SDA */ + >; + pinctrl-single,power-source = <0x0800 0x1800>; + pinctrl-single,bias = <0 0xe000 0 0xa000 0xc000>; + pinctrl-single,input-schmitt = <0x40 0x70 0x40>; + }; + twsi3_pins: pinmux_twsi3_pins { + pinctrl-single,pins = < + 0x2b0 0x1 /* GPIO71_TWSI3_SCL */ + 0x2b4 0x1 /* GPIO72_TWSI3_SDA */ + >; + pinctrl-single,power-source = <0x0800 0x1800>; + pinctrl-single,bias = <0 0xe000 0 0xa000 0xc000>; + pinctrl-single,input-schmitt = <0x40 0x70 0x40>; + }; + twsi4_pins: pinmux_twsi4_pins { + pinctrl-single,pins = < + 0x2bc 0x0 /* TWSI4_SCL */ + 0x2c0 0x0 /* TWSI4_SDA */ + >; + pinctrl-single,power-source = <0x0800 0x1800>; + pinctrl-single,bias = <0 0xe000 0 0xa000 0xc000>; + pinctrl-single,input-schmitt = <0x40 0x70 0x40>; + }; + twsi5_pins: pinmux_twsi5_pins { + pinctrl-single,pins = < + 0x1d4 0x4 /* GPIO99_TWSI5_SCL */ + 0x1d8 0x4 /* GPIO100_TWSI5_SDA */ + >; + pinctrl-single,power-source = <0x0800 0x1800>; + pinctrl-single,bias = <0 0xe000 0 0xa000 0xc000>; + pinctrl-single,input-schmitt = <0x40 0x70 0x40>; + }; + twsi6_pins: pinmux_twsi6_pins { + pinctrl-single,pins = < + 0x1cc 0x2 /* GPIO97_TWSI6_SCL */ + 0x1d0 0x2 /* GPIO98_TWSI6_SDA */ + >; + pinctrl-single,power-source = <0x0800 0x1800>; + pinctrl-single,bias = <0 0xe000 0 0xa000 0xc000>; + pinctrl-single,input-schmitt = <0x40 0x70 0x40>; + }; + sspa1_pins: pinmux_sspa1_pins { + pinctrl-single,pins = < + 0x0b0 0x0 /* GPIO23_GPIO */ + 0x0b4 0x1 /* GPIO24_I2S_SYSCLK */ + 0x0b8 0x1 /* GPIO25_I2S_BITCLK */ + 0x0bc 0x1 /* GPIO26_I2S_SYNC */ + 0x0c0 0x1 /* GPIO27_I2S_DATA_OUT */ + 0x0c4 0x1 /* GPIO28_I2S_SDATA_IN */ + >; + pinctrl-single,power-source = <0x1000 0x1800>; + pinctrl-single,bias = <0 0xe000 0 0xa000 0xc000>; + pinctrl-single,input-schmitt = <0x40 0x70 0x40>; + }; + sspa2_pins: pinmux_sspa2_pins { + pinctrl-single,pins = < + 0x0d8 0x1 /* GPIO33_SSPA2_CLK */ + 0x0dc 0x1 /* GPIO34_SSPA2_FRM */ + 0x0e0 0x1 /* GPIO35_SSPA2_TXD */ + 0x0e4 0x1 /* GPIO36_SSPA2_RXD */ + >; + pinctrl-single,power-source = <0x1000 0x1800>; + pinctrl-single,bias = <0 0xe000 0 0xa000 0xc000>; + pinctrl-single,input-schmitt = <0x40 0x70 0x40>; + }; + nand_pins: pinmux_nand_pins { + pinctrl-single,pins = < + 0x1e0 0x0 /* GPIO168_DFI_D0 */ + 0x1e4 0x0 /* GPIO167_DFI_D1 */ + 0x1e8 0x0 /* GPIO166_DFI_D2 */ + 0x1ec 0x0 /* GPIO165_DFI_D3 */ + 0x1f0 0x0 /* GPIO107_DFI_D4 */ + 0x1f4 0x0 /* GPIO106_DFI_D5 */ + 0x1f8 0x0 /* GPIO105_DFI_D6 */ + 0x1fc 0x0 /* GPIO104_DFI_D7 */ + 0x200 0x0 /* GPIO111_DFI_D8 */ + 0x204 0x0 /* GPIO164_DFI_D9 */ + 0x208 0x0 /* GPIO163_DFI_D10 */ + 0x20c 0x0 /* GPIO162_DFI_D11 */ + 0x210 0x0 /* GPIO161_DFI_D12 */ + 0x214 0x0 /* GPIO110_DFI_D13 */ + 0x218 0x0 /* GPIO109_DFI_D14 */ + 0x21c 0x0 /* GPIO108_DFI_D15 */ + 0x220 0x0 /* GPIO143_ND_nCS0 */ + 0x224 0X0 /* GPIO144_ND_nCS1 */ + 0x230 0x0 /* GPIO147_ND_nWE */ + 0x234 0x0 /* GPIO148_ND_nRE */ + 0x238 0x0 /* GPIO149_ND_CLE */ + 0x23c 0x0 /* GPIO150_ND_ALE */ + 0x244 0x0 /* GPIO112_ND_RDY0 */ + 0x250 0x0 /* GPIO160_ND_RDY1 */ + >; + pinctrl-single,power-source = <0x1000 0x1800>; + pinctrl-single,bias = <0 0xe000 0 0xa000 0xc000>; + pinctrl-single,input-schmitt = <0x40 0x70 0x40>; + }; + keypad_pins: pinmux_keypad_pins { + pinctrl-single,pins = < + 0x094 0x1 /* GPIO16_KP_DKIN0 */ + 0x098 0X1 /* GPIO17_KP_DKIN1 */ + 0x09c 0x1 /* GPIO18_KP_DKIN2 */ + 0x0a0 0x1 /* GPIO19_KP_DKIN3 */ + >; + pinctrl-single,power-source = <0x1000 0x1800>; + pinctrl-single,bias = <0xc000 0xe000 0 0xa000 0xc000>; + pinctrl-single,input-schmitt = <0x40 0x70 0x40>; + }; + }; uart3: uart at d4018000 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins>; status = "okay"; }; twsi1: i2c at d4011000 { + pinctrl-names = "default"; + pinctrl-0 = <&twsi1_pins>; status = "okay"; }; rtc: rtc at d4010000 {
arch/arm/boot/dts/mmp2.dtsi +204 -0
210 lines not on this page · raw message
Signature · 1 line
1.7.10.4
PATCH 2/2 ARM: mmp: support pinctrl single in brownstone
arch/arm/boot/dts/mmp2-brownstone.dts line 18
Quoted 7 lines · Haojian Zhuang
Support pinctrl-single driver in brownstone platform with DT.
arch/arm/boot/dts/mmp2-brownstone.dts +1
-1chosen { - bootargs = "console=ttyS2,38400 root=/dev/nfs nfsroot=192.168.1.100:/nfsroot/ ip=192.168.1.101:192.168.1.100::255.255.255.0::eth0:on"; + bootargs = "console=ttyS2,38400 root=/dev/nfs nfsroot=192.168.1.100:/nfsroot/ ip=192.168.1.101:192.168.1.100::255.255.255.0::eth0:on earlyprintk";
That seems unrelated.
PATCH 2/2 ARM: mmp: support pinctrl single in brownstone
Quoted 11 lines · Stephen Warren
arch/arm/boot/dts/mmp2-brownstone.dts line 18
Quoted 7 lines · Haojian Zhuang
Support pinctrl-single driver in brownstone platform with DT.
arch/arm/boot/dts/mmp2-brownstone.dts +1
-1chosen { - bootargs = "console=ttyS2,38400 root=/dev/nfs nfsroot=192.168.1.100:/nfsroot/ ip=192.168.1.101:192.168.1.100::255.255.255.0::eth0:on"; + bootargs = "console=ttyS2,38400 root=/dev/nfs nfsroot=192.168.1.100:/nfsroot/ ip=192.168.1.101:192.168.1.100::255.255.255.0::eth0:on earlyprintk";That seems unrelated.
But it's helpful on debug. Should I remove this? I prefer that I could keep this.
Since I want to watch the whole log before console is enabled.
PATCH 2/2 ARM: mmp: support pinctrl single in brownstone
Quoted 10 lines · Haojian Zhuang
Quoted 9 lines · Stephen Warren
Quoted 7 lines · Haojian Zhuang
Support pinctrl-single driver in brownstone platform with DT.
arch/arm/boot/dts/mmp2-brownstone.dts +1
-1chosen { - bootargs = "console=ttyS2,38400 root=/dev/nfs nfsroot=192.168.1.100:/nfsroot/ ip=192.168.1.101:192.168.1.100::255.255.255.0::eth0:on"; + bootargs = "console=ttyS2,38400 root=/dev/nfs nfsroot=192.168.1.100:/nfsroot/ ip=192.168.1.101:192.168.1.100::255.255.255.0::eth0:on earlyprintk";
Quoted 6 lines
Quoted 2 lines
That seems unrelated.
But it's helpful on debug. Should I remove this? I prefer that I could keep this.
Since I want to watch the whole log before console is enabled.
It should be a separate patch at least.
PATCH 1/2 ARM: dts: support pinctrl single in aspenite
In reply to Haojian Zhuangarch/arm/boot/dts/pxa168.dtsi line 66
Quoted 11 lines · Haojian Zhuang
Support pinctrl-single driver in aspenite DTS file.
arch/arm/boot/dts/pxa168.dtsi +6
-0+ pmx: pinmux at d401e000 { + range0: range at d401e04c { + /* GPIO0 ~ GPIO15 */ + reg = <0xd401e04c 0x40>; + /* gpio base & gpio func */ + pinctrl-single,gpio = <0 5>;
So I see that the "0" here is the first GPIO number, but what is the "5"? The comment says GPIO 0..15, but I don't see anywhere that the "16" count of GPIOs/pins is defined.
PATCH 1/2 ARM: dts: support pinctrl single in aspenite
Quoted 13 lines · Stephen Warren
arch/arm/boot/dts/pxa168.dtsi line 66
Quoted 11 lines · Haojian Zhuang
Support pinctrl-single driver in aspenite DTS file.
arch/arm/boot/dts/pxa168.dtsi +6
-0+ pmx: pinmux at d401e000 { + range0: range at d401e04c { + /* GPIO0 ~ GPIO15 */ + reg = <0xd401e04c 0x40>; + /* gpio base & gpio func */ + pinctrl-single,gpio = <0 5>;
Quoted 4 lines
So I see that the "0" here is the first GPIO number, but what is the "5"? The comment says GPIO 0..15, but I don't see anywhere that the "16" count of GPIOs/pins is defined.
GPIO base number & GPIO function mode is followed by pinctrl-single,gpio. So 0 is GPIO base number, and 5 is GPIO function mode.
GPIO0~GPIO15 is already covered by reg property.
0x40 >>2 = 0x10 (because they're 32-bit registers). So 16 count of GPIOs/pins are mentioned at here.